JP2011193312A - Semiconductor switch circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor switch circuit that reduces switching time and current consumption. <P>SOLUTION: Only for a preset time immediately after the change of the state of a route switching signal from the outside, a switch circuit is driven with a high voltage without being level-shifted by a level-shift short-circuiting switch circuit. After the lapse of a predetermined time, the level shift short-circuiting switch circuit is opened to drive the switch circuit with a voltage dropped through the level shift circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor switch circuit that switches connection between an antenna of a communication device and a transmission circuit or a reception circuit in a mobile phone terminal, a mobile communication device, and the like, and in particular, shortens the switching time of the semiconductor switch circuit and reduces current consumption. It relates to the thing which aimed at reduction coexistence.

  In recent years, wireless communication devices such as mobile phone terminals and wireless LANs have become widespread and demand has increased. In these wireless communication devices, semiconductor switch circuits are widely used for switching transmission / reception, switching frequency bands associated with multiband switching, and switching communication methods. Further, in order to improve the transmission / reception sensitivity by switching a plurality of antennas, a configuration in which a plurality of antennas can be selected using a semiconductor switch circuit is also performed.

  FIG. 5 shows an example of a conventionally known semiconductor switch circuit, which is an SPDT (Single Pole Double Throw) semiconductor switch circuit driven by positive and negative voltages. In addition, this kind of semiconductor switch circuit is disclosed by patent document 1, for example. The semiconductor switch circuit shown in FIG. 5 includes either the first individual input / output terminal 21A or the second individual input / output terminal 22A in accordance with a path switching signal externally applied to the path switching signal input terminal (VCTL) 40A. On the other hand, the common input / output terminal 20A is connected via the switch circuit 6A so that a high-frequency signal passing path is formed. The level shift circuit 3A, the negative voltage output circuit 4A, and the drive circuit 5A are provided.

  In the level shift circuit 3A, the power supply voltage VDD is supplied from the power supply terminal 41A, and a voltage obtained by level shifting the power supply voltage VDD is supplied from the drive voltage High supply terminal 42A to the drive circuit 5A.

  The negative voltage output circuit 4A is a circuit to which a negative voltage is supplied from a not-shown negative voltage generation circuit or the like, and supplies the negative voltage VSS to the drive circuit 5A.

  The drive circuit 5A is configured such that a voltage for the drive voltage High is supplied from the level shift circuit 3A and a voltage for the drive voltage Low is supplied from the negative voltage output circuit 4A. The drive voltage High is a voltage applied to the gate of the switch FET in order to make the switch FET described later conductive, and the drive voltage Low is a voltage applied to the gate of the switch FET in order to make the switch FET nonconductive. It is. In response to a path switching signal applied to the path switching signal input terminal 40A, drive voltages Vcnt1 and Vcnt2 are output that make one of the switch FETs S11A and S12A constituting the switch circuit 6A conductive and the other nonconductive. .

  Such a semiconductor switch circuit is required to have desired characteristics such as insertion loss characteristics, isolation characteristics, low current consumption, distortion characteristics, and switching time. In general, as shown in FIG. 5, when a switch FET is used, there are advantages that it is easy to reduce the size of an IC and reduce current consumption.

  By the way, among the characteristics required for the semiconductor switch circuit, the switching time is one of the important characteristics for a circuit that switches high-frequency signals. The switching time is a delay time from when the control signal is input until the switch circuit is switched. In general, the delay time range allowed by the communication standard is determined, and the switch time is preferably shorter.

  As a method for shortening the switching time, there are a method for reducing the time constant when driving the switch circuit and a method for increasing the voltage for driving the switch circuit.

  First, a method for reducing the time constant when driving the switch circuit will be described with reference to FIG. FIG. 6 shows a switch FET constituting the switch circuit. The time constant of the switch FET is determined by the gate resistance, the gate-drain parasitic capacitance, and the gate-source parasitic capacitance. Therefore, in order to reduce the time constant when driving the switch circuit, the gate resistance of the switch FET is reduced or the gate width of the switch FET is reduced to reduce the gate-drain parasitic capacitance and the gate-source parasitic capacitance. Just make it smaller. However, if the gate resistance is too small, there is a problem that a malfunction occurs in a circuit configured to input a high-frequency signal to the gate electrode, which is not preferable in a high-frequency semiconductor switch circuit. Further, when the gate width is reduced, there are problems such as deterioration of insertion loss characteristics and distortion characteristics of the switch FET.

  Next, a method for increasing the voltage for driving the switch circuit will be described with reference to FIG. In the method of increasing the voltage for driving the switch circuit, when the switch FET is turned on, a voltage higher than the pinch-off voltage Vp is applied to the gate-source voltage of the switch FET. As shown in FIG. 7, when the driving voltage is increased, the time constant when driving the switch circuit does not change, but the time to reach the pinch-off voltage Vp, which is the voltage at which the switch FET switches between the ON state and the OFF state, is fast. I understand that

  On the other hand, FIG. 8 shows the gate current characteristics of the switch FET. As shown in FIG. 8, when the gate voltage (voltage for driving) of the switch FET increases, the gate current increases exponentially and the current consumption increases.

JP 2006-115422 A

  As described above, in a semiconductor switch circuit using a switch FET in a semiconductor switch circuit used for high frequency, if the drive voltage is increased to shorten the switching time, the gate voltage of the switch FET increases, and the semiconductor switch There was a problem that the current consumption of the circuit increased.

  The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor switch circuit capable of shortening a switching time while suppressing an increase in current consumption.

  In order to achieve the above object, the invention according to claim 1 of the present application includes at least one common input / output terminal, two or more individual input / output terminals, the common input / output terminal and the plurality of individual input / output terminals. A semiconductor switch circuit comprising: a switch circuit that selectively connects to each other; a drive circuit that outputs a drive voltage to the switch circuit in response to an external path switching signal; and a level shift circuit that generates the drive voltage. A detection circuit for detecting that the input state of the path switching signal has changed, a pulse generation circuit for generating a pulse signal from the detection signal output from the detection circuit, and a pulse output from the pulse generation circuit And a level shift short circuit switch circuit that bypasses the level shift circuit when the pulse signal is input, and the path switching signal A voltage that outputs the pulse signal from the pulse generation circuit to the level shift short-circuit switch for a preset time from when the force state changes, bypasses the level shift short-circuit switch, and is input to the shift level circuit Is output to the drive circuit as the drive voltage, and after the preset time has elapsed, output of the pulse signal from the pulse generation circuit is stopped, the level shift short-circuit switch is opened, and the level shift is performed. The voltage dropped through the circuit is output to the drive circuit as the drive voltage.

  According to a second aspect of the present invention, in the semiconductor switch circuit according to the first aspect, the detection circuit inputs at least two signals having different logics corresponding to a path switching state output from the drive circuit, and Only the above signal is delayed and output, and the pulse generation circuit forms a pulse signal from the delayed signal.

  According to the present invention, immediately after the path switching signal is input, a high driving voltage is output from the driving circuit, and the switching circuit is driven to shorten the switching time, and is set in advance from switching. In a steady state after a lapse of time, an increase in current consumption can be suppressed by outputting a lower drive voltage from the drive circuit and driving the switch circuit.

It is a figure explaining the basic composition of the semiconductor switch circuit of the present invention. It is explanatory drawing of the Example of this invention. 3 is a timing chart illustrating the operation of the semiconductor switch circuit of the present invention. It is a characteristic diagram which shows the switching characteristic of the Example of this invention. It is explanatory drawing of the conventional semiconductor switch circuit. It is explanatory drawing of switch FET which comprises a switch circuit. It is a figure explaining the method to raise the voltage which drives a switch circuit, in order to shorten switching time. It is a figure explaining the gate current characteristic of switch FET. It is a characteristic line figure which shows the switching characteristic of the conventional semiconductor switch circuit.

  Hereinafter, embodiments of the present invention will be described in detail. The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.

  FIG. 1 is a diagram illustrating a basic configuration of a semiconductor switch circuit according to the present invention. The semiconductor switch circuit shown in FIG. 1 is an SPDT semiconductor switch circuit driven with positive and negative voltages. One of the first individual input / output terminal 21 and the second individual input / output terminal 22 and the common input / output terminal 20 in accordance with a path switching signal applied to the path switching signal input terminal (VCTL) 40 from the outside. Are connected via a switch circuit 6 so that a high-frequency signal passing path is formed. In addition to the conventional level shift circuit 3, negative voltage output circuit 4, and drive circuit 5, the present invention includes a detection circuit 1, a pulse generation circuit 2, and a level shift short circuit S1.

  As in the conventional example, the level shift circuit 3 is supplied with the power supply voltage VDD from the power supply terminal 41, and supplies the drive circuit 5 with the voltage that has been dropped by level shifting the power supply voltage VDD from the drive voltage High supply terminal 42. ing.

  The negative voltage output circuit 4 is a circuit to which a negative voltage is supplied from a negative voltage generation circuit or the like (not shown), and supplies the negative voltage VSS from the drive voltage Low supply terminal 43 to the drive circuit 5.

  The drive circuit 5 is configured such that a voltage for the drive voltage High is supplied from the level shift circuit 3 and a voltage for the drive voltage Low is supplied from the negative voltage output circuit 5. The drive voltage High is a voltage applied to the gate of the switch FET in order to turn on the switch FET constituting the switches S11 and S12 of the switch circuit 6, and the drive voltage Low is used to put the switch FET in a non-conductive state. The voltage applied to the gate of the switch FET. In response to a path switching signal applied to the path switching signal input terminal 40, drive voltages Vcnt1 and Vcnt2 are output that make one of the switches S11 and S12 conductive and the other nonconductive.

  The detection circuit 1 is connected to the drive circuit 5 through the path switching signal state output terminals 31 and 32, and the logical value High and the logical value Low are output from the drive circuit 5 in response to the external path switching signal and are supplied to the detection circuit 1. Entered. When the detection circuit 1 detects that the path switching signal has changed, the detection signal is output from the detection circuit output terminals 33 and 34. A power supply voltage VDD for driving the detection circuit 1 is supplied from the power supply terminal 41.

  The pulse generation circuit 2 is connected to the detection circuit 1 and the detection circuit output terminals 33 and 34, and receives a detection signal output by detecting that the external path switching signal has changed. When the detection signal is input, the pulse signal generated by the pulse generation circuit 2 for a preset time is output from the pulse generation circuit output terminal 35 to the level shift short circuit S1. A power supply voltage VDD for driving the pulse generation circuit 2 is supplied from the power supply terminal 41.

  The level shift short circuit switch circuit S1 inputs the pulse signal output from the pulse generation circuit output terminal 35 of the pulse generation circuit 2. While the pulse signal is being input, the level shift short-circuit switch circuit S1 is short-circuited to form a path that bypasses the level shift circuit.

  The level shift circuit 3 is connected in parallel with the level shift short-circuit switch circuit S1, and when the level shift short-circuit switch circuit S1 is short-circuited, the power supply voltage VDD does not go through the level shift circuit 3 but the level shift short-circuit switch circuit. In the state where the level shift short-circuit switch circuit S1 is open via S1, the voltage VSCH obtained by dropping the power supply voltage VDD by the level shift circuit 3 is supplied to the drive circuit 5. It is configured as follows.

  Next, the operation of the semiconductor switch circuit will be described. When the path switching signal applied to the path switching signal input terminal 40 changes from one state to another state, the drive circuit 5 detects a logical value High and a logical value Low from the path switching signal state output terminals 31 and 32. Output to 1. Thereafter, the detection circuit 1 outputs a signal (detection signal output by detecting that the external path switching signal has changed), which is detected by the path switching signal, and is input to the pulse generation circuit 2. The pulse generation circuit 2 to which the detection signal is input generates a pulse signal for a preset time. Generation of a pulse signal is stopped when a predetermined time has elapsed since the state of the path switching signal has changed. The level shift short circuit switch circuit S1 keeps the level shift circuit 3 short-circuited while the pulse signal is input from the pulse generation circuit 2. In this state, the power supply voltage VDD is supplied to the drive circuit 5. Thereafter, when a predetermined time has elapsed, the pulse signal stops, the level shift short-circuit switch circuit S1 returns to the open state, and the voltage VSCH obtained by dropping the power supply voltage VDD by the level shift circuit 3 is supplied to the drive circuit 5. Supplied. When the line switching signal applied to the path switching signal input terminal 40 changes, the conduction state of the switches S11 and S12 is inverted, and the same operation is repeated.

  As described above, the semiconductor switch circuit according to the present invention is driven by the power supply voltage VDD, which is a high voltage, when the non-conducting state is switched to the conducting state immediately after the path switching signal is changed. By configuring so, the switching time can be shortened. On the other hand, after a predetermined time has elapsed since the state of the path switching signal has changed, the voltage VSCH that has been dropped by the level shift circuit is output as the drive voltage High, so that an increase in current consumption can be suppressed.

  Next, examples will be described. FIG. 2 shows a specific configuration of a semiconductor switch circuit suitable when a GaAsFET is used as a switching element constituting the switch circuit.

  The detection circuit 1 mainly includes resistors R1 and R2 and capacitors C1 and C2 as delay circuits for delaying the rise of the output signals of the inverter circuits 61 and 62 and the inverter circuits 61 and 62. The pulse generation circuit 2 includes a NOR circuit 63 as a main component. The level shift circuit 3 is mainly composed of one (a plurality of diodes Dx1 may be connected in series).

  As shown in FIG. 2, the inverter circuit 61 configuring the detection circuit 1 is connected to the drive circuit 5 through the path switching signal state output terminal 31, and the path switching signal state output terminal 31 has the same state as the external path switching signal. The logic value is input, and the inverter circuit 62 is connected to the drive circuit 5 through the path switching signal state output terminal 32, and the logic value in a state where the external path switching signal is inverted is input from the path switching signal state output terminal 32. It has become so. Specifically, when the state of the external path switching signal is High, the logic value High is input from the drive circuit 5 to the inverter circuit 61 through the path switching signal state output terminal 31, and the inverter circuit 62 is input to the inverter circuit 62. A logical value Low is inputted through the path switching signal state output terminal 32. When the state of the path switching signal from the outside is Low, the logic value Low is input from the drive circuit 5 to the inverter circuit 61 through the path switching signal status output terminal 31, and the path switching signal is input to the inverter circuit 62. The logic value High is input through the status output terminal 32.

  The power supply voltage VDD for driving the inverter circuit 61 is supplied from the power supply terminal 41, and the logical value output of the inverter circuit 61 is output through the inverter circuit output terminal 33. In order to delay the rise of the output signal of the inverter circuit 61, a resistor R1 is connected between the power supply terminal 41 and the inverter circuit 61, and a capacitor C1 is connected as a ground capacitance of the inverter circuit output terminal 33. The power supply voltage VDD for driving the inverter circuit 62 is also supplied from the power supply terminal 41, and the logical value output of the inverter circuit 62 is output through the inverter circuit output terminal 34. In order to delay the rise of the output signal of the inverter circuit 62, a resistor R2 is connected between the power supply terminal 41 and the inverter circuit 62, and a capacitor C2 is connected as a ground capacitance of the inverter circuit output terminal 34.

  The NOR circuit 63 constituting the pulse generation circuit 2 is connected to the inverter circuit 61 through the inverter circuit output terminal 33, and the logical value output of the inverter circuit 61 is input to the NOR circuit 63 through the inverter circuit output terminal 33. The inverter circuit 62 is connected to the inverter circuit output terminal 34, and the logical value output of the inverter circuit 62 is input to the NOR circuit 63 through the inverter circuit output terminal 34. The power supply voltage VDD for driving the NOR circuit 63 is supplied from the power supply terminal 41, and a pulse signal output is output from the NOR circuit 63 through the NOR circuit output terminal 35.

  The level shift short-circuit switch circuit S1 can be composed of a semiconductor element such as a field effect transistor. For example, when the output of the NOR circuit 63 is connected to the gate of the level shift short-circuit switch circuit S1, the output from the NOR circuit 63 The open or short circuit state is controlled by the pulse signal. The level shift short-circuit switch circuit S1 is connected in parallel with the diode Dx1 constituting the level shift circuit 3.

  The diode Dx1 constituting the level shift circuit 3 has the anode of the diode Dx1 connected to the power supply voltage VDD through the power supply terminal 41 and the cathode connected to the drive circuit 5 through the drive voltage High supply terminal 42.

  Next, the operation will be described with reference to FIG. In FIG. 3, the horizontal axis represents time, and the vertical axis represents the path switching signal voltage 40, the inverter circuit (61) output terminal 33, the inverter circuit (62) output terminal 34, the NOR circuit output terminal 35, and the drive voltage High supply. The terminal 42 and the drive voltages Vcnt1 and Vcnt2 are represented by their respective potentials. The operation when the path switching signal is alternately input to the path switching signal input terminal 40 with the logical values Low and High is as follows.

  During time t1 to t2, the logical value Low is inputted to the external path switching signal input terminal 40. During this time, the logic value Low is output from the drive circuit 5 to the inverter circuit 61 through the path switching signal state output terminal 31, and the logic value High is output from the drive circuit 5 to the inverter circuit 62 through the path switching signal state output terminal 32. Is done.

  The inverter circuit 61 outputs the logic value High obtained by inverting the input logic value Low through the inverter circuit output terminal 33, and the inverter circuit 62 outputs the logic value Low obtained by inverting the input logic value High to the inverter circuit output terminal. 34 for output.

  The NOR circuit 63 to which the logical value High is input through the inverter circuit output terminal 33 and the logical value Low is input through the inverter circuit output terminal 34 outputs the logical value Low to the level shift short circuit switch circuit S1 through the NOR circuit output terminal 35. This signal is input to the gate of the level shift short circuit switch circuit S1, and the level shift short circuit switch circuit S1 is in an open state.

  On the other hand, the power supply voltage VDD supplied from the power supply terminal 41 to the level shift circuit 3 is output from the drive voltage High supply terminal 42 to the drive circuit 5 via the diode Dx1. The drive circuit 5 outputs the voltage VSCH supplied from the level shift circuit 3 to the switch S11 of the switch circuit 7 as the drive voltage Vcnt1. Further, the negative voltage VSS is supplied from the negative voltage output circuit 4, and is output to the switch S12 of the switch circuit 7 as the drive voltage Vcnt2.

  As a result, the switch S11 is turned on by the drive voltage Vcnt1, the switch S12 is turned off by the drive voltage Vcnt2, and the first individual input / output terminal 21 is connected to the common input terminal 20. At this time, the drive voltage Vcnt1 for driving the switch S11 is supplied with the voltage VSCH that has been dropped by the level shift circuit 3, so that the current consumed by the switch S11 is suppressed.

  Next, it is assumed that the input signal from the external path switching signal input terminal 40 is switched from the logic value Low to the logic value High at time t2. Immediately after the input signal from the external path switching signal input terminal 40 is switched from the logic value Low to the logic value High (when the input state of the path switching signal changes), the path switching signal is sent from the drive circuit 5 to the inverter circuit 61. A logical value High is output through the state output terminal 31, and a logical value Low is output from the drive circuit 5 to the inverter circuit 62 through the path switching signal state output terminal 32.

  The inverter circuit 61 outputs a logic value Low obtained by inverting the input logic value High through the inverter circuit output terminal 33, and the inverter circuit 62 outputs a logic value High obtained by inverting the input logic value Low through the inverter circuit output terminal 34. Will be output. Here, switching from the logic value Low to the logic value High is delayed by the delay circuits R2 and C2. Therefore, the potential of the output terminal 34 of the inverter circuit 62 has a waveform with a slow rise as shown in FIG.

  When such a waveform with a dull rise is input, the NOR circuit 63 has a time during which signals lower than the threshold value of the NOR circuit 63 are input from the inverter circuit output terminals 33 and 34. As a result, a pulse signal is output from the NOR circuit 63 as shown in FIG.

  This pulse-like signal is input to the gate of the level shift short-circuit switch circuit S1 through the NOR circuit output terminal 35, and the level shift short-circuit switch circuit S1 is short-circuited.

  When the level shift short circuit switch circuit S1 is in a short circuit state, the power supply voltage VDD is supplied from the drive voltage High supply terminal 42 via the level shift short circuit switch circuit S1 without being dropped by the diode Dx1. The drive circuit 5 outputs the power supply voltage VDD that has not been dropped to the switch S12 of the switch circuit 6 as the drive voltage Vcnt2. Further, the negative voltage VSS is supplied from the negative voltage output circuit 4, and is output to the switch S11 of the switch circuit 6 as the drive voltage Vcnt1.

  The switch S12 is turned on by the drive voltage Vcnt2, the switch S11 is turned from the conductive state to the nonconductive state by the drive voltage Vcnt1, and the second individual input / output terminal 22 is connected to the common input / output terminal 20. At this time, the drive voltage Vcnt2 for driving the switch S12 is supplied from the power supply voltage VDD without being dropped by the level shift circuit 3. Therefore, the switching time of the switch S12 is shortened. On the other hand, the current consumption increases while the level shift short-circuit switch S1 is short-circuited.

  However, as shown in FIG. 3, this state is very short because the NOR circuit 63 outputs the logic value Low again when the threshold value of the NOR circuit 63 is exceeded. This time can be set to a desired value by the time constants of the delay circuits R2 and C2 and the threshold value of the NOR circuit 63.

  When the output of the NOR circuit 63 becomes the logic value Low at time t3, the level shift short-circuit switch circuit S1 is again opened, and the power supply voltage VDD supplied from the power supply terminal 41 to the level shift circuit 3 passes through the diode Dx1. Then, the voltage VSCH that has undergone the voltage drop is output from the drive voltage High supply terminal 42 to the drive circuit 5. The drive circuit 5 outputs the voltage VSCH supplied from the level shift circuit 3 to the switch S12 of the switch circuit 6 as the drive voltage Vcnt2. Further, the negative voltage VSS is supplied from the negative voltage output circuit 4, and is output to the switch S11 of the switch circuit 6 as the drive voltage Vcnt1.

  As a result, the switch S12 is kept conductive by the drive voltage Vcnt2, the switch S11 is kept non-conductive by the drive voltage Vcnt1, and the state where the second individual input / output terminal 22 is connected to the common input terminal 20 is maintained. The At this time, the drive voltage Vcnt2 for driving the switch S12 is supplied with the voltage VSCH that has been dropped by the level shift circuit 3, so that the current consumed by the switch S12 is suppressed.

  Similarly, when the input signal from the external path switching signal input terminal 40 is switched from the logical value High to the logical value Low at time t4, the potential of the inverter circuit output terminal 33 of the inverter circuit 61 becomes a dull waveform as shown in FIG. A pulse signal is generated in the NOR circuit 63, and the power supply voltage VDD can be supplied as the drive voltage of the switch S11.

  As described above, according to the present invention, the switches S11 and S12 are turned on after the external path switching signal is switched from the logical value Low to the logical value High or from the logical value High to the logical value Low. By selecting the time constants of the delay circuits R1 and C1, R2, and C2 and the threshold value of the NOR circuit 63 so that the level shift short-circuit switch circuit S1 is short-circuited until the state is reached, the switching time characteristics are improved and the current consumption It is possible to achieve both of the suppression.

  In the embodiment of the present invention, the current consumption increases while switching the switch circuit, but the switching time is very small as viewed from the whole switch driving, and the average current hardly increases.

  Next, switching characteristics of the switch circuit of the present invention will be described. FIG. 4 is a simulation result of switching characteristics of the semiconductor switch circuit of the present invention shown in FIG. For comparison, FIG. 9 shows a simulation result of the switching characteristics of the conventional semiconductor switch circuit shown in FIG. In the figure, the horizontal axis represents time, and the vertical axis represents the high-frequency signal level. The simulation conditions are as follows: the frequency f of the high-frequency signal f = 100 MHz, the power supply voltage VDD = 3 V, the voltage VSCH dropped by the level shift circuit = about 1 V, the negative voltage output voltage VSS = −5 V, the pinch-off voltage Vp = −0 of the switch FET .7V.

  When a path switching signal that changes from the logic value Low to the logic value High is applied to the path switching signal input terminals 40 and 40A, the high-frequency signals input from the individual input / output terminals 22 and 22A are the common input / output terminals 20 and 20A. This represents the rise time required for the output from. The rise time is defined as the time from when the path switching signal is applied as described above until the high frequency signal finally reaches 90% of the signal level in a stable state. In the figure, waveforms with reference signs G1 and G3 represent path switching signal voltages, and waveforms with reference signs G2 and G4 represent high-frequency signal levels output from the common input / output terminals 20 and 20A, respectively. ing. Since the frequency of the high frequency signal level is high, the shape of the sine wave is not limited, and information on the envelope of the high frequency signal level is obtained.

  First, when a path switching signal that changes from the logic value Low to the logic value High is applied to the path switching signal input terminals 40 and 40A, the high-frequency signal input from the individual input / output terminals 22 and 22A is the common input / output terminal 20. 9A is compared with the rise time required for output from 20A, it is 1.99 μsec in the conventional example shown in FIG. This is an improvement of about 40% compared to the conventional example. The rise time is defined as the time from when the path switching signal is applied as described above until the high frequency signal finally reaches 90% of the signal level in a stable state, as described in FIG. Yes.

  When comparing the current consumption, in the present invention, immediately after the path switching signal is switched, the conductive switch FET is driven by the power supply voltage VDD, so that the current consumption is about 50 uA. It increases to about 10 times. However, the time for switching is on the order of μsec, which is very small compared with the time for the entire switch driving being on the order of msec, and the average current hardly increases.

  The embodiments of the present invention have been described by taking the SPDT switch as an example. However, the present invention is not limited to the SPDT switch, and can be applied to other multi-input, multi-output switch circuits. it can. When the path switching signal input terminal is multi-bit, each bit has a detection circuit, a pulse generation circuit, and a level shift short circuit, and the level shift short circuit at each bit is connected to the level shift circuit 3 in parallel. The effects of the above-described invention can be obtained.

1: detection circuit, 2: pulse generation circuit, 3: level shift circuit, 4: negative voltage output generation circuit, 5: drive circuit, 6: switch circuit, 20: common input / output terminal, 21, 22: individual input / output terminal , 31, 32: path switching signal status output terminal, 33, 34: inverter circuit output terminal, 35: pulse generation circuit (NOR circuit) output terminal, 40: path switching signal input terminal, 41: power supply terminal, 42: drive Voltage High supply terminal, 61, 62: Inverter circuit, 63: NOR circuit, S1: Level shift short circuit switch circuit, Dx1: Diode, C1, C2: Delay circuit capacitance, R1, R2: Delay circuit resistance, S11, S12: Switch

Claims (2)

At least one common input / output terminal, two or more individual input / output terminals, a switch circuit for selectively connecting the common input / output terminal and the plurality of individual input / output terminals, and path switching from the outside A semiconductor switch circuit comprising: a drive circuit that outputs a drive voltage to the switch circuit in response to a signal; and a level shift circuit that generates the drive voltage,
A detection circuit that detects that the input state of the path switching signal has changed, a pulse generation circuit that generates a pulse signal from the detection signal output from the detection circuit, and a pulse signal output from the pulse generation circuit And a level shift short circuit switch circuit that bypasses the level shift circuit when the pulse signal is input,
The pulse signal is output from the pulse generation circuit to the level shift short-circuit switch for a preset time from when the input state of the path switching signal is changed, the level shift short-circuit switch is bypassed, and the shift level A voltage input to the circuit is output to the drive circuit as the drive voltage;
After the preset time has elapsed, the output of the pulse signal from the pulse generation circuit is stopped, the level shift short-circuit switch is opened, and the voltage dropped through the level shift circuit is driven. A semiconductor switch circuit that outputs the voltage to the drive circuit as a voltage. The semiconductor switch circuit according to claim 1,
The detection circuit inputs at least two signals having different logics corresponding to the path switching state output from the drive circuit, delays and outputs only at least one signal,
The semiconductor switch circuit, wherein the pulse generation circuit forms a pulse signal from the delayed signal.

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