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JP2011187812A - High-frequency module - Google Patents

High-frequency module Download PDF

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JP2011187812A
JP2011187812A JP2010053164A JP2010053164A JP2011187812A JP 2011187812 A JP2011187812 A JP 2011187812A JP 2010053164 A JP2010053164 A JP 2010053164A JP 2010053164 A JP2010053164 A JP 2010053164A JP 2011187812 A JP2011187812 A JP 2011187812A
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multilayer
multilayer substrate
signal
grid array
ball grid
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Mikio Hatamoto
幹夫 畑本
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To secure electromagnetic shield properties by suppressing space leakage of electromagnetic waves in a module. <P>SOLUTION: A high frequency module is constituted by including a multilayer package constituted by a multilayer substrate housing a semiconductor element and a multilayer mother board to which the multilayer package is connected via a ball grid array. The multilayer package is provided with a vertical power supply via connected to the semiconductor element. The ball grid array has a signal bump whose periphery is surrounded by the grounded bump. The multilayer mother board is provided with the vertical power supply via connected to the signal bump of the ball grid array, and a triplate line connected to the vertical power supply via. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、マイクロ波やミリ波の高周波信号を処理する高周波モジュールに関する。   The present invention relates to a high-frequency module for processing microwave or millimeter-wave high-frequency signals.

従来の高周波モジュールは、増幅器を収納した金属でカバーされた多層パッケージと、前後に配置される基板との間で、金ワイヤや金リボンなどによる接続が行われる。この接続部やマイクロストリップ線路から空間漏洩する電磁波が、自身や隣接して配置する回路に結合して誤動作や性能の劣化を起こさないように、モジュール内で十分に電磁シールド性を確保する必要がある。   In a conventional high-frequency module, a connection using a gold wire, a gold ribbon, or the like is performed between a multilayer package covered with a metal containing an amplifier and substrates disposed in front and back. It is necessary to ensure sufficient electromagnetic shielding in the module so that electromagnetic waves leaking in space from this connection part or microstrip line do not cause malfunction or deterioration of performance due to coupling with itself or adjacent circuits. is there.

このような電磁シールド性を確保する方法として、例えば、特許文献１に示すように、金属カバーを用いて閉空間内のカットオフ周波数を高くして、電磁シールド性を確保する技術が知られている。   As a method for ensuring such electromagnetic shielding properties, for example, as shown in Patent Document 1, a technique for securing electromagnetic shielding properties by increasing the cutoff frequency in a closed space using a metal cover is known. Yes.

特開２００９−１７０８４３号公報JP 2009-170843 A

しかしながら、特許文献１に示す従来の電磁シールド方法では、多層パッケージ数が多い場合に全体を覆うための金属カバーが大きくなるため、接地領域や固定ネジ数の増大に伴ってモジュール寸法が大きくなり、また多層パッケージのサイズが大きい場合、カットオフ周波数を高くすることができない問題があった。   However, in the conventional electromagnetic shielding method shown in Patent Document 1, when the number of multilayer packages is large, the metal cover for covering the whole becomes large, so that the module size increases as the grounding area and the number of fixing screws increase. Further, when the size of the multilayer package is large, there is a problem that the cut-off frequency cannot be increased.

この発明は、係る課題を解決するためになされたものであり、モジュール内の電磁波の空間漏洩を抑圧し、電磁シールド性を確保することを目的とする。   The present invention has been made to solve such a problem, and an object thereof is to suppress spatial leakage of electromagnetic waves in a module and to secure electromagnetic shielding properties.

この発明による高周波モジュールは、半導体素子を収納する多層基板から構成される多層パッケージと、ボールグリッドアレイを介して、上記多層パッケージが接続される多層母基板とを備え、上記多層パッケージは、上記半導体素子に接続される垂直給電ビアが設けられ、上記ボールグリッドアレイは、接地されたバンプで周囲を囲まれる信号バンプを有し、上記多層母基板は、上記ボールグリッドアレイの信号バンプに接続される垂直給電ビアと、当該垂直給電ビアに接続されるトリプレート線路が設けられる。   A high-frequency module according to the present invention includes a multilayer package composed of a multilayer substrate containing semiconductor elements, and a multilayer mother substrate to which the multilayer package is connected via a ball grid array, and the multilayer package includes the semiconductor Vertical feed vias connected to the elements are provided, the ball grid array has signal bumps surrounded by grounded bumps, and the multilayer mother board is connected to the signal bumps of the ball grid array A vertical feed via and a triplate line connected to the vertical feed via are provided.

この発明によれば、半導体素子を収納する多層パッケージと、多層母基板に内蔵するトリプレート線路を、ボールグリッドアレイを構成する信号バンプで接続することにより、電磁波の空間漏洩を抑圧することができるため、高周波信号特性を安定化することが可能となる。   According to the present invention, by connecting the multi-layer package housing the semiconductor elements and the triplate line built in the multi-layer mother board with the signal bumps constituting the ball grid array, it is possible to suppress the spatial leakage of electromagnetic waves. For this reason, the high-frequency signal characteristics can be stabilized.

この発明の実施の形態１に係わる高周波モジュールの構成を示す図である。It is a figure which shows the structure of the high frequency module concerning Embodiment 1 of this invention. この発明の実施の形態１に係わる高周波モジュールのトリプレート線路の構成を示す図である。It is a figure which shows the structure of the triplate track | line of the high frequency module concerning Embodiment 1 of this invention. この発明の実施の形態１に係わる高周波モジュールの垂直給電部の構成を示す図である。It is a figure which shows the structure of the vertical electric power feeding part of the high frequency module concerning Embodiment 1 of this invention.

実施の形態１．
図１はこの発明に係る実施の形態１による高周波モジュールの構成を示す図であり、図２はこの高周波モジュールのトリプレート線路の構成を示す部分上面視図であり、図３はこの高周波モジュールの垂直給電部の構成を示す部分上面視図である。以下、図について説明する。 Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of a high-frequency module according to Embodiment 1 of the present invention, FIG. 2 is a partial top view showing a configuration of a triplate line of this high-frequency module, and FIG. It is a partial top view which shows the structure of a vertical electric power feeding part. Hereinafter, the drawings will be described.

図１において、実施の形態１の高周波モジュールは、母基板である多層基板（多層母基板）１０と、多層基板１０に接合される複数の多層パッケージ６を備えている。多層基板１０は、樹脂基板からなるプリント配線板を構成し、表面または裏面に多数の電気部品が実装されている。多層パッケージ６は多層基板１によって構成される。多層基板１は、多層基板１０に複数個実装されても良い。   1, the high-frequency module according to the first embodiment includes a multilayer substrate (multilayer mother substrate) 10 that is a mother substrate and a plurality of multilayer packages 6 that are bonded to the multilayer substrate 10. The multilayer substrate 10 constitutes a printed wiring board made of a resin substrate, and a large number of electrical components are mounted on the front surface or back surface. The multilayer package 6 is constituted by the multilayer substrate 1. A plurality of multilayer substrates 1 may be mounted on the multilayer substrate 10.

多層基板１は、複数の絶縁体が積層された例えばセラミック積層体によって構成される。多層基板１は、上面に凹状のキャビティ（空洞）１００が設けられ、キャビティ底面には接地導体層１ａが形成されている。多層基板１は、最上面に接地導体層１ｃと信号導体層１ｂが形成されており、最上面の接地導体層にはシールリング５０が接合されている。シールリング５０の上面には、導体蓋（リッド）６０が接合されている。シールリング５０と導体蓋６０は金属カバー３を構成する。多層基板１の底面には接地導体層１ｄと信号導体層１ｆが形成されている。   The multilayer substrate 1 is constituted by, for example, a ceramic laminate in which a plurality of insulators are laminated. The multilayer substrate 1 is provided with a concave cavity (cavity) 100 on the top surface, and a ground conductor layer 1a is formed on the bottom surface of the cavity. The multilayer substrate 1 has a ground conductor layer 1c and a signal conductor layer 1b formed on the uppermost surface, and a seal ring 50 is joined to the uppermost ground conductor layer. A conductor lid (lid) 60 is joined to the upper surface of the seal ring 50. The seal ring 50 and the conductor lid 60 constitute the metal cover 3. A ground conductor layer 1 d and a signal conductor layer 1 f are formed on the bottom surface of the multilayer substrate 1.

多層基板１上面の接地導体層１ａには、キャビティ１００内に収容される、半導体素子を含む電子部品（半導体チップ）である増幅器２が載置されている。増幅器２の上面と多層基板１の信号導体層１ｂとは、金ワイヤや金リボンなどの導電性部材７０により接続されている。なお、増幅器２の上面と多層基板１の信号導体層１ｂとの高さは、同じになるように調整されている。   An amplifier 2, which is an electronic component (semiconductor chip) including a semiconductor element, housed in the cavity 100 is placed on the ground conductor layer 1 a on the upper surface of the multilayer substrate 1. The upper surface of the amplifier 2 and the signal conductor layer 1b of the multilayer substrate 1 are connected by a conductive member 70 such as a gold wire or a gold ribbon. The height of the upper surface of the amplifier 2 and the signal conductor layer 1b of the multilayer substrate 1 are adjusted to be the same.

多層基板１底面の接地導体層１ｄには、複数のバンプ１１、１１ｂが接合されている。バンプ１１、１１ｂは、半田バンプや金バンプなどで構成され、多層基板１の底面に設けられたボールグリッドアレイを構成する。複数のバンプ１１、１１ｂはグランドに接続される。また、多層基板１底面の信号導体層１ｆには、信号バンプ１２が接合されている。信号バンプ１２は、半田バンプや金バンプなどで構成される。   A plurality of bumps 11, 11 b are bonded to the ground conductor layer 1 d on the bottom surface of the multilayer substrate 1. The bumps 11 and 11b are constituted by solder bumps, gold bumps, or the like, and constitute a ball grid array provided on the bottom surface of the multilayer substrate 1. The plurality of bumps 11 and 11b are connected to the ground. Further, signal bumps 12 are bonded to the signal conductor layer 1 f on the bottom surface of the multilayer substrate 1. The signal bump 12 is composed of a solder bump, a gold bump, or the like.

多層基板１の内層には、接地導体ビア（ＶＩＡ）４と、導体からなる垂直給電ビア５が設けられている。接地導体ビア（ＶＩＡ）４は、多層基板１の外周を取り囲むように複数個配列されている。導体ビア４は、複数配列されることで擬似的な電磁シールド壁面を構成する。   In the inner layer of the multilayer substrate 1, a ground conductor via (VIA) 4 and a vertical feed via 5 made of a conductor are provided. A plurality of ground conductor vias (VIA) 4 are arranged so as to surround the outer periphery of the multilayer substrate 1. A plurality of conductor vias 4 are arranged to constitute a pseudo electromagnetic shield wall surface.

また、垂直給電ビア５の周囲は、複数個の接地導体ビア（ＶＩＡ）４によって取り囲まれている。垂直給電ビア５は、多層基板１底面の信号導体層１ｆに接続される。また、接地導体ビア（ＶＩＡ）４は、多層基板１底面の接地導体層１ｄに接続される。さらに、多層基板１の外周に配列された接地導体ビア（ＶＩＡ）４は、多層基板１底面の多層基板１の外周側に設けられた接地導体層１ｄに接続される。接地導体層１ｄはグランドに接続される。   The periphery of the vertical power supply via 5 is surrounded by a plurality of ground conductor vias (VIA) 4. The vertical power supply via 5 is connected to the signal conductor layer 1 f on the bottom surface of the multilayer substrate 1. The ground conductor via (VIA) 4 is connected to the ground conductor layer 1 d on the bottom surface of the multilayer substrate 1. Furthermore, the ground conductor vias (VIA) 4 arranged on the outer periphery of the multilayer substrate 1 are connected to a ground conductor layer 1 d provided on the outer periphery side of the multilayer substrate 1 on the bottom surface of the multilayer substrate 1. The ground conductor layer 1d is connected to the ground.

多層基板１０は、表面に導体層（２０ａ、２０ｂ、２０ｃ）が設けられ、裏面に接地導体層２１が形成されている。この表面の導体層は、信号導体層２０ａ、２０ｂと、接地導体層２０ｃから形成される。また、多層基板１０は、内層にトリプレート線路導体７と垂直給電ビア９と接地導体ビア８が設けられている。トリプレート線路導体７は、上下面が接地面を構成する導体層２０ｃと接地導体層２１の間に挟まれ、トリプレート線路を構成している。接地導体層２０ｃ、２１はグランドに接続される。   The multilayer substrate 10 is provided with conductor layers (20a, 20b, 20c) on the front surface and a ground conductor layer 21 on the back surface. The conductor layer on the surface is formed of signal conductor layers 20a and 20b and a ground conductor layer 20c. The multilayer substrate 10 is provided with a triplate line conductor 7, a vertical feed via 9, and a ground conductor via 8 in the inner layer. The triplate line conductor 7 is sandwiched between the conductor layer 20c and the ground conductor layer 21 whose upper and lower surfaces constitute a ground plane, and constitutes a triplate line. The ground conductor layers 20c and 21 are connected to the ground.

多層基板１０の信号導体層２０ａは、信号バンプ１２に接続されるとともに、導体からなる垂直給電ビア９を介して、トリプレート線路導体７に接続されている。
図２に示すように、トリプレート線路導体７に接続された垂直給電ビア９は、周囲を接地導体ビア８によって馬蹄形状に囲まれている。接地導体層２０ｃは、複数のバンプ１１に接合されている。信号導体層２０ｂは、垂直給電ビア９を介してトリプレート線路導体７に接続されており、外部回路または他の高周波モジュールに接続される外部信号端子を構成している。 The signal conductor layer 20a of the multilayer substrate 10 is connected to the signal bumps 12 and is connected to the triplate line conductor 7 through a vertical feed via 9 made of a conductor.
As shown in FIG. 2, the vertical feed via 9 connected to the triplate line conductor 7 is surrounded by a horseshoe shape by the ground conductor via 8. The ground conductor layer 20 c is bonded to the plurality of bumps 11. The signal conductor layer 20b is connected to the triplate line conductor 7 through the vertical feed via 9, and constitutes an external signal terminal connected to an external circuit or another high-frequency module.

図３に示すように、多層基板１および多層基板１０において、信号バンプ１２は、平面内で正方形状に配置されたバンプ１１ｂによって四方向が囲まれることで、擬似的に同軸線路を構成している。また、信号バンプ１２およびバンプ１１ｂによって構成される擬似的な同軸線路は、さらに複数のバンプ１１によって囲まれている。これによって、信号バンプ１２は、グランドに接続された８個のバンプによって周囲を囲まれることとなるので、擬似的な同軸線路からの電磁波の漏洩をより確実に抑えることができる。   As shown in FIG. 3, in the multilayer substrate 1 and the multilayer substrate 10, the signal bump 12 is surrounded in four directions by bumps 11 b arranged in a square shape in a plane, thereby forming a pseudo coaxial line. Yes. The pseudo coaxial line constituted by the signal bumps 12 and the bumps 11 b is further surrounded by a plurality of bumps 11. As a result, the signal bump 12 is surrounded by eight bumps connected to the ground, so that leakage of electromagnetic waves from the pseudo coaxial line can be more reliably suppressed.

実施の形態１による高周波モジュールは以上のように構成され、多層基板１上に増幅器２を搭載し、増幅器２は金属カバー３、接地導体１ａ、１ｄおよび導体ビア４から構成される擬似的な電磁壁で囲まれることによって電磁シールドされる。また、垂直給電ビア５、信号バンプ１２および垂直給電ビア９は垂直給電構造を構成し、導体ビア４、バンプ１１ｂおよび接地導体ビア８によって周囲を囲まれた擬似的な同軸線路を構成する。多層基板１０は、複数のバンプ１１、１１ｂが設けられ、増幅器２が収納され、金属カバー３が接合されて増幅器２を気密封止することで、多層パッケージ６を構成する。多層パッケージ６は、垂直給電ビア５を介して多層基板１の裏面の信号バンプ１２から信号を入力および出力し、内部の増幅器２により入力信号の信号増幅処理を行い、増幅された信号をパッケージ外部に出力する。バンプ１１、１１ｂおよび信号バンプ１２からなるボールグリッドアレイは垂直給電接続部を構成する。多層基板１と多層基板１０の間を接合するバンプ１１はグランドに接続されることで、多層基板１と多層基板１０の間の空隙を通過する高周波信号を抑制する。   The high-frequency module according to the first embodiment is configured as described above, and the amplifier 2 is mounted on the multilayer substrate 1, and the amplifier 2 is a pseudo electromagnetic wave composed of the metal cover 3, the ground conductors 1a and 1d, and the conductor via 4. It is electromagnetically shielded by being surrounded by a wall. The vertical power supply via 5, the signal bump 12 and the vertical power supply via 9 constitute a vertical power supply structure, and form a pseudo coaxial line surrounded by the conductor via 4, the bump 11b and the ground conductor via 8. The multilayer substrate 10 is provided with a plurality of bumps 11, 11 b, the amplifier 2 is accommodated, and the metal cover 3 is joined to hermetically seal the amplifier 2, thereby forming the multilayer package 6. The multilayer package 6 inputs and outputs signals from the signal bumps 12 on the back surface of the multilayer substrate 1 through the vertical power supply vias 5, performs signal amplification processing of the input signals by the internal amplifier 2, and outputs the amplified signals to the outside of the package Output to. The ball grid array composed of the bumps 11 and 11b and the signal bumps 12 constitutes a vertical feeding connection portion. The bumps 11 that join the multilayer substrate 1 and the multilayer substrate 10 are connected to the ground, thereby suppressing high-frequency signals passing through the gaps between the multilayer substrate 1 and the multilayer substrate 10.

また、多層基板１０は、トリプレート線路７を内蔵し、垂直給電ビア９で構成された垂直給電線路とトリプレート線路導体７を介して、基板表面の信号導体層２０ａ、２０ｂから信号を入力および出力する。多層パッケージ６は、その垂直給電接続部を介して多層基板１０に接続され、多層基板１０のトリプレート線路導体７を介して、信号導体層２０ｂとの間で信号の入力および出力を行う。   The multilayer substrate 10 includes a triplate line 7 and inputs signals from the signal conductor layers 20a and 20b on the surface of the substrate via the vertical feed line formed by the vertical feed vias 9 and the triplate line conductor 7. Output. The multilayer package 6 is connected to the multilayer substrate 10 through the vertical power supply connection portion, and inputs and outputs signals to and from the signal conductor layer 20 b through the triplate line conductor 7 of the multilayer substrate 10.

実施の形態１による高周波モジュールは以上のように構成されているので、多層基板１０内は垂直給電線路に接続されるトリプレート線路導体７が、グランドに囲まれた内層のトリプレート線路を構成しているため、多層基板１０の外部空間への電磁波の漏洩がない。また、ボールグリッドアレイを構成する多層パッケージ６の垂直給電接続部は、グランドに接続された導体ビア４で垂直給電ビア５が覆われているため、金属カバーで遮蔽することなく、外部空間への電磁波の漏洩を抑圧することができる。   Since the high-frequency module according to the first embodiment is configured as described above, the triplate line conductor 7 connected to the vertical feed line in the multilayer substrate 10 forms an inner layer triplate line surrounded by the ground. Therefore, there is no leakage of electromagnetic waves to the external space of the multilayer substrate 10. Further, since the vertical power supply vias 5 of the multilayer package 6 constituting the ball grid array are covered with the conductor vias 4 connected to the ground, the vertical power supply vias 5 are not shielded by the metal cover. Electromagnetic leakage can be suppressed.

また、金属カバーで封止された多層パッケージ６と、母基板の多層基板１０に内蔵するトリプレート線路を、ボールグリッドアレイを構成する垂直給電接続部で接続することにより、電磁波の空間漏洩を抑圧することができるため、ＲＦ（Radio Frequency）信号の通過損失を抑制することで、高周波信号の伝送特性を安定化することが可能となる。   Also, the multi-layer package 6 sealed with a metal cover and the triplate line built in the multi-layer substrate 10 of the mother board are connected by a vertical power supply connecting portion constituting a ball grid array, thereby suppressing spatial leakage of electromagnetic waves. Therefore, it is possible to stabilize the transmission characteristics of the high frequency signal by suppressing the passage loss of the RF (Radio Frequency) signal.

１ 多層基板、１ａ 接地導体層、１ｂ 信号導体層、１ｃ 接地導体層、１ｄ 接地導体層、２ 増幅器、３ 金属カバー、４ 接地導体ビア、５ 垂直給電ビア、６ 多層パッケージ、７ トリプレート線路導体、８ 接地導体ビア、９ 垂直給電ビア、１０ 多層基板（多層母基板）、１１ バンプ、１１ｂ バンプ、１２ 信号バンプ、２０ａ 信号導体層、２０ｂ 信号導体層、２０ｃ 接地導体層。   1 multilayer substrate, 1a ground conductor layer, 1b signal conductor layer, 1c ground conductor layer, 1d ground conductor layer, 2 amplifier, 3 metal cover, 4 ground conductor via, 5 vertical feed via, 6 multilayer package, 7 triplate line conductor 8 Ground conductor vias, 9 Vertical feed vias, 10 Multilayer substrate (multilayer motherboard), 11 Bump, 11b Bump, 12 Signal bump, 20a Signal conductor layer, 20b Signal conductor layer, 20c Ground conductor layer.

Claims (1)

半導体素子を収納する多層基板から構成される多層パッケージと、
ボールグリッドアレイを介して、上記多層パッケージが接続される多層母基板と、
を備え、
上記多層パッケージは、上記半導体素子に接続される垂直給電ビアが設けられ、
上記ボールグリッドアレイは、接地されたバンプで周囲を囲まれる信号バンプを有し、
上記多層母基板は、上記ボールグリッドアレイの信号バンプに接続される垂直給電ビアと、当該垂直給電ビアに接続されるトリプレート線路が設けられた高周波モジュール。 A multi-layer package composed of a multi-layer substrate containing semiconductor elements;
A multilayer mother board to which the multilayer package is connected via a ball grid array;
With
The multilayer package is provided with a vertical feed via connected to the semiconductor element,
The ball grid array has signal bumps surrounded by grounded bumps,
The multi-layer mother board is a high-frequency module in which a vertical feed via connected to a signal bump of the ball grid array and a triplate line connected to the vertical feed via are provided.
JP2010053164A 2010-03-10 2010-03-10 High-frequency module Pending JP2011187812A (en)

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US9368457B2 (en) 2012-03-07 2016-06-14 Mitsubishi Electric Corporation High-frequency package
US9591756B2 (en) 2011-05-24 2017-03-07 Mitsubishi Electric Corporation High-frequency package
WO2017098741A1 (en) * 2015-12-07 2017-06-15 三菱電機株式会社 Microwave module
JP6173611B1 (en) * 2016-04-27 2017-08-02 三菱電機株式会社 High frequency circuit
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9591756B2 (en) 2011-05-24 2017-03-07 Mitsubishi Electric Corporation High-frequency package
US9368457B2 (en) 2012-03-07 2016-06-14 Mitsubishi Electric Corporation High-frequency package
WO2017098741A1 (en) * 2015-12-07 2017-06-15 三菱電機株式会社 Microwave module
WO2017099145A1 (en) * 2015-12-07 2017-06-15 三菱電機株式会社 Microwave module and high-frequency module
JPWO2017099145A1 (en) * 2015-12-07 2018-04-19 三菱電機株式会社 Microwave module and high frequency module
US10707910B2 (en) 2015-12-07 2020-07-07 Mitsubishi Electric Corporation Microwave module
JP6173611B1 (en) * 2016-04-27 2017-08-02 三菱電機株式会社 High frequency circuit
WO2017187559A1 (en) * 2016-04-27 2017-11-02 三菱電機株式会社 High frequency circuit
US10512153B2 (en) 2016-04-27 2019-12-17 Mitsubishi Electric Corporation High frequency circuit
CN111698824A (en) * 2020-05-22 2020-09-22 中国电子科技集团公司第二十九研究所 Integrated interconnection structure of self-airtight packaging functional module and implementation method
CN111698824B (en) * 2020-05-22 2022-03-08 中国电子科技集团公司第二十九研究所 Integrated interconnection structure of self-airtight packaging functional module and implementation method

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