JP2011187792A - Semiconductor package, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of a semiconductor package which prevents a junction area from being reduced as a pad opening diameter of a connection terminal decreases to degrade junction strength, and excels in junction strength between the connection terminal and a bump, and to provide a method of manufacturing the same. <P>SOLUTION: In this semiconductor package, wiring and a pad 102 used as a connection terminal are formed on a circuit board, and parts other than the pad are covered with solder resist 103. In the semiconductor package, an electroless-copper-plated layer 104 is formed on a solder resist tapered part 112 in a solder resist opening, and a metal coating treatment is applied to a surface of the electroless-copper-plated layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a circuit board used for a semiconductor package or the like and a manufacturing method thereof.

  Semiconductor packages are becoming more and more miniaturized, the pad diameter used as an IC chip connection terminal is reduced, and the solder bump pitch is reduced. FIG. 2 is a process procedure diagram showing a conventional bump forming manufacturing method with respective drawings of sequential symbols (a) to (d). 2A to 2D are all cross-sectional views.

  In FIG. 2A, electroless copper plating is used as a power feeding layer on an insulating resin 201, a photo dry film resist is laminated thereon, patterning is performed, and copper wiring and pads are formed by electrolytic copper plating. After the film resist is peeled off and the power feeding layer is peeled off, a state where the bumps of the connection terminals and the chip capacitor are mounted is covered with the solder resist 203.

  FIG. 2B shows a state where electroless nickel plating 206 is applied to the pad 202 serving as a connection terminal, and gold flash plating 207 is applied on the electroless nickel plating 206.

  FIG. 2C shows a state in which the solder paste 209 is printed through the squeegee 208 and the metal mask 210, and the solder resist opening 205 serving as the connection terminal is filled with the solder paste 209.

  In FIG. 2D, when the solder paste is heated in the reflow process, the solder paste is melted to form nickel and an alloy layer, thereby being bonded to the pad, and the formation of the solder bump 211 is completed. However, as the pad diameter of the connection terminal is reduced, the bonding area is reduced, and the bonding strength between the connection terminal and the bump is reduced.

Japanese Patent Laid-Open No. 9-232463

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor package structure and a manufacturing method excellent in bonding strength between connection terminals and bumps.

  In order to solve the above-mentioned problems, the invention of claim 1 is a semiconductor package in which a pad to be a wiring and a connection terminal is formed on a circuit board, and a portion other than the pad is covered with a solder resist. An electroless copper plating layer is formed on the solder resist taper portion, and the surface of the electroless copper plating layer is further subjected to a metal film treatment.

The invention of claim 2 is a method of manufacturing a semiconductor package,
Forming an electroless copper plating layer on the entire surface of the substrate;
Forming a plating resist in addition to the pad portion and the solder resist taper portion; and
Forming an electroless nickel plating layer on the electroless copper plating layer formed on the pad portion and the solder resist taper portion; and
Forming gold plating on the electroless nickel plating layer formed on the pad portion and the solder resist taper portion; and
Removing the plating resist;
Peeling the electroless copper plating layer under the plating resist;
Forming solder bumps on the gold plating layer formed on the pad portion and the solder resist taper portion; and
In a semiconductor package manufacturing method.

  The invention according to claim 3 is characterized in that the step of forming the solder bump uses any one of a paste printing method, a solder dam pre-coating method, and a solder ball mounting method. It is a manufacturing method of a package.

  The invention of claim 4 is the method for manufacturing a semiconductor package according to claim 2, wherein the surface treatment applied to the electroless copper plating is electroless tin plating.

  According to the present invention, the semiconductor package having a reduced bump diameter has the following advantages over the semiconductor package substrate of the conventional bump forming method. Excellent bonding between connection terminals and pads by forming solder bumps with increased bonding area by applying electroless copper plating to pads and solder resist taper, and surface treatment such as nickel gold plating on top Strength can be obtained.

Explanatory drawing of the process sequence which shows 1st Embodiment by the solder bump formation method by this invention Explanatory drawing of process procedure showing conventional solder bump formation method Explanatory drawing of the process sequence which shows 2nd Embodiment by the solder bump formation method by this invention Explanatory drawing of the process procedure which shows 3rd Embodiment by the solder bump formation method by this invention

  As a method for manufacturing a semiconductor package of the present invention, an electroless copper plating layer is formed on the entire surface of a substrate on which pads to be wiring and connection terminals are formed, and a plating resist is formed in addition to the pad portion and the solder resist taper portion, Electroless nickel plating and gold plating are sequentially formed on the electroless copper plating formed on the pad portion and the solder resist taper portion, the plating resist is peeled off, and the electroless copper plating under the plating resist is peeled off. The bonding area between the bump and the bump can be increased by a manufacturing method comprising sequentially forming solder bumps on the gold plating layer formed on the pad portion and the solder resist taper portion.

  The solder bumps can be formed by a printing method in which solder paste is formed with a squeegee and a metal mask, a ball mounting method in which a solder ball is transferred after a flux is printed in the pad, and a photo dry film resist as a mask instead of a metal mask. Any of the solder dam pre-coating methods may be used.

  The surface treatment on the pad and the solder resist taper may be electroless tin plating.

Next, embodiments will be described with reference to the drawings.
[First embodiment]
FIG. 1 is a diagram for explaining a process procedure shown in the drawings with sequential symbols (a) to (g) showing the form of a method for manufacturing a semiconductor package according to the present invention, and all show sectional views. Hereinafter, a general manufacturing method will be described.

  In FIG. 1A, electroless copper plating is used as a power supply layer on an insulating resin 101, a photo dry film resist is laminated thereon, wiring and pads 102 are patterned, and the pattern plating layer is formed by electrolytic copper plating. The photo dry film resist is peeled off with an alkali-based stripping solution or an amine-based stripping solution, the power feeding layer is stripped with a sulfuric acid / hydrogen peroxide-based etching solution, and other than necessary portions such as connection terminals are covered with a solder resist 103. A state in which the surface of the resist 102 is roughened using an alkaline permanganate etching solution is shown.

  FIG. 1B shows a state where the electroless copper plating 104 is applied to the substrate surface.

  In FIG. 1C, after plating resist 105 is laminated with a roll laminator, exposure is performed using an exposure apparatus such as a contact exposure machine, a stepper exposure machine, or a laser exposure machine, and development is performed with an alkaline developer. In addition, the surface of the solder resist taper portion 112 is opened.

  FIG. 1D shows a state in which an electroless nickel plating 106 is applied on the electroless copper plating 104 film and a gold flash plating 107 is applied on the electroless nickel plating film 106.

  FIG. 1 (e) shows a state in which the plating resist 105 is stripped with an alkaline stripping solution or an amine stripping solution, and the exposed electroless copper plating 104 is removed with a sulfuric acid / hydrogen peroxide etching solution.

  FIG. 1F shows a state where the solder paste 109 is printed on the solder resist 103 using the squeegee 108 via the metal mask 110.

  FIG. 1 (g) shows a state in which the solvent in the solder paste 109 evaporates and the solder melts into a spherical shape by reflowing. In this way, the formation of the solder bump 111 is completed.

  As described above, according to the first embodiment, the electroless copper plating 104 film is formed on the pad 102 and the solder resist taper portion, the electroless nickel plating 106 film is further formed thereon, and the gold flash is further formed thereon. By forming the solder bump 111 with the surface provided with 107 as a bonding interface, the bonding area can be increased, and excellent bonding strength between the connection terminal and the pad can be obtained.

[Second Embodiment]
FIG. 3 is a diagram for explaining a partial process procedure showing a second embodiment of the semiconductor package manufacturing method according to the present invention. In FIG. 3, for the sake of simplification of explanation, other bump forming methods in the steps after FIG. 1 (f) of the first embodiment are given the sequential symbols of FIG. 3 (a) to (d). This will be described with reference to each figure. In FIG. 3, (a) to (d) are all cross-sectional views.

In FIG. 3A, a heat-resistant photodry film resist 312 that can cope with the reflow temperature is laminated on a solder resist 303 by roll lamination or the like, and exposed with a contact exposure machine or a stepper exposure machine, and an alkaline developer or the like. In this state, development is performed, patterning is performed, and the pad 302 which is a connection terminal portion is opened. The thickness of the heat resistant photo dry film resist 312 varies depending on the required height of the solder bump 311.

  FIG. 3B shows a state in which the solder paste 309 is printed with the squeegee 308 with the heat-resistant photodry film resist 213 having the connection terminals opened as a mask.

  FIG. 3C shows a state in which the solvent content in the solder paste 309 is evaporated by reflowing, the solder is melted, the solder becomes spherical, and becomes solder bumps 311.

  FIG. 3D shows a state in which the heat-resistant photodry film resist 312 is peeled off with an alkaline stripping solution or an amine stripping solution. In this way, the formation of the solder bump 311 is completed.

  As described above, according to the second embodiment, the same effect as the effect described in the description of the first effect can be obtained. However, in the case of this embodiment, it is not necessary to prepare a metal mask. Although the metal mask had to be prepared with a plurality of metal masks due to the expansion and contraction of the substrate, it is possible to form solder bumps without a mask, leading to cost reduction.

[Third embodiment]
FIG. 4 is a diagram for explaining a partial process procedure showing a third embodiment of the semiconductor package manufacturing method according to the present invention. In FIG. 4, for simplification of explanation, other bump forming methods in the steps after FIG. 1 (f) of the first embodiment are given the sequential symbols of FIGS. 4 (a) to (c). This will be described with reference to each figure. In FIG. 4, (a) to (c) are all cross-sectional views.

  FIG. 4A shows a state in which the flux 413 is printed on the solder resist 403 using the squeegee 408 through the flux metal mask 414.

  FIG. 4B shows a state in which the solder balls 413 are transferred through the ball mounting mask 416. As the transfer method of the solder ball 413, there are a method using a low weak spring force and a fiber bundle, a high-speed flow stirring, a natural drop method, and the like. Any method for transferring the solder balls may be used.

  In FIG. 4C, by performing reflow, the flux 413 can remove the oxide film of the pad 402 of the connection terminal portion and the solder ball 415, and the solder ball 415 and the pad 402 of the connection terminal can be bonded more strongly. .

  As described above, according to the third embodiment, the same effect as that described in the explanation of the first effect can be obtained. However, in the case of this embodiment, when the solder bump pitch is narrowed, adjacent bumps are not short-circuited, and since the solder balls are used, the solder bump height can be made uniform. .

  In the above description, an example using electroless nickel plating has been described. However, the present invention can be similarly applied to a pad interface made of electrolytic nickel plating or a pad interface made of tin plating.

101, 201, 301, 401: Insulating resin 102, 202, 302, 402: Pad 103, 203, 303, 403: Solder resist 104, 304, 404: Electroless copper plating 104: Plating resist 106, 206, 306, 406 : Electroless nickel plating 107, 207, 307, 407: Gold flash plating 108, 208, 308: Squeegee 109, 209, 309: Solder paste 110, 210: Metal mask 111, 211, 311, 411: Solder bump 112: Solder Resist taper portion 205: Solder resist opening 312: Heat resistant photo dry film resist 413: Flux 414: Flux metal mask 415: Solder ball 416: Ball mounting metal mask

Claims (4)

  In a semiconductor package in which pads that serve as wiring and connection terminals are formed on a circuit board and the portions other than the pads are covered with a solder resist, an electroless copper plating layer is formed on the solder resist taper in the solder resist opening. Furthermore, a metal package treatment is applied to the surface of the electroless copper plating layer. A method for manufacturing a semiconductor package, comprising:
Forming an electroless copper plating layer on the entire surface of the substrate;
Forming a plating resist in addition to the pad portion and the solder resist taper portion; and
Forming an electroless nickel plating layer on the electroless copper plating layer formed on the pad portion and the solder resist taper portion; and
Forming gold plating on the electroless nickel plating layer formed on the pad portion and the solder resist taper portion; and
Removing the plating resist;
Peeling the electroless copper plating layer under the plating resist;
Forming solder bumps on the gold plating layer formed on the pad portion and the solder resist taper portion; and
A method for manufacturing a semiconductor package, characterized by sequentially performing the steps.   3. The method of manufacturing a semiconductor package according to claim 2, wherein the step of forming the solder bump uses any one of a paste printing method, a solder dam pre-coating method, and a solder ball mounting method.   4. The method of manufacturing a semiconductor package according to claim 2, wherein the surface treatment applied on the electroless copper plating is electroless tin plating.

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