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JP2011176112A - Semiconductor integrated circuit and method of manufacturing the same - Google Patents

Semiconductor integrated circuit and method of manufacturing the same Download PDF

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Publication number
JP2011176112A
JP2011176112A JP2010038893A JP2010038893A JP2011176112A JP 2011176112 A JP2011176112 A JP 2011176112A JP 2010038893 A JP2010038893 A JP 2010038893A JP 2010038893 A JP2010038893 A JP 2010038893A JP 2011176112 A JP2011176112 A JP 2011176112A
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semiconductor chip
integrated circuit
reinforcing material
semiconductor integrated
substrate
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Inventor
Satoru Matsuda
覚 松田
Tsukasa Yasuda
司 安田
Ichiro Matsumoto
市郎 松本
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2010038893A priority Critical patent/JP2011176112A/en
Priority to US12/929,759 priority patent/US20110204497A1/en
Priority to CN2011100472189A priority patent/CN102169865A/en
Publication of JP2011176112A publication Critical patent/JP2011176112A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/028—Bending or folding regions of flexible printed circuits
    • H05K1/0281—Reinforcement details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01—ELECTRIC ELEMENTS
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/14—Integrated circuits
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/30—Technical effects
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    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector

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Abstract

【課題】テープまたはフィルム状の基板に半導体チップを実装し、かつ曲げに対する強度がより高い半導体集積回路及びその製造法を提供すること。
【解決手段】半導体集積回路１は、外部端子、矩形の半導体チップ２０に接続するために設けられた内部端子および内部端子と外部端子とを接続する配線５０を有する屈曲可能なテープ状の基板１０と、テープ状基板１０に電気的に接続された半導体チップ２０と、テープ状基板１０上の半導体チップ２０の長手方向を補強する補強材３０とを有し、半導体チップ２０と補強材３０とが樹脂４０により封止されたものである。
【選択図】図１To provide a semiconductor integrated circuit having a semiconductor chip mounted on a tape or film-like substrate and having higher bending strength, and a method for manufacturing the same.
A semiconductor integrated circuit includes a bendable tape-like substrate having external terminals, internal terminals provided for connection to a rectangular semiconductor chip, and wirings for connecting the internal terminals and external terminals. And a semiconductor chip 20 electrically connected to the tape-like substrate 10 and a reinforcing member 30 that reinforces the longitudinal direction of the semiconductor chip 20 on the tape-like substrate 10, and the semiconductor chip 20 and the reinforcing member 30 are It is sealed with resin 40.
[Selection] Figure 1

Description

本発明は半導体集積回路及びその製造方法に関し、特にテープまたはフィルム状の基板に半導体チップが実装された半導体集積回路及びその製造方法に関する。   The present invention relates to a semiconductor integrated circuit and a manufacturing method thereof, and more particularly to a semiconductor integrated circuit in which a semiconductor chip is mounted on a tape or film substrate and a manufacturing method thereof.

近年、テレビやパソコン用ディスプレーに使用される表示デバイスの大画面化・高精細化が進んでおり、表示デバイス用ＩＣ、特にソースドライバの出力端子数は９００を超えるようになってきている。   In recent years, display devices used in television and personal computer displays have been increased in screen size and definition, and the number of output terminals of display device ICs, particularly source drivers, has exceeded 900.

また、表示パネル外周部の非表示エリア部分の寸法がより小さいデザインの、いわゆる狭額縁仕様の表示パネルの需要も根強い。加えて、コスト競争も激しくなってきている。これらへの方策の一つとして、ドライバＩＣのチップサイズのシュリンクがある。材料面、工数面からの製造コストが抑えられるからである。   In addition, there is a strong demand for a so-called narrow frame display panel having a design in which the size of the non-display area portion on the outer periphery of the display panel is smaller. In addition, cost competition is intensifying. As one of the measures against these, there is shrinkage of the chip size of the driver IC. This is because the manufacturing cost in terms of material and man-hour can be suppressed.

他方、実装形態においても、表示デバイス用ＩＣは、多くの出力を狭額縁領域に実装する必要があるため、薄い可撓性基材を使用し、屈曲可能かつ高さを抑えたＴＡＢもしくはＣＯＦ構成をとることが多い。さらに、ドライバＩＣの出力端子の狭ピッチ化に伴い、ドライバＩＣと表示装置の負荷ラインとの接続信頼性の観点からもＴＣＰ，ＣＯＦが主流となっている。   On the other hand, since the display device IC also needs to be mounted in a narrow frame region in the mounting form, a TAB or COF configuration that uses a thin flexible substrate, can be bent, and has a reduced height. Is often taken. Further, TCP and COF are mainly used from the viewpoint of connection reliability between the driver IC and the load line of the display device as the pitch of the output terminals of the driver IC is narrowed.

特に、表示デバイス用ドライバＩＣは、昨今の狭額縁仕様の表示デバイスに組み込み可能でなければならない。すなわち、多出力であって、小面積かつ十分な薄さを有することが求められている。   In particular, the display device driver IC must be able to be incorporated into a display device with a narrow frame specification. That is, it is required to have multiple outputs, a small area, and a sufficient thinness.

そのような条件を満たすため、チップの短辺を短くし、かつ外周長を大きくした、細長く薄いチップをフィルム状の基板に実装した半導体集積回路がある。しかし、チップを薄くすると、断面二次モーメントがより小さくなり、フィルムに実装した後の長辺方向に対する曲げ、すなわち、ドライバＩＣの回路集積面に作用する力に対して折損しやすく、極端に弱くなる。そのため、製品として可搬性・実装時の抗折強度等への配慮が必要とされている。   In order to satisfy such a condition, there is a semiconductor integrated circuit in which a long and thin chip having a shorter short side and a larger outer peripheral length is mounted on a film-like substrate. However, if the chip is made thinner, the moment of inertia of the cross section becomes smaller, and it is easy to break with respect to the bending in the long side direction after mounting on the film, that is, the force acting on the circuit integration surface of the driver IC, and extremely weak Become. For this reason, consideration is required for portability and bending strength at the time of mounting as a product.

フィルム状の基板の上に半導体チップを実装したＣＯＦ（Chiop on film）型の半導体集積回路が特許文献１乃至５に記載されている。図６は、特許文献１に記載の半導体集積回路１００を示す図である。図６に示すように、半導体素子１０２はテープキャリア１０１と接続され、テープキャリア１０１と半導体素子１０２の間は絶縁性樹脂１０３で封止されている。半導体素子１０２には突起電極１０５が複数設けられている。また、テープキャリア１０１は、半導体素子１０２を接続・搭載するためのものであり、配線パターン１０７、ソルダーレジスト１０８、絶縁テープ１０９を備えている。配線パターン１０７は、部分的に厚さが異なっている。具体的には、配線パターン１０７と半導体素子１０２とが接続されている部分（接続部）のみの厚さが、それ以外の部分（非接続部）の厚さよりも薄くなっている。これにより、接続部では配線パターン１０７をファインピッチ化することが可能となり、非接続部では配線パターン１０７の機械的強度を向上させることが可能となり、半導体装置１００の強度も向上させている。   Patent Documents 1 to 5 describe a COF (Chiop on film) type semiconductor integrated circuit in which a semiconductor chip is mounted on a film-like substrate. FIG. 6 is a diagram showing a semiconductor integrated circuit 100 described in Patent Document 1. In FIG. As shown in FIG. 6, the semiconductor element 102 is connected to the tape carrier 101, and the tape carrier 101 and the semiconductor element 102 are sealed with an insulating resin 103. The semiconductor element 102 is provided with a plurality of protruding electrodes 105. The tape carrier 101 is for connecting and mounting the semiconductor element 102 and includes a wiring pattern 107, a solder resist 108, and an insulating tape 109. The wiring pattern 107 is partially different in thickness. Specifically, the thickness of only the portion (connection portion) where the wiring pattern 107 and the semiconductor element 102 are connected is thinner than the thickness of the other portion (non-connection portion). As a result, the wiring pattern 107 can be fine pitched at the connection portion, and the mechanical strength of the wiring pattern 107 can be improved at the non-connection portion, and the strength of the semiconductor device 100 is also improved.

図７は、特許文献２に記載の半導体集積回路１１０を示す図である。半導体集積回路１１０は、ベースフィルム１１１と、半導体素子１１３と、配線パターンの半導体素子１１３との接続部１１４と、配線パターンの外部接続用コネクタ部１１５と、接着剤層１１６と、ポリイミド系絶縁フィルムからなる補補強用部材１１７と、バンプ１１８と、封止樹脂１１９とを有する。半導体集積回路１１０は、長尺のベースフィルム１の配線パターン形成面と反対の面に、厚さ１５〜４００μｍの膜厚のポリイミド系補強用部材１１７が設けられている。これにより、折り曲げ性を従来のＣＯＦと変えることなく、ＣＯＦ、ＴＣＰ（Tape carrier package）の配線パターンの外部接続用コネクタ部１１５又は半導体素子１１３との接続部等の累積ピッチの寸法精度及び強度を向上させている。   FIG. 7 is a diagram showing a semiconductor integrated circuit 110 described in Patent Document 2. In FIG. The semiconductor integrated circuit 110 includes a base film 111, a semiconductor element 113, a connection portion 114 of the wiring pattern semiconductor element 113, a wiring pattern external connection connector portion 115, an adhesive layer 116, and a polyimide insulating film. A reinforcing reinforcing member 117, a bump 118, and a sealing resin 119. The semiconductor integrated circuit 110 is provided with a polyimide reinforcing member 117 having a thickness of 15 to 400 μm on the surface opposite to the wiring pattern forming surface of the long base film 1. As a result, the dimensional accuracy and strength of the accumulated pitch of the external connection connector 115 of the wiring pattern of COF, TCP (Tape carrier package) or the connection with the semiconductor element 113 can be increased without changing the bendability to the conventional COF. It is improving.

図８は、特許文献３に記載の半導体集積回路１３０を示す図である。基板１３１は、テープ基材１３５の表面上に配線層が形成され、この配線層の各配線パターン１３６の両端にリード部１３７とランド部１３８が設けられ、このランド部１３８が裏面側に露出するようにテープ基材１３５に開口部１３９が形成されている。この基板１３１の表面上の配線パターン１３６は、リード部１３７を除いてソルダーレジスト１４０で覆われている。
チップ１３２は、表面上に、所定の集積回路に接続された電極部１４１が設けられ、基板１３１の表面上にフェイスダウンで搭載され、金（Ａｕ）バンプなどからなる電極部１４１が基板１３１のリード部１３７に電気的に接続される。ポリイミド樹脂などからなる封止材１３３は、チップ１３２の電極部１４１と基板１４１のリード部１３７との接続部分を封止する。すず（Ｓｎ）または鉛（Ｐｂ）や鉛フリーなどのはんだボールからなる外部端子１３４は、開口部１３９を通じてランド部１３８に電気的に接続される。また、テープ基材１３５からなる基板１３１の変形を防ぐために、基板１３１の表面上に補強枠１４２が貼り付けられている。 FIG. 8 is a diagram showing a semiconductor integrated circuit 130 described in Patent Document 3. As shown in FIG. In the substrate 131, a wiring layer is formed on the surface of the tape base 135, and a lead portion 137 and a land portion 138 are provided at both ends of each wiring pattern 136 of the wiring layer, and the land portion 138 is exposed on the back surface side. Thus, an opening 139 is formed in the tape base material 135. The wiring pattern 136 on the surface of the substrate 131 is covered with the solder resist 140 except for the lead portion 137.
The chip 132 is provided with an electrode portion 141 connected to a predetermined integrated circuit on the surface, mounted face down on the surface of the substrate 131, and the electrode portion 141 made of gold (Au) bumps or the like is provided on the substrate 131. The lead portion 137 is electrically connected. A sealing material 133 made of polyimide resin or the like seals a connection portion between the electrode portion 141 of the chip 132 and the lead portion 137 of the substrate 141. An external terminal 134 made of a solder ball such as tin (Sn), lead (Pb), or lead-free is electrically connected to the land portion 138 through the opening 139. In addition, in order to prevent deformation of the substrate 131 made of the tape base material 135, a reinforcing frame 142 is attached on the surface of the substrate 131.

これにより、チップの電極部と結線する基板のリード部がテープ基材上に固定されているので、リード曲がりによる不良を低減することが可能となり、リード曲がりによる不良を低減することができるので、半導体集積回路のパッドのピッチを狭くすることを可能としている。   Thereby, since the lead portion of the substrate connected to the electrode portion of the chip is fixed on the tape base material, it becomes possible to reduce defects due to lead bending, and it is possible to reduce defects due to lead bending. The pad pitch of the semiconductor integrated circuit can be narrowed.

図９は特許文献４に記載の半導体集積回路１５０の断面を示す図（Ａ）及び平面を示す図（Ｂ）である。半導体集積回路１５０は、フィルム回路１５１にその周辺部に延設されたグランドラインである配線膜１５３Ｅ、１５３ｅを設け、導電性を有する補強板１７５を用い、該グランドライン配線膜１５３Ｅおよび１５３ｅと、該導電性補強板１７５とをフィルム回路１５１周辺部で、例えば銅電ペースト１７６により電気的に接続する。必要に応じて、ヒートシンク１７７を半導体素子１５４及びフィルム回路１５１の裏面に接着する。その製造は、フィルム回路１５１に補強板１７５を接着し、その後、半導体素子１５４を補強板１７５で囲繞されたところに位置させてその各電極をフィルム回路１５１の半導体素子側端子とボンディングし、しかる後、補強板１７５、フィルム回路１５１及び半導体素子１５４の相互間を封止剤１７４で封止することにより行う。   9A and 9B are a cross-sectional view and a plan view of the semiconductor integrated circuit 150 described in Patent Document 4, respectively. The semiconductor integrated circuit 150 is provided with wiring films 153E and 153e, which are ground lines extending in the periphery of the film circuit 151, and using a conductive reinforcing plate 175, the ground line wiring films 153E and 153e, The conductive reinforcing plate 175 is electrically connected to the periphery of the film circuit 151 by, for example, a copper electric paste 176. A heat sink 177 is bonded to the back surfaces of the semiconductor element 154 and the film circuit 151 as necessary. In the manufacture, the reinforcing plate 175 is bonded to the film circuit 151, and then the semiconductor element 154 is positioned at a position surrounded by the reinforcing plate 175, and the respective electrodes are bonded to the semiconductor element side terminals of the film circuit 151. Thereafter, the reinforcing plate 175, the film circuit 151, and the semiconductor element 154 are sealed with a sealant 174.

これにより、半導体素子１５４を囲繞する補強板１７５をグランドラインとすることができ、延いては他と静電シールドしている。従って、半導体装置外部から半導体素子１５４内へのノイズの侵入を防止し、また、半導体素子１５４内部に発生したノイズが外部に放射されることを防止し、また、補強板１７５に接続されたグランドライン１５３ｅによって半導体素子内部におけるクロストークを防止している。   As a result, the reinforcing plate 175 surrounding the semiconductor element 154 can be used as a ground line, and thus electrostatically shielded from others. Therefore, the intrusion of noise from outside the semiconductor device into the semiconductor element 154 is prevented, noise generated inside the semiconductor element 154 is prevented from being radiated to the outside, and the ground connected to the reinforcing plate 175 is prevented. The line 153e prevents crosstalk inside the semiconductor element.

図１０は特許文献５に記載の半導体集積装置１８０を示す図である。特許文献５に記載の半導体集積回路１８０は、半導体集積回路１８０を実装するための支持フィルム１８１と、支持フィルム１８１上に形成されたインナーリード１８２と、支持フィルム１８１上のチップ搭載領域およびチップ封止領域の周囲に形成されたダム部１８３とを有する。この技術では、半導体チップ１８４の実装面から樹脂をポッティングすることにより、半導体チップ１８４の底面とフィルム１８１上に形成されたダム部１８３との間を樹脂１８５で封止し、またチップ１８４の側面とダム領域の側面とを樹脂１８５で封止する。ダム部を有するフィルム素材を用いることにより、インナーリードの曲がりを防止し、樹脂の吐出量を増加させることができると共に、チップ実装面への樹脂の流れ込み不足を防止することができる。   FIG. 10 is a diagram showing a semiconductor integrated device 180 described in Patent Document 5. In FIG. A semiconductor integrated circuit 180 described in Patent Document 5 includes a support film 181 for mounting the semiconductor integrated circuit 180, inner leads 182 formed on the support film 181, a chip mounting region on the support film 181, and a chip seal. And a dam portion 183 formed around the stop region. In this technique, resin is potted from the mounting surface of the semiconductor chip 184 to seal between the bottom surface of the semiconductor chip 184 and the dam portion 183 formed on the film 181 with the resin 185, and also to the side surface of the chip 184. And the side surface of the dam region are sealed with resin 185. By using a film material having a dam portion, it is possible to prevent the inner lead from being bent, to increase the discharge amount of the resin, and to prevent insufficient flow of the resin to the chip mounting surface.

特開２００８−１７７６１８号公報JP 2008-177618 A 特開２００１−０５３１０８号公報JP 2001-053108 A 特開２００２−１５８３０９号公報JP 2002-158309 A 特開平０９−２４６３１５号公報JP 09-246315 A 特開２００２−１１８１２７号公報JP 2002-118127 A

特許文献１に記載の半導体集積回路では、非接続部の配線層の厚さを接続部の配線層の厚さよりも厚くし、配線層の機械的強度を向上させている。しかしながら、接続部近傍の絶縁性樹脂の厚さを増しただけの構造では、特に、長辺両端を支点として基材側が凹、チップ表面側が凸になるような曲げを加えると、非常に折れやすく、十分な抗折強度を得られない。   In the semiconductor integrated circuit described in Patent Document 1, the thickness of the wiring layer in the non-connection portion is made larger than the thickness of the wiring layer in the connection portion, thereby improving the mechanical strength of the wiring layer. However, with a structure in which the thickness of the insulating resin in the vicinity of the connecting portion is increased, it is very easy to break, especially when bending is performed so that the base material side is concave and the chip surface side is convex with both ends of the long side as fulcrums. The sufficient bending strength cannot be obtained.

特許文献２に記載の半導体集積回路では、補強材１１７で曲げに対する強度を補強しているが、厚さ１５〜４００μｍの膜厚のポリイミド系補強用部材１１７だけでは、十分な抗折強度を得ることは難しい。   In the semiconductor integrated circuit described in Patent Document 2, the strength against bending is reinforced by the reinforcing material 117, but sufficient bending strength is obtained only by the polyimide-based reinforcing member 117 having a thickness of 15 to 400 μm. It ’s difficult.

特許文献３に記載の半導体集積回路では、チップ１３２、補強枠１４２の要素間が封止材１４０で満たされておらず、回路集積面に作用する力に対して、十分な抗折強度を有していない。   In the semiconductor integrated circuit described in Patent Document 3, the space between the elements of the chip 132 and the reinforcing frame 142 is not filled with the sealing material 140 and has a sufficient bending strength against the force acting on the circuit integrated surface. Not done.

特許文献４に記載の半導体集積回路では、半導体素子１５４、補強板１７５の要素間が封止剤１７４で満たされているが、補強板１７５が半導体素子１５４に比して大きく、表示デバイス用ドライバＩＣのような長尺チップのＦＰＣ（Flexible Printed Circuits）への実装には適さない。また、補強板１７５の断面形状が平たく、抗折強度を十分に向上できない。   In the semiconductor integrated circuit described in Patent Document 4, the space between the elements of the semiconductor element 154 and the reinforcing plate 175 is filled with the sealant 174. However, the reinforcing plate 175 is larger than the semiconductor element 154, and the display device driver. It is not suitable for mounting long chips such as ICs on FPC (Flexible Printed Circuits). Further, the cross-sectional shape of the reinforcing plate 175 is flat, and the bending strength cannot be sufficiently improved.

特許文献５に記載の半導体集積回路は、樹脂の回り込み不足を解消するためにダム領域を形成したものであり、曲げに対する強度を向上するための工夫はされていない。   The semiconductor integrated circuit described in Patent Document 5 is formed with a dam region in order to eliminate the shortage of the wraparound of the resin, and has not been devised to improve the strength against bending.

本発明にかかる半導体集積回路は、外部端子、矩形の半導体チップに接続するために設けられた内部端子および内部端子と外部端子とを接続する配線を有する屈曲可能なテープ状の基板と、基板に電気的に接続された半導体チップと、基板上の半導体チップの長手方向を補強する補強材とを有し、半導体チップと補強材とが樹脂により封止されたものである。これにより、半導体の長手方向への曲げに対する強度をより高めることができる。   A semiconductor integrated circuit according to the present invention includes a bendable tape-like substrate having external terminals, internal terminals provided for connection to a rectangular semiconductor chip, and wiring connecting the internal terminals and the external terminals, and the substrate. The semiconductor chip has an electrically connected semiconductor chip and a reinforcing material that reinforces the longitudinal direction of the semiconductor chip on the substrate, and the semiconductor chip and the reinforcing material are sealed with a resin. Thereby, the intensity | strength with respect to the bending to the longitudinal direction of a semiconductor can be raised more.

本発明によれば、テープまたはフィルム状の基板に半導体チップを実装し、かつ曲げに対する強度がより高い半導体集積回路及びその製造法を提供することができる。   According to the present invention, it is possible to provide a semiconductor integrated circuit having a semiconductor chip mounted on a tape or film-like substrate and having higher bending strength, and a method for manufacturing the same.

実施の形態１にかかる半導体集積回路の概要を示す図である。1 is a diagram showing an outline of a semiconductor integrated circuit according to a first embodiment; 実施の形態１にかかる半導体集積回路の断面を示す図である。1 is a diagram showing a cross section of a semiconductor integrated circuit according to a first exemplary embodiment; 実施の形態２にかかる半導体集積回路の概要を示す図である。FIG. 3 is a diagram showing an outline of a semiconductor integrated circuit according to a second embodiment; 実施の形態２にかかる半導体集積回路の断面を示す図である。FIG. 3 is a diagram showing a cross section of a semiconductor integrated circuit according to a second exemplary embodiment; 実施の形態３にかかる半導体集積回路の概要を示す図である。FIG. 4 is a diagram illustrating an outline of a semiconductor integrated circuit according to a third embodiment; 従来の半導体集積回路を示す図である。It is a figure which shows the conventional semiconductor integrated circuit. 従来の半導体集積回路を示す図である。It is a figure which shows the conventional semiconductor integrated circuit. 従来の半導体集積回路を示す図である。It is a figure which shows the conventional semiconductor integrated circuit. 従来の半導体集積回路を示す図である。It is a figure which shows the conventional semiconductor integrated circuit. 従来の半導体集積回路を示す図である。It is a figure which shows the conventional semiconductor integrated circuit.

実施の形態１
以下、図面を参照して本発明の実施の形態について説明する。本実施の形態にかかる半導体集積回路は、ＣＯＦ、又はＴＣＰと呼ばれる、テープ状、又はフィルム状のパッケージを有する半導体集積回路である。図１は、本実施の形態にかかる半導体集積回路１の概要を示す図である。半導体集積回路１は、テープ状の基板１０と、半導体チップ２０と、補強材３０とを有し、半導体チップ２０と補強材３０とは樹脂４０で封止されている。 Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. The semiconductor integrated circuit according to this embodiment is a semiconductor integrated circuit having a tape-like or film-like package called COF or TCP. FIG. 1 is a diagram showing an outline of a semiconductor integrated circuit 1 according to the present embodiment. The semiconductor integrated circuit 1 includes a tape-shaped substrate 10, a semiconductor chip 20, and a reinforcing material 30, and the semiconductor chip 20 and the reinforcing material 30 are sealed with a resin 40.

本実施の形態にかかるテープ状基板１０は屈曲可能なテープ状の基板であり、外部端子（不図示）と半導体チップ２０と接続するための内部端子（不図示）と、外部端子および内部端子を接続する配線５０とを有している。   The tape-like substrate 10 according to the present embodiment is a bendable tape-like substrate, and includes an external terminal (not shown), an internal terminal (not shown) for connecting the semiconductor chip 20, an external terminal and an internal terminal. And wiring 50 to be connected.

半導体チップ２０は、テープ状基板１０の内部端子と、半導体チップ２０の有するバンプ（不図示）を介して電気的に接続されている。   The semiconductor chip 20 is electrically connected to internal terminals of the tape-like substrate 10 via bumps (not shown) of the semiconductor chip 20.

補強材３０は、半導体チップ２０の全周に略平行な枠型であり、半導体チップ２０との間と、テープ状基板１０との間を樹脂４０により封止されている。   The reinforcing member 30 has a frame shape substantially parallel to the entire circumference of the semiconductor chip 20, and the space between the semiconductor chip 20 and the tape-shaped substrate 10 is sealed with a resin 40.

本実施の形態にかかるテープ状基板１０は、例えば、厚さ数百μｍのポリイミド製のものである。半導体集積回路１は、屈曲可能なテープ状基板１０の上に配置されているため、このテープ状基板１０の可撓性により、外部から半導体集積回路１を曲げようとする力が加わると、他の可撓性のない基板の半導体集積回路に比べ、チップが折れやすい。本実施の形態に係る半導体集積回路１は、テープ状基板１０に接続された半導体チップ２０を、補強材３０を樹脂４０で封止することにより、曲げに対する強度を高めることができる。   The tape-shaped substrate 10 according to the present embodiment is made of polyimide having a thickness of several hundreds of micrometers, for example. Since the semiconductor integrated circuit 1 is disposed on the bendable tape-like substrate 10, if a force for bending the semiconductor integrated circuit 1 is applied from the outside due to the flexibility of the tape-like substrate 10, Compared with a semiconductor integrated circuit having a non-flexible substrate, the chip is easily broken. The semiconductor integrated circuit 1 according to the present embodiment can increase the strength against bending by sealing the reinforcing material 30 with the resin 40 on the semiconductor chip 20 connected to the tape-like substrate 10.

本実施の形態に係る半導体集積回路１について、さらに説明する。本実施の形態に係る半導体集積回路１は、テープ状基板１０に半導体チップ２０を配置し、高周波・超音波等で、テープ状基板１０の内部端子と半導体チップ２０のバンプとを電気的・機械的に接続する。次に、半導体チップ２０の全周に平行な枠構造の補強材３０を置き、半導体チップ２０と補強材３０との間に、半導体チップ２０の略垂直方向から毛細管現象等を利用して樹脂４０を注入することにより、半導体チップ２０と前記補強材との間を前記樹脂で封止する。そして、熱を加えて樹脂４０を硬化させることにより、補強材３０をテープ状基板１０に固定する。   The semiconductor integrated circuit 1 according to the present embodiment will be further described. In the semiconductor integrated circuit 1 according to the present embodiment, the semiconductor chip 20 is disposed on the tape-like substrate 10, and the internal terminals of the tape-like substrate 10 and the bumps of the semiconductor chip 20 are electrically and mechanically connected by high frequency, ultrasonic waves, or the like. Connect. Next, a reinforcing member 30 having a frame structure parallel to the entire circumference of the semiconductor chip 20 is placed, and a resin 40 is utilized between the semiconductor chip 20 and the reinforcing member 30 using a capillary phenomenon or the like from a substantially vertical direction of the semiconductor chip 20. Is injected between the semiconductor chip 20 and the reinforcing material with the resin. Then, the reinforcing material 30 is fixed to the tape-like substrate 10 by applying heat to cure the resin 40.

ここで、半導体チップ２０と、補強材３０の隙間は略０．０１乃至０．５ｍｍであることが望ましい。半導体チップ２０と、補強材３０の隙間を略０．０１乃至０．５ｍｍとすることにより、毛細管現象が生じる。したがって、補強材３０と半導体チップ２０の間に樹脂４０を注入すれば、毛細管現象により補強材３０がセルフアラインメントされ、補強材３０とテープ状基板１０と半導体チップ半導体チップ２０とそれぞれの間を樹脂４０で封止する構造となる。   Here, the gap between the semiconductor chip 20 and the reinforcing member 30 is preferably about 0.01 to 0.5 mm. By setting the gap between the semiconductor chip 20 and the reinforcing member 30 to approximately 0.01 to 0.5 mm, a capillary phenomenon occurs. Therefore, if the resin 40 is injected between the reinforcing material 30 and the semiconductor chip 20, the reinforcing material 30 is self-aligned by capillary action, and the resin between the reinforcing material 30, the tape-like substrate 10, and the semiconductor chip semiconductor chip 20 is provided. It becomes the structure sealed with 40.

ここで、半導体チップ２０と補強材３０の隙間は、樹脂４０の粘性により最適な間隔を決定する。一般に、半導体チップ２０をテープ状基板１０に装着した際の半導体チップ２０とテープ状基板１０との隙間が１０μｍ程度の値になる。この隙間を埋める特性を持った樹脂４０を使用する必要があるため、半導体チップ２０と、補強材３０の隙間は略０．０１乃至０．５ｍｍ程度の値になることが望ましい。しかしここでの略０．０１乃至０．５ｍｍという数値は、は補強材３０とテープ状基板１０と半導体チップ半導体チップ２０の表面の材料及び加工方法、又は樹脂４０のぬれ性により変更することができる。   Here, the gap between the semiconductor chip 20 and the reinforcing member 30 determines an optimum interval depending on the viscosity of the resin 40. Generally, the gap between the semiconductor chip 20 and the tape-like substrate 10 when the semiconductor chip 20 is mounted on the tape-like substrate 10 has a value of about 10 μm. Since it is necessary to use the resin 40 having the characteristic of filling the gap, it is desirable that the gap between the semiconductor chip 20 and the reinforcing material 30 has a value of about 0.01 to 0.5 mm. However, the numerical value of about 0.01 to 0.5 mm here can be changed depending on the surface material and processing method of the reinforcing material 30, the tape-like substrate 10 and the semiconductor chip semiconductor chip 20, or the wettability of the resin 40. it can.

樹脂４０の材質は、−５０℃乃至１５０℃程度の温度範囲で、熱膨張係数が半導体チップ２０の材質であるシリコンと比較的近いものが望ましい。更に、半導体チップ２０と、補強材３０とを封止するため、樹脂４０はシリコンと補強材３０に対してぬれ性がよいものであるとするとよい。   The material of the resin 40 is desirably a material having a thermal expansion coefficient that is relatively close to that of silicon that is the material of the semiconductor chip 20 in a temperature range of about −50 ° C. to 150 ° C. Furthermore, in order to seal the semiconductor chip 20 and the reinforcing material 30, it is preferable that the resin 40 has good wettability with respect to silicon and the reinforcing material 30.

樹脂４０のぬれ性を調整することにより、フィレットが自然に形成され、応力集中を避けることができる。また、ぬれ性を調整することにより、補強材３０とテープ状基板１０と半導体チップ２０を一体化させることができる。ぬれ性は、補強材３０とテープ状基板１０の表面の粗さ、表面のコーティング、及び樹脂４０の材料で調整できる。   By adjusting the wettability of the resin 40, a fillet is formed naturally and stress concentration can be avoided. Further, by adjusting the wettability, the reinforcing material 30, the tape-like substrate 10, and the semiconductor chip 20 can be integrated. The wettability can be adjusted by the surface roughness of the reinforcing material 30 and the tape-like substrate 10, the surface coating, and the material of the resin 40.

図２は、図１に示す半導体集積回路１を、図１のＡ−Ａ′線における断面図である。図２（ａ）乃至（ｃ）は、本実施の形態における半導体集積回路１の第１乃至第３例を示し、それぞれテープ状基板１１〜１３、半導体チップ２１〜２３、補強材３１〜３３及び樹脂４１〜４４を有している。   2 is a cross-sectional view of the semiconductor integrated circuit 1 shown in FIG. 1 taken along the line AA ′ of FIG. 2A to 2C show first to third examples of the semiconductor integrated circuit 1 according to the present embodiment. The tape-like substrates 11 to 13, the semiconductor chips 21 to 23, the reinforcing members 31 to 33, and It has resin 41-44.

図２（ａ）は、補強材３１の断面が矩形ものである半導体集積回路１を示す図である。
図２（ｂ）は、補強材３２の断面が配線基板１２を底辺とする略三角形である半導体集積回路１を示す図である。図２（ｃ）は、補強材３３の断面が、テープ状基板１３を底面とする略台形である半導体集積回路１を示す図である。 FIG. 2A is a diagram showing the semiconductor integrated circuit 1 in which the reinforcing member 31 has a rectangular cross section.
FIG. 2B is a diagram showing the semiconductor integrated circuit 1 in which the cross section of the reinforcing member 32 is a substantially triangular shape with the wiring board 12 as a base. FIG. 2C is a diagram showing the semiconductor integrated circuit 1 in which the cross section of the reinforcing member 33 is substantially trapezoidal with the tape-like substrate 13 as a bottom surface.

半導体集積回路１は、それぞれテープ状基板１１〜１３の上に半導体チップ２１〜２３を接続した後、補強材３１〜３３を置き、毛細管現象を使用して樹脂４１〜４３により封止する。そのため、図２（ａ）乃至（ｃ）のように、半導体チップ２１〜２３とテープ状基板１１〜１３の間、および半導体チップ２１〜２３とテープ状基板１１〜１３のそれぞれの隙間を樹脂４１〜４３で封止した構造になる。   In the semiconductor integrated circuit 1, the semiconductor chips 21 to 23 are connected to the tape-like substrates 11 to 13, respectively, and then reinforcing members 31 to 33 are placed and sealed with the resins 41 to 43 using a capillary phenomenon. Therefore, as shown in FIGS. 2A to 2C, the gaps between the semiconductor chips 21 to 23 and the tape-like substrates 11 to 13 and between the semiconductor chips 21 to 23 and the tape-like substrates 11 to 13 are made of resin 41. It becomes the structure sealed with ~ 43.

ここで、補強材３１〜３３の構造について説明する。図２（ｂ）に示すように、ここでは補強材３１〜３３の高さをｈ、補強材３１〜３３の断面の幅をｔとする。補強材３１〜３３の高さｈは、半導体チップと同じであってもよいが、半導体チップ２１〜２３の高さ以上であると更に望ましい。補強材３０は、少ない枠材で断面係数を効率的に増すために、曲げられる方向に厚みがある方が有利であるからである。補強材３１〜３３は、樹脂４１〜４４と一体化するために、半導体集積回路１を曲げようとする際、補強材３１〜３３の中央部分は外に広がりにくくなっている。よって、補強材３１〜３３の断面の幅ｔが小さくても曲げに対する強度を強くできる。   Here, the structure of the reinforcing members 31 to 33 will be described. As shown in FIG. 2B, here, the height of the reinforcing members 31 to 33 is h, and the width of the cross section of the reinforcing members 31 to 33 is t. The height h of the reinforcing members 31 to 33 may be the same as that of the semiconductor chip, but is more preferably equal to or higher than the height of the semiconductor chips 21 to 23. This is because it is advantageous that the reinforcing member 30 has a thickness in the bending direction in order to efficiently increase the section modulus with a small number of frame members. Since the reinforcing members 31 to 33 are integrated with the resins 41 to 44, when the semiconductor integrated circuit 1 is to be bent, the central portions of the reinforcing members 31 to 33 are difficult to spread outward. Therefore, even if the cross section width t of the reinforcing members 31 to 33 is small, the strength against bending can be increased.

図２（ｂ）示すように、補強材３０の断面形状が、テープ状基板１０に対して垂直方向に高く、補強材３０の断面の幅ｔが補強材３０の高さｈより小さくなる。これにより、半導体チップ２０の実装構造の長尺方向の曲げ剛性を、チップの寸法を大きくせず、より効果的に高めている。   As shown in FIG. 2B, the cross-sectional shape of the reinforcing material 30 is high in the direction perpendicular to the tape-like substrate 10, and the width t of the cross-section of the reinforcing material 30 is smaller than the height h of the reinforcing material 30. Thereby, the bending rigidity in the longitudinal direction of the mounting structure of the semiconductor chip 20 is increased more effectively without increasing the size of the chip.

また、補強材３１〜３３の断面の高さは半導体チップ２１〜２３の高さより高いことが望ましいが、樹脂４１〜４３から飛び出す分の高さが大きすぎると、パッケージが大きくなってしまうので、適宜調整するようにすることが望ましい。   In addition, the height of the cross section of the reinforcing members 31 to 33 is preferably higher than the height of the semiconductor chips 21 to 23, but if the height of the portion protruding from the resins 41 to 43 is too large, the package becomes large. It is desirable to adjust appropriately.

補強材３１〜３３は、導電物であっても隙間に樹脂が入り込んで絶縁できればよい。しかし、半導体チップ２１〜２３と補強材３１〜３３の熱膨張係数が異なると、熱応力が発生するので、補強材３１〜３３は、シリコンと比較的近い熱膨張係数を持ち、強度の強いものが望ましい。   Even if the reinforcing members 31 to 33 are conductive materials, it is sufficient that the resin enters the gap and can be insulated. However, if the thermal expansion coefficients of the semiconductor chips 21 to 23 and the reinforcing materials 31 to 33 are different, thermal stress is generated. Therefore, the reinforcing materials 31 to 33 have a thermal expansion coefficient relatively close to that of silicon and have a high strength. Is desirable.

また、補強材３１〜３３は、絶縁体かまたは表面を絶縁加工したものであることが望ましい。更に詳しくは、補強材３１〜３３は、セラミックスか又は表面を絶縁加工されたステンレス材料とすることが望ましい。これにより、パッケージの強度および熱の放熱性を高めることができる。   Moreover, it is desirable that the reinforcing members 31 to 33 are insulators or those whose surfaces are insulated. More specifically, it is desirable that the reinforcing members 31 to 33 are ceramics or a stainless material whose surface is insulated. Thereby, the intensity | strength of a package and the heat dissipation of a heat | fever can be improved.

本実施の形態にかかる半導体集積回路１は、補強材３０により曲げに対する強度を強化し、さらに、樹脂４０が補強材３０と半導体チップ２０を一体化させることによって更に曲げに対する強度を大きくすることができる。これにより、半導体チップ２０長手方向に曲げ応力が加わった際、抗折強度を増すことができる。   In the semiconductor integrated circuit 1 according to the present embodiment, the strength against bending is enhanced by the reinforcing material 30, and further, the resin 40 further increases the strength against bending by integrating the reinforcing material 30 and the semiconductor chip 20. it can. Thereby, the bending strength can be increased when a bending stress is applied in the longitudinal direction of the semiconductor chip 20.

言い換えれば、補強材３０の断面形状自体の曲げ剛性、補強材３０の内外両側面に充填された樹脂４０の曲げ剛性、及び補強材３０の内外両側面と樹脂４０との接着による曲げ剛性により、効果的に抗折強度を高めている。   In other words, due to the bending rigidity of the cross-sectional shape of the reinforcing material 30 itself, the bending rigidity of the resin 40 filled on both the inner and outer side surfaces of the reinforcing material 30, and the bending rigidity due to the adhesion between the inner and outer side surfaces of the reinforcing material 30 and the resin 40, It effectively increases the bending strength.

よって、本実施の形態によれば、テープ状基板１０、半導体チップ２０および補強材３０を樹脂４０で封止することにより、曲げに対する強度がより高い半導体集積回路を提供することができる。   Therefore, according to the present embodiment, by sealing the tape-shaped substrate 10, the semiconductor chip 20, and the reinforcing material 30 with the resin 40, it is possible to provide a semiconductor integrated circuit having higher bending strength.

実施の形態２
以下、図面を用いて本実施の形態について説明する。なお、実施の形態１と同一の構成要素は同一の符号を付し、その詳細な説明は省略する。 Embodiment 2
Hereinafter, the present embodiment will be described with reference to the drawings. In addition, the same component as Embodiment 1 attaches the same code | symbol, and the detailed description is abbreviate | omitted.

図３は、本実施の形態にかかる半導体集積回路２の概要を示す図である。本実施の形態にかかる半導体集積回路２は、テープ状基板１０と、半導体チップ２０と、補強材３０と、樹脂４０と、配線５０と、補強材６０とを有する。   FIG. 3 is a diagram showing an outline of the semiconductor integrated circuit 2 according to the present embodiment. The semiconductor integrated circuit 2 according to the present embodiment includes a tape-like substrate 10, a semiconductor chip 20, a reinforcing material 30, a resin 40, a wiring 50, and a reinforcing material 60.

半導体集積回路２は、外部端子（不図示）、半導体チップ２０に接続するために設けられた内部端子（不図示）および内部端子（不図示）と外部端子（不図示）とを接続する配線５０を有する屈曲可能なテープ状の基板１０に、矩形の半導体チップ２０を電気的に接続し、半導体チップ２０の全周に平行な枠構造の補強材６０を設け、半導体チップ２０と補強材６０との間に、半導体チップ２０の略垂直方向から樹脂を注入することにより、半導体チップ２０と補強材６０との間を樹脂６０で封止してテープ状基板１０に固定する。   The semiconductor integrated circuit 2 includes an external terminal (not shown), an internal terminal (not shown) provided for connection to the semiconductor chip 20, and a wiring 50 that connects the internal terminal (not shown) and the external terminal (not shown). The rectangular semiconductor chip 20 is electrically connected to a bendable tape-shaped substrate 10 having a frame structure, and a reinforcing member 60 having a frame structure parallel to the entire circumference of the semiconductor chip 20 is provided. In between, by injecting resin from the substantially vertical direction of the semiconductor chip 20, the space between the semiconductor chip 20 and the reinforcing material 60 is sealed with the resin 60 and fixed to the tape-like substrate 10.

半導体集積回路２は、まずテープ状基板１０に、補強材６０を形成する。補強材６０は強度が確保されればどのようなものでもよいが、配線５０どうしをショートしないように、テープ状基板１０との接続面には絶縁性の材質を使用する。補強材６０の形状は補強材３０と同様に半導体チップ２０の全周に略平行な枠型であるが、テープ状基板１０に補強材３０を固定する。そのため、テープ状基板１０を含めて、半導体チップ２０が入る部分はバスタブ形状となる。その後樹脂４０を注入するため、補強材３０により半導体チップ２０の周囲を補強材３０で囲む構造となり、樹脂４０の拡がりを抑えることができる。   In the semiconductor integrated circuit 2, first, the reinforcing material 60 is formed on the tape-like substrate 10. The reinforcing member 60 may be any material as long as strength is ensured, but an insulating material is used for the connection surface with the tape-like substrate 10 so as not to short-circuit the wirings 50. The shape of the reinforcing member 60 is a frame shape that is substantially parallel to the entire circumference of the semiconductor chip 20, as with the reinforcing member 30, but the reinforcing member 30 is fixed to the tape-like substrate 10. Therefore, the part into which the semiconductor chip 20 enters including the tape-like substrate 10 has a bathtub shape. Thereafter, since the resin 40 is injected, the reinforcing material 30 surrounds the semiconductor chip 20 with the reinforcing material 30, and the spread of the resin 40 can be suppressed.

本実施の形態について、さらに説明する。図４は、図３に示す半導体集積回路２を、図１のＢ−Ｂ′線における断面図である。図４（ａ）乃至（ｃ）は、それぞれテープ状基板１１〜１３、半導体チップ２１〜２３、補強材６１〜６３及び樹脂４１〜４４を有している。図４（ａ）は、補強材６１の断面が略矩形ものである半導体集積回路２を示す図である。図４（ｂ）は、補強材６２の断面が配線基板１２を底辺とする略三角形である半導体集積回路２を示す図である。図４（ｃ）は、補強材６３の断面が、テープ状基板１３を底面とする略台形である半導体集積回路３を示す図である。半導体集積回路１は、補強材３０を、半導体チップ２０を設置した後から置き、テープ状基板１０との接着は樹脂４０により行うため、補強材３０の下側にも樹脂４０が存在する。それに対し、本実施の形態における半導体集積回路２は、図３の補強材６０は半導体チップ２０の実装前にテープ状基板１０に接着してあるので、樹脂４０は補強材６０と半導体チップ２０の間にのみ存在し、補強材６０とテープ状基板１０の間に回り込むことはない。   This embodiment will be further described. 4 is a cross-sectional view of the semiconductor integrated circuit 2 shown in FIG. 3 taken along the line BB ′ of FIG. 4A to 4C have tape-shaped substrates 11 to 13, semiconductor chips 21 to 23, reinforcing materials 61 to 63, and resins 41 to 44, respectively. FIG. 4A is a diagram showing the semiconductor integrated circuit 2 in which the reinforcing member 61 has a substantially rectangular cross section. FIG. 4B is a diagram showing the semiconductor integrated circuit 2 in which the cross section of the reinforcing material 62 is a substantially triangular shape with the wiring board 12 as a base. FIG. 4C is a diagram showing the semiconductor integrated circuit 3 in which the cross section of the reinforcing member 63 is a substantially trapezoidal shape with the tape-like substrate 13 as a bottom surface. In the semiconductor integrated circuit 1, the reinforcing material 30 is placed after the semiconductor chip 20 is installed, and the resin 40 is adhered to the tape-like substrate 10 by the resin 40. On the other hand, in the semiconductor integrated circuit 2 according to the present embodiment, since the reinforcing material 60 in FIG. It exists only between them, and does not wrap around between the reinforcing material 60 and the tape-like substrate 10.

これにより、樹脂４０が周りに広がることを抑えつつ、曲げに対する強度を高めた半導体集積回路を製造することができる。   As a result, it is possible to manufacture a semiconductor integrated circuit with increased strength against bending while preventing the resin 40 from spreading around.

実施の形態３
以下、図面を用いて本実施の形態について説明する。なお、実施の形態１及び２と同一の構成要素は同一の符号を付し、その詳細な説明は省略する。 Embodiment 3
Hereinafter, the present embodiment will be described with reference to the drawings. In addition, the same component as Embodiment 1 and 2 attaches | subjects the same code | symbol, and abbreviate | omits the detailed description.

図５は本実施の形態にかかる半導体集積回路３を示す図である。本実施の形態にかかる半導体集積回路は、テープ状基板１０と、半導体チップ２０と、補強材３０と、配線５０と、補強材７０とを有する。   FIG. 5 is a diagram showing a semiconductor integrated circuit 3 according to the present embodiment. The semiconductor integrated circuit according to the present embodiment includes a tape-like substrate 10, a semiconductor chip 20, a reinforcing material 30, a wiring 50, and a reinforcing material 70.

半導体集積回路３は、半導体集積回路１と比べ、半導体チップ２０の長辺方向に、略平行な板状の補強材７０を有する点が異なる。補強材７０はの長さは半導体チップ２０の長辺以上である。なお、断面の形状、材料などについては他の実施の形態における補強材と同一である。   The semiconductor integrated circuit 3 is different from the semiconductor integrated circuit 1 in that the semiconductor integrated circuit 3 includes a substantially parallel plate-shaped reinforcing material 70 in the long side direction of the semiconductor chip 20. The length of the reinforcing material 70 is longer than the long side of the semiconductor chip 20. The cross-sectional shape, material, and the like are the same as the reinforcing material in the other embodiments.

半導体集積回路３は、半導体集積回路２と同様に、テープ状基板１０に補強材７０を固定した後に樹脂４０を注入する。その他の点では半導体集積回路２と同様である。   Similar to the semiconductor integrated circuit 2, the semiconductor integrated circuit 3 injects the resin 40 after fixing the reinforcing material 70 to the tape-like substrate 10. The other points are the same as those of the semiconductor integrated circuit 2.

半導体集積回路３では、より少ない補強材７０で半導体チップ２０を補強することができる。   In the semiconductor integrated circuit 3, the semiconductor chip 20 can be reinforced with less reinforcing material 70.

本発明によれば、チップ厚を薄くしつつ、大幅な重量増無しにＣＯＦ,ＴＡＢパッケージ製品の抗折強度（長尺方向の曲げ剛性）を確保できる。また、実装工数増が少なく、従来設備がほぼ使用できる。更に、パッケージ全体として熱容量が増加し、材質を選ぶことで放熱性も期待できる。   According to the present invention, the bending strength (longitudinal bending rigidity) of the COF and TAB packaged products can be secured without reducing the chip thickness while reducing the chip thickness. In addition, the number of mounting steps is small and conventional equipment can be used almost. Furthermore, the heat capacity of the entire package increases, and heat dissipation can be expected by selecting the material.

なお、本発明は上記実施の形態に限られたものではなく、趣旨を逸脱しない範囲で適宜変更することが可能である。   Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

１〜３ 半導体集積回路
１０〜１３ テープ状基板
２０〜２３ 半導体チップ
３０〜３３ 補強材
４０〜４３ 樹脂
５０ 配線
６０〜６３ 補強材
７０ 補強材
１００ 半導体集積回路
１０１ テープキャリア
１０２ 半導体素子
１０３ 絶縁性樹脂
１０５ 突起電極
１０７ 配線パターン
１０８ ソルダーレジスト
１０９ 絶縁テープ
１１０ 半導体集積回路
１１１ ベースフィルム
１１３ 半導体素子
１１４ 配線パターン半導体素子との接続部
１１５ 配線パターンの外部接続用コネクタ部
１１６ 接着剤層
１１７ 補補強用部材
１１８ バンプ
１１９ 封止樹脂
１３０ 半導体集積回路
１３１ 基板
１３２ チップ
１３３ 封止材
１３４ 外部端子
１３５ テープ基材
１３６ 配線パターン
１３７ リード部
１３８ ランド部
１３９ 開口部
１４０ ソルダーレジスト
１４１ 電極部
１４２ 補強枠
１５０ 半導体集積回路
１５１ フィルム回路
１５３Ｅ グランドライン
１５３ｅ グランドライン
１７４ 封止剤
１７５ 導電性補強板
１７６ 銅電ペースト
１７７ ヒートシンク
１８０ 半導体集積回路
１８１ 支持フィルム
１８２ インナーリード
１８３ ダム部
１８４ 半導体チップ
１８５ 樹脂 DESCRIPTION OF SYMBOLS 1-3 Semiconductor integrated circuit 10-13 Tape-like board | substrate 20-23 Semiconductor chip 30-33 Reinforcement material 40-43 Resin 50 Wiring 60-63 Reinforcement material 70 Reinforcement material 100 Semiconductor integrated circuit 101 Tape carrier 102 Semiconductor element 103 Insulating resin DESCRIPTION OF SYMBOLS 105 Protrusion electrode 107 Wiring pattern 108 Solder resist 109 Insulating tape 110 Semiconductor integrated circuit 111 Base film 113 Semiconductor element 114 Connection part with wiring pattern semiconductor element 115 Connector part for external connection of wiring pattern 116 Adhesive layer 117 Supplementary reinforcement member 118 Bump 119 Sealing resin 130 Semiconductor integrated circuit 131 Substrate 132 Chip 133 Sealing material 134 External terminal 135 Tape substrate 136 Wiring pattern 137 Lead portion 138 Land portion 139 Opening portion 140 Solder Gist 141 Electrode 142 Reinforcing frame 150 Semiconductor integrated circuit 151 Film circuit 153E Ground line 153e Ground line 174 Sealant 175 Conductive reinforcing plate 176 Copper paste 177 Heat sink 180 Semiconductor integrated circuit 181 Support film 182 Inner lead 183 Dam part 184 Semiconductor Chip 185 resin

Claims (12)

外部端子、矩形の半導体チップに接続するために設けられた内部端子および前記内部端子と前記外部端子とを接続する配線を有する屈曲可能なテープ状の基板と、
前記基板に電気的に接続された半導体チップと、
前記基板上の前記半導体チップの長手方向を補強する補強材とを有し、
前記半導体チップと前記補強材とが樹脂により封止された半導体集積回路。 A bendable tape-like substrate having external terminals, internal terminals provided for connection to a rectangular semiconductor chip, and wiring connecting the internal terminals and the external terminals;
A semiconductor chip electrically connected to the substrate;
A reinforcing material for reinforcing the longitudinal direction of the semiconductor chip on the substrate;
A semiconductor integrated circuit in which the semiconductor chip and the reinforcing material are sealed with a resin. 前記補強材は、前記半導体チップの全周に略平行な枠型である請求項１記載の半導体集積回路   2. The semiconductor integrated circuit according to claim 1, wherein the reinforcing material is a frame shape substantially parallel to the entire circumference of the semiconductor chip. 前記補強材は、前記半導体チップの長手方向に略平行な板状であり、前記補強材の長手方向の長さは前記半導体チップの長辺以上である請求項１又は２記載の半導体集積回路。   3. The semiconductor integrated circuit according to claim 1, wherein the reinforcing material has a plate shape substantially parallel to the longitudinal direction of the semiconductor chip, and the length of the reinforcing material in the longitudinal direction is equal to or longer than the long side of the semiconductor chip. 前記補強材を当該前記補強材の長手方向と直交する断面の形状は、矩形または前記配線基板を底辺とする略三角形または略台形である請求項１乃至３のいずれか１項記載の半導体集積回路。   4. The semiconductor integrated circuit according to claim 1, wherein a shape of a cross section of the reinforcing member perpendicular to a longitudinal direction of the reinforcing member is a rectangle or a substantially triangular shape or a substantially trapezoidal shape having the wiring substrate as a base. 5. . 前記補強材の高さは、前記半導体チップの高さ以上である請求項１乃至４のいずれか１項記載の半導体集積回路。   The semiconductor integrated circuit according to claim 1, wherein a height of the reinforcing material is equal to or higher than a height of the semiconductor chip. 前記補強材は、当該補強材の高さ及び前記断面の底辺の長さの関係は、
補強材の高さ＞補強材の断面の底辺の長さ
である請求項１乃至５のいずれか１項記載の半導体集積回路。 The reinforcing material has a relationship between the height of the reinforcing material and the length of the bottom of the cross section.
6. The semiconductor integrated circuit according to claim 1, wherein the height of the reinforcing material> the length of the bottom of the cross section of the reinforcing material. 前記補強材は、絶縁体または表面を絶縁加工したものである請求項１乃至５のいずれか１項記載の半導体集積回路。   The semiconductor integrated circuit according to claim 1, wherein the reinforcing material is an insulator or a surface whose surface is insulated. 前記補強材は、セラミックス又は表面を絶縁加工されたステンレスからなる請求項１乃至６のいずれか１項記載の半導体集積回路。   The semiconductor integrated circuit according to claim 1, wherein the reinforcing material is made of ceramics or stainless steel whose surface is insulated. 前記補強材と前記半導体チップとの隙間は０．０１乃至０．５ｍｍである請求項１乃至８のいずれか１項記載の半導体集積回路。   The semiconductor integrated circuit according to claim 1, wherein a gap between the reinforcing material and the semiconductor chip is 0.01 to 0.5 mm. 外部端子、半導体チップに接続するために設けられた内部端子および前記内部端子と前記外部端子とを接続する配線を有する屈曲可能なテープ状の基板に、矩形の半導体チップを電気的に接続し、
前記半導体チップの全周に平行な枠構造の補強材を設け、
前記半導体チップと前記補強材との間に、前記半導体チップの略垂直方向から樹脂を注入することにより、前記半導体チップと前記補強材との間を前記樹脂で封止して前記基板に固定する半導体集積回路の製造方法。 A rectangular semiconductor chip is electrically connected to a bendable tape-like substrate having an external terminal, an internal terminal provided for connection to the semiconductor chip, and a wiring connecting the internal terminal and the external terminal,
A reinforcing member having a frame structure parallel to the entire circumference of the semiconductor chip is provided,
By injecting resin between the semiconductor chip and the reinforcing material from a substantially vertical direction of the semiconductor chip, the space between the semiconductor chip and the reinforcing material is sealed with the resin and fixed to the substrate. A method for manufacturing a semiconductor integrated circuit. 前記補強材と前記半導体チップとの隙間は略０．０１乃至０．５ｍｍであって、
前記補強材と前記半導体の間に前記樹脂を注入し、
毛細管現象により前記枠構造がセルフアラインメントされ、前記枠構造と前記基板と前記半導体チップとの間を前記樹脂で封止する請求項１０記載の半導体集積回路の製造方法。 The gap between the reinforcing material and the semiconductor chip is approximately 0.01 to 0.5 mm,
Injecting the resin between the reinforcing material and the semiconductor,
The method for manufacturing a semiconductor integrated circuit according to claim 10, wherein the frame structure is self-aligned by a capillary phenomenon, and the space between the frame structure, the substrate, and the semiconductor chip is sealed with the resin. 外部端子、半導体チップに接続するために設けられた内部端子および前記内部端子と前記外部端子とを接続する配線とを有する屈曲可能なテープ状の基板に、矩形の半導体チップを電気的に接続した半導体集積回路の製造方法であって、
前記基板は、当該基板に固定された前記半導体チップの長辺又は全周に平行な補強材を有し、
前記半導体チップと前記補強材との間に樹脂を注入することにより、前記半導体チップと前記補強材との間を前記樹脂で封止する半導体集積回路の製造方法。 A rectangular semiconductor chip was electrically connected to a bendable tape-like substrate having external terminals, internal terminals provided for connection to the semiconductor chip, and wiring connecting the internal terminals and the external terminals. A method for manufacturing a semiconductor integrated circuit, comprising:
The substrate has a reinforcing material parallel to the long side or the entire circumference of the semiconductor chip fixed to the substrate,
A method of manufacturing a semiconductor integrated circuit, wherein a resin is injected between the semiconductor chip and the reinforcing material to seal between the semiconductor chip and the reinforcing material with the resin.
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