JP2011176011A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inexpensively prevent the deterioration of a timing reliability, which is caused by the influence of stress to be added from a pad to a chip internal element, in a semiconductor integrated circuit device having a flip-chip structure. <P>SOLUTION: The layout of the structure and arrangement position, etc., of pads 102 in the outer peripheral strings of a semiconductor chip 101, which receive the influence of the stress, is previously made so that the operation trouble of an LSI due to the influence of the stress does not easily occur concerning the semiconductor integrated circuit device having the flip-chip structure. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device having a flip chip structure.

  With the recent miniaturization of semiconductor manufacturing technology, the number of transistors constituting an LSI is steadily increasing. In addition, as the number of LSI components increases, there is a concern about an increase in chip area, and suppressing the chip area is one of the most important issues from a cost standpoint. On the other hand, a wire bonding method has been generally used as a connection method between an LSI and a package. When this mounting form is used, the LSI has a structure in which IO cells are arranged around the chip. A problem when this structure is used is that the chip area increases depending on the number of IO cells. Furthermore, when the wire bonding method as described above is used, it is necessary to crimp the wire to the IO cell, and the IO cell is made to have a certain size or more so that the IO cell is not destroyed by this crimping. Need to keep. Moreover, since a certain area is required for crimping, there is a limitation that the IO cell cannot be physically reduced. For these reasons, in a fine process, if the number of IO cells in a chip increases, the chip area is determined by the IO cells. For this reason, even if an area reduction method using an internal logic arrangement / synthesis method is used, the chip area as a whole cannot be reduced.

  A flip chip structure is used as a solution to the problems described above.

  As shown in FIG. 18, according to the planar structure of a chip (LSI) 21 used for flip chip connection, a plurality of pads 12 are arranged on the entire surface of the chip 21, and IO cells 11 are arranged on the periphery of the chip 21. Has been. The IO cell 11 and the pad 12 are electrically connected via a wiring 13 called a rewiring.

  As shown in FIG. 19, according to the cross-sectional structure in which the chip 21 shown in FIG. 18 is flip-chip connected to the package 22, the chip 21 is mounted face down on the surface of the package 22 and the package 22 through the pad 12. And electrically connected. The chip 21 is covered with a resin 23 on the surface of the package 22, and an external electrode 24 is provided on the back surface of the package 22. As described above, by using the flip chip structure, it is not necessary to wire the IO cell, so that the IO cell can be formed smaller than the conventional structure. Further, it is not necessary to arrange the IO cell itself at the peripheral portion of the chip 21, that is, around the LSI. Therefore, it is possible to solve the problem in the wire bonding method, that is, the problem that the IO cell determines the area of the LSI. In the following description, the pads arranged on the entire surface of the chip by the flip chip method are particularly referred to as area pads.

  By the way, as a problem to be dealt with when using the flip chip method, there is an influence of stress applied to an LSI internal element from an area pad arranged on an LSI (chip) surface. Specifically, since external stress is applied to the LSI through the area pad, a portion where stress is applied and a portion where stress is not applied are mixed on the LSI corresponding to the arrangement of the area pad. Further, with respect to the stress distribution in the chip surface, there is a tendency that a stronger stress is applied to the outer peripheral portion of the chip due to the difference in the amount of expansion and contraction due to the temperature dependence of the chip and the interposer. Here, as an influence caused by the stress applied to the LSI, there is a concern that the characteristics of the transistor directly under the area pad change. That is, the operation speed of the LSI transistors becomes non-uniform due to this influence. If this influence is not taken into consideration, the operation timing of the LSI is affected, which causes a serious problem with respect to the malfunction of the LSI function and the yield. .

  As a method for solving this problem, for example, a technique including dummy terminals provided on the four corners or diagonal lines of a semiconductor chip and an interposer has been proposed (see, for example, Patent Document 1). Further, for example, a method of providing a dummy bump electrode using a mark opening that functions as an alignment mark has been proposed (see, for example, Patent Document 2).

JP 2008-60587 A JP 2005-12065 A

  However, the method disclosed in Patent Document 1 is a method of stress relaxation on the four corners and diagonal lines of the chip, and no countermeasure is taken against the stress on the entire outer periphery of the chip.

  The method of Patent Document 2 is a method of using alignment marks, which are often arranged at the four corners of a chip, as dummy bump electrodes. However, since the number thereof is small, a great effect of suppressing the stress at the outer periphery of the chip is I can't expect it.

  In view of the above, an object of the present invention is to reduce the cost of a semiconductor integrated circuit device having a flip-chip structure, and particularly to the influence of stress applied to internal elements of the semiconductor chip from pads arranged on the surface of the semiconductor chip. It is to reduce the influence of stress on the outer peripheral portion of a chip having a large value, thereby preventing deterioration in timing performance and malfunction due to variations in transistor operation speed.

  In order to achieve the above-mentioned object, the inventor of the present application has made extensive studies on a measure that makes it less susceptible to the stress by performing a treatment corresponding to the stress from the pad at the stage of LSI design. As a result, it is unlikely that LSI malfunctions due to the influence of stress on the pad placement position of the outer peripheral row of the semiconductor chip affected by the stress, the placement position of the cell below the pad, or the opening shape of the pad, etc. The technical idea of laying out in advance was found.

  Specifically, a first semiconductor integrated circuit device of the present invention is formed on a semiconductor chip having a plurality of input / output cells, a plurality of pads formed on the surface of the semiconductor chip, and a surface of the semiconductor chip. And a wiring for electrically connecting at least a part of the plurality of input / output cells and at least a part of the plurality of pads, wherein the plurality of pads are pads formed in an outer peripheral row of the semiconductor chip, and the semiconductor chip The pad is formed on the inner peripheral row, and a resin protective film is formed on each of the plurality of pads. The shape of the resin protective film on the pad formed on the outer peripheral row is the inner peripheral row. It differs from the shape of the resin protective film on the pad formed in the row.

  Specifically, according to the second semiconductor integrated circuit device of the present invention, in the first semiconductor integrated circuit device, the resin protective film has openings formed on each of the plurality of pads, The opening diameters of the openings on the pads formed in the above are different from the opening diameters of the openings on the pads formed in the inner circumferential row.

  Specifically, the third semiconductor integrated circuit device of the present invention is the second semiconductor integrated circuit device, wherein the opening diameter of the opening on the pad formed in the outer circumferential row is the pad formed in the inner circumferential row. It is characterized by being smaller than the opening diameter of the upper opening.

  By reducing the opening diameter of the resin protective film on the pad in the outer peripheral row of the semiconductor chip that is more susceptible to stress, it is possible to reduce the range affected by the stress due to flip chip bonding. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, in the fourth semiconductor integrated circuit device according to the present invention, in the third semiconductor integrated circuit device, the opening diameter of the opening on the pad formed in the outer circumferential row is formed in the inner circumferential row. It is characterized by being larger than the opening diameter of the opening on the pad.

  By increasing the opening diameter of the resin protective film on the pad in the outer peripheral row of the semiconductor chip that is more susceptible to stress, the stress itself due to flip chip bonding can be reduced. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, the fifth semiconductor integrated circuit device according to the present invention is characterized in that, in the first semiconductor integrated circuit device, the upper surface of the pad formed in the outer peripheral row is covered with a resin protective film. To do.

  By not opening the resin protective film on the pad in the outer peripheral row of the semiconductor chip that is more susceptible to stress, it is possible to reduce the effect of stress due to flip chip bonding. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, in a sixth semiconductor integrated circuit device according to the present invention, in the first semiconductor integrated circuit device, an opening is formed in the resin protective film on the pad formed in the outer peripheral row, The opening shape of the opening on the pad formed in the outer circumferential row is a ring shape.

  Since the opening shape of the resin protective film on the pad in the outer peripheral row of the semiconductor chip that is more susceptible to stress is a ring shape, it is possible to reduce the influence range of the stress due to flip chip bonding. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. Here, the ring shape is not limited to a circular shape, but can be used as a countermeasure to relieve stress in the same manner even when various shapes such as an octagonal shape and a rectangular shape are used as appropriate. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, in the seventh semiconductor integrated circuit device of the present invention, in the first semiconductor integrated circuit device, an opening is formed in the resin protective film on the pad formed in the outer peripheral row, and the outer periphery is formed. The opening shape of the opening on the pad formed in a row is a shape in which a plurality of openings arranged in an array are formed.

  The effect of stress due to flip chip bonding is achieved by making the opening shape of the resin protective film on the pad in the outer peripheral row of the semiconductor chip more susceptible to stress into a shape in which multiple openings arranged in an array are formed. The range can be reduced. In addition, the outer peripheral row of the semiconductor chip may be appropriately treated not only for the outer peripheral row but also for the outer peripheral row 2 and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, an eighth semiconductor integrated circuit device according to the present invention is the sixth semiconductor integrated circuit device, wherein the resin protective film on the pad formed in the outer peripheral row is arranged in an array inside the ring shape. A plurality of aligned openings are further formed.

  The opening shape of the resin protective film on the pad in the outer peripheral row of the semiconductor chip which is more susceptible to stress is a ring shape, and a plurality of openings arranged in an array inside the ring shape are further formed. Thus, it is possible to reduce the influence of stress caused by flip chip bonding. When the opening of the resin protective film on the pad has a ring shape, the stress may be relieved by appropriately forming a plurality of ring shapes such as two rows and three rows as well as one row on the outer periphery. When forming a plurality of openings arranged in an array in the resin protective film on the pad, the openings are not limited to a circle, but may be appropriately formed in various shapes such as an octagon and a rectangle. It may be a measure to relieve stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, the ninth semiconductor integrated circuit device according to the present invention is the sixth semiconductor integrated circuit device, wherein a plurality of resin protective films on the pads formed in the outer circumferential row are arranged outside the ring shape. The opening is further formed.

  The opening shape of the resin protective film on the pad in the outer peripheral row of the semiconductor chip that is more susceptible to stress is a ring shape, and a plurality of openings are further formed outside the ring shape shape, It is possible to reduce the influence of stress caused by flip chip bonding. When the opening of the resin protective film on the pad has a ring shape, the stress may be relieved by appropriately forming a plurality of ring shapes such as two rows and three rows as well as one row on the outer periphery. When further forming a plurality of openings on the outside of the ring shape, the stress is similarly relieved even if the openings are not only circular but also various shapes such as octagons and squares. It may be a countermeasure. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, in a tenth semiconductor integrated circuit device according to the present invention, in the first semiconductor integrated circuit device, the diameter of the pad formed in the outer circumferential row is larger than the diameter of the pad formed in the inner circumferential row. It is large.

  By increasing the diameter of the pad in the outer peripheral row of the semiconductor chip that is more susceptible to stress, the stress due to flip chip bonding can be reduced. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, in an eleventh semiconductor integrated circuit device according to the present invention, in the first semiconductor integrated circuit device, the diameter of the pad formed in the outer circumferential row is larger than the diameter of the pad formed in the inner circumferential row. It is small.

  By reducing the diameter of the pad in the outer peripheral row of the semiconductor chip that is more susceptible to the influence of stress, it is possible to reduce the range of influence of stress due to flip chip bonding. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, in a twelfth semiconductor integrated circuit device according to the present invention, in the first semiconductor integrated circuit device, the diameter of the bump arranged on the pad formed in the outer peripheral row is formed in the inner peripheral row. It is characterized by being larger than the diameter of the bump arranged on the pad.

  By increasing the diameter of the bumps in the outer peripheral row of the semiconductor chip that is more susceptible to stress, the stress due to flip chip bonding can be reduced. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, in the thirteenth semiconductor integrated circuit device according to the present invention, the diameter of the bumps arranged on the pads formed in the outer circumferential row is the same as that of the bumps arranged on the pads formed in the inner circumferential row. It is smaller than the diameter.

  By reducing the diameter of the bumps in the outer peripheral row of the semiconductor chip that is more susceptible to stress, it is possible to reduce the stress-affected range by flip-chip bonding. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, in the fourteenth semiconductor integrated circuit device according to the present invention, in the first semiconductor integrated circuit device, the arrangement density of the pads formed in the outer circumferential row is the arrangement density of the pads formed in the inner circumferential row. It is characterized by being higher than.

  It is possible to reduce the influence of the flip chip bonding stress by increasing the arrangement density of the pads in the outer peripheral row of the semiconductor chip that is more susceptible to the influence of the stress. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, the fifteenth semiconductor integrated circuit device according to the present invention is characterized in that, in the first semiconductor integrated circuit device, pads formed in the outer peripheral row are used as power supply terminals.

  The outer peripheral rows of semiconductor chips that are more susceptible to stress are places where the wiring of semiconductor chips and interposers tends to be crowded, and flip chips without causing wiring congestion by using the connected pads as power supply terminals It becomes possible to reduce the influence of stress due to bonding. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, according to the sixteenth semiconductor integrated circuit device of the present invention, in the first semiconductor integrated circuit device, the arrangement density of the pads formed at the four corners of the semiconductor chip among the plurality of pads is equal to that of the plurality of pads. Of these, the arrangement density of pads formed at portions other than the four corners of the semiconductor chip is higher.

  It is possible to reduce the influence of the stress due to the flip chip bonding by making the pad arrangement density dense at the outer peripheral row of the semiconductor chip and the four corners of the semiconductor chip that are more susceptible to the influence of the stress. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. The range of the four corners of the semiconductor chip can correspond to a rectangular region or a triangular region from the four corner ends of the semiconductor chip. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, in the seventeenth semiconductor integrated circuit device according to the present invention, the pads formed at the four corners of the semiconductor chip among the plurality of pads are used as power supply terminals in the first semiconductor integrated circuit device. It is characterized by.

  The outer peripheral row of the semiconductor chip and the four corners of the semiconductor chip that are more susceptible to stress are places where the wiring of the semiconductor chip and the interposer tends to be crowded, and using the pad connection as a power supply terminal causes wiring congestion. It is possible to reduce the influence of stress caused by flip chip bonding without any problem. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, the eighteenth semiconductor integrated circuit device according to the present invention is the first semiconductor integrated circuit device, wherein the plurality of input / output cells are a first type that does not cause a malfunction in the semiconductor chip even if timing variation occurs. And a second type of cell that causes a malfunction in the semiconductor chip when timing variations occur, and the interior of the semiconductor chip located below the pad formed in the outer peripheral row. In the region, the arrangement density of the first type cells is higher than the arrangement density of the second type cells.

  Here, the “first type cell”, that is, the “cell that does not cause a malfunction in the semiconductor chip even if timing variation occurs” corresponds to, for example, a cell that does not operate in synchronization with the clock. The “cell”, that is, the “cell that causes malfunction in the semiconductor chip when timing variation occurs” corresponds to a cell that operates at a severe timing by high-speed clock synchronization, for example.

  According to the eighteenth semiconductor integrated circuit device, in the internal region of the semiconductor chip below the pads in the outer peripheral row of the semiconductor chip, the arrangement density of the first type cells that does not cause malfunction in the semiconductor chip even if timing variation occurs Is higher than the arrangement density of the second type cells that cause malfunction in the semiconductor chip when timing variation occurs. This makes it difficult for LSI malfunctions due to the effect of stress applied to the inside of the semiconductor chip from the pads arranged on the surface of the semiconductor chip, thereby preventing cost reliability and preventing timing reliability from deteriorating. it can. In addition, in this way, the above-mentioned effects can be obtained while suppressing costs by performing a treatment corresponding to the stress from the pad at the stage of LSI design.

  Specifically, a nineteenth semiconductor integrated circuit device according to the present invention is characterized in that the first semiconductor integrated circuit device further includes an interposer for flip-joining with a semiconductor chip.

  Specifically, the twentieth semiconductor integrated circuit device according to the present invention is the eighteenth semiconductor integrated circuit device according to the eighteenth semiconductor integrated circuit device, wherein the opening diameter of the interposer bonding portion bonded to the bump disposed on the pad formed in the outer peripheral row is provided. Is larger than the opening diameter of the interposer joint portion to be joined to the bump arranged on the pad formed in the inner circumferential row.

  By increasing the opening diameter of the interposer joint in the outer peripheral row of the semiconductor chip that is more susceptible to stress, it is possible to reduce the stress due to flip chip joining. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  Specifically, the twenty-first semiconductor integrated circuit device according to the present invention is the eighteenth semiconductor integrated circuit device, wherein an opening diameter of an interposer joint portion to be joined to a bump disposed on a pad formed in the outer peripheral row. Is smaller than the opening diameter of the interposer joint portion to be joined to the bump arranged on the pad formed in the inner circumferential row.

  By reducing the opening diameter of the solder interposer joint in the outer peripheral row of the semiconductor chip that is more susceptible to stress, it is possible to reduce the range of influence of the stress due to flip chip joining. The outer peripheral rows of the semiconductor chips may be appropriately treated not only for the outer peripheral row but also for the outer peripheral rows and the third row, and the region that is more strongly affected by the stress. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  According to a twenty-second semiconductor integrated circuit device of the present invention, in the eighteenth semiconductor integrated circuit device, the resin material for joining the semiconductor chip and the interposer in the outer peripheral row of the semiconductor chips on the interposer flip-connected to the semiconductor chip is a semiconductor It is applied to the periphery of the chip and the upper peripheral row of the semiconductor chip.

  The range of influence of stress due to flip chip bonding by forming a resin material that joins the semiconductor chip and interposer in the outer peripheral row that is more susceptible to stress to the periphery of the semiconductor chip and the upper part of the outer peripheral row of the semiconductor chip. Can be reduced. As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  As described above, according to the present invention, it is possible to realize the LSI design and the structure of the semiconductor integrated circuit device in consideration of the influence of the stress from the pad on the outer peripheral row of the semiconductor chip in the flip chip structure. For this reason, the malfunction of the semiconductor integrated circuit device caused by the stress can be prevented without increasing the cost.

FIG. 1 is a top view showing the configuration of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing the configuration of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 3 is a top view showing the configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention. FIG. 4 is a top view showing a configuration of a semiconductor integrated circuit device according to the third embodiment of the present invention. FIG. 5 is a sectional view showing a configuration of a semiconductor integrated circuit device according to the third embodiment of the present invention. FIG. 6 is a top view showing the configuration of the pad portion of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 7 is a cross-sectional view showing a configuration of a semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 8 is a top view showing the configuration of the pad portion of the semiconductor integrated circuit device according to the fifth embodiment of the present invention. FIG. 9 is a cross-sectional view showing a configuration of a semiconductor integrated circuit device according to the fifth embodiment of the present invention. FIG. 10 is a top view showing the configuration of the pad portion of the semiconductor integrated circuit device according to the sixth embodiment of the present invention. FIG. 11 is a top view showing a configuration of a semiconductor integrated circuit device according to the sixth embodiment of the present invention. FIG. 12 is a top view showing the configuration of the pad portion of the semiconductor integrated circuit device according to the seventh embodiment of the present invention. FIG. 13 is a top view showing a configuration of a semiconductor integrated circuit device according to the eighth, tenth and seventeenth embodiments of the present invention. FIG. 14 is a top view showing a configuration of a semiconductor integrated circuit device according to the ninth, eleventh, and eighteenth embodiments of the present invention. FIG. 15 is a top view showing a configuration of a semiconductor integrated circuit device according to the twelfth and thirteenth embodiments of the present invention. FIG. 16 is a top view showing a configuration of a semiconductor integrated circuit device according to the fourteenth and fifteenth embodiments of the present invention. FIG. 17 is a cross-sectional view showing the configuration of the semiconductor integrated circuit device according to the nineteenth embodiment of the present invention. FIG. 18 is a plan view showing a configuration of a chip using a conventional flip chip structure. FIG. 19 is a cross-sectional view showing a configuration in which a chip using a conventional flip chip structure and a package are connected.

  Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings. In the following, the technical idea of the present invention will be clearly described with reference to the drawings and detailed description. Any person skilled in the art will understand the preferred embodiment of the present invention, and Modifications and additions can be made by the technology disclosed in the invention, and this does not depart from the technical idea and scope of the present invention.

(First embodiment)
Hereinafter, a semiconductor integrated circuit device according to a first embodiment of the present invention will be described in detail with reference to the drawings.

  In this embodiment, in particular, as a semiconductor integrated circuit device in consideration of the stress from the area pad in the outer peripheral row of the chip, the opening diameter of the resin protective film 103 on the pad (pad metal) 102 in the outer peripheral row of the semiconductor chip 101 is the semiconductor chip. A semiconductor integrated circuit device having an opening diameter smaller than the opening diameter of the resin protective film 103 on the pad 102 in the inner circumferential row will be described.

  FIG. 1 is a plan view showing the configuration of the semiconductor integrated circuit device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the configuration of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG.

  Pads 102 as shown in the sectional view of FIG. 2 are arranged in an array on the semiconductor chip 101 in FIG. 1 to form an area pad structure. In particular, FIG. 1 shows the shape of the pad 102 disposed on the semiconductor chip 101. For convenience of explanation, a portion of the resin protective film 103 formed on the pad 102 is taken out and shown together. Yes. Further, although not shown, the pad 102 is electrically connected to at least a part of the input / output cells (see FIG. 18) formed on the peripheral edge of the semiconductor chip 101 through wiring formed on the semiconductor chip 101.

  As shown in FIG. 2, the surface of the semiconductor chip 101 is covered with a resin protective film 103 having an opening 103 hs or 103 hr on the pad 102, and the pad 103 is filled with the opening 103 hs or 103 hr. The barrier metal 106 is formed on the barrier metal 106, and the solder bump 107 is formed on the barrier metal 106. A structure is formed to electrically and physically join the electrode metal 109 serving as an interposer joint portion of the interposer substrate 110 via the solder bump 107. The semiconductor chip 101 and the interposer substrate 110 have a structure in which the semiconductor chip 101 and the interposer substrate 110 are physically bonded by the bonding resin 111 through the interposer resin material protective film 108, the resin protective film 103, and the nitride protective film.

  Here, as shown in FIG. 1, for the pads 102 formed on the surface of the semiconductor chip 101, openings provided in the resin protective film 103 located on the pads 102 arranged in the outer peripheral row of the semiconductor chip 101. The opening diameter 103 s of 103 hs is smaller than the opening diameter 103 r of the opening 103 hr provided in the resin protective film 103 located on the pad 102 arranged in the inner row of the semiconductor chip 101.

  By reducing the opening diameter 103s of the opening 103hs provided in the resin protective film 103 on the pad 102 in the outer peripheral row of the semiconductor chip 101 that is more susceptible to stress, the range affected by the stress due to flip chip bonding is reduced. It is possible to reduce. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 1 but also two outer peripheral rows and three rows may be appropriately taken for the region that is more strongly affected by the stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Second Embodiment)
Hereinafter, a semiconductor integrated circuit device according to a second embodiment of the present invention will be described in detail with reference to the drawings.

  In this embodiment, in particular, as a semiconductor integrated circuit device in consideration of stress from an area pad in the outer peripheral row of the chip, the opening diameter of the resin protective film 103 on the pad 102 in the outer peripheral row of the semiconductor chip 101 is the inner periphery of the semiconductor chip 101. A semiconductor integrated circuit device having an opening diameter larger than the opening diameter of the resin protective film 103 on the pad 102 in the row will be described.

  FIG. 3 is a plan view showing the configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention, and FIG. 2 shows the configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention. It is also a sectional view.

  As shown in FIG. 3, for the pads 102 formed on the surface of the semiconductor chip 101, the openings 103 hr provided in the resin protective film 103 located on the pads 102 arranged in the outer peripheral row of the semiconductor chip 101 are opened. The diameter 103r is larger than the opening diameter 103s of the opening 103hs provided in the resin protective film 103 located on the pad 102 arranged in the inner row of the semiconductor chip 101.

  By increasing the opening diameter 103r of the opening 103hr provided in the resin protective film 103 on the pad 102 in the outer peripheral row of the semiconductor chip 101 that is more susceptible to stress, the stress itself due to flip-chip bonding can be reduced. Is possible. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 3 but also two outer peripheral rows and three rows may be appropriately taken for the region more strongly affected by the stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Third embodiment)
Hereinafter, a semiconductor integrated circuit device according to a third embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, the upper surface of the pad 102 formed in the outer peripheral row of the semiconductor chip 101 is covered with the resin protective film 103, particularly as a semiconductor integrated circuit device in consideration of the stress from the area pad in the outer peripheral row of the chip. A semiconductor integrated circuit device characterized by this will be described.

  FIG. 4 is a plan view showing the configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention, and FIG. 5 is a cross-sectional view showing the configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention. FIG.

  As shown in FIG. 4, with respect to the pad 102 formed on the surface of the semiconductor chip 101 having a plurality of input / output cells, an opening is formed in the resin protective film 103a on the pad 102 in the outer peripheral row of the semiconductor chip 101. Not. That is, as shown in FIG. 5, a resin protective film 103 a in which no opening is formed and a barrier metal 106 are sequentially formed on the pads 102 in the outer peripheral row of the semiconductor chip 101 through the nitride protective film 105. Has been. Thus, in the present embodiment, the bumps 102 formed in the outer peripheral row are dummy bumps that are not electrically joined to the input / output cells. The resin protective film 103 on the pad 102 in the inner circumferential row of the semiconductor chip 101 has an opening 103hs having the opening diameter 103s as described in the second embodiment, for example. The size of the opening is not limited to this.

  By not forming an opening in the resin protective film 103a on the pad 102 in the outer peripheral row of the chip that is more susceptible to stress, it is possible to reduce the effect of the stress itself due to flip chip bonding. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 4 but also two outer peripheral rows and three rows may be appropriately taken for the region that is more strongly affected by the stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Fourth embodiment)
Hereinafter, a semiconductor integrated circuit device according to a fourth embodiment of the present invention will be described in detail with reference to the drawings.

  In this embodiment, as a semiconductor integrated circuit device in consideration of stress from an area pad, the semiconductor integrated circuit device is characterized in that the opening shape of the resin protective film 103b on the pad 102 of the semiconductor chip 101 is a ring shape. explain.

  FIG. 6 is a plan view showing a configuration of a pad of a semiconductor integrated circuit device according to the fourth embodiment of the present invention, and FIG. 7 shows a configuration of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. It is sectional drawing shown, Comprising: It is sectional drawing corresponding to center part vicinity of FIG.

  As shown in FIGS. 6 and 7, the pad 102 formed on the surface of the semiconductor chip 101 having a plurality of input / output cells is the resin protective film 103 b on the pad 102 in the outer peripheral row of the semiconductor chip 101. The opening shape of the opening 103bh provided in the ring shape is a ring shape having a ring diameter of 103bht. The resin protective film 103 on the pads 102 in the inner circumferential row of the semiconductor chip 101 may be formed with an opening 103hs having an opening diameter 103s as described in the second embodiment, for example. The opening diameter and the size and shape of the opening are not limited thereto.

  The opening 103bh provided in the resin protective film 103b on the pad 102 shown in FIG. 6 has a ring shape, and is arranged in the outer peripheral row of the semiconductor chip 101 that is more susceptible to stress, thereby flip-chip bonding. It is possible to reduce the range of influence of stress due to. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row but also two outer peripheral rows and three rows may be appropriately taken for the region that is more strongly affected by the stress. The ring shape is not limited to a circular shape, and may be a measure to relieve stress in the same manner even when various shapes such as an octagonal shape and a quadrangular shape are appropriately used.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Fifth embodiment)
Hereinafter, a semiconductor integrated circuit device according to a fifth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, as a semiconductor integrated circuit device in consideration of the stress from the area pad on the outer periphery of the chip, openings 103ch having a small opening diameter 103cht are arranged in an array in the resin protective film 103c on the pad 102. A semiconductor integrated circuit device having the shape formed in the above will be described.

  FIG. 8 is a plan view showing a configuration of a pad of a semiconductor integrated circuit device according to the fifth embodiment of the present invention, and FIG. 9 shows a configuration of the semiconductor integrated circuit device according to the fifth embodiment of the present invention. It is sectional drawing shown, Comprising: It is sectional drawing corresponding to the center part vicinity of FIG.

  As shown in FIGS. 8 and 9, the resin protective film 103c on the pad 102 in the outer peripheral row of the semiconductor chip 101 is formed with openings 103ch having a small diameter 103cht arranged in an array. The resin protective film 103 on the pad 102 in the inner circumferential row of the semiconductor chip 101 may be formed with, for example, the opening 103 hs having the opening diameter 103 s as described in the second embodiment. The opening diameter and the size and shape of the opening are not limited thereto.

  By arranging the pads 102 having the shape in which the openings 103ch having the small-diameter opening diameter 103cht shown in FIG. 8 are arranged in an array in the outer peripheral row of the semiconductor chip that is more susceptible to stress, It is possible to reduce the influence range of the bonding stress. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row but also two outer peripheral rows and three rows may be appropriately taken for the region that is more strongly affected by the stress. Further, the opening shape of the small-diameter opening 103ch is not limited to a circular shape, but may be a measure to relieve stress in the same manner even when various shapes such as an octagonal shape and a rectangular shape are used as appropriate.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Sixth embodiment)
Hereinafter, a semiconductor integrated circuit device according to a sixth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, the opening shape of the opening 103bh provided in the resin protective film 103d on the pad 102 is a ring shape, particularly as a semiconductor integrated circuit device in consideration of the stress from the area pad in the outer peripheral portion of the chip. In addition, a semiconductor integrated circuit device will be described in which openings 103ch having a small opening diameter 103cht are formed in an array inside the ring shape. That is, this embodiment is characterized by a combination of the above-described fourth and fifth embodiments.

  FIG. 10 is a plan view showing a configuration of a pad of a semiconductor integrated circuit device according to the sixth embodiment of the present invention, and FIG. 11 shows a configuration of the semiconductor integrated circuit device according to the sixth embodiment of the present invention. It is sectional drawing shown, Comprising: It is sectional drawing corresponding to center part vicinity of FIG.

  As shown in FIGS. 10 and 11, the resin protective film 103 d on the pad 102 in the outer peripheral row of the semiconductor chip 101 is formed with a ring-shaped opening 103 bh having a ring diameter 103 bht, and the ring-shaped shape thereof. Are formed with an opening 103ch having a small opening diameter 103cht arranged in an array. The resin protective film 103 on the pads 102 in the inner circumferential row of the semiconductor chip 101 may be formed with an opening 103hs having an opening diameter 103s as described in the second embodiment, for example. The opening diameter and the size and shape of the opening are not limited thereto.

  The opening shape of the opening 103bh provided in the resin protective film 103d on the pad 102 shown in FIGS. 10 and 11 is a ring shape, and a plurality of openings 103ch are arranged in an array inside the ring shape. By disposing the pads 102 on the outer peripheral rows of the semiconductor chip 101, it is possible to reduce the influence of stress due to flip chip bonding. When the opening shape of the opening 103bh provided in the resin protective film 103d on the pad 102 is changed to a ring shape, not only one row on the outer periphery but also two rows, three rows, and a plurality of ring shapes are provided as appropriate so that stress can be applied. It may be a mitigating measure. The ring shape and the opening shape of the small-diameter opening 103ch are not limited to a circular shape, and may be various measures such as an octagonal shape and a quadrilateral shape as appropriate.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Seventh embodiment)
Hereinafter, a semiconductor integrated circuit device according to a seventh embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, the opening shape of the opening 103bh provided in the resin protective film 103e on the pad 102 is a ring shape, particularly as a semiconductor integrated circuit device considering the stress from the area pad in the outer periphery of the chip, In addition, a semiconductor integrated circuit device in which an opening 103ch having a small opening diameter 103cht is formed outside the ring shape will be described.

  FIG. 12 is a plan view showing the configuration of the pads of the semiconductor integrated circuit device according to the seventh embodiment of the present invention. Although a cross-sectional view corresponding to the vicinity of the central portion in FIG. 12 is omitted, it can be easily recalled from the above-described FIG. 7, FIG. 9, FIG.

  As shown in FIG. 12, in the resin protective film 103e on the pad 102 in the outer peripheral row of the semiconductor chip 101, a ring-shaped opening 103bh having a ring diameter of 103bht is formed and on the outside of the ring-shaped shape. Is formed with an opening 103ch having a small-diameter opening diameter 103cht. The resin protective film 103 on the pads 102 in the inner circumferential row of the semiconductor chip 101 may be formed with an opening 103hs having an opening diameter 103s as described in the second embodiment, for example. The opening diameter and the size and shape of the opening are not limited thereto.

  The opening 103bh provided in the resin protective film 103e on the pad 102 shown in FIG. 12 has a ring shape, and the pad 102 having a plurality of small diameter openings 103ch outside the ring shape is By disposing the semiconductor chip 101 in the outer peripheral row, it is possible to reduce the influence of stress caused by flip chip bonding. When the opening shape of the opening 103bh provided in the resin protective film 103e on the pad 102 is changed to a ring shape, not only one row on the outer periphery but also two rows, three rows, and a plurality of ring shapes are appropriately provided so that stress can be applied. It may be a mitigating measure. The ring shape and the opening shape of the small-diameter opening 103ch are not limited to a circular shape, and may be various measures such as an octagonal shape and a quadrilateral shape as appropriate.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Eighth embodiment)
Hereinafter, a semiconductor integrated circuit device according to an eighth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, in particular, as a semiconductor integrated circuit device in consideration of stress from area pads in the outer peripheral row of the chip, the diameter of the pad 102r in the outer peripheral row of the semiconductor chip 101 is larger than the diameter of the pad 102s in the inner peripheral row of the chip. A semiconductor integrated circuit device having a caliber will be described.

  FIG. 13 is a plan view showing a configuration of a semiconductor integrated circuit device according to the eighth embodiment of the present invention.

  As shown in FIG. 13, the diameter of the pad 102 r in the outer circumferential row among the plurality of pads formed on the surface of the semiconductor chip 101 is larger than the diameter of the pad 102 s in the inner circumferential row of the semiconductor chip 101.

  By increasing the diameter of the pad 102r in the outer peripheral row of the semiconductor chip 101 that is more susceptible to stress, it is possible to reduce the stress itself due to flip chip bonding. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 13 but also two outer peripheral rows and three rows may be appropriately taken for areas that are more strongly affected by stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Ninth embodiment)
Hereinafter, a semiconductor integrated circuit device according to a ninth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, in particular, as a semiconductor integrated circuit device in consideration of stress from area pads in the outer peripheral row of the chip, the diameter of the pad 102s in the outer peripheral row of the semiconductor chip 101 is equal to the diameter of the pad 102r in the inner peripheral row of the semiconductor chip 101. A semiconductor integrated circuit device having a smaller diameter than the above will be described.

  FIG. 14 is a plan view showing a configuration of a semiconductor integrated circuit device according to the ninth embodiment of the present invention.

  As shown in FIG. 14, the diameter of the pad 102 s in the outer peripheral row among the plurality of pads formed on the surface of the semiconductor chip 101 is smaller than the diameter of the pad 102 r in the inner peripheral row of the semiconductor chip 101.

  By reducing the diameter of the pad 102s in the outer peripheral row of the chip that is more susceptible to stress, it is possible to reduce the stress-affected range due to flip-chip bonding. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 14 but also two outer peripheral rows and three rows may be appropriately taken for the region that is more strongly affected by the stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Tenth embodiment)
Hereinafter, a semiconductor integrated circuit device according to a tenth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, the solder bumps 107r and 107s arranged on the pad 102 are used as the semiconductor integrated circuit device in consideration of the stress from the area pad in the outer peripheral portion of the chip. A semiconductor integrated circuit device will be described in which the diameter of 107r is larger than the diameter of the solder bump 107s in the inner circumferential row of the semiconductor chip 101.

  FIG. 13 is also a plan view showing the configuration of the semiconductor integrated circuit device according to the tenth embodiment of the present invention.

  As shown in FIG. 13, the diameter of the solder bump 107 r in the outer peripheral row of the semiconductor chip 101 is larger than the diameter of the solder bump 107 s in the inner peripheral row of the semiconductor chip 101.

  By increasing the diameter of the solder bump 107r in the outer peripheral row of the semiconductor chip 101 that is more susceptible to stress, it is possible to reduce the stress itself due to flip chip bonding. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 13 but also two outer peripheral rows and three rows may be appropriately taken for areas that are more strongly affected by stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Eleventh embodiment)
Hereinafter, a semiconductor integrated circuit device according to an eleventh embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, the solder bumps 107r and 107s arranged on the pad 102 are used as the semiconductor integrated circuit device in consideration of the stress from the area pad in the outer peripheral portion of the chip. A semiconductor integrated circuit device will be described in which the diameter of 107s is smaller than the diameter of the solder bump 107r in the inner circumferential row of the semiconductor chip 101.

  FIG. 14 is also a plan view showing the configuration of the semiconductor integrated circuit device according to the eleventh embodiment of the present invention.

  As shown in FIG. 14, the diameter of the solder bump 107 s in the outer peripheral row of the semiconductor chip 101 is smaller than the diameter of the solder bump 107 r in the inner peripheral row of the semiconductor chip 101.

  By reducing the diameter of the solder bump 107s in the outer peripheral row of the semiconductor chip 101 that is more susceptible to the influence of stress, it is possible to reduce the range of influence of the stress due to flip chip bonding. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 14 but also two outer peripheral rows and three rows may be appropriately taken for the region that is more strongly affected by the stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Twelfth embodiment)
Hereinafter, a semiconductor integrated circuit device according to a twelfth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, in particular, as a semiconductor integrated circuit device that takes into account the stress from the area pad in the outer peripheral portion of the chip, the arrangement density of the pads 102 in the outer peripheral row of the semiconductor chip 101 A semiconductor integrated circuit device that is dense with respect to the arrangement density will be described.

  FIG. 15 is a plan view showing a configuration of a semiconductor integrated circuit device according to the twelfth embodiment of the present invention.

  As shown in FIG. 15, the arrangement density of pads 102 arranged in, for example, the region 140R as the region of the outer peripheral row in the semiconductor chip 101 is the pad arranged in the inner peripheral row of the semiconductor chip 101, for example, the region inside the region 140R. It is dense with respect to the arrangement density of 102.

  By increasing the arrangement density of the pads 102 on the outer peripheral portion of the semiconductor chip 101 that is more susceptible to the influence of stress, it is possible to reduce the influence of stress due to flip chip bonding. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 15 but also two outer peripheral rows and three rows may be appropriately taken for the region that is more strongly affected by the stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(13th Embodiment)
Hereinafter, a semiconductor integrated circuit device according to a thirteenth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, as a semiconductor integrated circuit device taking into account stress from area pads in the outer peripheral portion of the chip in particular, in the semiconductor integrated circuit device of the twelfth embodiment described above, the pads 102 arranged in the outer peripheral row are power supplies. A semiconductor integrated circuit device used as a terminal will be described.

  FIG. 15 is also a plan view showing the configuration of the semiconductor integrated circuit device according to the thirteenth embodiment of the present invention.

  As shown in FIG. 15, in the semiconductor integrated circuit device of this embodiment, in the twelfth semiconductor integrated circuit device described above, the connection of the pad 102 arranged in the region 140R of the outer peripheral row is used as the power supply terminal.

  The outer peripheral row of the semiconductor chip 101 that is more susceptible to stress is a place where the wiring of the semiconductor chip 101 and the interposer tends to be crowded, and the connection of the pad 102 is used as a power supply terminal without causing wiring congestion. It is possible to reduce the influence of stress caused by flip chip bonding. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 15 but also two outer peripheral rows and three rows may be appropriately taken for the region that is more strongly affected by the stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Fourteenth embodiment)
Hereinafter, a semiconductor integrated circuit device according to a fourteenth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, in particular, as a semiconductor integrated circuit device considering the stress from the area pad in the outer peripheral portion of the chip, the arrangement density of the pads 102 at the four corners (corner portions) of the semiconductor chip 101 A semiconductor integrated circuit device that is dense with respect to the arrangement density of 102 will be described.

  FIG. 16 is a plan view showing a configuration of a semiconductor integrated circuit device according to the fourteenth embodiment of the present invention.

  As shown in FIG. 16, for example, the arrangement density of the pads 102 in the region 150 </ b> R as the four corners of the semiconductor chip 101 is dense with respect to the arrangement density of the pads 102 in the region other than the area 150 </ b> R as the inside of the semiconductor chip 101. Yes.

  By making the arrangement density of the pads 102 arranged at the four corners in the outer peripheral row of the semiconductor chip 101 that is more susceptible to the influence of stress, it is possible to reduce the influence of the stress due to the flip chip bonding. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 16 but also two outer peripheral rows and three rows may be appropriately taken for the region that is more strongly affected by the stress. The range of the four corners of the semiconductor chip 101 may be a square region or a triangular region from the four corner ends of the semiconductor chip 101.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Fifteenth embodiment)
Hereinafter, a semiconductor integrated circuit device according to a fifteenth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, as the semiconductor integrated circuit device taking into account the stress from the area pad in the outer peripheral portion of the chip, in the fifteenth semiconductor integrated circuit device described above, the pads 102 arranged at the four corners are used as power supply terminals. A semiconductor integrated circuit device characterized by the above will be described.

  FIG. 16 is also a plan view showing the configuration of the semiconductor integrated circuit device according to the fifteenth embodiment of the present invention.

  As shown in FIG. 16, in the semiconductor integrated circuit device of this embodiment, the connection of the pads 102 arranged in the region 150R which is the four corners is used as the power supply terminal in the above-described fourteenth semiconductor integrated circuit device. .

  The four corners of the outer peripheral row of the semiconductor chip 101 that are more susceptible to stress are places where the wiring of the semiconductor chip 101 and the interposer tends to be crowded. By using the connection of the pad 102 as a power supply terminal, the wiring congestion is reduced. It is possible to reduce the effect of stress due to flip chip bonding without causing it. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 16 but also two outer peripheral rows and three rows may be appropriately taken for the region that is more strongly affected by the stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Sixteenth embodiment)
Hereinafter, a semiconductor integrated circuit device according to a sixteenth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, as a semiconductor integrated circuit device that takes into account the stress from the area pad in the outer peripheral portion of the chip, in the inner region of the semiconductor chip 101 located below the pad 102 in the outer peripheral row of the semiconductor chip 101, A semiconductor integrated circuit device will be described in which the arrangement density of the type cell is higher than the arrangement density of the second type cell.

  FIG. 15 is also a plan view showing the configuration of the semiconductor integrated circuit device according to the sixteenth embodiment of the present invention.

  As shown in FIG. 15, for example, in the inner region of the semiconductor chip 101 located below the pad 102 in the region 140R as the outer peripheral row of the semiconductor chip 101, the arrangement density of the first type cells is the arrangement of the second type cells. It is higher than the density.

  Here, the “first type cell” means “a cell that does not cause a malfunction in the semiconductor chip even if timing variation occurs”. For example, a cell that does not operate in synchronization with the clock corresponds to the “first type cell”. The “two types of cells” means “cells that cause malfunctions in the semiconductor chip when timing variations occur”, for example, cells that operate at severe timing by high-speed clock synchronization.

  According to the sixteenth semiconductor integrated circuit device of the present invention, even if timing variation occurs in the inner region of the semiconductor chip 101 located below the pad 102 in the region 140R as the outer peripheral row of the semiconductor chip 101, the semiconductor chip 101 The arrangement density of the first type cells that do not cause malfunctions is higher than the arrangement density of the second type cells that cause malfunctions in the semiconductor chip 101 when timing variation occurs. This makes it difficult for LSI malfunctions due to the effect of stress applied to the inside of the semiconductor chip 101 from the pads 102 arranged on the surface of the semiconductor chip 101. As a result, it is possible to prevent deterioration in timing reliability while suppressing costs. In addition, as described above, by performing a treatment corresponding to the stress from the pad 102 at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Seventeenth embodiment)
Hereinafter, a semiconductor integrated circuit device according to a seventeenth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, an opening diameter serving as an interposer joint portion to be joined to the solder bumps 107r and 107s disposed on the pads 102r and 102s as a semiconductor integrated circuit device particularly considering the stress from the area pad in the outer peripheral portion of the chip. In the semiconductor integrated circuit device, the opening diameter in the outer peripheral row of the semiconductor chip 101 is larger than the opening diameter in the inner peripheral row of the semiconductor chip 101.

  FIG. 13 is also a plan view showing the configuration of the semiconductor integrated circuit device according to the seventeenth embodiment of the present invention.

  As shown in FIG. 13, the region where the solder bump 107r on the pad 102r in the outer peripheral row of the semiconductor chip 101 is joined to the electrode metal 109 in the interposer substrate 110 (see FIG. 2), that is, the opening diameter of the interposer joint is The opening diameter of the corresponding interposer joint portion of the solder bump 107s on the pad 102s in the inner circumferential row of the semiconductor chip 101 is large.

  By increasing the opening diameter of the interposer bonding portion in the outer peripheral row of the semiconductor chip 101 that is more susceptible to stress, it is possible to reduce the stress itself due to flip chip bonding. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 13 but also two outer peripheral rows and three rows may be appropriately taken for areas that are more strongly affected by stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Eighteenth embodiment)
Hereinafter, a semiconductor integrated circuit device according to an eighteenth embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, an opening diameter serving as an interposer joint portion to be joined to the solder bumps 107r and 107s disposed on the pads 102r and 102s as a semiconductor integrated circuit device particularly considering the stress from the area pad in the outer peripheral portion of the chip. In the semiconductor integrated circuit device, the opening diameter in the outer peripheral row of the semiconductor chip 101 is smaller than the opening diameter in the inner peripheral row of the semiconductor chip 101.

  FIG. 14 is also a plan view showing the configuration of the semiconductor integrated circuit device according to the eighteenth embodiment of the present invention.

  As shown in FIG. 14, the region (see FIG. 2) where the solder bump 107s on the pad 102s in the outer peripheral row of the semiconductor chip 101 is joined to the electrode metal 109 in the interposer substrate 110, that is, the opening diameter of the interposer joint is The aperture is smaller than the aperture of the corresponding interposer joint of the solder bump 107r on the pad 102r in the inner circumferential row of the semiconductor chip 101.

  By reducing the opening diameter of the interposer joint at the outer periphery of the semiconductor chip 101 that is more susceptible to stress, it is possible to reduce the range of influence of the stress due to flip chip joining. As the outer peripheral row of the semiconductor chip 101, not only one outer peripheral row shown in FIG. 14 but also two outer peripheral rows and three rows may be appropriately taken for the region that is more strongly affected by the stress.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

(Nineteenth embodiment)
The following is a detailed description of a semiconductor integrated circuit device according to a nineteenth embodiment of the present invention, with reference to the drawings.

  In this embodiment, the semiconductor chip on the interposer in the package 122 (having the external electrode 124 on the back surface) flip-connected to the semiconductor chip 101 as a semiconductor integrated circuit device taking into account the stress from the area pad in the outer peripheral portion of the chip. In the outer peripheral region of 101, a resin material 123 that joins the semiconductor chip 101 and the interposer is applied to the periphery of the semiconductor chip 101 and to the upper part of the outer peripheral row of the semiconductor chip 101.

  FIG. 17 is a cross-sectional view showing the configuration of the semiconductor integrated circuit device according to the nineteenth embodiment of the present invention.

  As shown in FIG. 17, in the outer peripheral row (outer peripheral region) of the semiconductor chip 101 on the interposer flip-chip connected to the semiconductor chip 21, the resin material 123 that joins the semiconductor chip 101 and the interposer is disposed around the semiconductor chip 101 and It is applied to the upper part of the outer peripheral row of the semiconductor chip 101.

  In the outer peripheral row of the semiconductor chip 101 that is more susceptible to stress, a resin material 123 that joins the semiconductor chip 101 and the interposer is applied to the periphery of the semiconductor chip 101 and the upper portion of the outer peripheral row of the semiconductor chip 101.

  As described above, by performing the treatment corresponding to the stress from the pad at the stage of LSI design, the above-described effects can be obtained while suppressing the cost.

  It should be noted that the constituent elements in the first to nineteenth embodiments (including modifications) described above can be arbitrarily combined without departing from the spirit of the present invention.

  The present invention is suitable for a semiconductor integrated circuit device, in particular, a semiconductor integrated circuit device in which a semiconductor circuit composed of a transistor or the like is formed below a pad, and a design method thereof.

101 Semiconductor chip 102, 102r, 102s Pad (pad metal)
102t Pad width 103, 103a, 103b, resin material protective film 105 nitride protective film 106 barrier metal 107 solder bump 108 (interposer) resin material protective film 109 (interposer junction) electrode metal 110 interposer substrates 103s, 103r, 103bht, 103cht Open Diameter 103hs, 103rs, 103bh, 103ch Opening 122 Package 123 Resin material 124 External electrode 140R Four corners (corner part)
150R outer periphery

Claims (22)

A semiconductor chip having a plurality of input / output cells;
A plurality of pads formed on the surface of the semiconductor chip;
A wiring formed on a surface of the semiconductor chip and electrically connecting at least a part of the plurality of input / output cells and at least a part of the plurality of pads;
The plurality of pads are composed of pads formed in an outer peripheral row of the semiconductor chip and pads formed in an inner peripheral row of the semiconductor chip,
A resin protective film is formed on each of the plurality of pads,
The shape of the resin protective film on the pad formed in the outer peripheral row is different from the shape of the resin protective film on the pad formed in the inner peripheral row. In the resin protective film, an opening is formed on each of the plurality of pads,
2. The semiconductor integrated circuit according to claim 1, wherein an opening diameter of the opening on the pad formed in the outer circumferential row is different from an opening diameter of the opening on the pad formed in the inner circumferential row. Circuit device.   3. The semiconductor according to claim 2, wherein an opening diameter of the opening on the pad formed in the outer circumferential row is smaller than an opening diameter of the opening on the pad formed in the inner circumferential row. Integrated circuit device.   3. The semiconductor according to claim 2, wherein an opening diameter of the opening on the pad formed in the outer circumferential row is larger than an opening diameter of the opening on the pad formed in the inner circumferential row. Integrated circuit device.   2. The semiconductor integrated circuit device according to claim 1, wherein an upper surface of the pad formed in the outer circumferential row is covered with the resin protective film. An opening is formed in the resin protective film on the pad formed in the outer circumferential row,
2. The semiconductor integrated circuit device according to claim 1, wherein an opening shape of the opening on the pad formed in the outer circumferential row is a ring shape. An opening is formed in the resin protective film on the pad formed in the outer circumferential row,
2. The semiconductor integrated circuit device according to claim 1, wherein the opening shape of the opening on the pad formed in the outer circumferential row is a shape in which a plurality of openings arranged in an array are formed.   The said resin protective film on the pad formed in the said outer periphery row | line | column is further formed with the some opening located in an array at the inner side of the said ring shape. Semiconductor integrated circuit device.   The semiconductor integrated circuit device according to claim 6, wherein a plurality of openings are further formed outside the ring shape in the resin protective film on the pads formed in the outer circumferential row.   2. The semiconductor integrated circuit device according to claim 1, wherein a diameter of the pad formed in the outer peripheral row is larger than a diameter of the pad formed in the inner peripheral row.   The semiconductor integrated circuit device according to claim 1, wherein a diameter of the pad formed in the outer circumferential row is smaller than a diameter of the pad formed in the inner circumferential row.   2. The semiconductor according to claim 1, wherein a diameter of the bump disposed on the pad formed in the outer circumferential row is larger than a diameter of the bump disposed on the pad formed in the inner circumferential row. Integrated circuit device.   2. The semiconductor according to claim 1, wherein a diameter of the bump disposed on the pad formed in the outer circumferential row is smaller than a diameter of the bump disposed on the pad formed in the inner circumferential row. Integrated circuit device.   2. The semiconductor integrated circuit device according to claim 1, wherein the arrangement density of pads formed in the outer circumferential row is higher than the arrangement density of pads formed in the inner circumferential row.   The semiconductor integrated circuit device according to claim 1, wherein pads formed in the outer circumferential row are used as power supply terminals.   Of the plurality of pads, the placement density of the pads formed at the four corners of the semiconductor chip is higher than the placement density of the pads formed at the corners other than the four corners of the semiconductor chip. The semiconductor integrated circuit device according to claim 1.   The semiconductor integrated circuit device according to claim 1, wherein pads formed at four corners of the semiconductor chip among the plurality of pads are used as power supply terminals. The plurality of input / output cells are formed in the semiconductor chip and the first type cell that does not cause malfunction in the semiconductor chip even if timing variation occurs, and the semiconductor chip malfunctions if timing variation occurs. A second type of cell that triggers,
The arrangement density of the first type cells is higher than the arrangement density of the second type cells in an internal region of the semiconductor chip located below the pads formed in the outer circumferential row. Item 14. The semiconductor integrated circuit device according to Item 1.   The semiconductor integrated circuit device according to claim 1, further comprising an interposer for flip-joining with the semiconductor chip.   The opening diameter of the interposer joints that are bonded to the bumps arranged on the pads formed in the outer circumferential row is the opening diameter of the interposer joints that are joined to the bumps arranged on the pads formed in the inner circumferential row. The semiconductor integrated circuit device according to claim 19, wherein the semiconductor integrated circuit device is larger than the diameter.   The opening diameter of the interposer joints that are bonded to the bumps arranged on the pads formed in the outer circumferential row is the opening diameter of the interposer joints that are joined to the bumps arranged on the pads formed in the inner circumferential row. The semiconductor integrated circuit device according to claim 19, wherein the semiconductor integrated circuit device is smaller than the diameter.   In the outer peripheral row of the semiconductor chip on the interposer flip-connected to the semiconductor chip, the resin material that joins the semiconductor chip and the interposer is applied around the semiconductor chip and above the outer peripheral row of the semiconductor chip. The semiconductor integrated circuit device according to claim 19.

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