JP2011176099A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board coping with a request to improve electrical connection reliability between an electronic component and a mother board. <P>SOLUTION: The wiring board has a laminated body which includes a resin layer and a conductive layer having a larger coefficient of thermal expansion than the resin layer and has a mounting region M for mounting an electronic component on an upper surface; the conductive layer has a first conductive layer 17a having a plurality of through-holes P formed penetrating in a thickness direction and filled with parts of the resin layer; the first conductive layer 17a has a first region R1 right below the mounting region M and a second region R2 not right below the mounting region M; the plurality of through-holes P include a plurality of first through-holes P1 formed in the first region R1 of the first conductive layer 17a, and a plurality of second through-holes P2 formed in the second region R2 of the first conductive layer 17a; and each of the first through-holes P1 has an area in plane view, larger than that of the second through-holes P2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a wiring board used for electronic equipment (for example, various audiovisual equipment, home appliances, communication equipment, computer equipment and peripheral equipment).

  2. Description of the Related Art Conventionally, as an electronic device used for an electronic device, a mounting structure in which an electronic component is mounted on a wiring board is mounted on a motherboard.

  Patent Document 1 describes a wiring board that is electrically connected to an electronic component on an upper surface and electrically connected to a motherboard on a lower surface.

  By the way, the electronic component has a smaller coefficient of thermal expansion in the planar direction than the mother board, and the electronic component and the mother board have significantly different coefficients of thermal expansion in the planar direction. Therefore, when heat is applied to the electronic component, the wiring board, and the motherboard due to heat generated during the operation of the electronic component, the thermal stress due to the difference in thermal expansion coefficient between the electronic component and the motherboard is This may be applied to the electrical connection part of the circuit board or the electrical connection part of the wiring board and the motherboard to cause disconnection, and the electrical connection reliability of the electronic component, the wiring board and the motherboard is likely to be lowered.

Japanese Patent Laid-Open No. 2001-210554

  The present invention provides a wiring board that meets the demand for improving the reliability of electrical connection with electronic components and a mother board.

  A wiring board according to an aspect of the present invention includes a laminate including a resin layer and a conductive layer having a larger coefficient of thermal expansion than the resin layer, and having a mounting region for mounting an electronic component on the top surface, The conductive layer has a first conductive layer that penetrates in the thickness direction and has a plurality of through holes filled with a part of the resin layer, and the first conductive layer is a region immediately below the mounting region. A plurality of first through holes formed in the first region of the first conductive layer, and a second region which is a region immediately below the mounting region. A plurality of second through holes formed in the second region of the first conductive layer, and the first through hole has a larger area in plan view than the second through hole.

  According to the wiring board according to one aspect of the present invention, since the coefficient of thermal expansion immediately below the mounting area of the electronic component can be locally reduced, when heat is applied to the electronic component, the wiring board, and the motherboard, the electronic It is possible to reduce the thermal stress applied to the electrical connection portion of the wiring board and the motherboard while reducing the thermal stress applied to the electrical connection portion of the component and the wiring board, and consequently to both the electronic component and the motherboard. A wiring board having excellent electrical connection reliability can be obtained.

FIG. 1 is a top view seen through electrode pads of an electronic device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view along the thickness direction along the line II in FIG. FIG. 3 is a cross-sectional view along the plane direction along the line II-II in FIG. FIG. 4 is a cross-sectional view along the plane direction along the line III-III in FIG. It is sectional drawing cut | disconnected in the thickness direction explaining the manufacturing process of the electronic device shown in FIG.

  Hereinafter, an electronic device including a wiring board according to an embodiment of the present invention will be described in detail with reference to the drawings.

  The electronic device 1 shown in FIGS. 1 and 2 is used for electronic devices such as various audiovisual devices, home appliances, communication devices, computer devices or peripheral devices thereof. The electronic device 1 includes a mounting structure 2 and a flat mother board 4 on which the mounting structure 2 is mounted via solder balls 3.

  The mounting structure 2 includes an electronic component 5 and a flat wiring board 7 on which the electronic component 5 is flip-chip mounted via bumps 6.

  The electronic component 5 has an electrode electrically connected to the bump 6 and is a semiconductor element such as an IC or an LSI, for example, and the base material is, for example, silicon, germanium, gallium arsenide, gallium arsenide phosphorus, gallium nitride, or carbide. It is made of a semiconductor material such as silicon. The electronic component 5 has a thickness set to, for example, 0.1 mm to 1 mm, and a coefficient of thermal expansion in the plane direction (XY plane direction) and the thickness direction (Z direction) is, for example, 3 ppm / ° C. to 5 ppm / ° C. For example, the Young's modulus is set to 50 GPa or more and 200 GPa or less.

  For the thickness, the sample is cut along the thickness direction, the polished surface or fractured surface is observed with a scanning electron microscope, the length along the thickness direction is measured at 10 or more points, and the average value is calculated. Is measured. The thermal expansion coefficient is measured by a measuring method according to JISK7197-1991 using a commercially available TMA apparatus. The Young's modulus is measured using a Nano Indentor XP / DCM manufactured by MTS Systems.

  The bump 6 is made of a conductive material such as solder containing, for example, lead, tin, silver, gold, copper, zinc, bismuth, indium, or aluminum, and has a coefficient of thermal expansion in the plane direction and the thickness direction of, for example, 10 ppm / The Young's modulus is set to 10 GPa or more and 150 GPa or less, for example.

  The wiring substrate 7 includes a flat core substrate 8 and a laminated body 10 including a pair of buildup portions 9 formed on both sides of the core substrate 8, a plurality of electrode pads 11 formed on the upper surface of the laminated body 10, Including a plurality of external connection pads 12 formed on the lower surface of the multilayer body 10 and a mounting region M formed on the upper surface of the multilayer body 10, and the thickness is set to, for example, 0.2 mm or more and 1.2 mm, The thermal expansion coefficient in the plane direction is set to, for example, 8 ppm / ° C. or more and 12 ppm / ° C. or less, and the thermal expansion coefficient in the plane direction is set to, for example, two times or more and three times or less that of the electronic component 5. The rate is set to, for example, 30 ppm / ° C. or more and 50 ppm / ° C. or less.

Further, the wiring board 7 is set such that the thermal expansion coefficient in the plane direction is smaller than that of the electronic component 5 and larger than that of the mother board 4 described later. As a result, the wiring board 7 interposed between the electronic component 5 and the mother board 4 can alleviate the difference in coefficient of thermal expansion between the electronic component 5 and the mother board 4. When heat is applied to the motherboard 4, thermal stress applied to the electrical connection portion between the electronic component 5 and the wiring substrate 7, and thermal stress applied to the electrical connection portion between the wiring substrate 7 and the motherboard 4; Both of them can be reduced, and as a result, the electrical connection reliability of the electronic component 5, the wiring board 7, and the mother board 4 can be improved.

  The core substrate 8 is intended to increase the strength of the wiring substrate 7 while achieving electrical connection between the pair of build-up portions 9. The core substrate 8 has a flat base 13 and a plurality of cylindrical through holes penetrating the base 13 in the thickness direction. The hole conductor 14 and the columnar insulator 15 formed inside the through-hole conductor 14 are included, and the thickness is set to, for example, 0.1 mm or more and 1.0 mm or less.

  The base body 13 is a main part of the core substrate 5 and increases the rigidity. For example, the base body 13 includes a resin material, a base material coated with the resin material, and an inorganic insulating filler contained in the resin material. The coefficient of thermal expansion in the direction is set to, for example, 3 ppm / ° C. to 20 ppm / ° C., the coefficient of thermal expansion in the thickness direction is set to, for example, 30 ppm / ° C. to 50 ppm / ° C., and the Young's modulus is, for example, 0.2 GPa to 20 GPa It is set as follows.

  The resin material contained in the base 13 is a main part of the base 13, and for example, epoxy resin, bismaleimide triazine resin, cyanate resin, polyparaphenylene benzbisoxazole resin, wholly aromatic polyamide resin, polyimide resin, aromatic Resin materials such as group liquid crystal polyester resin, polyether ether ketone resin or polyether ketone resin can be used, and the coefficient of thermal expansion in the plane direction and thickness direction is set to 20 ppm / ° C. or more and 50 ppm / ° C. or less, for example, The Young's modulus is set to, for example, 0.1 GPa or more and 5 GPa or less.

  The base material coated with the resin material enhances the rigidity of the base 13 and has a smaller coefficient of thermal expansion in the plane direction than in the thickness direction. Therefore, thermal expansion in the plane direction of the wiring board 7 and the electronic component 5 is performed. The difference in rate can be reduced, and the warpage of the wiring board 7 can be reduced. As the base material, a woven or non-woven fabric composed of fibers, or fibers arranged in one direction can be used, and as the fibers, for example, glass fibers, resin fibers, carbon fibers or metal fibers are used. can do.

  The inorganic insulating filler contained in the resin material reduces the coefficient of thermal expansion of the base 13 and increases the rigidity of the base 13. For example, silicon oxide, aluminum oxide, aluminum nitride, aluminum hydroxide, calcium carbonate, etc. In this case, the particle size is set to 0.5 μm or more and 5.0 μm or less, the coefficient of thermal expansion is set to 0 ppm / ° C. or more and 15 ppm / ° C. or less, and the substrate 13 is used. The content in the resin material is set to 3% by volume or more and 60% by volume or less, for example.

  The particle size of the inorganic insulating filler was measured by observing the polished surface or fractured surface of the substrate 13 with a field emission electron microscope, photographing a cross-section expanded to include particles of 20 particles or more and 50 particles or less, It is measured by measuring the maximum diameter of each particle in the enlarged cross section. In addition, the content (volume%) of the inorganic insulating filler in the resin portion of the base 13 occupies the resin material of the base 13 by photographing the polished surface of the base 13 with a field emission electron microscope and using an image analyzer or the like. It is measured by measuring the area ratio (area%) of the inorganic insulating filler at 10 cross-sections, calculating the average value of the measured values, and regarding the content (volume%).

  The through-hole conductor 14 penetrating the base 13 in the thickness direction electrically connects the build-up portions 9 on the upper and lower sides of the core substrate 8, for example, a conductive material such as copper, silver, gold, aluminum, nickel, or chromium. The thermal expansion coefficient in the plane direction and the thickness direction is set to, for example, 5 ppm / ° C. or more and 25 ppm / ° C. or less, and the Young's modulus is set to, for example, 50 GPa or more and 200 GPa or less.

  The insulator 15 formed inside the through-hole conductor 14 forms a support surface of a via conductor 18 to be described later. For example, polyimide resin, acrylic resin, epoxy resin, cyanate resin, fluorine resin, silicon resin, polyphenylene What was formed with resin materials, such as an ether resin or a bismaleimide triazine resin, can be used.

  On the other hand, a pair of build-up portions 9 are formed on both sides of the core substrate 8 as described above. The build-up unit 9 includes a plurality of laminated resin layers 16, a plurality of conductive layers 17 formed on the substrate 13, between the resin layers 16, or on the resin layer 16, and a conductive layer 17 that penetrates the resin layer 16. And a plurality of via conductors 18 electrically connected to each other.

  The resin layer 16 not only functions as a support member that supports the conductive layer 17 but also functions as an insulating member that prevents a short circuit between the conductive layers 17. For example, the resin layer 16 includes inorganic material contained in the resin material and the resin material. Including an insulating filler, the thickness is set to, for example, 3 μm to 20 μm, the coefficient of thermal expansion in the thickness direction and the planar direction is set to, for example, 0 ppm / ° C. to 5 ppm / ° C., and the Young's modulus is, for example, 5 GPa to 40 GPa Is set. In addition, the resin layer 16 has a coefficient of thermal expansion in the thickness direction and the planar direction that is set to be smaller than that of the conductive layer 17 described later, and is set to be 0.1 to 0.5 times that of the conductive layer 17, for example. ing.

  Examples of the resin material contained in the resin layer 16 include epoxy resin, bismaleimide triazine resin, cyanate resin, polyparaphenylene benzbisoxazole resin, wholly aromatic polyamide resin, polyimide resin, aromatic liquid crystal polyester resin, polyether ether ketone. What was formed with resin or polyetherketone resin etc. can be used.

  As the inorganic insulating filler contained in the resin material of the resin layer 16, the same inorganic insulating filler as that contained in the substrate 13 described above can be used, and the content of the resin layer 16 in the resin material is, for example, 5 The volume is set to 65% by volume or more.

  The conductive layers 17 are spaced apart from each other in the thickness direction and are disposed on the base 13 and the resin layer 16 with a gap, and are formed of a metal material such as copper, silver, gold, aluminum, nickel, or chromium, for example. Can be used, the thickness is set to, for example, 3 μm to 20 μm, the thermal expansion coefficient in the plane direction and the thickness direction is set to, for example, 5 ppm / ° C. to 25 ppm / ° C., and the Young's modulus is 50 GPa to 250 GPa Is set to

The via conductor 18 that is electrically connected to the conductive layer 17 connects the conductive layers 17 that are spaced apart from each other in the thickness direction. For example, the via conductor 18 has a circular cross section along the plane direction and an area of the cross section. Is formed in a columnar shape that becomes smaller toward the core substrate 8, and can be formed of, for example, a conductive material of copper, silver, gold, aluminum, nickel, or chromium, and has a cross-sectional area along the plane direction. There is set to 300 [mu] m ² or more 700 .mu.m ² or less, is set below 25 ppm / ° C. coefficient of thermal expansion for example 7 ppm / ° C. or higher in the planar direction and the thickness direction, the thermal expansion coefficient resin layer in the planar direction and the thickness direction For example, 16 is set to 10 times to 50 times, and Young's modulus is set to 50 GPa or more and 250 GPa or less.

  The core substrate 8 and the pair of buildup portions 9 described above constitute a laminated body 10, and the laminated body 10 has a mounting region M on which the electronic component 5 is mounted on the upper surface. The mounting region M is a region on the upper surface of the stacked body 10 that is located immediately below the electronic component 5.

A plurality of electrode pads 11 are formed on the upper surface of the buildup portion 9 located above the core substrate 8, that is, on the upper surface of the stacked body 10. The plurality of electrode pads 7 function as a support portion for the electronic component 5 and constitute an electrical connection portion between the electronic component 5 and the wiring board 7 together with the electrodes and the bumps 6 of the electronic component 5. It is formed in a circular shape. As the electrode pad 11, the same material as the conductive layer 17 described above in terms of the constituent material, thickness, thermal expansion coefficient, or the like can be used. Further, the plurality of electrode pads 11 are arranged in a grid pattern in the mounting region M, for example.

  A plurality of external connection pads 12 are formed on the lower surface of the buildup portion 9 located below the core substrate 8, that is, on the lower surface of the stacked body 10. The plurality of external connection pads 12 constitute an electrical connection portion between the wiring board 7 and the mother board 4 together with the electrodes of the mother board 4 and the solder balls 6, and are formed, for example, in a circular shape in plan view. As the external connection pad 12, the same material as the conductive layer 17 described above in terms of the constituent material, thickness, thermal expansion coefficient, or the like can be used.

  The electrode pad 11, the external connection pad 12, the through-hole conductor 14, the conductive layer 17, and the via conductor 18 described above constitute a set of wiring portions L by being electrically connected to each other. The wiring portion L has a function of electrically connecting the mother board 4 and the electronic component 5 and is formed in a plurality of sets on the wiring substrate 7 and has a first wiring portion L1 functioning as a grounding wiring or a power supply wiring. And a second wiring portion L2 functioning as a signal wiring. Therefore, the second wiring portion L2 has a function of transmitting a signal, and the first wiring portion L1 is disposed at a predetermined position with respect to the second wiring portion L2, so that the second wiring portion L2 It has a function to improve signal transmission characteristics.

  On the other hand, the mother board 4 has its electrode electrically connected to the wiring portion L via the solder ball 3, and includes, for example, a resin material and a base material coated with the resin material, and has a thickness of 0.5 mm or more, for example. 2 mm or less, the thermal expansion coefficient in the plane direction is set to, for example, 15 ppm / ° C. or more and 20 ppm / ° C. or less, and the thermal expansion coefficient in the plane direction is set to, for example, 3 to 5 times that of the electronic component 5, The coefficient of thermal expansion in the plane direction is set to, for example, 1.2 times or more and 2 times or less that of the wiring substrate 7, and the Young's modulus is set to, for example, 3 GPa or less and 30 GPa or less.

  As the resin material included in the mother board 4, for example, an epoxy resin, a bismaleimide triazine resin or a cyanate resin can be used, and as the base material included in the mother board 4, for example, glass fibers are woven vertically and horizontally. A woven fabric or the like can be used.

  The solder ball 3 is made of a conductive material such as solder containing, for example, copper, silver, zinc, lead, tin, indium, bismuth or antimony, and has a coefficient of thermal expansion in the plane direction and thickness direction of, for example, 10 ppm / ° C. It is set to 40 ppm / ° C. or less, and the Young's modulus is set to, for example, 10 GPa or more and 150 GPa or less.

  Here, in the wiring substrate 7 of the present embodiment, the resin layer 16 is located in the buildup portion 9 above the core substrate 6 and the one located in the uppermost layer is the first resin layer 16a, and the first resin layer The second resin layer 16b is adjacent to the lower portion 16a below, and the third resin layer 16c is adjacent to the second resin layer 16b below.

  In addition, among the conductive layers 17 constituting the first wiring portion L1, those disposed between the first resin layer 16a and the second resin layer 16b serve as the first conductive layer 17a, and the second resin layer 16b and The layer disposed between the third resin layers 16c is referred to as a second conductive layer 17b. In addition, among the conductive layer 17 constituting the second wiring portion L2, the conductive layer 17 is disposed between the first resin layer 16a and the second resin layer 16b as the third conductive layer 17c, and the second resin layer 16b and The layer disposed between the third resin layers 16c is referred to as a fourth conductive layer 17d.

In the first conductive layer 17a, a region immediately below the mounting region M is a first region R1, and a region directly below the mounting region M is a second region R2. In the second conductive layer 17b, a region immediately below the mounting region M is a third region R3, and a region directly below the mounting region M is a fourth region R4.

  The first conductive layer 17a and the second conductive layer 17b are configured to surround the third conductive layer 17c and the fourth conductive layer 17d so as to surround the third conductive layer 17c and the fourth conductive layer 17d in order to enhance the function as a grounding wiring or a power supply wiring. It is formed over the entire region other than 17c and the fourth conductive layer 17d, and the area in plan view is set wider than the third conductive layer 17c and the fourth conductive layer 17d. The first conductive layer 17a and the second conductive layer 17b have an area in plan view that is set to be 250,000 times or more that of the third conductive layer 17c and the fourth conductive layer 17d, for example.

  Further, as shown in FIG. 3, the first conductive layer 17a is formed with a plurality of through holes P penetrating in the thickness direction and filled with a part of the first resin layer 16a. And a plurality of first through holes P1 formed in the first region R1 directly below the mounting region M, and a plurality of second through holes P2 formed in the second region R2 directly below the mounting region M. . Further, as shown in FIG. 4, the second conductive layer 17 b is formed with a plurality of through holes P penetrating in the thickness direction and filled with a part of the second resin layer 16 b. And a plurality of third through holes P3 formed in the third region R3 immediately below the mounting region M, and a plurality of fourth through holes P4 formed in the fourth region R4 directly below the mounting region M. .

Since the third conductive layer 17c and the fourth conductive layer 17d have a function as a land for improving the connection reliability between the via conductors 18 arranged linearly in the thickness direction, the third conductive layer 17c and the fourth conductive layer 17d have a circular shape in plan view. In order to achieve high-density wiring, the area in plan view is set smaller than the third conductive layer 17c and the fourth conductive layer 17d. The third conductive layer 17c and the second conductive layer 17d are set to have an area in a plan view of, for example, 1000 μm ² or more and 10000 μm ² or less.

  By the way, since the thermal expansion coefficient in the plane direction of the resin layer 16 described above is set to be smaller than that of the conductive layer 17, the thermal expansion coefficient of the wiring substrate 7 is reduced by reducing the thermal expansion coefficient of the resin layer 16. Although the difference in thermal expansion coefficient between the wiring board 7 and the electronic component 5 can be reduced, the difference in thermal expansion coefficient between the wiring board 7 and the mother board 4 tends to increase.

  On the other hand, in the wiring substrate 7 of the present embodiment, as shown in FIG. 3, the first conductive layer 17a has an area in a plan view of the first through hole P1 formed in the first region R1 immediately below the mounting region M. The area of the second through hole P2 formed in the second region R2 just below the mounting region M is set larger than the area in plan view.

  As a result, the volume of the conductive layer 17 having a high coefficient of thermal expansion can be easily reduced and the volume of the resin layer 16 having a low coefficient of thermal expansion can be reduced in the area immediately below the mounting area M compared to the area directly below the mounting area M. Since the ratio of the volume of the conductive material to the volume of the wiring board 3 (remaining copper ratio) can be locally reduced in the area immediately below the mounting area M, the area immediately below the mounting area M can be easily increased. Can be locally reduced.

Therefore, the thermal expansion coefficient is reduced in the area immediately below the mounting area M on the wiring board 7 where the electronic component 3 is mounted, and the decrease in the thermal expansion coefficient is alleviated in the entire area of the wiring board 7 mounted on the motherboard 4. Therefore, when heat is applied to the electronic component 3, the wiring substrate 7, and the motherboard 4, the thermal stress applied to the electrical connection portion of the electronic component 3 and the wiring substrate 7 is reduced, and the wiring substrate is reduced. 7 and the thermal stress applied to the electrical connection portion of the mother board 4 can be reduced. Therefore, the electrical connection portion between the electronic component 3 and the wiring board 7 and the wiring board 7.
In addition, it is possible to reduce the disconnection caused by the thermal stress at the electrical connection portion of the motherboard 4 and to obtain the wiring substrate 3 excellent in electrical connection reliability with both the electronic component 3 and the motherboard 4.

  In addition, since the remaining copper ratio is locally reduced in the planar direction, it is possible to reduce the warpage of the flat wiring board 7 as compared with the case where the remaining copper ratio is reduced in the thickness direction. it can.

  Further, compared to the case where the volume of the conductive layer 17 is reduced by increasing the number of through holes having the same size as the second through holes P2 in the region immediately below the mounting region M, the wiring board according to the present embodiment. 3 increases the area in plan view of each first through hole P1 in the region immediately below the mounting region M, so there is no need to increase the number of intervals between the adjacent first through holes P1, Since the total volume of the conductive layer 17 required for the interval is small, the volume of the larger number of the conductive layers 17 can be efficiently reduced within a certain region, and as a result, the mounting region where the wiring density is likely to increase. The first through holes P1 can be efficiently arranged in the region immediately below M, and the volume of the conductive layer 17 can be further reduced.

The area of the first through hole P1 in a plan view is set to, for example, 0.05 mm ² or more and 0.2 mm ² or less, and is set to, for example, 1.5 times or more and 3 times or less of the second through hole P2. Also, second through holes P2 is set to the area in plan view for example 0.03 mm ² or more 0.07 mm ² or less.

  The ratio of the total area of the plurality of first through holes P1 in the plan view to the area of the first conductive layer 17a in the plan view of the first region R1 is the area of the plurality of second through holes P2 in the plan view. Is preferably set to be larger than the ratio of the first conductive layer 17a to the area of the second region R2 in plan view. As a result, since the remaining copper ratio can be locally reduced in the region immediately below the mounting region M, the thermal expansion coefficient in the region immediately below the mounting region M can be locally reduced.

  The ratio of the total area of the plurality of first through holes P1 in the plan view to the area of the first conductive layer 17a in the plan view of the first region R1 is the plan view of the plurality of second through holes P2. The total value of the areas is set to, for example, 0.4 to 0.8 times the ratio of the second region R2 of the first conductive layer 17a to the area in plan view.

  The first conductive layer 17a is formed with a land through-hole PL penetrating in the thickness direction so as to be separated from and surrounded by the third conductive layer 17c functioning as a land. The gap G between the layer 17a and the third conductive layer 17c is filled with a part of the first resin layer 16a, and the first through hole P1 is set to have a larger area in plan view than the land through hole PL. ing. As a result, by forming the third conductive layer 17c small, high-density wiring is possible, and the distance from the third conductive layer 17c is set to a predetermined distance from the viewpoint of signal transmission characteristics, and the size is set. By making the first through hole P1 larger than the land through hole PL, the remaining copper ratio can be locally reduced in the region immediately below the mounting region M. The area of the second through hole P2 in plan view is set smaller than, for example, the land through hole PL.

  The first conductive layer 17 a and the second conductive layer 17 b are preferably formed in the buildup portion 9 above the core substrate 6. As a result, the stress applied to the electrical connection portion between the electronic component 5 and the wiring board 7 is reduced, and the decrease in the stress applied to the electrical connection portion between the wiring board 7 and the mother board 4 is further alleviated. Can do. Furthermore, as in the first conductive layer 17a and the second conductive layer 17b, the through hole P formed in the region directly below the mounting region M has an area in plan view of the through hole P formed in the region immediately below the mounting region M. It is desirable that the conductive layer 17 larger than the area in the plan view is formed only in the buildup portion 9 above the core substrate 6.

  As shown in FIG. 4, the second conductive layer 17b has a third through-hole P3 formed in the third region R3 immediately below the mounting region M, and the fourth region R4 outside the mounting region M has an area in plan view. It is formed larger than the fourth through-hole P4 formed in. As a result, similarly to the first conductive layer 17a, the remaining copper ratio can be locally reduced in the region immediately below the mounting region M.

  Further, the third through hole P3 formed in the second conductive layer 17b is separated from the first through hole P1 formed in the first conductive layer 17a in plan view. As a result, the first through-hole P1 and the second through-hole P2 that are likely to concentrate stress on the inner wall surface, which is the interface between the resin layer 16 and the conductive layer 17, are separated in plan view, so that the first Cracks of the second resin layer 16b between the first through hole P1 and the second through hole P2 can be reduced.

  Next, a method for manufacturing the mounting structure 2 described above will be described.

  (1) The core substrate 8 is prepared. Specifically, this is performed as follows.

  First, for example, a plurality of resin sheets including an uncured resin and a base material are stacked, and the base 13 is produced by heating and pressing to cure the uncured resin. The uncured state is an A-stage or B-stage according to ISO 472: 1999. Next, a plurality of through holes penetrating the base 13 in the thickness direction are formed by, for example, drilling or laser processing. Next, a cylindrical through-hole conductor 14 is formed by depositing a conductive material on the inner wall of the through-hole by, for example, electroless plating, vapor deposition, CVD, sputtering, or the like. Further, a conductive material layer is formed by depositing a conductive material on the upper surface and the lower surface of the base 13. Next, the inside of the cylindrical through-hole conductor 14 is filled with a resin material or the like to form the insulator 15. Next, after a conductive material is deposited on the exposed portion of the insulator 15, the conductive layer material layer is patterned by a conventionally known photolithography technique, etching or the like to form the conductive layer 17.

  As described above, the core substrate 8 shown in FIG. 5A can be manufactured.

  (2) A pair of build-up portions 9 are formed on both sides of the core substrate 8, and the electrode pads 11 and the external connection pads 12 are formed, thereby producing the wiring substrate 7. Specifically, this is performed as follows.

  First, an uncured resin is disposed on the conductive layer 17, and the resin layer 16 is formed on the conductive layer 17 by further heating and curing the resin while heating and fluidly adhering the resin. Next, a via hole V is formed in the resin layer 16 by, for example, a YAG laser device or a carbon dioxide gas laser device, and at least a part of the conductive layer 17 is exposed in the via hole V. Next, the via conductor 13 is formed in the via hole V and the second conductive layer 17b is formed on the upper surface of the resin layer 16 by, for example, a semi-additive method, a subtractive method, or a full additive method.

  In addition, the 3rd through-hole P3 and the 4th through-hole P4 can be formed by patterning the 2nd conductive layer 17b in arbitrary shapes in the case of this 2nd conductive layer 17b formation.

  By repeating this process, the build-up part 9 can be formed. In addition, when the conductive layer 17 is formed on the uppermost layer and the lowermost resin layer 16, the electrode pad 11 and the external connection pad 12 can be formed in the same manner as the conductive layer 17. Further, the first conductive layer 17a can be formed in the same manner as the second conductive layer 17b.

  As described above, the wiring board 7 shown in FIG. 5B can be manufactured.

  (3) The bump 6 is formed on the upper surface of the electrode pad 11 and the electronic component 5 is flip-chip mounted on the wiring board 7 via the bump 6.

  As described above, the mounting structure 2 shown in FIG. 5c can be manufactured.

  (4) The solder ball 3 is formed on the lower surface of the external connection pad 12 and the mounting structure 2 is flip-chip mounted on the mother board 4 via the solder ball 3.

  As described above, the electronic device 1 shown in FIGS. 1 and 2 can be manufactured.

  The present invention is not limited to the above-described embodiments, and various modifications, improvements, combinations, and the like can be made without departing from the spirit of the present invention.

  For example, in the above-described embodiment, the configuration using a semiconductor element as an electronic component has been described as an example, but a capacitor or the like may be used as the electronic component.

  Further, in the achieved embodiment, the configuration in which the electronic component is flip-chip mounted on the wiring board has been described as an example, but the electronic component may be mounted on the wiring board by wire bonding.

  In the above-described embodiment, the configuration in which the build-up portion is formed by three resin layers has been described as an example, but any number of resin layers may be used.

  In the above-described embodiment, the configuration using the resin as the material for the base and the insulating layer has been described as an example. However, the base and the insulating layer are made of a metal material coated with a resin material or a ceramic. You may use things.

  In the above-described embodiment, the conductive layer in which the area in plan view of the through hole formed in the region immediately below the mounting region is larger than the area in plan view of the through hole formed in the region directly under the mounting region is the core The configuration formed only in the buildup part above the substrate has been described as an example, but in all conductive layers, the area in the plan view of the through hole formed in the region immediately below the mounting region is formed in the region directly below the mounting region. It may be larger than the area of the formed through hole in plan view.

DESCRIPTION OF SYMBOLS 1 Electronic device 2 Mounting structure 3 Solder ball 4 Mother board 5 Electronic component 6 Bump 7 Wiring board 8 Core board 9 Build-up part 10 Laminated body 11 Electrode pad
12 External Connection Pad 13 Base 14 Through-hole Conductor 15 Insulator 16 Resin Layer 17 Conductive Layer 18 Via Conductor M Mounting Area P Through-hole G Gap

Claims (8)

A laminate including a resin layer and a conductive layer having a larger coefficient of thermal expansion than the resin layer, and having a mounting region for mounting an electronic component on the upper surface;
The conductive layer has a first conductive layer that penetrates in the thickness direction and has a plurality of through holes filled with a part of the resin layer,
The first conductive layer includes a first region that is a region immediately below the mounting region, and a second region that is a region immediately below the mounting region,
The plurality of through holes include a plurality of first through holes formed in a first region of the first conductive layer and a plurality of second through holes formed in a second region of the first conductive layer. Including
The wiring substrate, wherein the first through hole has a larger area in plan view than the second through hole. The wiring board according to claim 1,
The ratio of the total value of the areas of the plurality of first through holes in plan view to the area of the first region of the first conductive layer in plan view is the ratio of the area of the plurality of second through holes in plan view. The wiring board, wherein the total value is larger than a ratio of the first conductive layer to the area of the second region in plan view. The wiring board according to claim 1,
The wiring substrate according to claim 1, wherein the first through hole has an area in a plan view that is set to be 1.5 to 3 times that of the second through hole. The wiring board according to claim 1,
The wiring board according to claim 1, wherein the first conductive layer is for grounding or for power supply. The wiring board according to claim 1,
The first conductive layer is further formed with a plurality of land through holes penetrating in the thickness direction,
A land disposed in the through hole for the land and spaced from the first conductive layer;
A portion of the resin layer is filled between the first conductive layer and the land,
The first through hole has a larger area in plan view than the land through hole. The wiring board according to claim 1,
The conductive layer is formed with a plurality of through holes penetrating in the thickness direction and filled with a part of the resin layer, and a second conductive layer adjacent to the first conductive layer in the thickness direction is formed. In addition,
The second conductive layer includes a third region that is a region immediately below the mounting region, and a fourth region that is a region immediately below the mounting region,
The plurality of through holes formed in the second conductive layer include a plurality of third through holes formed in the third region of the second conductive layer and a plurality of holes formed in the fourth region of the second conductive layer. A fourth through hole, and
The wiring board, wherein the third through hole has a larger area in plan view than the fourth through hole and is separated from the first through hole in plan view. The wiring board according to claim 1;
An electronic component mounted in the mounting region of the wiring board and electrically connected to the conductive layer;
A mounting structure characterized by comprising: The mounting structure according to claim 7,
A motherboard mounted with the mounting structure and electrically connected to the conductive layer;
A mounting structure characterized by comprising:

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