JP2011172425A - Gate drive circuit for bidirectional switch, and inverter or matrix converter using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gate drive circuit used for a GaN bidirectional switch having a double gate, in which shift to a reverse blocking mode (first mode or second mode) enabling conduction in only one or only the another out of the bidirections is speeded up. <P>SOLUTION: The gate drive circuit has a configuration in which at least either a first source terminal 4 or a second source terminal 5 is connected in series to a first gate resistance 18A (18B) and a second gate resistance 19A (19B) respectively, and a diode 21A (21B) as a bypass member capable of applying current to a connection point 20A (20B) when difference between source potentials occurs between a connection point 20A of the first gate resistances 18A and the second gate resistance 19A and a connection point 20B of the first gate resistance 18B and the second gate resistance 19B is provided. Thus, the gate drive circuit is obtained in which electricity conduction in the reverse blocking mode is achieved by applying a gate current via the diodes 21A or 21B when the potential of either the first source terminal 4 or the second source terminal 5 increases. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a gate drive circuit of a bidirectional switch used as a semiconductor of a motor drive device, and an inverter or matrix converter using the same.

  Conventionally, although this type of gate drive circuit is not used, a circuit in which an anti-series circuit of Zener diodes is connected as a spike voltage suppression circuit for a bidirectional switch is known. (For example, refer to Patent Document 1).

  The spike voltage suppression circuit will be described below with reference to FIG.

  As shown in FIG. 11, Zener diodes 105A and 105B are connected between the gates 103A and 103B and the collectors 104A and 104B of the transistors 101A and 101B of the semiconductor bidirectional switch 102 in which the transistors 101A and 101B are connected in reverse series. The anti-series circuit of the diodes 106A and 106B is connected. If either of the collectors 104A or 104B is connected to the inductive load or the like of the semiconductor bidirectional switch 102, a spike voltage is generated in the collector 104A or 104B, but the terminal voltage of the collector 104A or 104B increases. At the same time, the voltage of the Zener diode 105A or 105B increases. Further, the terminal voltage of the semiconductor bidirectional switch 102 continues to rise. Thereafter, when the voltage of the Zener diode 105A or 105B reaches the Zener voltage, the Zener diode 105A or 105B becomes conductive, and a current flows through the gate 103A or 103B of the transistor 101A or 101B. As a result, the transistor 101A or 101B is turned on again in the active state. As described above, since the voltage of the transistor 101A or 101B is clamped by the Zener voltage of the Zener diode 105A or 105B, the spike voltage can be suppressed.

  Some of these types of gate drive circuits are connected from a CMOS driver to a semiconductor switch via a gate resistor. (For example, refer to Patent Document 2).

  The gate drive circuit will be described below with reference to FIG.

  As shown in FIG. 12, the power conversion device using the bidirectional switch 108 in which the reverse blocking IGBTs 107A and 107B are connected in antiparallel to each other as the switching element includes the current detection means 110A of the gate terminals 109A and 109B of the reverse blocking IGBTs 107A and 107B. 110B and a comparison means 111 for comparing the detected current value are provided to detect the reverse blocking IGBT 107A or 107B to which the reverse voltage is applied and to turn on the gate terminal 109A or 109B. It has a configuration.

JP 2001-111398 A JP 2006-166582 A

  In such a conventional spike voltage suppression circuit in Patent Document 1, when the Zener voltage is reached, a current flows to the gate terminal via the Zener diode, and the transistor can be turned on, but the Zener voltage is reached. The time until the transistor keeps the off state, and the time until the transistor starts to become conductive becomes longer. In recent years, while high-speed switching devices such as SiC and GaN have begun to spread, it is necessary to shorten the time until the gate current flows through the Zener diode in order to maximize the potential. In this state, for example, when an inductive load is connected as a load and the time until the transistor turns on is long, a path through which the return current from the inductive load flows cannot be secured, and the potential of the emitter terminal or collector terminal of the transistor suddenly increases. It had the subject that it will raise | generate and reliability may fall.

  Further, in the conventional gate drive circuit in Patent Document 2, when an inductive load is connected in the same manner, when the current flows to the gate terminal and the reverse blocking IGBT is turned on, the gate terminal is actively driven. It is necessary to construct a complicated and high-speed sequence to be performed, or to secure a path for passing a current to the gate terminal via the CMOS and gate resistance. At this time, it is necessary to actively use the parasitic diode, that is, the parasitic diode inside the CMOS, that is, the parasitic diode, and this type of gate drive circuit has a problem of deteriorating the reliability of the device. It was. Also, if it is connected to only one gate resistor or connected in series, the current is supplied to the gate terminal via multiple gate resistors, so only the current based on the current value for driving the gate is supplied. It was not possible and had the subject of deteriorating responsiveness.

  Therefore, the present invention solves the above-described conventional problems, and connects at least one of the first source terminal or the second source terminal, the first gate resistance, and the second gate resistance in series, and the first gate resistance A bypass means capable of allowing a current to flow to the connection point side of the first gate resistor and the second gate resistor when a source potential fluctuation occurs between the intermediate point connected in series with the second gate resistor, and By doing so, it is possible to form a low-impedance circuit different from the current path for gate current for normal gate driving, shortening the time until turn-on, that is, preventing increase in loss of the bidirectional switch, ensuring reliability, An object of the present invention is to provide a bidirectional switch gate drive circuit capable of maximizing the potential of a high-speed switching device.

  In order to achieve this object, the present invention provides a semiconductor layer stack having a channel formed on a substrate and a first ohmic formed on the semiconductor layer stack at a distance from each other. A first gate electrode and a second gate formed in order from the first ohmic electrode side between the electrode and the second ohmic electrode, and between the first ohmic electrode and the second ohmic electrode; An electrode, a first p-type semiconductor layer formed between the semiconductor layer stack and the first gate electrode, and a second formed between the semiconductor layer stack and the second gate electrode. A first gate terminal for inputting a gate drive signal between the first ohmic electrode and the first gate electrode, the second ohmic electrode, and the second gate. Gate drive signal between electrodes A second source terminal connected to the first ohmic electrode, a second source terminal connected to the second ohmic electrode, and turning on only the first gate terminal. The first mode in which the bidirectional device in the ON state and the reverse diode are connected in series from the first source terminal to the second source terminal and operating as a semiconductor connected in series, turning on only the second gate terminal, A second mode in which a forward diode and an on-state bidirectional device operate as a semiconductor connected in series from the first source terminal to the second source terminal, the first gate terminal and the second gate terminal are turned on. Then, the third mode, which operates so as to conduct in a bidirectional manner without a diode between the first source terminal and the second source terminal, the first gate A gate drive circuit applied to a bidirectional switch having a fourth mode that cuts off current in both forward and reverse directions when the child and the second gate terminal are turned off, and at least one of the first source terminal and the second source terminal One of the first gate resistor and the second gate resistor is connected in series, and when the source potential fluctuates between the first gate resistor and the middle point of the second gate resistor connected in series, the first Bypass means capable of allowing current to flow to the connection point side of the gate resistance and the second gate resistance is provided, thereby achieving the intended purpose.

  According to the present invention, a semiconductor layer stack having a channel formed on a substrate, and a first ohmic electrode and a second ohmic electrode formed on the semiconductor layer stack at a distance from each other; A first gate electrode and a second gate electrode formed in order from the first ohmic electrode side between the first ohmic electrode and the second ohmic electrode, and the semiconductor layer stack And a first p-type semiconductor layer formed between the semiconductor layer stack and the second gate electrode. , A first gate terminal for inputting a gate drive signal between the first ohmic electrode and the first gate electrode, and a gate drive signal between the second ohmic electrode and the second gate electrode. Input the second gate terminal and the front A first source terminal connected to the first ohmic electrode; and a second source terminal connected to the second ohmic electrode; when only the first gate terminal is turned on, the first source terminal A first mode in which an on-state bidirectional device and a reverse diode operate as a semiconductor connected in series toward two source terminals. When only the second gate terminal is turned on, the first source terminal to the second source A second mode in which a forward diode and an on-state bidirectional device operate as a semiconductor connected in series toward the terminals, when the first gate terminal and the second gate terminal are turned on, from the first source terminal A third mode that operates to conduct in both directions without a diode between the second source terminals, the first gate terminal and the second gate terminal A gate drive circuit applied to a bidirectional switch having a fourth mode that cuts off current in both forward and reverse directions when turned off, comprising at least one of the first source terminal or the second source terminal and a first gate resistor, A second gate resistor is connected in series, and when a source potential fluctuation occurs between the first gate resistor and the middle point of the second gate resistor connected in series, the first gate resistor and the second gate resistor By providing a bypass means capable of flowing current to the connection point side, the inductive load is connected, and the return current from the inductive load is energized in the state of the first mode or the second mode of the bidirectional switch. Even if the first gate terminal or the second gate terminal is turned off, a small current is passed through the gate terminal and the parasitic capacitance between the gate terminal and the source terminal. The amount of time required to open the gate by increasing the voltage between the gate terminal and the source terminal at a higher speed and charging the reflux current at a higher speed can be achieved. There is no need to provide a path for supplying a special current in parallel between the source terminals, and it is possible to obtain an effect that an inexpensive gate driving circuit can be formed with a simple configuration.

The figure which shows the structure of the bidirectional | two-way switch of Embodiment 1 of this invention. Equivalent circuit diagram of the bidirectional switch ((a) Equivalent circuit diagram composed of first and second transistors, (b) Equivalent circuit diagram of the second transistor, (c) The second transistor is regarded as a diode. Equivalent circuit diagram) Voltage / current correlation diagram of the bidirectional switch ((a) A diagram showing a case where Vg1 and Vg2 are changed simultaneously, (b) A case where Vg2 is changed to 0 V below the second threshold voltage and Vg1 is changed. (C) The figure which shows the case where Vg2 is changed by setting Vg1 to 0 V below the first threshold voltage) Diagram showing the operation mode of the bidirectional switch Configuration diagram of the gate drive circuit Configuration diagram of a gate drive circuit according to a second embodiment of the present invention Configuration diagram of the gate drive circuit of Embodiment 3 of the present invention Configuration diagram of a gate drive circuit according to a fourth embodiment of the present invention The block diagram of the inverter using the gate drive circuit provided with the bypass means of Embodiment 5 of this invention The block diagram of the matrix converter using the gate drive circuit provided with the bypass means of Embodiment 6 of this invention The figure which shows the spike voltage suppression (gate drive) circuit in the conventional patent document 1 The figure which shows the gate drive circuit in the conventional patent document 2

  According to a first aspect of the present invention, there is provided a bidirectional switch gate drive circuit comprising: a semiconductor layer stack having a channel formed on a substrate; and a semiconductor layer stack formed on the semiconductor layer stack at a distance from each other. A first gate electrode and a second ohmic electrode, and a first gate electrode and a second ohmic electrode, which are sequentially formed from the first ohmic electrode side between the first ohmic electrode and the second ohmic electrode. Two gate electrodes, a first p-type semiconductor layer formed between the semiconductor layer stack and the first gate electrode, and between the semiconductor layer stack and the second gate electrode. A first gate terminal for inputting a gate drive signal between the first ohmic electrode and the first gate electrode, the second ohmic electrode, and the first ohmic electrode. Between the two gate electrodes A second gate terminal for inputting a driving signal; a first source terminal connected to the first ohmic electrode; and a second source terminal connected to the second ohmic electrode, wherein only the first gate terminal is provided. When ON is turned on, only the second gate terminal is turned on in the first mode in which the bidirectional device and the reverse diode are connected in series from the first source terminal to the second source terminal. Then, a second mode in which a forward diode and an on-state bidirectional device operate as a semiconductor connected in series from the first source terminal to the second source terminal, the first gate terminal and the second gate When the terminal is turned on, the third mode, which operates so as to conduct in a bidirectional manner without a diode between the first source terminal and the second source terminal, A gate driving circuit applied to a bidirectional switch having a fourth mode that cuts off current in both forward and reverse directions when the first gate terminal and the second gate terminal are turned off, wherein the first source terminal or the second source terminal When at least one of the first gate resistance and the second gate resistance is connected in series, and a source potential fluctuation occurs between the first gate resistance and the middle point of the second gate resistance connected in series A configuration is provided in which bypass means capable of flowing a current to the connection point side of the first gate resistor and the second gate resistor is provided. As a result, the bidirectional switch is in the first mode or the second mode, that is, either the first gate terminal or the second gate terminal is in the off state, and corresponds to the first gate terminal or the second gate terminal in the off state. When the potential on the first source terminal or the second source terminal side that rises, current can flow to the connection point side of the first gate resistance and the second gate resistance through the bypass means according to the rise in potential. Therefore, the parasitic capacitance between the first gate terminal and the first source terminal or the parasitic capacitance between the second gate terminal and the second source terminal can be charged faster, and the bidirectional switch can be Even in the second mode, the same conduction speed as that in the third mode can be secured.

  According to a second aspect of the present invention, the bypass means has a configuration in which the bypass means can flow a current from the connection point side of the first gate resistor and the second gate resistor to the source terminal side. As a result, when an inductive load is connected and the potential on the source terminal side decreases due to continuous pulling by the inductance component, current can flow from the gate terminal side to the source terminal side, which is more stable. The gate driving can be performed.

  In the bidirectional switch gate drive circuit according to claim 3, the bypass means has a configuration of a diode. As a result, while the current from the gate terminal to the source terminal side is blocked, the current can flow through the diode when the potential on the source terminal side rises. This is advantageous in that it can be realized with a simpler and lower cost circuit configuration.

  According to another aspect of the gate drive circuit of the bidirectional switch, the bypass means is constituted by a constant current diode. As a result, when the potential on the source terminal side rises while blocking the current from the gate terminal to the source terminal side, the current can flow through the constant current diode. While limiting, the bypass can be achieved with a simple configuration, and an effect is achieved that a more stable gate drive and a simple and low-cost circuit configuration can be realized.

  In the bidirectional switch gate drive circuit according to claim 5, the bypass means includes a constant voltage diode. As a result, the current from the gate terminal to the source terminal flows only when the Zener voltage is exceeded, and the current from the source terminal to the gate terminal flows the current according to the increase in the potential of the source terminal. Therefore, while limiting the voltage applied to the gate terminal side, the parasitic capacitance between the first gate terminal and the first source terminal or the parasitic capacitance between the second gate terminal and the second source terminal is limited. The battery can be charged at a higher speed, and even when the bidirectional switch is in the first mode or the second mode, the same conduction speed as that in the third mode can be secured.

  In the bidirectional switch gate drive circuit according to claim 6, the bypass means is connected only to the first gate terminal or the second gate terminal corresponding to the first source terminal or the second source terminal on the low potential side. Have As a result, when the polarity of the input voltage is not reversed and the polarity is fixed as in an inverter or the like, parts are not required, so that an effect can be realized with a cheaper circuit configuration.

  The bidirectional switch gate drive circuit according to claim 7 has a configuration in which the bypass means is connected to both the first gate terminal and the second gate terminal. As a result, the polarity of the input voltage is reversed by reversing the polarity of the input voltage as in a matrix converter, etc., so that when the potential on the first source terminal or second source terminal side rises alternately, Since the current can flow to the connection point side of the first gate resistor and the second gate resistor through the bypass means, the parasitic capacitance between the first gate terminal and the first source terminal or the second gate terminal and the second source The parasitic capacitance between the terminals can be charged faster, and even when the bidirectional switch is in the first mode or the second mode, the same conduction speed as the third mode can be secured. .

  In the bidirectional switch gate drive circuit according to claim 8, the bypass means has a configuration shared with a constant voltage diode having a gate drive power supply voltage as a desired voltage. As a result, the gate drive power supply voltage is limited by the constant voltage diode, and when the potential at the first source terminal or the second source terminal rises, the first gate resistor and the second gate through the bypass means according to the rise in potential. Since current can flow to the connection point side of the two-gate resistor, the parasitic capacitance between the first gate terminal and the first source terminal or the parasitic capacitance between the second gate terminal and the second source terminal is more It is possible to charge at high speed, and even if the bidirectional switch is in the first mode or the second mode, it is possible to ensure the same conduction speed as the third mode, and at the same time, it can be realized with a cheaper circuit configuration There is an effect.

  The gate drive circuit of the bidirectional switch according to claim 9 is configured such that the first gate resistor connected to the source terminal side is shared with a resistor that changes the oscillation frequency due to the inductance and parasitic capacitance of the lead of the bidirectional switch. Have. As a result, the gate current is limited by the first gate resistor and the oscillation frequency due to the inductance and parasitic capacitance of the bidirectional switch lead is shared for two purposes. There is an effect that can be realized.

  According to a tenth aspect of the present invention, there is provided a bidirectional switch gate drive circuit including a speed-up circuit for improving a turn-off speed in parallel with the second gate resistor. As a result, the turn-off time is shortened, so that the balance with the turn-on time having a short switching time is achieved, and the system can be more stable.

  In the bidirectional switch gate drive circuit according to claim 11, the speed-up circuit has a configuration in which a third gate resistor and a diode are connected in series. As a result, the speed-up circuit can be configured with a simple configuration, so that an effect can be realized with a more inexpensive configuration.

  According to a twelfth aspect of the present invention, an inverter using the bidirectional switch gate drive circuit has a configuration using a bidirectional switch gate drive circuit including a bypass means. As a result, the speed of the gate drive of each bidirectional switch of the inverter is further increased, so that there is an effect that a reduction in size and a reduction in size due to a reduction in loss can be realized.

  A matrix converter using a bidirectional switch gate drive circuit according to claim 13 has a configuration using a bidirectional switch gate drive circuit including a bypass means. As a result, the gate drive of each bidirectional switch of the matrix converter can be speeded up, so that the loss can be reduced and the size can be reduced by reducing the loss, and when an inductive load is connected, the short circuit can be prevented. There is an effect that downsizing can be realized by reducing the capacitance of the capacitor inside the clamp circuit which prevents the increase of the inductive load terminal voltage due to the provided dead time.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
First, the configuration of the bidirectional switch 1 will be described with reference to FIG. As shown in FIG. 1, the bidirectional switch 1 includes a first gate terminal 2, a second gate terminal 3, a first source terminal 4, and a second source terminal 5. The bidirectional switch 1 has a thickness of 1 μm formed by alternately laminating 10 nm thick aluminum nitride (AlN) and 10 nm thick gallium nitride (GaN) on a substrate 6 made of silicon (Si). A buffer layer 7 is formed, and a semiconductor layer stack 8 is formed thereon. In the semiconductor layer stacked body 8, a first semiconductor layer and a second semiconductor layer having a band gap larger than that of the first semiconductor layer are sequentially stacked from the substrate side. The first semiconductor layer is a GaN (undoped gallium nitride) layer 9 having a thickness of 2 μm, and the second semiconductor layer is an n-type AlGaN (aluminum gallium nitride) layer 10 having a thickness of 20 nm. In the vicinity of the hetero interface between the GaN layer 9 and the AlGaN layer 10, charges are generated due to spontaneous polarization and piezoelectric polarization. Accordingly, and mobility 1 × 1013cm- ² or sheet carrier concentration channel region is generated a 1000 cm ² V / sec or more two-dimensional electron gas (2DEG) layer. That is, the semiconductor layer stack 8 has a channel region that is a two-dimensional electron gas (2DEG) layer and is formed on the substrate. On the semiconductor layer stacked body 8, a first ohmic electrode 11A and a second ohmic electrode 11B are formed at a distance from each other. The first ohmic electrode 11A and the second ohmic electrode 11B are formed by stacking titanium (Ti) and aluminum (Al), and form an ohmic junction with the channel region. Further, in order to reduce the contact resistance, a part of the AlGaN layer 10 is removed and the GaN layer 9 is dug down by about 40 nm, so that the first ohmic electrode 11A and the second ohmic electrode 11B become the AlGaN layer 10 and the GaN layer 9. The example formed so that it may contact | connect an interface with is shown. Note that the first ohmic electrode 11 </ b> A and the second ohmic electrode 11 </ b> B may be formed on the AlGaN layer 10. In the region between the first ohmic electrode 11A and the second ohmic electrode 11B on the n-type AlGaN layer 10, the first p-type semiconductor layer 12A and the second p-type semiconductor layer 12B are spaced from each other. And selectively formed. A first gate electrode 13A is formed on the first p-type semiconductor layer 12A, and a second gate electrode 13B is formed on the second p-type semiconductor layer 12B. The first gate electrode 13A and the second gate electrode 13B are each formed by stacking palladium (Pd) and gold (Au), and the first p-type semiconductor layer 12A and the second p-type semiconductor layer 12B. Ohmic contact. A protective film 14 made of silicon nitride (SiN) is formed so as to cover the AlGaN layer 10, the first p-type semiconductor layer 12A, and the second p-type semiconductor layer 12B. By forming the protective film 14, it is possible to ensure a defect that causes so-called current collapse and to improve current collapse. The first p-type semiconductor layer 12A and the second p-type semiconductor layer 12B each have a thickness of 300 nm and are made of p-type GaN doped with magnesium (Mg). The first p-type semiconductor layer 12A, the second p-type semiconductor layer 12B, and the AlGaN layer 10 form PN junctions. As a result, when the voltage between the first ohmic electrode 11A and the first gate electrode 13A is 0 V, for example, the depletion layer spreads from the first p-type GaN layer into the channel region, so that the current flowing through the channel is cut off. Similarly, when the voltage between the second ohmic electrode 11B and the second gate electrode 13B is, for example, 0 V or less, a depletion layer spreads from the second p-type GaN layer into the channel region. Thus, a semiconductor element capable of interrupting a current flowing through the channel and performing a so-called normally-off operation is realized. The potential of the first ohmic electrode 11A is V1, the potential of the first gate electrode 13A is V2, the potential of the second gate electrode 13B is V3, and the potential of the second ohmic electrode 11B is V4. In this case, if V2 is higher than V1 by 1.5V or more, the depletion layer extending from the first p-type semiconductor layer 12A into the channel region is reduced, so that a current can flow in the channel region. Similarly, if V3 is higher than V4 by 1.5V or more, the depletion layer extending from the second p-type semiconductor layer 12B into the channel region is reduced, and current can flow through the channel region. That is, the so-called threshold voltage of the first gate electrode 13A and the so-called threshold voltage of the second gate electrode 13B are both 1.5V. In the following, the threshold voltage of the first gate electrode 13A at which the depletion layer extending in the channel region below the first gate electrode 13A is reduced and current can flow through the channel region is set to the first threshold voltage. The threshold voltage is set to the second gate electrode 13B so that the depletion layer extending in the channel region on the lower side of the second gate electrode 13B is reduced and current can flow in the channel region. The threshold voltage is used. The distance between the first p-type semiconductor layer 12A and the second p-type semiconductor layer 12B can withstand the maximum voltage applied to the first ohmic electrode 11A and the second ohmic electrode 11B. Constitute.

  That is, the bidirectional switch 1 includes a semiconductor layer stack 8 having a channel region, a first ohmic electrode 11A and a second ohmic electrode 11B formed on the semiconductor layer stack 8 with a space therebetween, A first p-type semiconductor layer 12A and a second p-type semiconductor layer 12B formed in order from the first ohmic electrode 11A side between the first ohmic electrode 11A and the second ohmic electrode 11B; A substrate comprising a first gate electrode 13A formed on one p-type semiconductor layer 12A and a second gate electrode 13B formed on a second p-type semiconductor layer 12B; A first source terminal 4 connected to the ohmic electrode 11A; a second source terminal 5 connected to the second ohmic electrode 11B; a first gate terminal 2 connected to the first gate electrode 13A; Composed of the second gate terminal 3 connected to the second gate electrode 13B.

  Next, the operation of the bidirectional switch 1 will be described. For explanation, the potential of the first ohmic electrode 11A is set to 0V, the voltage applied to the first gate terminal 2 is Vg1, the voltage applied to the second gate terminal 3 is Vg2, and the second ohmic electrode 11B and the first The voltage between the ohmic electrode 11A is Vs2s1, and the current flowing between the second ohmic electrode 11B and the first ohmic electrode 11A is Is2s1.

  When V4 is higher than V1, for example, when V4 is + 100V and V1 is 0V, the input voltages Vg1 and Vg2 of the first gate terminal 2 and the second gate terminal 3 are set to the first threshold voltage and the first threshold voltage, respectively. A voltage equal to or lower than a threshold voltage of 2, for example, 0V. As a result, the depletion layer extending from the first p-type semiconductor layer 12A extends in the channel region toward the second p-type GaN layer, so that the current flowing through the channel can be blocked. Therefore, even when V4 is a positive high voltage, it is possible to realize a cut-off state in which a current flowing from the second ohmic electrode 11B to the first ohmic electrode 11A is cut off. On the other hand, when V4 is lower than V1, for example, even when V4 is −100 V and V1 is 0 V, the depletion layer extending from the second p-type semiconductor layer 12B is in the channel region in the first p-type semiconductor layer. The current spreads in the direction of 12A and can flow through the channel. For this reason, even when a negative high voltage is applied to the second ohmic electrode 11B, the current flowing from the first ohmic electrode 11A to the second ohmic electrode 11B can be blocked. That is, the bidirectional current of the bidirectional switch 1 can be cut off.

  In the structure and operation as described above, the first gate electrode 13A and the second gate electrode 13B share a channel region for ensuring a withstand voltage. In this device, the bidirectional switch 1 can be realized with the area of the channel region for one device. Considering the entire bidirectional switch 1, two diodes and two normally-off type AlGaN / GaN-HFETs are provided. The chip area can be reduced as compared with the case where it is used, and the bidirectional switch 1 can be reduced in cost and size.

  Next, when the input voltages Vg1 and Vg2 of the first gate terminal 2 and the second gate terminal 3 are higher than the first threshold voltage and the second threshold voltage, respectively, for example, 5V, the first voltage Both of the voltages applied to the gate electrode 13A and the second gate electrode 13B are higher than the threshold voltage. Accordingly, since the depletion layer does not extend from the first p-type semiconductor layer 12A and the second p-type semiconductor layer 12B to the channel region, the channel region is also formed below the first gate electrode 13A. It is not pinched off on the lower side of 13B. As a result, it is possible to realize a conductive state in which a current flows bidirectionally between the first ohmic electrode 11A and the second ohmic electrode 11B.

  Next, the operation when Vg1 is higher than the first threshold voltage and Vg2 is equal to or lower than the second threshold voltage will be described. When the bidirectional switch 1 having the first gate terminal 2 and the second gate terminal 3 is represented by an equivalent circuit, a first transistor 15 and a second transistor 16 are connected in series as shown in FIG. It can be regarded as a circuit. In this case, the source (S) of the first transistor 15 corresponds to the first ohmic electrode 11A, the gate (G) of the first transistor 15 corresponds to the first gate electrode 13A, and the source ( S) corresponds to the second ohmic electrode 11B, and the gate (G) of the second transistor 16 corresponds to the second gate electrode 13B. In such a circuit, for example, when Vg1 is 5V and Vg2 is 0V, the fact that Vg2 is 0V is equivalent to the state where the gate and the source of the second transistor 16 are short-circuited. Can be regarded as a circuit as shown in FIG.

  Further, description will be made assuming that the source (S) of the second transistor 16 shown in FIG. 2B is the A terminal, the drain (D) is the B terminal, and the gate (G) is the C terminal. When the potential of the B terminal shown in the figure is higher than the potential of the A terminal, it can be regarded as a transistor in which the A terminal is a source and the B terminal is a drain. In such a case, the C terminal (gate) and the A terminal Since the voltage between the source and the source is 0 V and is equal to or lower than the threshold voltage, no current flows from the B terminal (drain) to the A terminal (source). On the other hand, when the potential of the A terminal is higher than the potential of the B terminal, the transistor can be regarded as a transistor in which the B terminal is a source and the A terminal is a drain. In such a case, since the potentials of the C terminal (gate) and the A terminal (drain) are the same, when the potential of the A terminal is equal to or lower than the threshold voltage with respect to the B terminal, the A terminal (drain) to the B terminal Do not supply current to the (source). When the potential of the A terminal becomes equal to or higher than the threshold voltage with reference to the B terminal, a voltage higher than the threshold voltage is applied to the gate with reference to the B terminal (source), and current flows from the A terminal (drain) to the B terminal (source). be able to. That is, when the gate and the source of the transistor are short-circuited, the transistor functions as a diode having a drain as a cathode and a source as an anode, and the forward rising voltage becomes the threshold voltage of the transistor. Therefore, the portion of the second transistor 16 shown in FIG. 2A can be regarded as a diode, and an equivalent circuit as shown in FIG. In the equivalent circuit shown in FIG. 2C, when the potential of the first source terminal 4 of the bidirectional switch 1 is higher than the potential of the second source terminal 5, 5V is applied to the first gate terminal 2 of the first transistor 15. When the voltage is applied, the first transistor 15 is in an on state, and a current can flow from S2 to S1. However, an on-voltage is generated due to the forward rising voltage of the diode. Further, when the potential of S1 of the bidirectional switch 1 is higher than the potential of S2, the voltage is carried by the diode composed of the second transistor 16, and the current flowing from S1 to S2 of the bidirectional switch 1 is blocked. That is, by applying a voltage equal to or higher than the threshold voltage to the first gate terminal 2 and applying a voltage equal to or lower than the threshold voltage to the second gate terminal 3, the so-called bidirectional element is turned on and the drain side (first source side). A switch that can operate by connecting the cathode side of the diode in series can be realized.

  FIG. 3 shows the relationship between Vs2s1 and Is2s1 of the bidirectional switch 1. FIG. 3A shows a case where Vg1 and Vg2 are changed simultaneously, and FIG. 3B shows a case where Vg2 is 0 V that is equal to or lower than the second threshold voltage. (C) shows a case where Vg2 is changed with Vg1 being 0 V which is equal to or lower than the first threshold voltage. In FIG. 3, the voltage between S2 and S1 (Vs2s1), which is the horizontal axis in FIG. 3, is a voltage based on the first ohmic electrode 11A, and the current between S2 and S1 (Is2s1), which is the vertical axis, is the second ohmic. The current flowing from the electrode 11B to the first ohmic electrode 11A is positive. As shown in FIG. 3A, when Vg1 and Vg2 are 0 V and 1 V, Is2s1 does not flow regardless of whether Vs2s1 is positive or negative, and the bidirectional switch 1 is cut off. . Further, when both Vg1 and Vg2 become higher than the threshold voltage, a conductive state in which Is2s1 flows bidirectionally according to Vs2s1 is established. On the other hand, as shown in FIG. 3B, when Vg2 is set to 0 V that is equal to or lower than the second threshold voltage and Vg1 is set to 0 V that is equal to or lower than the first threshold voltage, Is2s1 is blocked in both directions. However, when Vg1 is 2V to 5V that is equal to or higher than the first threshold voltage, Is2s1 does not flow when Vs2s1 is less than 1.5V, but Is2s1 flows when Vs2s1 becomes 1.5V or higher. That is, a reverse blocking state is reached in which current flows only from the second ohmic electrode 11B to the first ohmic electrode 11A, and no current flows from the first ohmic electrode 11A to the second ohmic electrode 11B. Further, when Vg1 is set to 0V and Vg2 is changed, as shown in FIG. 3C, a current flows only from the first ohmic electrode 11A to the second ohmic electrode 11B, and the second ohmic electrode A reverse blocking state in which no current flows from 11B to the first ohmic electrode 11A is obtained.

  As described above, the bidirectional switch 1 has a function of interrupting and energizing the bidirectional current according to the gate bias condition, and can also operate as a diode, and can also switch the direction in which the current of the diode is energized.

  As described above, the operation can be performed in the four operation modes shown in FIG. 4 according to the ON or OFF condition of the first gate terminal 2 and the second gate terminal 3 of the bidirectional switch 1. That is, when the bidirectional switch 1 inputs a gate drive signal only between the first gate terminal 2 and the first source terminal 4 (in short, only the first gate terminal 2 is turned on), A first mode in which an on-state bidirectional device and a reverse diode are connected in series from one source terminal 4 to the second source terminal 5; and the second gate terminal 3 and the second source When a gate drive signal is inputted only between the terminals 5 (in short, only the second gate terminal 3 is turned on), a forward diode is directed from the first source terminal 4 to the second source terminal 5. And a second mode in which a bidirectional device in an on state operates as a semiconductor connected in series, between the first gate terminal 2 and the first source terminal 4 and between the second gate terminal 3 and the second source terminal 5 A gate drive signal is input (in short, a signal for turning on the first gate terminal 2 and the second gate terminal 3 is input), and a forward direction is applied between the first source terminal 4 and the second source terminal 5. A third mode which operates in both directions without passing through either a diode or a reverse diode; and between the first gate terminal 2 and the first source terminal 4 and between the second gate terminal 3 and the second source terminal 5 No gate drive signal is applied to any of the above (in a simplified manner, the first gate terminal 2 and the second gate terminal 3 are turned off) and a fourth mode for blocking forward and reverse currents It is.

  This structure is similar to a JFET, but operates on a completely different operating principle from a JFET that performs carrier modulation in a channel region by a gate electric field in that carrier injection is intentionally performed. Specifically, it operates as a JFET up to a gate voltage of 3V. However, when a gate voltage of 3V or more exceeding the built-in potential of the pn junction is applied, holes are injected into the gate, and the current flows through the mechanism described above. Increases, and a large current and low on-resistance operation becomes possible.

  In the bidirectional switch 1, the first gate electrode 13A is formed on the first p-type semiconductor layer 12A having p-type conductivity, and the second gate electrode 13B has p-type conductivity. It is formed on the second p-type semiconductor layer 12B. For this reason, a forward bias is applied from the first gate electrode 13A and the second gate electrode 13B to the channel region generated in the interface region between the first semiconductor layer and the second semiconductor layer. Thus, holes can be injected into the channel region. In a nitride semiconductor, the mobility of holes is much lower than the mobility of electrons, so that holes injected into the channel region hardly contribute as carriers for passing current. For this reason, holes injected from the first gate electrode 13A and the second gate electrode 13B generate the same amount of electrons in the channel region, so that the effect of generating electrons in the channel region is increased, and the donor is increased. It functions like an ion. That is, since the carrier concentration can be modulated in the channel region, it is possible to realize a normally-off type nitride semiconductor layer bidirectional switch having a large operating current.

  Next, the gate drive circuit 17 for driving the bidirectional switch 1 will be described with reference to FIG. As shown in FIG. 5, the gate drive circuit 17 connects the second gate terminal 3, the first gate resistor 18A, and the second gate resistor 19A in series, and the first gate resistor 18A and the second gate resistor 19A are connected in series. A diode 21A as a bypass means capable of flowing a current from the second gate terminal 3 to the connection point 20A between the connected node 20A, the first source terminal 4, the first gate resistor 18B, and the second gate resistor 19B. A diode 21B serving as a bypass means that is connected in series and can flow current from the first source terminal 4 to the connection point 20B between the connection point 20B of the first gate resistor 18B and the second gate resistor 19B connected in series. I have. The diode 21B is connected to the first source when the bidirectional switch 1 is turned off in the reverse blocking state, that is, when the parasitic capacitance between the first gate terminal 2 and the first source terminal 4 is not charged. When the potential of the terminal 4 rises, current can flow from the first source terminal 4 to the first gate terminal 2 via the diode 21B and the first gate resistor 18B, and the first gate terminal 2 and the first source terminal 4 It is possible to charge the parasitic capacitance between the two. The first gate resistors 18A and 18B are configured to be shared with resistors for changing the oscillation frequency due to the inductance and parasitic capacitance of the lead of the bidirectional switch 1, and in parallel with the second gate resistors 19A and 19B. Each of the third gate resistors 22A and 22B and the diodes 23A and 23B as a speed-up circuit for improving the turn-off speed is a series circuit.

  In the above configuration, the gate input signal from the illustrated photocoupler can be turned on via the second gate resistors 19A and 19B and the first gate resistors 18A and 18B when switching from OFF to ON. When an off signal is input, the charge accumulated between the first gate terminal 2 and the first source terminal 4 or between the second gate terminal 3 and the second source terminal 5 is transferred to the first gate resistor 18A, 18B, the third gate resistors 22A and 22B, and the diodes 23A and 23B can be pulled out, that is, turned off. When the potential of the second source terminal 5 rises, the parasitic capacitance between the first gate terminal 2 and the second gate terminal 3 and the first gate terminal 2 via the diode 21B and the first gate resistor 18B. And the first source terminal 4 can be charged at high speed without passing through the second gate resistors 19A and 19B.

(Embodiment 2)
In FIG. 6, the same components as those in FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 6 shows a constant voltage diode 24A as a bypass means so that the gate drive circuit 17B in this embodiment can pass a current from the connection points 20A and 20B to the first source terminal 4 and the second source terminal 5. , 24B. The constant voltage diodes 24A and 24B are configured to be shared with means for setting the gate drive power supply voltage to a desired voltage (for example, 5V). The constant voltage diodes 24 </ b> A and 24 </ b> B cause a current to flow in the forward direction when the potential of either the first source terminal 4 or the second source terminal 5 rises, to the first gate terminal 2 or the second gate terminal 3. Current flows. Also, when the potential of either the first source terminal 4 or the second source terminal 5 drops and exceeds the Zener voltage, a current flows in the reverse direction to prevent false firing, or the first gate terminal 2 or The second gate terminal 3 is protected. Furthermore, the constant voltage diodes 24A and 24B clamp the drive power supply voltage to a desired voltage (zener voltage) when the gate signal becomes Hi.

  In the above configuration, when the gate input signal is switched from OFF to ON, it can be turned on via the second gate resistors 19A and 19B and the first gate resistors 18A and 18B, and when the OFF signal is input. The charge accumulated between the first gate terminal 2 and the first source terminal 4 or between the second gate terminal 3 and the second source terminal 5 is transferred to the first gate resistors 18A and 18B, the third gate resistors 22A and 22B, It can be pulled out through the diodes 23A and 23B, that is, turned off. Further, when the potential of the second source terminal 5 rises, the parasitic capacitance between the first gate terminal 2 and the second gate terminal 3 and the first gate via the constant voltage diode 24B and the first gate resistor 18B. The parasitic capacitance between the terminal 2 and the first source terminal 4 can be charged at high speed without passing through the second gate resistors 19A and 19B, and either the first source terminal 4 or the second source terminal 5 can be charged. When the potential of the current drops and exceeds the zener voltage, a current flows in the reverse direction, and erroneous firing can be prevented.

(Embodiment 3)
In FIG. 7, the same components as those in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 7 shows that the gate drive circuit 17C in the present embodiment can make the current when the current flows from the first source terminal 4 and the second source terminal 5 to the connection points 20A and 20B constant current. Constant current diodes 25A and 25B are provided as bypass means. The constant current diodes 25 </ b> A and 25 </ b> B limit the current that tends to flow to the first gate terminal 2 or the second gate terminal 3 when the potential of the first source terminal 4 or the second source terminal 5 rises. .

  In the above configuration, when the gate input signal is switched from OFF to ON, it can be turned on via the second gate resistors 19A and 19B and the first gate resistors 18A and 18B, and when the OFF signal is input. The charge accumulated between the first gate terminal 2 and the first source terminal 4 or between the second gate terminal 3 and the second source terminal 5 is transferred to the first gate resistors 18A and 18B, the third gate resistors 22A and 22B, It can be pulled out through the diodes 23A and 23B, that is, turned off. Further, when the potential of the second source terminal 5 rises, the parasitic capacitance between the first gate terminal 2 and the second gate terminal 3 and the first gate via the constant current diode 25B and the first gate resistor 18B. The parasitic capacitance between the terminal 2 and the first source terminal 4 can be charged at high speed without passing through the second gate resistors 19A and 19B, and further, the first gate terminal 2, The current to the second gate terminal 3 can be limited, and the first gate terminal 2 and the second gate terminal 3 can be protected.

(Embodiment 4)
8, the same components as those in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 8 illustrates the gate drive circuit 17D in the present embodiment with the low potential side as the second source terminal 5. A diode 21B is provided as a bypass means for passing a current from the second source terminal 5 to the connection point 20B. When the bidirectional switch 1 is an upper arm of the inverter circuit and an inductive load is connected, the lower When the arm is turned off, the potential of the second source terminal 5 rises due to the return current from the inductive load. Here, the bidirectional switch 1 is in the first mode in order to prevent the upper and lower arms from being short-circuited and to allow a reflux current to flow through the upper arm. At that time, the parasitic capacitance between the second gate terminal 3 and the first gate terminal 2 and the parasitic capacitance between the first gate terminal 2 and the first source terminal 4 are charged via the diode 21B and the first gate resistor 18B. Will be able to. Although the low potential side has been described as the second source terminal 5, even when the low potential side is the first source terminal 4, the bidirectional switch 1 can control the current in both directions, so the same operation is performed. Therefore, detailed description is omitted.

  In the above configuration, when the gate input signal is switched from OFF to ON, it can be turned on via the second gate resistors 19A and 19B and the first gate resistors 18A and 18B. When an off signal is input, the charge accumulated between the first gate terminal 2 and the first source terminal 4 or between the second gate terminal 3 and the second source terminal 5 is transferred to the first gate resistor 18A, 18B, the third gate resistors 22A and 22B, and the diodes 23A and 23B can be pulled out, that is, turned off. Further, when the inverter is configured, for example, when the potential of the second source terminal 5 connected to the low potential side rises, the first gate terminal 2 and the second gate terminal 2 are connected via the diode 21B and the first gate resistor 18B. The parasitic capacitance between the gate terminal 3 and the parasitic capacitance between the first gate terminal 2 and the first source terminal 4 can be charged at high speed without passing through the second gate resistors 19A and 19B, and an inductive load or the like. Since the diode 21B as the bypass means is added only to the second source terminal 5 on the low potential side where the potential rises when is connected as a load, the cost can be reduced.

(Embodiment 5)
9, the same components as those in FIGS. 1 to 8 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the inverter 26 in the present embodiment, both the gate drive circuits 17A to 17F having the diodes 21A to 21F at the second gate terminals corresponding to the second source terminals on the low potential side as bypass means are described in the first embodiment. The directional switch 1 is connected to bidirectional switches 1a to 1f arranged on each arm of the inverter 26, and a brushless DC motor 27 is connected as a load. In the brushless DC motor 27, for example, even when the lower arm of each phase is turned off, the phase current tends to flow continuously. Therefore, the conduction speed is increased by the gate drive circuits 17A to 17F including the diodes 21A to 21F. And the time until the bidirectional switches 1a to 1f start energization in the first mode or the second mode can be shortened.

  In the above configuration, when the gate input signal is switched from OFF to ON, the gate input signal can be turned on via the second gate resistors 19A to 19L and the first gate resistors 18A to 18L. When an off signal is input, the charge accumulated between the first gate terminal 2 and the first source terminal 4 or between the second gate terminal 3 and the second source terminal 5 is transferred to the first gate resistors 18A to 18A. 18L, the third gate resistors 22A to 22L, and the diodes 23A to 23L can be pulled out, that is, turned off. Further, when the potential of the second source terminal 5 connected to the low potential side is increased by the reflux current from the brushless DC motor 27, the first gate is connected via the diodes 21A to 21F and the first gate resistors 18G to 18L. The parasitic capacitance between the terminal 2 and the second gate terminal 3 and the parasitic capacitance between the first gate terminal 2 and the first source terminal 4 can be charged at high speed without passing through the second gate resistors 19G to 19L. In addition, since the bidirectional switch 1 can start conducting at high speed, it is possible to suppress a drop in the phase current of the brushless DC motor 27 and to prevent a transient increase in the voltage of each phase.

(Embodiment 6)
10, the same components as those in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The matrix converter 28 in the present embodiment includes the bidirectional drive described in the first embodiment with the gate drive circuits 17A to 17F having diodes 21A to 21L connected to both the first gate terminal and the second gate terminal as bypass means. The switch 1 is connected to bidirectional switches 1a to 1f arranged on each arm of the matrix converter 28, and a brushless DC motor 27 is connected as a load. In the brushless DC motor 27, for example, even when any of the low-potential side arms of each phase is turned off, the phase current tends to continuously flow, and thus the gate drive circuits 17A to 17L having diodes 21A to 21L. With 17F, the conduction speed can be increased, and the time until the bidirectional switches 1a to 1f start energization in the first mode or the second mode can be shortened.

  In the above configuration, when the gate input signal is switched from OFF to ON, the gate input signal can be turned on via the second gate resistors 19A to 19L and the first gate resistors 18A to 18L. When an off signal is input, the charge accumulated between the first gate terminal 2 and the first source terminal 4 or between the second gate terminal 3 and the second source terminal 5 is transferred to the first gate resistors 18A to 18A. 18L, the third gate resistors 22A to 22L, and the diodes 23A to 23L can be pulled out, that is, turned off. Further, due to the return current from the brushless DC motor 27, for example, when the bidirectional switch 1b, 1d, or 1f is turned off during the period from 0 to π of the power supply voltage of the AC power supply 29, the bidirectional switch 1a, Since the potential of the second source terminal 5 of 1c or 1e rises, the parasitic capacitance between the first gate terminal 2 and the second gate terminal 3 through the diodes 21A to 21F and the first gate resistors 18A to 18F, In addition, the parasitic capacitance between the first gate terminal 2 and the first source terminal 4 can be charged at high speed without going through the second gate resistors 19A to 19F, and the bidirectional switch 1 starts to conduct at high speed. Therefore, a drop in the phase current of the brushless DC motor 27 can be suppressed, and at the same time, a transient increase in each phase voltage can be prevented. Similarly, during the period of π to 2π of the power supply voltage of the AC power supply 29, when the bidirectional switch 1a, 1c, or 1e is turned off, the first source terminal 4 of the bidirectional switch 1b, 1d, or 1f is turned on. Since the potential rises, the parasitic capacitance between the first gate terminal 2 and the second gate terminal 3 and the second gate terminal 3 and the second source terminal via the diodes 21G to 21L and the first gate resistors 18A to 18F. 5 can be charged at high speed without passing through the second gate resistors 19A to 19F.

  The invention according to the present invention is an invention relating to a gate drive circuit of a bidirectional switch used as a semiconductor of a motor drive device, and any one of the gate drive circuits used in a GaN bidirectional switch having a double gate. It is intended to speed up the transition to the reverse blocking mode (first mode and second mode) in which current can be supplied only in the direction, and can be applied to an inverter for driving a motor or a matrix converter device.

DESCRIPTION OF SYMBOLS 1 Bidirectional switch 1a-1f Bidirectional switch 2 1st gate terminal 3 2nd gate terminal 4 1st source terminal 5 2nd source terminal 6 Substrate 7 Buffer layer 8 Semiconductor layer laminated body 9 GaN layer 10 AlGaN layer 11A 1st Ohmic electrode 11B Second ohmic electrode 12A First p-type semiconductor layer 12B Second p-type semiconductor layer 13A First gate electrode 13B Second gate electrode 14 Protective film 15 First transistor 16 Second transistor 17 Gate drive circuits 17A to 17F Gate drive circuits 18A and 18B First gate resistors 18A to 18L First gate resistors 19A and 19B Second gate resistors 19A to 19L Second gate resistors 20A and 20B Connection points 21A and 21B Diodes 21A to 21L Diodes 22A, 22B Third gate resistance 22A-2 L third gate resistor 23A, 23B diode 23A~23L diodes 24A, 24B constant voltage diode 25A, 25B constant current diode 26 inverter 27 Brushless DC motor 28 matrix converter

Claims (13)

A semiconductor layer stack having a channel formed on a substrate; a first ohmic electrode and a second ohmic electrode formed on the semiconductor layer stack spaced apart from each other; and the first ohmic electrode. A first gate electrode, a second gate electrode, and the semiconductor layer stack and the first gate electrode, which are sequentially formed from the first ohmic electrode side between the electrode and the second ohmic electrode; A first p-type semiconductor layer formed between the semiconductor layer stack and a second gate electrode, and the first ohmic contact. A first gate terminal for inputting a gate drive signal between an electrode and the first gate electrode; and a second gate for inputting a gate drive signal between the second ohmic electrode and the second gate electrode A terminal and the first ohmic A first source terminal connected to the electrode and a second source terminal connected to the second ohmic electrode; when only the first gate terminal is turned on, the first source terminal to the second source terminal A first mode in which a bidirectional device that is in an on state and a reverse diode operate as a semiconductor connected in series, and when only the second gate terminal is turned on, between the first source terminal and the second source terminal A second mode in which a forward diode and an on-state bidirectional device operate as a semiconductor connected in series, and when the first gate terminal and the second gate terminal are turned on, the first source terminal to the second source terminal Third mode, which operates to conduct in both directions without a diode in between, forward and reverse when the first gate terminal and the second gate terminal are turned off A gate driving circuit applied to a bidirectional switch having a fourth mode for cutting off a current in a direction, wherein at least one of the first gate terminal or the second gate terminal, a first gate resistance, and a second gate resistance Are connected in series, and when the potential fluctuation of the first source terminal or the second source terminal occurs, the connection point side of the first gate resistance and the second gate resistance from the first source terminal or the second source terminal A bidirectional drive gate drive circuit, characterized in that a bypass means is provided to allow a current to flow through. 2. The gate drive circuit for a bidirectional switch according to claim 1, wherein the bypass means is configured to allow a current to flow from the connection point side of the first gate resistor and the second gate resistor to the source terminal side. 2. The bidirectional switch gate drive circuit according to claim 1, wherein the bypass means is a diode. 2. A bidirectional switch gate drive circuit according to claim 1, wherein the bypass means is a constant current diode. 3. The bidirectional switch gate drive circuit according to claim 1, wherein the bypass means is a constant voltage diode. 6. The bidirectional device according to claim 1, wherein the bypass means is connected only to the first gate terminal or the second gate terminal corresponding to the first source terminal or the second source terminal on the low potential side. Switch gate drive circuit. 6. The bidirectional gate drive circuit according to claim 1, wherein the bypass means is connected to both the first gate terminal and the second gate terminal. 6. The bidirectional drive gate drive circuit according to claim 5, wherein the bypass means is shared with a constant voltage diode having a gate drive power supply voltage as a desired voltage. 9. The bidirectional switch according to claim 1, wherein the first gate resistor connected to the gate terminal side is shared with a resistor for changing an oscillation frequency due to inductance and parasitic capacitance of a lead of the bidirectional switch. Gate drive circuit. 10. The bidirectional switch gate drive circuit according to claim 1, further comprising a speed-up circuit for improving a turn-off speed in parallel with the second gate resistor. 11. The bidirectional switch gate drive circuit according to claim 1, wherein the speed-up circuit is a series circuit of a third gate resistor and a diode. An inverter using the bidirectional switch gate drive circuit according to claim 1. A matrix converter using the bidirectional switch gate drive circuit according to any one of claims 1 to 5 or claims 7 to 11.

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