JP2011165824A - Semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress noise propagation between a digital circuit and an analog circuit via a multi-layer wiring layer, even when the noise is at high frequencies. <P>SOLUTION: A circuit separation region 40 is located between a first circuit region 20 and a second circuit region 30. A plurality of first conductors and a plurality of first via holes are provided in the circuit separation region 40. The plurality of first conductors is provided, at a layer that is lower than a power source line 110, facing the power source line 110, and are arranged repeatedly. The plurality of first via holes are provided in the multi-layer wiring layer, for each of the first conductors and connects each first conductor with the power source line 110. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of suppressing the propagation of noise within the same substrate.

  In recent years, development of a semiconductor device in which an analog circuit and a digital circuit are mixedly mounted on the same chip has been advanced. In such a semiconductor device, noise generated from the digital circuit may propagate to the analog circuit and affect the operation of the analog circuit. Patent Document 1 discloses that noise propagation is suppressed by providing a decoupling capacitor between a power supply wiring and a ground wiring.

  Patent Document 2 discloses that a decoupling capacitor is provided above an element isolation insulating film by arranging wirings in the same layer side by side.

No. 2005-116587 No. 2008-103527

  In recent years, since the speed of semiconductor devices has been increased, noise generated from circuits has also been increased in frequency. When the noise is high frequency, the decoupling capacitor cannot block the noise propagating through the multilayer wiring layer.

  An object of the present invention is to provide a semiconductor device capable of suppressing the propagation of noise between a plurality of circuits via a multilayer wiring layer even when the noise is a high frequency.

According to the present invention, the first circuit region in which the first circuit is provided, the second circuit region in which the second circuit is provided, and the circuit positioned between the first circuit region and the second circuit region A substrate having an isolation region;
A multilayer wiring layer formed on the substrate;
A power supply line provided in any one of the multilayer wiring layers located in the circuit isolation region;
A plurality of first conductors provided below the power supply line and repeatedly disposed;
A conductive layer located below the plurality of first conductors and facing the plurality of first conductors;
A plurality of first vias connecting each of the plurality of first conductors to the power line or the conductive layer;
A semiconductor device is provided.

  ADVANTAGE OF THE INVENTION According to this invention, it can suppress that the noise of a wide zone | band including a high frequency propagates between several circuits via a multilayer wiring layer.

1 is a plan view of a semiconductor device according to a first embodiment. It is AA 'sectional drawing of FIG. It is BB 'sectional drawing of FIG. FIG. 2 is an equivalent circuit diagram of the semiconductor device shown in FIG. 1. It is sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 5th Embodiment. It is a figure which shows an example of the planar shape of wiring. It is sectional drawing which shows the structure of the semiconductor device which concerns on 6th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 7th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 8th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 9th Embodiment. It is a figure which shows the modification of FIG. It is sectional drawing which shows the structure of the semiconductor device which concerns on 10th Embodiment. It is a top view which shows the structure of the semiconductor device which concerns on 11th Embodiment. FIG. 17 is a cross-sectional view taken along the line AA ′ of the semiconductor device illustrated in FIG. 16. It is a figure which shows the modification of 1st Embodiment. It is a figure which shows the modification of 6th Embodiment. It is a figure which shows the modification of 6th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a plan view of the semiconductor device according to the first embodiment. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line BB ′ of FIG. As shown in FIG. 2, the semiconductor device includes a substrate 10, a multilayer wiring layer 100, a power supply line 110, and a diffusion layer (conductive layer) 143. As shown in FIG. 1, the substrate 10 is provided with a first circuit region 20, a second circuit region 30, and a circuit isolation region 40. In the first circuit region 20, a first circuit 22, for example, one of an analog circuit and a digital circuit is provided. The second circuit region 30 is provided with a second circuit 32, for example, the other of an analog circuit and a digital circuit. The circuit isolation region 40 is located between the first circuit region 20 and the second circuit region 30. As shown in FIG. 2, the circuit isolation region 40 is provided with a plurality of first conductors 140 and a plurality of first vias 142. That is, in the present embodiment, the circuit isolation region 40 is defined as a region in which a plurality of first conductors 140 and a plurality of first vias 142 are provided.

  In the example illustrated in FIG. 1, the circuit isolation region 40 is provided in a region where the power supply line 110 is provided among regions between the first circuit region 20 and the second circuit region 30. The circuit isolation region 40 only needs to overlap at least a part of the power supply line 110 when viewed in the extending direction of the power supply line 110, but when viewed in the width direction of the power supply line 110, It is preferable that they overlap. In the present embodiment, the width of the power supply line 110 is the same as that of other portions in the circuit isolation region 40, but is wider than other portions in the circuit isolation region 40 as shown in other embodiments described later. It may be.

  The plurality of first conductors 140 are provided below the power supply line 110, face the power supply line 110, and are repeatedly arranged. The plurality of first vias 142 are provided in the multilayer wiring layer 100 for each of the plurality of first conductors 140, and each first conductor 140 is connected to the power supply line 110. Specifically, one end of the first via 142 is connected to the first conductor 140, and the other end of the first via 142 is connected to the power supply line 110. Further, since the diffusion layer 143 is formed on the substrate 10, the diffusion layer 143 is positioned below the plurality of first conductors 140. The diffusion layer 143 faces the plurality of first conductors 140.

  In the present embodiment, the plurality of first conductors 140 are connected only to the first vias 142. The power supply line 110 is formed, for example, in the first wiring layer and extends on the first circuit region 20, the circuit isolation region 40, and the second circuit region 30 in this order. The first via 142 is formed in the same process as a via (not shown) connected to the transistor formed in the first circuit region 20 or the second circuit region 30.

  As shown in FIGS. 1 and 2, the substrate 10 is provided with an element isolation film 12. The element isolation film 12 is formed by, for example, the LOCOS oxidation method, but may be formed by the STI method. The element isolation film 12 isolates the transistors and the like formed in the first circuit region 20 and the second circuit region 30 from other elements. For example, as shown in FIG. 2, a MOS transistor is formed in the first circuit region 20. This MOS transistor has a gate insulating film 121, a gate electrode 120, and a diffusion layer 123 to be a source and a drain. The gate electrode 120 is a polysilicon wiring, for example, and is located on the gate insulating film 121.

  In the present embodiment, the element isolation film 12 is not formed in the circuit isolation region 40. As shown in FIG. 2, an isolation region insulating film 141 is provided on the substrate 10 located in the circuit isolation region 40. Since the isolation region insulating film 141 is formed in the same process as the gate insulating film 121, it has the same layer structure as the gate insulating film 121. The first conductor 140 is formed on the isolation region insulating film 141. Since the first conductor 140 is formed in the same process as the gate electrode 120, it has the same layer configuration as the gate electrode 120.

  The diffusion layer 143 is formed on the entire surface of the surface layer of the substrate 10 located in the circuit isolation region 40 and the periphery thereof. As shown in FIGS. 1 and 3, the diffusion layer 143 is connected to the ground line 132 through the via 130 outside the circuit isolation region 40. For this reason, a ground potential is applied to the diffusion layer 143. The ground line 132 may be formed in the same layer as the power supply line 110 or may be formed in a different layer. Note that the diffusion layer 143 is separated from other regions by the element isolation film 12.

  In such a configuration, the power supply line 110, the plurality of first first vias 142, the first conductor 140, and the diffusion layer 143 located in the circuit isolation region 40 form a structure that exhibits characteristics as a metamaterial. Yes. In this structure, the metamaterial has a configuration in which a plurality of unit cells 42 are repeatedly arranged, for example, periodically. The unit cell 42 has, for example, a two-dimensional array, but may be a one-dimensional array. The unit cell 42 is a so-called mushroom-type metamaterial unit cell, and corresponds to a conductor plane in which the power line 110 is connected to the mushroom. The first via 142 corresponds to the inductance portion of the mushroom, and the first conductor 140 corresponds to the head portion of the mushroom. The diffusion layer 143 corresponds to the second conductor plane facing the mushroom.

  The capacitance of each metamaterial is controlled by the thickness and material of the isolation region insulating film 141 and the size and arrangement of the first conductors 140, and the length and thickness of the first via 142 can control the metamaterial. The inductance component is controlled. By adjusting them, it is possible to adjust the band gap band when the structure functions as an EBG (Electromagnetic Band Gap). In the present embodiment, the unit cell 42 is designed such that the band gap band includes the frequency (for example, 1 GHz or more) of noise emitted from the logic circuit of the semiconductor device.

  Here, when the “repetitive” unit cells 42 are arranged, in the unit cells 42 adjacent to each other, the interval between the same vias (for example, the first via 142) (distance between the centers) is assumed to be an electromagnetic wave assumed as EBG noise. It is preferable to be within half of the wavelength λ. “Repetition” includes a case where a part of the configuration is missing in any unit cell 42. When the unit cell 42 has a two-dimensional array, “repetition” includes a case where the unit cell 42 is partially missing. Further, “periodic” includes a case where some of the constituent elements are deviated in some unit cells 42 and a case where the arrangement of some unit cells 42 is deviated. In other words, even when the periodicity in the strict sense collapses, if the unit cells 42 are repeatedly arranged, the characteristics as a metamaterial can be obtained, so that “periodicity” has some defect. Permissible. These defects may be caused when wiring or vias are passed between the unit cells 42, when adding the metamaterial structure to the existing wiring layout, and when the unit cells 42 cannot be arranged by existing vias or patterns, A case where an error and an existing via or pattern are used as a part of the unit cell 42 can be considered.

  Next, operations and effects in the present embodiment will be described with reference to FIG. 4 is an equivalent circuit diagram of the semiconductor device shown in FIG. In the present embodiment, the power supply line 110 is connected to the first circuit 22 and the second circuit 32. The power supply line 110 has a plurality of unit cells 42 serving as EBGs between the first circuit 22 and the second circuit 32. The EBG is designed to include the frequency of noise emitted from the logic circuit (specifically, one of the first circuit 22 and the second circuit 32). For this reason, it can suppress that noise propagates between the 1st circuit 22 and the 2nd circuit 32 via a power supply line.

  FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. The semiconductor device according to the present embodiment has the same configuration as that of the semiconductor device according to the first embodiment, except for the planar layout of the circuit isolation region 40.

  In the present embodiment, the width of the circuit isolation region 40 is wider than the width of the power supply line 110 located in the first circuit region 20 and the second circuit region 30. Accordingly, a portion of the power supply line 110 located in the circuit isolation region 40 is wider than other portions. A plurality of unit cells 42 (shown in FIG. 2) are arranged on the entire surface of the circuit isolation region 40.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. Moreover, since the circuit isolation region 40 can be made larger than in the first embodiment and the first conductor 140 constituting the unit cell 42 can be made larger, the capacitance component of the metamaterial can be increased. In this case, the band gap band of the unit cell 42 can be lowered.

  FIG. 6 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment. The semiconductor device according to this embodiment has the same configuration as that of the second embodiment except for the planar layout of the circuit isolation region 40.

  The width of the circuit isolation region 40 is wider than the width of the power supply line 110 located in the first circuit region 20 and the second circuit region 30, and all the portions where the first circuit region 20 and the second circuit region 30 are opposed to each other. Located between. That is, the first circuit region 20 and the second circuit region 30 are opposed to each other via the circuit isolation region 40 in any portion facing each other. Specifically, the portion of the power supply line 110 located in the circuit isolation region 40 is wider than the other portions and is provided on the entire surface of the circuit isolation region 40. A plurality of unit cells 42 (shown in FIG. 2) are arranged on the entire surface of the circuit isolation region 40.

  Also according to the present embodiment, it is possible to suppress the propagation of noise through the power supply line 110 as in the second embodiment. The circuit isolation region 40 is located between all the portions where the first circuit region 20 and the second circuit region 30 face each other. For this reason, noise propagates between the first circuit region 20 and the second circuit region 30 through the layer in which the unit cells 42 are provided in the multilayer wiring layer 100, that is, the layer below the power supply line 110. Can be suppressed. This effect is particularly remarkable when one of the first circuit region 20 and the second circuit region 30 is surrounded by the circuit isolation region 40.

  FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment. The semiconductor device according to the present embodiment has the same configuration as that of the semiconductor device according to the first embodiment except for the direction in which the power supply line 110 extends and the planar layout of the circuit isolation region 40.

  In the present embodiment, the power supply line 110 extends between the first circuit region 20 and the second circuit region 30 so as to partition the first circuit region 20 and the second circuit region 30. The circuit isolation region 40 is located between all the portions where the first circuit region 20 and the second circuit region 30 face each other.

  In the present embodiment, the circuit isolation region 40 is located between all the portions where the first circuit region 20 and the second circuit region 30 face each other. For this reason, noise propagates between the first circuit region 20 and the second circuit region 30 through the layer in which the unit cells 42 are provided in the multilayer wiring layer 100, that is, the layer below the power supply line 110. Can be suppressed.

  In this embodiment, the power supply line 110 may not be a power supply line to the first circuit region 20 or the second circuit region 30, but may be a power supply line to another circuit region. It may be a dummy power supply line that does not supply power. Even in this case, the unit cell 42 is formed in the multilayer wiring layer 100. That is, it is possible to suppress the radiation noise from propagating between the first circuit region 20 and the second circuit region 30 through the layer below the power supply line 110. The suppression of noise propagation in this case is mainly due to the shielding effect.

  FIG. 8 is a cross-sectional view showing the configuration of the semiconductor device according to the fifth embodiment. The semiconductor device according to the present embodiment has the same configuration as that of any of the semiconductor devices according to the first to fourth embodiments except for the following points.

  First, the power supply line 110 is formed in the second or higher wiring layer. That is, at least one wiring layer is located between the plurality of first conductors 140 and the power supply line 110. Each of the plurality of first conductors 140 is connected to the power supply line 110 via the wiring 145, the second via 149, and the third via 146. Specifically, the wiring 145 is formed in any wiring layer located between the plurality of first conductors 140 and the power supply line 110. The second via 149 connects the first conductor 140 and one end of the wiring 145. The third via 146 connects the power line 110 and the other end of the wiring 145.

  In the present embodiment, the unit cell 42 is a so-called mushroom-type metamaterial unit cell. Specifically, the power line 110 corresponds to a conductor plane connected to the mushroom. The second via 149, the wiring 145, and the third via 146 correspond to the mushroom inductance portion, and the first conductor 140 corresponds to the mushroom head portion. The diffusion layer 143 corresponds to the second conductor plane facing the mushroom.

  Each diagram in FIG. 9 is a diagram illustrating an example of a planar shape of the wiring 145. In the example shown in FIG. 9A, the wiring 145 extends in a spiral shape. In the example shown in FIG. 9B, the wiring 145 extends in a meander shape, that is, zigzag. In any case, the wiring 145 is longer than when the second via 149 and the third via 146 are connected in a straight line.

  Also according to this embodiment, the same effects as those of the first to fourth embodiments can be obtained. Further, in the unit cell 42, the mushroom inductance portion is configured by the second via 149, the wiring 145, and the third via 146, and thus the value thereof is larger than in the first to fourth embodiments. Therefore, the band gap band of EBG can be lowered. In particular, when the wiring 145 has the pattern shown in FIG. 9, the wiring length of the wiring 145 can be ensured without making the unit cell 42 large, so that the band gap band of the EBG can be further reduced. it can.

  In FIG. 8, the wiring 145 and the third via 146 are provided for each layer, but a plurality of these may be repeatedly stacked in this order. In this case, in the unit cell 42, the mushroom inductance portion is configured by the second via 149, the plurality of wirings 145, and the plurality of third vias 146.

  FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to the sixth embodiment. This semiconductor device has the same configuration as that of any of the semiconductor devices according to the first to fourth embodiments except for the following points.

  First, the power supply line 110 is formed in the second and higher wiring layers. A second conductor 147 is formed in the first wiring layer. The second conductor 147 is connected to the diffusion layer 143 of the substrate 10 through the fourth via 148.

  The second conductor 147 is a sheet-like conductor pattern, for example, and extends so as to face the plurality of first conductors 140. The second conductor 147 has an opening through which the first via 142 passes. That is, by providing this opening, insulation between the second conductor 147 and the first via 142 is ensured. The second conductor 147 may be provided in an island shape so as to fill the space between the first vias 142.

  In the present embodiment, the unit cell 42 has a configuration in which two unit cells of so-called mushroom type metamaterial are stacked. Specifically, the first mushroom is composed of the power supply line 110, the first via 142, the first conductor 140, and the diffusion layer 143. The power line 110 corresponds to a conductor plane connected to the mushroom. The first via 142 corresponds to the inductance portion of the mushroom, and the first conductor 140 corresponds to the head portion of the mushroom. The second mushroom is configured by the power supply line 110, the second conductor 147, the fourth via 148, and the diffusion layer 143. The diffusion layer 143 corresponds to a conductor plane connected to the mushroom. The fourth via 148 corresponds to the inductance portion of the mushroom, and the second conductor 147 corresponds to the head portion of the mushroom.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. The first conductor 140 forms a capacitance with the diffusion layer 143 and also forms a capacitance with the second conductor 147. For this reason, the capacity of the unit cell 42 is larger than that of the first embodiment. Therefore, the band gap band of EBG can be lowered. Furthermore, the unit cell 42 has a configuration in which two unit cells of mushroom type metamaterial are stacked. The periphery of the first conductor 140 and the second conductor 147 is opposed to each other. Therefore, the unit cells can be made substantially dense.

  In the present embodiment, as shown in FIG. 19, the first via 142 and the first conductor 140 need not be provided. Even in this case, since the metamaterial is constituted by the above-described second mushroom, the same effect as that of the first embodiment can be obtained. As shown in FIG. 20, the first conductor 140 and the second conductor 147 may be provided in the same layer. In this case, since the number of wiring layers necessary for configuring the unit cell 42 is reduced, the number of processes can be reduced.

  FIG. 11 is a cross-sectional view illustrating a configuration of a semiconductor device according to the seventh embodiment. This semiconductor device has the same configuration as that of the semiconductor device according to the sixth embodiment except for the following points.

First, the power supply line 110 is formed in the fourth or higher wiring layer. In the wiring layer below the power supply line 110, the wiring layer in which the second conductor 147 is formed and the wiring layer in which the first conductor 140 is provided are alternately arranged. In addition, another wiring layer may be located between the wiring layer in which the second conductor 147 is formed and the wiring layer in which the first conductor 140 is provided. The first via 142 is connected to the first conductor 140 of each layer, and the fourth via 148 is connected to the second conductor 147 of each layer.

  Also in this embodiment, the same effect as that of the semiconductor device according to the sixth embodiment can be obtained. Further, the capacity of the unit cell 42 is larger than that of the sixth embodiment. Therefore, the band gap band of the EBG can be further lowered.

  In the sixth embodiment and the seventh embodiment, the conductor layer for providing the second conductor 147 may be provided separately from the wiring layer. In this case, the second conductor 147 is added between the layer in which the first conductor 140 is provided and the wiring layer one layer above this layer. The insulating film located between the layer on which the first conductor 140 is provided and the second conductor 147 has a higher dielectric constant than the insulating film located between the second conductor 147 and the wiring layer one above it. It is preferably formed of a material.

  FIG. 12 is a cross-sectional view showing the configuration of the semiconductor device according to the eighth embodiment. This semiconductor device has the same configuration as that of any of the semiconductor devices according to the first to fourth embodiments except for the configuration of the unit cell 42.

  In the present embodiment, a plurality of convex insulating layers 150 are repeatedly provided on the diffusion layer 143 located in the circuit isolation region 40, for example, periodically. A third conductor 152, a dielectric layer 154, and a first conductor 156 are stacked in this order on the top and side surfaces of the insulating layer 150. Although the third conductor 152 is connected to the diffusion layer 143, the first conductor 156 is separated from the diffusion layer 143 and thus insulated from the diffusion layer 143. The first conductor 156 is connected to the power supply line 110 through the first via 142. The dielectric layer 154 is made of a material having a higher dielectric constant than that of the insulating layer constituting the multilayer wiring layer. When the dielectric layer 154 is sandwiched between the first conductor 156 and the third conductor 152, the capacitance of the unit cell 42 is formed.

  In the present embodiment, the unit cell 42 is a mushroom type, and includes a third conductor 152, a dielectric layer 154, a first conductor 156, a first via 142, and a power supply line 110. Specifically, the power line 110 corresponds to a conductor plane connected to the mushroom. The first via 142 corresponds to the inductance portion of the mushroom, and the first conductor 156 corresponds to the head portion of the mushroom. The third conductor 152 corresponds to a second conductor plane facing the mushroom.

  Also according to this embodiment, the same effects as those of the first to fourth embodiments can be obtained. The capacitance of the EBG is formed by the third conductor 152, the dielectric layer 154, and the first conductor 156, which are three-dimensionally formed. For this reason, the capacity of the unit cell 42 is larger than that of the first embodiment. Therefore, the band gap band of EBG can be lowered. Further, since the capacity of the EBG is formed in a convex shape, the capacity can be increased without increasing the occupied area.

  FIG. 13 is a cross-sectional view showing the configuration of the semiconductor device according to the ninth embodiment. This semiconductor device has the same configuration as that of any of the semiconductor devices according to the first to fourth embodiments except for the configuration of the unit cell 42.

  In the present embodiment, a plurality of capacitive elements 160 are repeatedly arranged, for example, periodically in the multilayer wiring layer located in the circuit isolation region 40. The capacitive element 160 is a cylinder-type capacitive element and is embedded in a recess formed in the interlayer insulating film. A lower electrode layer 162, a dielectric film 164, and an upper electrode layer 166 are stacked in this order on the bottom and side walls of the recess. The lower electrode layer 162 is connected to the diffusion layer 143 through the via 171, and the upper electrode layer 166 is connected to the power supply line 110 through the first via 142. The dielectric film 164 is formed of a material having a higher dielectric constant than the insulating layer constituting the multilayer wiring layer.

  In the present embodiment, the unit cell 42 is a mushroom type, and includes a lower electrode layer 162, an upper electrode layer 166, a first via 142, and a power supply line 110. Specifically, the power line 110 corresponds to a conductor plane connected to the mushroom. The first via 142 corresponds to the inductance portion of the mushroom, and the upper electrode layer 166 corresponds to the head portion of the mushroom. The lower electrode layer 162 corresponds to a second conductor plane facing the mushroom.

  Also according to this embodiment, the same effects as those of the first to fourth embodiments can be obtained. The capacity of the EBG is constituted by a cylinder type capacitive element 160. For this reason, the capacity of the unit cell 42 is larger than that of the first embodiment. Therefore, the band gap band of EBG can be lowered. Further, since the capacity of the EBG is formed in a concave shape, the capacity can be increased without increasing the occupied area.

  FIG. 14 is a diagram showing a modification of FIG. The semiconductor device shown in this figure has a structure in which a capacitor 160 is connected to a plurality of cylinders to form one capacitor. Even if it does in this way, the above-mentioned effect can be acquired. Further, by providing the via 171 at a position shifted from the via 142, the inductance of the unit cell 42 can be increased.

  FIG. 15 is a cross-sectional view showing the configuration of the semiconductor device according to the tenth embodiment. This semiconductor device has the same configuration as that of any of the semiconductor devices according to the first to fourth embodiments except for the configuration of the unit cell 42.

  In the present embodiment, the diffusion layer 143 has a recess. An insulating film 184 is formed on the side and bottom surfaces of the recess. The insulating film 184 is a thermal oxide film, for example. A first conductor 182 is embedded on the insulating film 184. That is, a capacitance is formed by the diffusion layer 143, the insulating film 184, and the first conductor 182. A first via 142 is connected to the first conductor 182.

  In the present embodiment, the unit cell 42 is a mushroom type, and includes a diffusion layer 143, an insulating film 184, a first conductor 182, a first via 142, and a power supply line 110. Specifically, the power line 110 corresponds to a conductor plane connected to the mushroom. The first via 142 corresponds to the inductance portion of the mushroom, and the first conductor 182 corresponds to the head portion of the mushroom. The diffusion layer 143 corresponds to the second conductor plane facing the mushroom.

  Also according to this embodiment, the same effects as those of the first to fourth embodiments can be obtained. The capacity of the unit cell 42 is formed by the diffusion layer 143, the insulating film 184, and the first conductor 182. The insulating film 184 is formed on the side surface of the recess formed in the diffusion layer 143. For this reason, the capacity of the unit cell 42 is larger than that of the first embodiment. Therefore, the band gap band of EBG can be lowered. Further, since it is not necessary to provide a wiring layer below the power supply line 110, the semiconductor device can be thinned.

  FIG. 16 is a plan view showing the configuration of the semiconductor device according to the eleventh embodiment. 17 is a cross-sectional view of the semiconductor device shown in FIG. This semiconductor device has the same configuration as that of any of the semiconductor devices according to the first to fourth embodiments except for the following points.

  First, the element isolation film 12 is also formed on the substrate 10 located in the circuit isolation region 40. A sheet-like second conductor 172 is formed on the element isolation film 12 located in the circuit isolation region 40. The second conductor 172 faces the first conductors 140 and is connected to the ground line 132 through the via 130. The second conductor 172 has, for example, the same layer configuration as the gate electrode 120 and is formed in the same process as the gate electrode 120. In the case where the gate electrode 120 has a multilayer structure, the second conductor 172 may be configured by a part of the conductor layer that constitutes the gate electrode 120. For example, when the gate electrode 120 has a barrier metal layer on the upper surface, the second conductor 172 may be formed of the barrier metal layer.

  In the present embodiment, the plurality of first conductors 140 are formed in any one of the multilayer wiring layers, for example, the first wiring layer. A dielectric layer 174 is formed on the second conductor 172. The plurality of first conductors 140 are located on the dielectric layer 174. The dielectric layer 174 is formed in a separate process from the insulating layer constituting the multilayer wiring layer, and is formed of a material having a dielectric constant higher than that of the insulating layer constituting the multilayer wiring layer.

  In the present embodiment, the unit cell 42 is a mushroom type, and includes a second conductor 172, a dielectric layer 174, a first conductor 140, a first via 142, and a power line 110. Specifically, the power line 110 corresponds to a conductor plane connected to the mushroom. The first via 142 corresponds to the inductance portion of the mushroom, and the first conductor 140 corresponds to the head portion of the mushroom. The second conductor 172 corresponds to a second conductor plane facing the mushroom.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. Since the dielectric layer 174 is formed in a separate process from the insulating layer constituting the multilayer wiring layer, the capacitance of the unit cell 42 can be increased by forming the dielectric layer 174 from a high dielectric constant material. Therefore, the band gap band of EBG can be lowered.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  For example, as shown in FIG. 18, the width of the first conductor 140 is increased in the first embodiment, and the first conductor region 20 and the second circuit region 30 are in the first conductor in any part facing each other. You may make it mutually oppose through 140. If it does in this way, the power supply line 110 will not be located in the upper part of the 1st conductor 140 most. For this reason, since another wiring can be provided in this part which is not located, the freedom degree of design of wiring improves.

  Moreover, in each above-mentioned embodiment, you may provide an unevenness | corrugation in the surface layer of a 1st conductor. Further, in the first to tenth embodiments and the example shown in FIG. 19, the diffusion layer 143 may not be provided. In this case, the substrate 10 replaces the diffusion layer 143.

10 Substrate 12 Element Isolation Film 20 First Circuit Area 22 First Circuit 30 Second Circuit Area 32 Second Circuit 40 Circuit Isolation Area 42 Unit Cell 100 Multilayer Wiring Layer 110 Power Line 120 Gate Electrode 121 Gate Insulating Film 123 Diffusion Layer 130 Via 132 ground line 140 first conductor 141 isolation region insulating film 142 first via 143 diffusion layer 145 wiring 146 third via 147 second conductor 148 fourth via 149 second via 150 insulating layer 152 third conductor 154 dielectric layer 156 first Conductor 160 Capacitor 162 Lower electrode layer 164 Dielectric film 166 Upper electrode layer 171 Via 172 Second conductor 174 Dielectric layer 182 First conductor 184 Insulating film

Claims (13)

A substrate having a first circuit region in which a first circuit is provided, a second circuit region in which a second circuit is provided, and a circuit isolation region located between the first circuit region and the second circuit region; ,
A multilayer wiring layer formed on the substrate;
A power supply line provided in any one of the multilayer wiring layers located in the circuit isolation region;
A plurality of first conductors provided below the power supply line and repeatedly disposed;
A conductive layer located below the plurality of first conductors and facing the plurality of first conductors;
A plurality of first vias connecting each of the plurality of first conductors to the power line or the conductive layer;
A semiconductor device comprising: The semiconductor device according to claim 1,
The power supply line is a semiconductor device connected to each of the first circuit and the second circuit.   3. The semiconductor device according to claim 1, wherein a ground potential is applied to the conductive layer. In the semiconductor device as described in any one of Claims 1-3,
The plurality of first conductors are respectively connected to the first vias only. In the semiconductor device according to claim 1,
The conductive layer is the substrate or a diffusion layer formed on the substrate,
A semiconductor device further comprising an element isolation film that isolates the conductive layer from other regions. The semiconductor device according to claim 5,
A transistor having a gate insulating film and a gate electrode is formed in the first circuit region,
An isolation region insulating film having the same layer configuration as the gate insulating film is formed on the surface of the substrate located in the circuit isolation region,
The plurality of first conductors are formed on the isolation region insulating film and have the same layer configuration as the gate electrode. In the semiconductor device according to claim 1,
An element isolation film provided on the substrate;
The element isolation film is also formed in the circuit isolation region,
The semiconductor device, wherein the conductive layer is a sheet-like conductor formed on a surface of the element isolation film located in the circuit isolation region. In the semiconductor device as described in any one of Claims 1-7,
In the planar layout, the first circuit region and the second circuit region are opposed to each other via the circuit isolation region in any portion where the first circuit region and the second circuit region are opposed to each other. A semiconductor device. In the semiconductor device according to claim 1,
Between the plurality of first conductors and the power line, at least one wiring layer is located,
Each of the plurality of first conductors includes a wiring formed in a wiring layer located between the first conductor and the power supply line, a second via connecting the first conductor and one end of the wiring, and the A semiconductor device connected to the power line via a third via that connects the power line and the other end of the wiring. The semiconductor device according to any one of claims 1 to 9,
At least one second conductor formed in a wiring layer located between the power line and the first conductor;
A fourth via connecting the second conductor to the substrate;
With
The semiconductor device wherein the at least one second conductor is opposed to the plurality of first conductors. In the semiconductor device according to claim 1,
The power supply line is a semiconductor device extending above the first circuit region, the circuit isolation region, and the second circuit region in this order. The semiconductor device according to claim 1,
The power supply line, the plurality of first conductors, and the plurality of first vias are semiconductor devices that constitute at least a part of an EBG (Electromagnetic Band Gap) structure. The semiconductor device according to claim 1,
One of the first circuit and the second circuit is an analog circuit, and the other is a digital circuit.

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