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JP2011159662A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2011159662A
JP2011159662A JP2010017870A JP2010017870A JP2011159662A JP 2011159662 A JP2011159662 A JP 2011159662A JP 2010017870 A JP2010017870 A JP 2010017870A JP 2010017870 A JP2010017870 A JP 2010017870A JP 2011159662 A JP2011159662 A JP 2011159662A
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embedded portion
substrate
embedded
semiconductor element
thermal conductivity
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Tomoyuki Shoji
智幸 庄司
Yuji Yagi
雄二 八木
Takashi Asada
崇史 浅田
Yuji Osada
裕司 長田
Tomokiyo Suzuki
智清 鈴木
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of dissipating heat generated by a semiconductor element through a substrate and more properly inhibiting deterioration of a junction between the semiconductor element and the substrate. <P>SOLUTION: The semiconductor device 10 includes the semiconductor element 11, the junction 12, and a heat sink 15 laminated in order. A direction in which the semiconductor element 11 and the heat sink 15 are laminated is assumed as a thickness direction, and a direction along a plane perpendicular to the thickness direction is assumed as a plane direction. The heat sink 15 includes: a first embedded portion 16 formed in a central region corresponding to a laminate range of the semiconductor element 11, the heat sink having a thermal conductivity in the thickness direction higher than the thermal conductivity in the plane direction and the thermal conductivity of a base material of the heat sink 15; and a second embedded portion 17 formed in a peripheral region, the second embedded portion having a linear expansion coefficient in the plane direction smaller than the linear expansion coefficient in the plane direction of the first embedded portion 16 and the linear expansion coefficient of the base material of the heat sink 15 and having a rigidity in the plane direction higher than the rigidity in the plane direction of the first embedded portion 16 and the rigidity of the base material of the heat sink 15. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体素子と基板とが積層されている半導体装置に関する。   The present invention relates to a semiconductor device in which a semiconductor element and a substrate are stacked.

特許文献１に開示される半導体装置は、半導体素子と基板（配線基板）とが積層されているとともに、半導体素子と基板との相対的な位置関係を固定するための接合部（ダイボンド剤）がこれらの間に介在している。半導体素子が作動すると、半導体素子が発熱する。半導体素子と基板との線膨張係数が異なると、半導体素子の発熱時に半導体素子と基板とが異なる比率で膨張するため、接合部に応力が作用して亀裂等が生じ、接合部が劣化する可能性がある。この半導体装置では、接合部と半導体素子がモールド樹脂によって覆われているため、半導体素子と配線基板とが熱によって異なる比率で膨張しても、接合部に生じる亀裂を軽減することができる。   In the semiconductor device disclosed in Patent Document 1, a semiconductor element and a substrate (wiring substrate) are stacked, and a bonding portion (die bond agent) for fixing the relative positional relationship between the semiconductor element and the substrate is provided. It is interposed between them. When the semiconductor element operates, the semiconductor element generates heat. If the linear expansion coefficients of the semiconductor element and the substrate are different, the semiconductor element and the substrate expand at different ratios when the semiconductor element generates heat, so that stress acts on the joint and a crack or the like may occur, which may deteriorate the joint. There is sex. In this semiconductor device, since the joint portion and the semiconductor element are covered with the mold resin, even if the semiconductor element and the wiring board expand at different ratios due to heat, cracks generated in the joint portion can be reduced.

特開２００８−２３５４９２号公報JP 2008-235492 A

特許文献１に記載の半導体装置では、モールド樹脂によって接合部の劣化をある程度は抑制することはできる。しかしながら、この技術では、基板と半導体素子との熱による膨張度合いの差を低減することができないため、接合部に作用する応力自体を低減することはできない。したがって、接合部の劣化を抑制するという点で十分とは言い難い。また、基板には、半導体素子で発生する熱を、基板を通じてその周囲又は基板に接続されている冷却器等に放熱させることが要求される。
本明細書に開示する技術は、上記実情に鑑みてなされたものであり、その目的は、半導体素子で発生する熱を基板を通じて放熱することができるとともに、半導体素子と基板との間の接合部の劣化をより適切に抑制することができる半導体装置を提供することにある。 In the semiconductor device described in Patent Document 1, it is possible to suppress degradation of the joint portion to some extent by the mold resin. However, this technique cannot reduce the difference in the degree of expansion between the substrate and the semiconductor element due to heat, and therefore cannot reduce the stress acting on the joint itself. Therefore, it is difficult to say that it is sufficient in terms of suppressing deterioration of the joint. In addition, the substrate is required to dissipate heat generated in the semiconductor element through the substrate to the periphery or a cooler connected to the substrate.
The technology disclosed in the present specification has been made in view of the above circumstances, and the purpose thereof is to dissipate heat generated in the semiconductor element through the substrate, and a junction between the semiconductor element and the substrate. An object of the present invention is to provide a semiconductor device that can more appropriately suppress deterioration of the semiconductor device.

本明細書に開示する技術は、半導体素子と、その半導体素子に直接的又は間接的に積層されている基板と、その半導体素子とその基板との間に介在するとともに、その半導体素子とその基板との相対的な位置関係を固定する接合部とを備えている半導体装置である。
この半導体装置では、基板が、半導体素子の積層範囲に対応する中央領域と、その中央領域の周囲に伸びている外周領域を備えている。基板の中央領域に、第１埋設部が形成されており、基板の外周領域に第２埋設部が形成されている。半導体素子と基板とが積層されている方向を厚さ方向とし、その厚さ方向と直交する面に沿った方向を面方向とすると、第１埋設部は、厚さ方向の熱伝導率が面方向の熱伝導率及び基板の母材の熱伝導率よりも高い。また、第２埋設部は、面方向の線膨張係数が第１埋設部の面方向の線膨張係数及び基板の母材の線膨張係数よりも小さく、且つ面方向の剛性が第１埋設部の面方向の剛性及び基板の母材の剛性よりも高い。 The technology disclosed in this specification includes a semiconductor element, a substrate directly or indirectly stacked on the semiconductor element, and the semiconductor element and the substrate. The semiconductor device is provided with a joint portion that fixes the relative positional relationship between the first and second portions.
In this semiconductor device, the substrate includes a central region corresponding to the stacking range of the semiconductor elements and an outer peripheral region extending around the central region. A first embedded portion is formed in the central region of the substrate, and a second embedded portion is formed in the outer peripheral region of the substrate. When the direction in which the semiconductor element and the substrate are stacked is defined as the thickness direction, and the direction along the plane perpendicular to the thickness direction is defined as the plane direction, the first embedded portion has a thermal conductivity in the thickness direction. Higher than the thermal conductivity of the direction and the base material of the substrate. Further, the second buried portion has a linear expansion coefficient in the surface direction smaller than the linear expansion coefficient in the surface direction of the first buried portion and the linear expansion coefficient of the base material of the substrate, and the rigidity in the surface direction of the first buried portion. It is higher than the rigidity in the surface direction and the rigidity of the base material of the substrate.

上記構成において、基板とは、専ら半導体素子の放熱のために半導体素子に接合されているものであってもよいし、半導体素子とワイヤなどを介して接続される電極板であってもよいし、配線基板であってもよい。上記構成において、基板が半導体素子に直接的又は間接的に積層されているとは、基板と半導体素子とが接合部のみを介して積層されている場合と、基板と半導体素子との間に接合部とともに金属層、半導体層、及び絶縁体層等の中間層が介在している場合とを含む。   In the above configuration, the substrate may be bonded to the semiconductor element exclusively for heat dissipation of the semiconductor element, or may be an electrode plate connected to the semiconductor element via a wire or the like. It may be a wiring board. In the above structure, the substrate is laminated directly or indirectly on the semiconductor element means that the substrate and the semiconductor element are laminated only through the bonding portion and the junction between the substrate and the semiconductor element. And a case where an intermediate layer such as a metal layer, a semiconductor layer, and an insulator layer intervenes together with the portion.

また、上記構成において、面方向の熱伝導率とは、面に沿った全ての方向の熱伝導率を平均した平均熱伝導率を意味しており、面方向の線膨張係数とは、面に沿った全ての方向の線膨張係数を平均した平均線膨張係数を意味している。また、面方向の剛性とは、面に沿った全ての方向の剛性を平均した平均剛性を意味している。   In the above configuration, the thermal conductivity in the plane direction means an average thermal conductivity obtained by averaging the thermal conductivities in all directions along the plane, and the linear expansion coefficient in the plane direction refers to the plane. It means an average coefficient of linear expansion obtained by averaging the coefficients of linear expansion in all directions along. Moreover, the rigidity in the plane direction means an average rigidity obtained by averaging the rigidity in all directions along the plane.

上記構成では、半導体素子で発生する熱が、基板の中央領域に形成されている第１埋設部を通じて厚さ方向に効率よく伝導することによって放熱される。
また、第２埋設部は、面方向の線膨張係数が第１埋設部の面方向の線膨張係数及び基板の母材の線膨張係数よりも小さいため、熱膨張しにくい。したがって、半導体素子が発熱しても、第２埋設部は半導体素子の発熱前と略同じ形状に維持される。また、第２埋設部は、面方向の剛性が第１埋設部の面方向の剛性及び基板の母材の剛性よりも高い。そのため、半導体素子の発熱によって、基板の母材と第１埋設部とが面方向に熱膨張しようとしても、その熱膨張が第１埋設部の周囲に位置する第２埋設部によって抑制される。したがって、基板が半導体素子に対して面方向に大きく膨張することを抑制することができるため、半導体素子と基板との熱膨張の差によって接合部に応力が作用することを抑制することができる。これにより、接合部に亀裂等が生じて劣化することをより適切に抑制することができる。 In the above configuration, heat generated in the semiconductor element is radiated by efficiently conducting in the thickness direction through the first embedded portion formed in the central region of the substrate.
Further, the second embedded portion is less likely to thermally expand because the linear expansion coefficient in the surface direction is smaller than the linear expansion coefficient in the surface direction of the first embedded portion and the linear expansion coefficient of the base material of the substrate. Therefore, even if the semiconductor element generates heat, the second embedded portion is maintained in substantially the same shape as before the semiconductor element generates heat. Further, the second embedded portion has a higher rigidity in the surface direction than the rigidity in the surface direction of the first embedded portion and the rigidity of the base material of the substrate. Therefore, even if the base material of the substrate and the first embedded portion try to thermally expand in the surface direction due to heat generation of the semiconductor element, the thermal expansion is suppressed by the second embedded portion located around the first embedded portion. Therefore, since it can suppress that a board | substrate expand | swells largely to a surface direction with respect to a semiconductor element, it can suppress that a stress acts on a junction part by the difference in thermal expansion of a semiconductor element and a board | substrate. Thereby, it can suppress more appropriately that a crack etc. arise in a junction part and deteriorate.

第１埋設部と第２埋設部とは、異なる材料で構成してもよいし、同じ材料で構成してもよい。同じ材料で構成する場合には、第１埋設部及び第２埋設部が六方晶構造のグラファイトで構成されていることが好ましい。この場合、第１埋設部ではグラファイトのｃ軸が面方向に揃っており、第２埋設部ではグラファイトのｃ軸が厚さ方向に揃っている。
グラファイトは、一方向の熱伝導率がその一方向と直交する面方向の熱伝導率よりも高く、面方向の線膨張係数が一方向の線膨張係数よりも大きく、面方向の剛性が一方向の剛性よりも大きいため、第１埋設部及び第２埋設部を構成することができる。ここでも、面方向の熱伝導率、線膨張係数及び剛性は、面内の全方向の平均を意味している。 The first embedded portion and the second embedded portion may be made of different materials or may be made of the same material. When comprised with the same material, it is preferable that the 1st embedding part and the 2nd embedding part are comprised with the graphite of the hexagonal structure. In this case, the c-axis of graphite is aligned in the surface direction in the first embedded portion, and the c-axis of graphite is aligned in the thickness direction in the second embedded portion.
Graphite has higher thermal conductivity in one direction than the thermal conductivity in the plane direction orthogonal to the one direction, the linear expansion coefficient in the plane direction is larger than the linear expansion coefficient in one direction, and the rigidity in the plane direction is one direction. Since it is larger than the rigidity of the first embedded portion, the first embedded portion and the second embedded portion can be configured. Again, the thermal conductivity, linear expansion coefficient and stiffness in the plane direction mean the average in all directions in the plane.

上記の半導体装置では、基板の全表面がその基板の母材からなり、第１埋設部及び第２埋設部が基板の表面に露出していないことが好ましい。
上記構成によれば、第１埋設部及び第２埋設部を基板の母材で保護することができるとともに、第１埋設部及び第２埋設部を他の部材に直接接着する必要がない。特に、第１埋設部及び第２埋設部の材料として、六方晶構造のグラファイトを用いる場合には有効である。 In the above semiconductor device, it is preferable that the entire surface of the substrate is made of the base material of the substrate, and the first embedded portion and the second embedded portion are not exposed on the surface of the substrate.
According to the above configuration, the first embedded portion and the second embedded portion can be protected by the base material of the substrate, and it is not necessary to directly bond the first embedded portion and the second embedded portion to other members. This is particularly effective when hexagonal graphite is used as the material for the first and second embedded portions.

第１埋設部の面内の少なくとも１方向における線膨張係数が基板の母材の線膨張係数よりも大きい場合には、基板の中央領域では、複数個の第１埋設部が、その第１埋設部と基板の母材からなる部位とが前記１方向に沿って交互に出現するように形成されていることが好ましい。
基板の中央領域の全体に第１埋設部が形成されている場合には、その熱膨張が第２埋設部によって抑制されているとはいえ、第１埋設部の上記１方向の線膨張係数が大きいことから、基板が上記１方向に熱膨張しやすくなる。この点、上記構成によれば、中央領域の全体に第１埋設部を形成されている場合よりも、基板が上記１方向に熱膨張することを抑制することができる。 When the linear expansion coefficient in at least one direction in the plane of the first embedded portion is larger than the linear expansion coefficient of the base material of the substrate, a plurality of first embedded portions are provided in the central region of the substrate. It is preferable that the portion and the portion made of the base material of the substrate are formed so as to alternately appear along the one direction.
When the first embedded portion is formed in the entire central region of the substrate, the thermal expansion is suppressed by the second embedded portion, but the linear expansion coefficient in the one direction of the first embedded portion is Since it is large, the substrate is likely to thermally expand in the one direction. In this regard, according to the above configuration, it is possible to suppress the thermal expansion of the substrate in the one direction as compared with the case where the first embedded portion is formed in the entire central region.

半導体装置では、基板の半導体素子が積層されている側と反対側の面が冷却器に接合しているといった態様を採用することもできる。この構成において、第２埋設部の面方向の熱伝導率が厚さ方向の熱伝導率よりも高いとともに、その厚さ方向の熱伝導率が基板の母材の熱伝導率よりも低い場合には、基板の外周領域に、複数個の第２埋設部が、その第２埋設部と基板の母材からなる部位とが面方向に交互に出現するように形成されていることが好ましい。
半導体素子から基板に伝導した熱は、基板の外周領域では、第２埋設部を通じて面方向に伝導し、その熱が基板の母材からなる部位に達すると、その一部の熱が母材からなる部位を通じて冷却器に向かう方向に伝導するとともに、残りの熱が再度出現する第２埋設部を通じて面方向に伝導する。第２埋設部を通じて面方向に伝導した熱が、基板の母材からなる部位を通じて冷却器に向かって伝導するため、基板に伝導した熱を冷却器へ効率よく伝導することができる。その結果、半導体素子をより効果的に放熱させることができる。 In the semiconductor device, a mode in which the surface of the substrate opposite to the side on which the semiconductor elements are stacked is bonded to the cooler can be adopted. In this configuration, when the thermal conductivity in the surface direction of the second embedded portion is higher than the thermal conductivity in the thickness direction, and the thermal conductivity in the thickness direction is lower than the thermal conductivity of the base material of the substrate. Preferably, the plurality of second embedded portions are formed in the outer peripheral region of the substrate so that the second embedded portions and the portions made of the base material of the substrate appear alternately in the surface direction.
The heat conducted from the semiconductor element to the substrate is conducted in the surface direction through the second embedded portion in the outer peripheral region of the substrate, and when the heat reaches a portion made of the base material of the substrate, a part of the heat is transferred from the base material. Conducted in the direction toward the cooler through the portion, and conducted in the surface direction through the second embedded portion where the remaining heat appears again. Since the heat conducted in the plane direction through the second embedded portion is conducted toward the cooler through the portion made of the base material of the substrate, the heat conducted to the substrate can be efficiently conducted to the cooler. As a result, the semiconductor element can dissipate heat more effectively.

また、基板を冷却器に接合する構成において、第２埋設部の面方向の熱伝導率が厚さ方向の熱伝導率よりも高いとともに、その厚さ方向の熱伝導率が基板の母材の熱伝導率よりも低くい場合には、基板の外縁に近いほど第２埋設部の厚さ方向の長さが長いことが好ましい。
基板の外周領域では、基板の外縁側よりも中央領域側のほうが、半導体素子に近接しているため、半導体素子の熱が伝導されやすく、高温となりやすい。上記構成では、基板の外周領域のうち高温となりやすい中央領域側ほど、基板の母材からなる部位の厚さ方向の長さが長いため、半導体素子から伝導された熱を基板の母材からなる部位を通じて効率的に冷却器へ伝導することができる。また、第２埋設部は、基板の外縁に近いほど厚さ方向に長いため、基板の外縁では面方向の熱膨張を抑制することができる。したがって、外縁の内側に位置する領域においても基板の面方向の熱膨張を抑制することができるため、結果的に基板全体の面方向の熱膨張を抑制することができる。 Moreover, in the structure which joins a board | substrate to a cooler, while the thermal conductivity of the surface direction of a 2nd embedding part is higher than the thermal conductivity of the thickness direction, the thermal conductivity of the thickness direction is the base material of a board | substrate. When it is lower than the thermal conductivity, it is preferable that the length of the second embedded portion in the thickness direction is longer as it is closer to the outer edge of the substrate.
In the outer peripheral region of the substrate, since the central region side is closer to the semiconductor element than the outer edge side of the substrate, the heat of the semiconductor element is easily conducted, and the temperature tends to be high. In the above configuration, since the length in the thickness direction of the portion made of the base material of the substrate is longer in the central region side that tends to be high in the outer peripheral region of the substrate, the heat conducted from the semiconductor element is made of the base material of the substrate. It can be efficiently conducted to the cooler through the site. Further, since the second embedded portion is longer in the thickness direction as it is closer to the outer edge of the substrate, thermal expansion in the surface direction can be suppressed at the outer edge of the substrate. Therefore, since the thermal expansion in the surface direction of the substrate can be suppressed even in the region located inside the outer edge, as a result, the thermal expansion in the surface direction of the entire substrate can be suppressed.

本明細書に開示する半導体装置によれば、基板に第１埋設部と第２埋設部が形成されているため、半導体素子で発生する熱を基板を通じて効率よく放熱することができるとともに、基板が半導体素子に対して面方向に大きく熱膨張することを抑制することによって接合部の劣化をより適切に抑制することができる。   According to the semiconductor device disclosed in the present specification, since the first embedded portion and the second embedded portion are formed on the substrate, heat generated in the semiconductor element can be efficiently radiated through the substrate, and the substrate By suppressing the thermal expansion of the semiconductor element greatly in the surface direction, it is possible to more appropriately suppress the deterioration of the joint portion.

実施例１の半導体装置を示す平面図。1 is a plan view showing a semiconductor device of Example 1. FIG. 図１のII−II線における断面図。Sectional drawing in the II-II line of FIG. グラファイトの結晶構造を示す模式図。The schematic diagram which shows the crystal structure of a graphite. 実施例１の半導体素子の発熱時の半導体装置を示す断面図。FIG. 3 is a cross-sectional view illustrating the semiconductor device when the semiconductor element of Example 1 generates heat. 実施例２の半導体装置を示す断面図。FIG. 6 is a cross-sectional view showing a semiconductor device of Example 2. 実施例３の半導体装置を示す断面図。FIG. 6 is a cross-sectional view showing a semiconductor device of Example 3; 実施例４の半導体装置を示す断面図。FIG. 6 is a cross-sectional view showing a semiconductor device of Example 4; 実施例５の半導体装置を示す断面図。FIG. 6 is a cross-sectional view showing a semiconductor device of Example 5; 実施例６の半導体装置を示す断面図。FIG. 9 is a cross-sectional view showing a semiconductor device of Example 6; 実施例７の半導体装置を示す平面図。FIG. 10 is a plan view showing a semiconductor device of Example 7. 実施例８の半導体装置を示す平面図。FIG. 10 is a plan view showing a semiconductor device of Example 8. 実施例９の半導体装置を示す平面図。FIG. 10 is a plan view showing a semiconductor device of Example 9.

以下に本発明の実施例の特徴を説明する。
（特徴１）基板は、放熱板であり、その放熱板は冷却器に接合されている。冷却器は、冷却板とフィンとを備えている。 The features of the embodiments of the present invention will be described below.
(Feature 1) The substrate is a heat radiating plate, and the heat radiating plate is joined to a cooler. The cooler includes a cooling plate and fins.

（実施例１）
本明細書に開示する技術を具体化した半導体装置の実施例１を図１〜図４を参照して説明する。図１は、実施例１の半導体装置１０の平面図であり、図２は、図１のII−II線における断面図である。
図１に示すように、半導体装置１０は、半導体素子１１と放熱板（基板）１５と絶縁体層２０と冷却器２５とが順に積層されている。図２に示すように、半導体素子１１と放熱板１５とは、これらの間に介在している接合部１２によって接合されている。すなわち、半導体素子１１と放熱板１５との相対的な位置関係が接合部１２により固定されている。接合部１２としては、はんだ等が例示される。以下の説明では、図１および半導体素子１１と放熱板１５とが積層されている方向（図１及び図２のｚ軸方向）を厚さ方向とし、その厚さ方向と直交する面に沿った方向（図１及び図２のｘｙ平面が伸びる方向）を面方向とする。 Example 1
A semiconductor device according to a first embodiment of the technology disclosed in this specification will be described with reference to FIGS. FIG. 1 is a plan view of the semiconductor device 10 according to the first embodiment, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG.
As shown in FIG. 1, the semiconductor device 10 includes a semiconductor element 11, a radiator plate (substrate) 15, an insulator layer 20, and a cooler 25 that are sequentially stacked. As shown in FIG. 2, the semiconductor element 11 and the heat dissipation plate 15 are joined by a joining portion 12 interposed therebetween. That is, the relative positional relationship between the semiconductor element 11 and the heat sink 15 is fixed by the joint 12. Examples of the joint 12 include solder. In the following description, the direction in which the semiconductor element 11 and the heat dissipation plate 15 are stacked (the z-axis direction in FIGS. 1 and 2) is the thickness direction, and the surface is perpendicular to the thickness direction. The direction (direction in which the xy plane in FIGS. 1 and 2 extends) is defined as a surface direction.

本実施例では、半導体素子１１がＩＧＢＴ（Insulated Gate Bipolar Transistor）であり、シリコン半導体で構成される。なお、半導体素子１１としては、例えば、サイリスタ、ＭＯＳＦＥＴ、ダイオード等を用いても良い。半導体素子１１は、図示しないワイヤを介して図示しない電極に接続されている。
絶縁体層２０は、絶縁体からなり、放熱板１５と冷却器２５とを絶縁している。絶縁体層２０の熱伝導率は高い。冷却器２５は、金属製であり、絶縁体層２０と接着している冷却板２６と、冷却板２６の下面から下方に向かって伸びる複数のフィン２７とを備えている。半導体装置１０は、冷却板２６の下面に冷却水などの冷却媒体を流通させた状態で使用される。冷却板２６の下面とフィン２７とに冷却媒体が接触して、半導体素子１１で発生する熱がこの冷却媒体に放熱される。 In this embodiment, the semiconductor element 11 is an IGBT (Insulated Gate Bipolar Transistor), and is formed of a silicon semiconductor. For example, a thyristor, MOSFET, or diode may be used as the semiconductor element 11. The semiconductor element 11 is connected to an electrode (not shown) via a wire (not shown).
The insulator layer 20 is made of an insulator and insulates the heat sink 15 and the cooler 25 from each other. The thermal conductivity of the insulator layer 20 is high. The cooler 25 is made of metal and includes a cooling plate 26 bonded to the insulator layer 20 and a plurality of fins 27 extending downward from the lower surface of the cooling plate 26. The semiconductor device 10 is used in a state where a cooling medium such as cooling water is circulated on the lower surface of the cooling plate 26. The cooling medium comes into contact with the lower surface of the cooling plate 26 and the fins 27, and heat generated in the semiconductor element 11 is radiated to the cooling medium.

放熱板１５の母材は銅である。放熱板１５は、半導体素子１１の積層範囲に対応する中央領域と、その中央領域の周囲に伸びている外周領域を備えている。放熱板１５の中央領域に、第１埋設部１６が形成されており、放熱板１５の外周領域には、第２埋設部１７が形成されている。第１埋設部１６及び第２埋設部１７は、六方晶構造の高配向性のグラファイトで構成されている。第１埋設部１６は、略直方体形状であり、図１に示すように平面視が半導体素子１１と同一の略矩形状に形成されている。第２埋設部１７は、略筒形状をしており、図１に示すように平面視が第１埋設部１６よりも大きい略矩形の枠状に形成されている。第１埋設部１６は、略筒形状の第２埋設部１７の内部に配置されており、第１埋設部１６と第２埋設部１６と間には放熱板の母材である銅が介在している。   The base material of the heat sink 15 is copper. The radiator plate 15 includes a central region corresponding to the stacking range of the semiconductor elements 11 and an outer peripheral region extending around the central region. A first embedded portion 16 is formed in the central region of the heat sink 15, and a second embedded portion 17 is formed in the outer peripheral region of the heat sink 15. The first embedded portion 16 and the second embedded portion 17 are composed of highly oriented graphite having a hexagonal crystal structure. The first embedded portion 16 has a substantially rectangular parallelepiped shape, and is formed in a substantially rectangular shape that is the same as the semiconductor element 11 in plan view as shown in FIG. The second embedded portion 17 has a substantially cylindrical shape, and is formed in a substantially rectangular frame shape that is larger in plan view than the first embedded portion 16 as shown in FIG. The first embedded portion 16 is disposed inside the substantially cylindrical second embedded portion 17, and copper, which is a base material of the heat sink, is interposed between the first embedded portion 16 and the second embedded portion 16. ing.

放熱板１５の全表面はその母材からなり、第１埋設部１６及び第２埋設部１７は放熱板１５の表面に露出していない。すなわち、第１埋設部１６及び第２埋設部１７の表面は銅によって保護されている。そのため、放熱板１５を接合部１２及び絶縁体層２０と接合するにあたって、第１埋設部１６及び第２埋設部１７を直接的に接合部１２及び絶縁体層２０と接着させる必要がない。したがって、第１埋設部１６及び第２埋設部１７に利用できる材料の幅が広がり、第１埋設部１６と第２埋設部１７として、他の部材と接着させにくいグラファイトを利用することができる。   The entire surface of the heat sink 15 is made of the base material, and the first embedded portion 16 and the second embedded portion 17 are not exposed on the surface of the heat sink 15. That is, the surfaces of the first embedded portion 16 and the second embedded portion 17 are protected by copper. Therefore, it is not necessary to directly bond the first embedded portion 16 and the second embedded portion 17 to the joint portion 12 and the insulator layer 20 when the heat sink 15 is joined to the joint portion 12 and the insulator layer 20. Therefore, the width of the material that can be used for the first embedded portion 16 and the second embedded portion 17 is widened, and graphite that is difficult to adhere to other members can be used as the first embedded portion 16 and the second embedded portion 17.

図３は、第１埋設部１６及び第２埋設部１７の材料であるグラファイトの結晶構造を示している。図３に示すように、グラファイトは、炭素原子１８が六方晶構造で結合している。すなわち、グラファイトでは、炭素原子１８がａ軸及びｂ軸方向に共有結合しており、炭素原子１８が亀甲状に共有結合した複数の層が、ｃ軸方向にファンデルワールス力で結合している。なお、以下の説明では、亀甲状に共有結合した炭素原子１８の層をａｂ平面といい、この層に沿った全ての方向をａｂ平面方向という。図２では、第１埋設部１６及び第２埋設部１７のグラファイトのａｂ平面を模式的に実線で示している。図２に示すように、第１埋設部１６では、グラファイトのｃ軸が半導体装置１０の面方向（ｘｙ平面のｘ軸方向）に揃っており、グラファイトのａｂ平面が半導体装置１０の厚さ方向（ｙｚ平面と平行）に沿って伸びている。また、第２埋設部１７ではグラファイトのｃ軸が半導体装置１０の厚さ方向に揃っており、グラファイトのａｂ平面が半導体装置１０の面方向に伸びている。   FIG. 3 shows the crystal structure of graphite, which is the material of the first embedded portion 16 and the second embedded portion 17. As shown in FIG. 3, in graphite, carbon atoms 18 are bonded in a hexagonal crystal structure. That is, in graphite, carbon atoms 18 are covalently bonded in the a-axis and b-axis directions, and a plurality of layers in which carbon atoms 18 are covalently bonded in a tortoiseshell shape are bonded by van der Waals force in the c-axis direction. . In the following description, a layer of carbon atoms 18 covalently bonded in a turtle shell shape is referred to as an ab plane, and all directions along this layer are referred to as ab plane directions. In FIG. 2, the ab planes of graphite of the first embedded portion 16 and the second embedded portion 17 are schematically shown by solid lines. As shown in FIG. 2, in the first embedded portion 16, the c-axis of graphite is aligned with the plane direction of the semiconductor device 10 (the x-axis direction of the xy plane), and the ab plane of graphite is the thickness direction of the semiconductor device 10. It extends along (parallel to the yz plane). In the second embedded portion 17, the c-axis of graphite is aligned in the thickness direction of the semiconductor device 10, and the ab plane of graphite extends in the surface direction of the semiconductor device 10.

本実施例では、放熱板１５に第１埋設部１６を形成することによって、半導体素子１１の作動時に発生する熱を効果的に放熱するようにしており、放熱板１５に第２埋設部１７を形成することによって、放熱板１５が面方向に熱膨張することが抑制するようにしている。この理由を、表１を参照して説明する。

Figure 2011159662
In the present embodiment, the first embedded portion 16 is formed in the heat radiating plate 15 to effectively radiate the heat generated during the operation of the semiconductor element 11, and the second embedded portion 17 is provided in the heat radiating plate 15. By forming it, it is made to suppress that the thermal radiation board 15 thermally expands in a surface direction. The reason for this will be described with reference to Table 1.
Figure 2011159662

表１は、グラファイトと銅の熱伝導率［Ｗ／ｍＫ］、線膨張係数［ｐｐｍ／Ｋ］、及びヤング率［ＧＰａ］を示している。また、シリコンとはんだの線膨張係数［ｐｐｍ／Ｋ］及びヤング率［ＧＰａ］も参考までに示している。
表１に示すように、グラファイトは、ａｂ平面方向では、熱伝導率が１５００［Ｗ／ｍＫ］と高く、ヤング率が１０５０［ＧＰａ］と高く、線膨張係数は−１［ｐｐｍ／Ｋ］と非常に小さい。また、グラファイトでは、ｃ軸方向の熱伝導率が１０［Ｗ／ｍＫ］と低く、ヤング率が３６［ＧＰａ］と低く、線膨張係数が２５［ｐｐｍ／Ｋ］と大きい。また、銅の熱伝導率は、３９４［Ｗ／ｍＫ］であり、グラファイトのａｂ平面方向の熱伝導率よりも低いとともに、グラファイトのｃ軸方の熱伝導率よりも高い。銅の線膨張係数１７［ｐｐｍ／Ｋ］は、グラファイトのａｂ平面方向の線膨張係数よりも大きく、グラファイトのｃ軸方向の線膨張係数よりも小さい。また、銅の線膨張係数及びグラファイトのｃ軸方向の線膨張係数は、シリコンの線膨張係数３［ｐｐｍ／Ｋ］よりも大きい。また、銅は、ヤング率が１２０［ＧＰａ］であり、グラファイトのａｂ平面方向のヤング率よりも低いとともに、グラファイトのｃ軸方向のヤング率よりも高い。したがって、銅の剛性は、グラファイトのａｂ平面方向の剛性よりも低く、グラファイトのｃ軸方向の剛性よりも高い。 Table 1 shows the thermal conductivity [W / mK], linear expansion coefficient [ppm / K], and Young's modulus [GPa] of graphite and copper. Further, the linear expansion coefficient [ppm / K] and Young's modulus [GPa] of silicon and solder are also shown for reference.
As shown in Table 1, in the ab plane direction, graphite has a high thermal conductivity of 1500 [W / mK], a high Young's modulus of 1050 [GPa], and a linear expansion coefficient of -1 [ppm / K]. Very small. In graphite, the thermal conductivity in the c-axis direction is as low as 10 [W / mK], the Young's modulus is as low as 36 [GPa], and the linear expansion coefficient is as large as 25 [ppm / K]. The thermal conductivity of copper is 394 [W / mK], which is lower than the thermal conductivity in the ab plane direction of graphite and higher than the thermal conductivity in the c-axis direction of graphite. The linear expansion coefficient 17 [ppm / K] of copper is larger than the linear expansion coefficient of graphite in the ab plane direction and smaller than the linear expansion coefficient of graphite in the c-axis direction. The linear expansion coefficient of copper and the linear expansion coefficient of graphite in the c-axis direction are larger than the linear expansion coefficient of silicon [3 ppm / K]. Copper has a Young's modulus of 120 [GPa], which is lower than the Young's modulus in the ab plane direction of graphite and higher than the Young's modulus in the c-axis direction of graphite. Therefore, the rigidity of copper is lower than that of graphite in the ab plane direction and higher than that of graphite in the c-axis direction.

第１埋設部１６は、上記したように、グラファイトのｃ軸が面方向に揃っているため、第１埋設部１６では、厚さ方向の熱伝導率が１５００［Ｗ／ｍＫ］と高い。一方、第１埋設部１６の面方向の熱伝導率は、図１及び図２のｘ軸方向では１０［Ｗ／ｍＫ］であり、ｙ軸方向では１５００［Ｗ／ｍＫ］である。したがって、第１埋設部１６では、厚さ方向の熱伝導率が面方向の平均の熱伝導率よりも高いとともに、放熱板１５の母材である銅の熱伝導率３９４［Ｗ／ｍＫ］よりも高い。   As described above, since the c-axis of graphite is aligned in the surface direction, the first embedded portion 16 has a high thermal conductivity of 1500 [W / mK] in the thickness direction. On the other hand, the thermal conductivity in the surface direction of the first embedded portion 16 is 10 [W / mK] in the x-axis direction of FIGS. 1 and 2 and 1500 [W / mK] in the y-axis direction. Therefore, in the first embedded portion 16, the thermal conductivity in the thickness direction is higher than the average thermal conductivity in the plane direction, and from the thermal conductivity 394 [W / mK] of copper that is the base material of the heat sink 15. Is also expensive.

また、第２埋設部１７では、上記したように、グラファイトのｃ軸が半導体装置１０の厚さ方向に揃っている。そのため、第２埋設部１７では、面方向の線膨張係数が−１［ｐｐｍ／Ｋ］と小さい。一方、第１埋設部１６の面方向の線膨張係数は、図１及び図２のｘ軸方向では、２５［ｐｐｍ／Ｋ］であり、ｙ軸方向では、−１［ｐｐｍ／Ｋ］である。そのため、第２埋設部１７の面方向の線膨張係数は、第１埋設部１６の面方向の平均の線膨張係数よりも小さく、放熱板の母材である銅の線膨張係数１７［ｐｐｍ／Ｋ］よりも小さい。また、第２埋設部１７では、面方向のヤング率が１０５０［ＧＰａ］である。一方、第１埋設部１６の面方向のヤング率は、図１及び図２のｘ軸方向では、３６［ＧＰａ］であり、ｙ軸方向では、１０５０［ＧＰａ］である。したがって、第２埋設部１７の面方向の剛性は、第１埋設部１６の面方向の平均の剛性よりも高く、銅の剛性（ヤング率１２０［ＧＰａ］）よりも高い。
上記では面内の全方位について平均した面方向の線膨張係数とヤング率で説明したが、第１埋設部１６の線膨張係数が大きい方向（この場合ｘ軸方向）において、第２埋設部１７の線膨張係数が第１埋設部１６の線膨張係数よりも小さく、第２埋設部１７のヤング率が第１埋設部１６のヤング率よりも大きい関係に設定されていれば、第２埋設部１７によって第１埋設部１６が面方向に膨張することを抑制することができる。本実施例の場合、ｙ軸方向にはもともと第１埋設部１６の線膨張係数が小さく、第２埋設部１７で膨張を抑える必要がない。第１埋設部１６は専らｘ軸方向に伸びようとする。ｘ軸方向では、第２埋設部１７の線膨張係数が−１［ｐｐｍ／Ｋ］であり、第１埋設部１６の線膨張係数である２５［ｐｐｍ／Ｋ］よりも小さい。また、ｘ軸方向では、第２埋設部１７のヤング率が１０５０［ＧＰａ］であり、第１埋設部１６のヤング率である３６［ＧＰａ］よりも大きい。本実施例では、第１埋設部１６が伸びやすいｘ軸方向において、伸びにくくて強い第２埋設部１７で伸びにくくしているということができる。 In the second embedded portion 17, the graphite c-axis is aligned in the thickness direction of the semiconductor device 10 as described above. Therefore, in the 2nd embedding part 17, the linear expansion coefficient of a surface direction is as small as -1 [ppm / K]. On the other hand, the linear expansion coefficient in the surface direction of the first embedded portion 16 is 25 [ppm / K] in the x-axis direction of FIGS. 1 and 2 and −1 [ppm / K] in the y-axis direction. . Therefore, the linear expansion coefficient in the surface direction of the second embedded portion 17 is smaller than the average linear expansion coefficient in the surface direction of the first embedded portion 16, and the linear expansion coefficient of copper, which is the base material of the heat sink, is 17 [ppm / K]. In the second embedded portion 17, the Young's modulus in the surface direction is 1050 [GPa]. On the other hand, the Young's modulus in the surface direction of the first embedded portion 16 is 36 [GPa] in the x-axis direction of FIGS. 1 and 2 and 1050 [GPa] in the y-axis direction. Therefore, the rigidity in the surface direction of the second embedded portion 17 is higher than the average rigidity in the surface direction of the first embedded portion 16 and higher than the rigidity of copper (Young's modulus 120 [GPa]).
In the above description, the linear expansion coefficient and Young's modulus in the plane direction averaged over all in-plane directions have been described. However, in the direction in which the linear expansion coefficient of the first embedded portion 16 is large (in this case, the x-axis direction), the second embedded portion 17. If the linear expansion coefficient is smaller than the linear expansion coefficient of the first embedded portion 16 and the Young's modulus of the second embedded portion 17 is set to be larger than the Young's modulus of the first embedded portion 16, the second embedded portion 17 can suppress the first embedded portion 16 from expanding in the surface direction. In the case of the present embodiment, the linear expansion coefficient of the first embedded portion 16 is originally small in the y-axis direction, and there is no need to suppress expansion at the second embedded portion 17. The first embedded portion 16 tends to extend exclusively in the x-axis direction. In the x-axis direction, the linear expansion coefficient of the second embedded portion 17 is −1 [ppm / K], which is smaller than 25 [ppm / K], which is the linear expansion coefficient of the first embedded portion 16. In the x-axis direction, the Young's modulus of the second embedded portion 17 is 1050 [GPa], which is larger than 36 [GPa], which is the Young's modulus of the first embedded portion 16. In the present embodiment, it can be said that the first embedded portion 16 is made difficult to extend by the second embedded portion 17 that is hard to extend and strong in the x-axis direction.

次に、半導体素子１１の作動時での半導体素子１１の熱伝導態様及び熱変形状態を図２及び図４を参照して説明する。なお、図２の実線矢印は、放熱板１５内での熱の流れを示しており、破線矢印は、第１埋設部１６及び第２埋設部１７の熱膨張しやすい方向を示している。   Next, the heat conduction mode and thermal deformation state of the semiconductor element 11 when the semiconductor element 11 is in operation will be described with reference to FIGS. 2 indicate the flow of heat in the heat radiating plate 15, and the broken line arrows indicate the direction in which the first embedded portion 16 and the second embedded portion 17 are likely to thermally expand.

半導体素子１１が作動すると、半導体素子１１が発熱する。半導体素子１１で発生する熱は、接合部１２を通じて放熱板１５に伝導する。放熱板１５では、上記したように、第１埋設部１６が半導体素子１１に対応する部位に形成されている。第１埋設部１６は厚さ方向の熱伝導率が面方向の熱伝導率よりも高い。そのため、放熱板１５に伝導した熱は、第１埋設部１６を通じて、冷却器２５側へと伝導する。また、第１埋設部１６の厚さ方向の熱伝導率は、銅の熱伝導率よりも高いため、放熱板１５の中央領域に第１埋設部１６を設けない（中央領域を母材の銅のみで構成する）場合よりも、熱が半導体素子１１側から冷却器２５側へと伝導されやすくなる。これにより、半導体素子１１で発生する熱を、冷却器２５の下側を流れる冷却媒体に効率よく放熱することができる。また、第２埋設部１７では、面方向の熱伝導率が厚さ方向の熱伝導率よりも高い。そのため、半導体素子１１から放熱板１５へ伝導した熱の一部が、図２の実線矢印に示すように、第２埋設部１７を通じて放熱板１５の外縁側に向かって伝導する。また、熱の一部は、放熱板１５の母材からなる部位を通じて冷却器２５へと伝導する。   When the semiconductor element 11 operates, the semiconductor element 11 generates heat. Heat generated in the semiconductor element 11 is conducted to the heat radiating plate 15 through the joint 12. In the heat radiating plate 15, as described above, the first embedded portion 16 is formed in a portion corresponding to the semiconductor element 11. The first embedded portion 16 has a higher thermal conductivity in the thickness direction than in the surface direction. Therefore, the heat conducted to the heat radiating plate 15 is conducted to the cooler 25 side through the first embedded portion 16. Further, since the thermal conductivity in the thickness direction of the first embedded portion 16 is higher than the thermal conductivity of copper, the first embedded portion 16 is not provided in the central region of the radiator plate 15 (the central region is made of copper as a base material). Heat is more likely to be conducted from the semiconductor element 11 side to the cooler 25 side than in the case of (only configured). Thereby, the heat generated in the semiconductor element 11 can be efficiently radiated to the cooling medium flowing under the cooler 25. Further, in the second embedded portion 17, the thermal conductivity in the surface direction is higher than the thermal conductivity in the thickness direction. Therefore, a part of the heat conducted from the semiconductor element 11 to the heat radiating plate 15 is conducted toward the outer edge side of the heat radiating plate 15 through the second embedded portion 17 as indicated by solid line arrows in FIG. Further, part of the heat is conducted to the cooler 25 through a portion made of the base material of the heat radiating plate 15.

第１埋設部１６は、上記のように、面方向の平均の線膨張係数が大きいため、面方向に熱膨張しやすい。第１埋設部１６は、詳細には、ｘ軸方向の線膨張係数が大きいため、図２の破線矢印に示す方向に熱膨張しやすい。また、銅の熱膨張係数も比較的大きいため、半導体素子１１で発生する熱により放熱板１５の母材も熱膨張しやすい。一方、第２埋設部１７は、上記したように、面方向の線膨張係数が第１埋設部１６の面方向の線膨張係数及び銅の線膨張係数よりも小さく、熱膨張しにくい。また、第２埋設部１７の面方向の剛性が、第１埋設部１６の平均の面方向の剛性及び銅の剛性よりも高い。そのため、半導体素子１１で発生する熱が放熱板１５に伝導することによって、放熱板１５の中央領域の銅と第１埋設部１６とが面方向に熱膨張しようとしても、その熱膨張が第１埋設部１６の周囲に位置する第２埋設部１７によって抑制される。なお、第２埋設部１７は、厚さ方向の線膨張係数が大きいため、図２の破線に示すように、厚さ方向に膨張しやすい。また、第１埋設部１６は、厚さ方向の線膨張係数が小さい。   Since the first buried portion 16 has a large average linear expansion coefficient in the plane direction as described above, it tends to thermally expand in the plane direction. Specifically, since the first embedded portion 16 has a large linear expansion coefficient in the x-axis direction, the first embedded portion 16 is likely to thermally expand in the direction indicated by the dashed arrow in FIG. In addition, since the coefficient of thermal expansion of copper is relatively large, the base material of the heat sink 15 is likely to thermally expand due to the heat generated in the semiconductor element 11. On the other hand, as described above, the second embedded portion 17 has a smaller linear expansion coefficient in the surface direction than the linear expansion coefficient in the surface direction of the first embedded portion 16 and the linear expansion coefficient of copper, and is difficult to thermally expand. Further, the rigidity in the surface direction of the second embedded portion 17 is higher than the rigidity in the average surface direction of the first embedded portion 16 and the rigidity of copper. Therefore, even if the heat generated in the semiconductor element 11 is conducted to the heat radiating plate 15 and the copper in the central region of the heat radiating plate 15 and the first embedded portion 16 try to thermally expand in the surface direction, the thermal expansion is the first. It is suppressed by the second embedded portion 17 located around the embedded portion 16. Since the second embedded portion 17 has a large linear expansion coefficient in the thickness direction, the second embedded portion 17 easily expands in the thickness direction as shown by the broken line in FIG. Further, the first embedded portion 16 has a small linear expansion coefficient in the thickness direction.

したがって、半導体素子１１が発熱すると、放熱板１５は図４に示すように変形する。すなわち、放熱板１５は、外周領域に形成される第２埋設部１７によって、面方向に大きく膨張することを抑制することができる。そのため、半導体素子１１と放熱板１５との熱膨張の差異が軽減され、接合部１２に応力が作用することを抑制することができる。これにより、接合部１２に亀裂等が生じることによって接合部１２が劣化することをより適切に抑制することができる。また、半導体素子１１と放熱板１５との面方向の熱膨張の差異に起因して、半導体装置１０が面方向に反ることも抑制することができる。なお、図４に示すように、第２埋設部１７は、厚さ方向に熱膨張する。しかしながら、放熱板１５の外周領域には半導体素子１１が積層されておらず、また厚さ方向の熱膨張は接合部１２の応力として作用しない。したがって、放熱板１５の外周領域が厚さ方向で熱変形したとしても、この熱変形によって接合部１２に作用する応力は変化しないことから、接合部１２の劣化は抑制される。   Therefore, when the semiconductor element 11 generates heat, the heat sink 15 is deformed as shown in FIG. That is, the heat sink 15 can suppress large expansion in the surface direction by the second embedded portion 17 formed in the outer peripheral region. Therefore, the difference in thermal expansion between the semiconductor element 11 and the heat radiating plate 15 is reduced, and it is possible to suppress the stress from acting on the joint portion 12. Thereby, it can suppress more appropriately that the junction part 12 deteriorates when a crack etc. arise in the junction part 12. FIG. Further, it is possible to suppress the semiconductor device 10 from warping in the surface direction due to the difference in thermal expansion in the surface direction between the semiconductor element 11 and the heat radiating plate 15. In addition, as shown in FIG. 4, the 2nd embedment part 17 is thermally expanded in the thickness direction. However, the semiconductor element 11 is not laminated on the outer peripheral region of the heat sink 15, and thermal expansion in the thickness direction does not act as a stress of the joint 12. Therefore, even if the outer peripheral region of the heat radiating plate 15 is thermally deformed in the thickness direction, the stress acting on the joint portion 12 does not change due to the thermal deformation, so that deterioration of the joint portion 12 is suppressed.

（実施例２）
次に、図５を参照して実施例２の半導体装置３０を説明する。なお、図５においても、放熱板３５における熱の流れを実線矢印で示し、第１埋設部３６及び第２埋設部３７の熱膨張しやすい方向を破線矢印で示している。本実施例の半導体装置３０は、放熱板３５の構成が実施例１の放熱板１５と異なる。その他の構成は、実施例１と同じであるため、同じ構成の部材については実施例１と同じ符号で示し、その説明を省略する。 (Example 2)
Next, the semiconductor device 30 according to the second embodiment will be described with reference to FIG. Also in FIG. 5, the heat flow in the heat radiating plate 35 is indicated by solid arrows, and the direction in which the first embedded portion 36 and the second embedded portion 37 are likely to thermally expand is indicated by broken line arrows. The semiconductor device 30 of the present embodiment is different from the heat sink 15 of the first embodiment in the configuration of the heat sink 35. Since the other configuration is the same as that of the first embodiment, members having the same configuration are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

本実施例では、放熱板３５の中央領域に、複数の第１埋設部３６が形成されており、この点が実施例１と異なっている。第１埋設部３６は、実施例１と同様に、グラファイトのｃ軸が面方向（ｘｙ平面のx軸方向）に揃っており、グラファイトのａｂ平面が図６のｙｚ平面に沿って伸びている。そのため、上記したようにｘ軸方向の線膨張係数が、放熱板３５の母材である銅の線膨張係数よりも大きい。第１埋設部３６のｙ軸方向の長さは、実施例１の第１埋設部１６の長さと同じ長さであり、半導体素子１１のｙ軸方向の長さと同じ長さである。第１埋設部３６のｘ軸方向の長さは、実施例１の第１埋設部１６の長さよりも短く、第１埋設部３６は、ｘ軸方向に複数配列されている。なお、図５に示す例では、第１埋設部３６のｘ軸方向の長さは、実施例１の第１埋設部１６のｘ軸方向の長さの１／３未満の長さであり、３つの第１埋設部３６が、第１埋設部３６と放熱板の母材からなる部位とがｘ軸方向に沿って交互に出現するように形成されている。放熱板３５の外周領域に形成される第２埋設部３７は、実施例１の第２埋設部１７と同じ構成である。   In the present embodiment, a plurality of first embedded portions 36 are formed in the central region of the heat radiating plate 35, and this point is different from the first embodiment. In the first embedded portion 36, the c-axis of graphite is aligned in the plane direction (the x-axis direction of the xy plane) as in the first embodiment, and the ab plane of graphite extends along the yz plane of FIG. . Therefore, as described above, the linear expansion coefficient in the x-axis direction is larger than the linear expansion coefficient of copper which is the base material of the heat radiating plate 35. The length of the first embedded portion 36 in the y-axis direction is the same as the length of the first embedded portion 16 of the first embodiment, and the same length as the length of the semiconductor element 11 in the y-axis direction. The length of the first embedded portion 36 in the x-axis direction is shorter than the length of the first embedded portion 16 of the first embodiment, and a plurality of the first embedded portions 36 are arranged in the x-axis direction. In the example shown in FIG. 5, the length of the first embedded portion 36 in the x-axis direction is less than 1/3 of the length of the first embedded portion 16 of the first embodiment in the x-axis direction. The three first embedded portions 36 are formed such that the first embedded portions 36 and the portions made of the base material of the heat sink appear alternately along the x-axis direction. The second embedded portion 37 formed in the outer peripheral region of the heat radiating plate 35 has the same configuration as the second embedded portion 17 of the first embodiment.

放熱板３５の中央領域の全体に第１埋設部３６が形成されている場合には、第２埋設部３７によって中央領域の周囲から熱膨張が抑制されているとはいえ、第１埋設部３６のｘ軸方向の線膨張係数が大きいことから、放熱板３５がｘ軸方向に熱膨張しやすくなる。この点、本実施例では、中央領域の全体に第１埋設部３６を形成するのではなく、ｘ軸方向に第１埋設部３６と銅からなる部位とが交互に出現するように形成されているため、放熱板３５のｘ軸方向の熱膨張をより適切に抑制することができる。したがって、接合部１２の劣化をより適切に抑制することができる。なお、その他の構成及び作用効果は実施例１と同じである。   When the first embedded portion 36 is formed in the entire central region of the heat radiating plate 35, the first embedded portion 36 is said to be able to suppress thermal expansion from the periphery of the central region by the second embedded portion 37. Since the coefficient of linear expansion in the x-axis direction is large, the heat radiating plate 35 is likely to thermally expand in the x-axis direction. In this regard, in the present embodiment, the first embedded portion 36 is not formed in the entire central region, but the first embedded portion 36 and the portion made of copper are alternately formed in the x-axis direction. Therefore, the thermal expansion of the heat sink 35 in the x-axis direction can be more appropriately suppressed. Therefore, the deterioration of the joint portion 12 can be more appropriately suppressed. Other configurations and operational effects are the same as those of the first embodiment.

（実施例３）
次に、図６を参照して実施例３の半導体装置４０を説明する。なお、図６においても、放熱板４５における熱の流れを実線矢印で示し、第１埋設部４６及び第２埋設部４７ａ，４７ｂ，４７ｃの熱膨張しやすい方向を破線矢印で示している。本実施例の半導体装置４０は、放熱板４５の構成が上記各実施例の放熱板１５，２５と異なる。その他の構成は、実施例１と同じであるため、同じ構成の部材については実施例１と同じ符号で示し、その説明を省略する。 (Example 3)
Next, the semiconductor device 40 of Example 3 will be described with reference to FIG. Also in FIG. 6, the heat flow in the heat radiating plate 45 is indicated by solid arrows, and the direction in which the first embedded portion 46 and the second embedded portions 47a, 47b, 47c are likely to thermally expand is indicated by broken line arrows. The semiconductor device 40 of the present embodiment is different from the heat sinks 15 and 25 of the above embodiments in the configuration of the heat sink 45. Since the other configuration is the same as that of the first embodiment, members having the same configuration are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

本実施例では、放熱板４５の中央領域に形成される第１埋設部４６は、実施例１の第１埋設部１６と同じ構成である。放熱板４５の外周領域には、複数の第２埋設部４７ａ，４７ｂ，４７ｃが形成されており、この点が実施例１と異なっている。各第２埋設部４７ａ，４７ｂ，４７ｃでは、実施例１と同様に、グラファイトのｃ軸が半導体装置４０の厚さ方向に揃っているため、面方向の熱伝導率が厚さ方向の熱伝導率よりも高いとともに、その厚さ方向の熱伝導率が母材の熱伝導率よりも低い。   In the present embodiment, the first embedded portion 46 formed in the central region of the heat radiating plate 45 has the same configuration as the first embedded portion 16 of the first embodiment. A plurality of second embedded portions 47 a, 47 b, 47 c are formed in the outer peripheral region of the heat radiating plate 45, and this point is different from the first embodiment. In each of the second embedded portions 47a, 47b, and 47c, the c-axis of graphite is aligned in the thickness direction of the semiconductor device 40 as in the first embodiment, so that the thermal conductivity in the plane direction is the thermal conductivity in the thickness direction. The thermal conductivity in the thickness direction is lower than the thermal conductivity of the base material.

図６に示す例では、放熱板４５の外周領域に、内側第２埋設部４７ａ、中間第２埋設部４７ｂ、及び外側第２埋設部４７ｃの３つの第２埋設部が形成されており、これらが放熱板４５の中央領域側から外縁に向かって順に配列されている。各第２埋設部４７ａ，４７ｂ，４７ｃの平面視は、図示を省略するが、いずれも略矩形の枠形状である。各第２埋設部４７ａ，４７ｂ，４７ｃは、面方向の長さがいずれも同じ長さであり、実施例１の第２埋設部１６の面方向の長さの１／３未満の長さである。また、各第２埋設部４７ａ，４７ｂ，４７ｃは、厚さ方向の長さがいずれも同じ長さであり、実施例１の第２埋設部１６の長さと同じ長さである。放熱板４５の外縁側に最も近い外側第２埋設部４７ｃの内側に、中間第２埋設部４７ｂが収容され、その内側に内側第２埋設部４７ａが収容されている。各第２埋設部４７ａ，４７ｂ，４７ｃの間には、放熱板４５の母材である銅からなる部位が介在している。３つの第２埋設部４７ａ，４７ｂ，４７ｃは、その第２埋設部４７ａ，４７ｂ，４７ｃと放熱板４５の母材である銅からなる部位とが面方向（ｘ軸方向及びｙ軸方向）に交互に出現するように形成されている。   In the example shown in FIG. 6, three second embedded portions of an inner second embedded portion 47 a, an intermediate second embedded portion 47 b, and an outer second embedded portion 47 c are formed in the outer peripheral region of the heat radiating plate 45. Are arranged in order from the central region side of the heat sink 45 toward the outer edge. The plan view of each of the second embedded portions 47a, 47b, 47c is omitted from illustration, but has a substantially rectangular frame shape. Each of the second embedded portions 47a, 47b, 47c has the same length in the surface direction, and is less than 1/3 of the length in the surface direction of the second embedded portion 16 of the first embodiment. is there. Further, each of the second embedded portions 47a, 47b, 47c has the same length in the thickness direction, and is the same length as the second embedded portion 16 of the first embodiment. The intermediate second embedded portion 47b is accommodated inside the outer second embedded portion 47c closest to the outer edge side of the heat sink 45, and the inner second embedded portion 47a is accommodated inside thereof. Between each 2nd embedment part 47a, 47b, 47c, the site | part which consists of copper which is a base material of the heat sink 45 is interposing. The three second embedded portions 47a, 47b, and 47c have the second embedded portions 47a, 47b, and 47c and a portion made of copper that is a base material of the heat radiating plate 45 in a plane direction (x-axis direction and y-axis direction). It is formed to appear alternately.

本実施例では、放熱板４５の外周領域では、半導体素子１１から放熱板４５に伝導した熱が、まず内側第２埋設部４７ａを面方向に伝導する。その熱が放熱板４５の銅からなる部位に達すると、その熱の一部が、この銅からなる部位を通じて冷却器２５に向かう方向に伝導するとともに、残りの熱が、中間第２埋設部４７ｂを通じて面方向に伝導する。さらに、熱が中間第２埋設部４７ｂを伝導して放熱板４５の銅からなる部位に達すると、その熱の一部が、この銅からなる部位を通じて冷却器に向かう方向に伝導するとともに、残りの熱が、外側第２埋設部４７ｃを通じて面方向に伝導する。このような態様で、放熱板４５の外周領域では、熱が各第２埋設部４７ａ，４７ｂ，４７ｃを通じて面方向に伝導するとともに、銅からなる部位を冷却器２５側へと伝導する。本実施例の放熱板３５の外周領域では、実施例１の放熱板１５の外周領域よりも銅からなる部位が多いため、放熱板４５に伝導した熱を冷却器２５へ効率よく伝導することができる。その結果、半導体素子１１をより効果的に冷却することができる。なお、その他の構成及び作用効果は実施例１と同じである。   In the present embodiment, in the outer peripheral region of the heat radiating plate 45, the heat conducted from the semiconductor element 11 to the heat radiating plate 45 first conducts the inner second embedded portion 47a in the surface direction. When the heat reaches the copper portion of the heat radiating plate 45, part of the heat is conducted in the direction toward the cooler 25 through the copper portion, and the remaining heat is transferred to the intermediate second embedded portion 47b. Conducted through the plane. Further, when heat is conducted through the intermediate second embedded portion 47b and reaches the part made of copper of the heat radiating plate 45, a part of the heat is conducted in the direction toward the cooler through the part made of copper, and the rest The heat is conducted in the surface direction through the outer second embedded portion 47c. In such a manner, in the outer peripheral region of the heat radiating plate 45, heat is conducted in the surface direction through the second embedded portions 47a, 47b, 47c, and a portion made of copper is conducted to the cooler 25 side. In the outer peripheral region of the heat radiating plate 35 of the present embodiment, since there are more parts made of copper than the outer peripheral region of the heat radiating plate 15 of the first embodiment, the heat conducted to the heat radiating plate 45 can be efficiently conducted to the cooler 25. it can. As a result, the semiconductor element 11 can be cooled more effectively. Other configurations and operational effects are the same as those of the first embodiment.

（実施例４）
次に、図７を参照して実施例４の半導体装置５０を説明する。なお、図７においても、放熱板５５における熱の流れを実線矢印で示し、第１埋設部５６及び第２埋設部５７ａ，５７ｂ，５７ｃの熱膨張しやすい方向を破線矢印で示している。本実施例の半導体装置５０は、放熱板５５の構成が上記各実施例の放熱板１５，２５，３５と異なる。その他の構成は、実施例１と同じであるため、同じ構成の部材については実施例１と同じ符号で示し、その説明を省略する。 Example 4
Next, the semiconductor device 50 of Example 4 will be described with reference to FIG. Also in FIG. 7, the heat flow in the heat radiating plate 55 is indicated by solid arrows, and the direction in which the first embedded portion 56 and the second embedded portions 57a, 57b, and 57c are likely to thermally expand is indicated by broken line arrows. The semiconductor device 50 of the present embodiment is different from the heat sinks 15, 25, and 35 of the above embodiments in the configuration of the heat sink 55. Since the other configuration is the same as that of the first embodiment, members having the same configuration are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

本実施例では、放熱板５５の中央領域に形成される第１埋設部５６は、実施例１の第１埋設部１６と同じ構成である。放熱板５５の外周領域には、複数の第２埋設部５７ａ，５７ｂ，５７ｃが形成されている。図７に示す例では、放熱板５５の中央領域に、内側第２埋設部５７ｂ、中間第２埋設部５７ｂ、及び外側第２埋設部５７ｃの３つの第２埋設部が形成されている。各第２埋設部５７ａ，５７ｂ，５７ｃは、図示を省略するが平面視が枠形状であり、面方向の長さが、実施例３の第２埋設部４７ａ，４７ｂ，４７ｃの長さと同じである。一方、各第２埋設部５７ａ，５７ｂ，５７ｃは、厚さ方向の長さが、放熱板５５の外縁に近いほど長い。その結果、放熱板５５の外周領域では、中央領域に近い部位ほど銅からなる部位の厚さ方向の長さが長くなっている。   In the present embodiment, the first embedded portion 56 formed in the central region of the heat sink 55 has the same configuration as the first embedded portion 16 of the first embodiment. A plurality of second embedded portions 57 a, 57 b, 57 c are formed in the outer peripheral region of the heat radiating plate 55. In the example shown in FIG. 7, three second embedded portions of an inner second embedded portion 57 b, an intermediate second embedded portion 57 b, and an outer second embedded portion 57 c are formed in the central region of the heat radiating plate 55. Each of the second embedded portions 57a, 57b, and 57c has a frame shape in plan view, although not shown, and the length in the surface direction is the same as the length of the second embedded portions 47a, 47b, and 47c in the third embodiment. is there. On the other hand, each of the second embedded portions 57 a, 57 b, 57 c has a longer length in the thickness direction as it is closer to the outer edge of the radiator plate 55. As a result, in the outer peripheral region of the heat radiating plate 55, the portion in the thickness direction of the portion made of copper becomes longer as the portion is closer to the central region.

放熱板５５の外周領域では、放熱板５５の外縁側よりも中央領域側のほうが、半導体素子１１に近接しているため、半導体素子１１の熱が伝導されやすく、高温となりやすい。本実施例では、放熱板５５の外周領域のうち半導体素子１１の熱が伝導されやすい部位で、放熱板５５の銅からなる部位の厚さ方向の長さが長いため、半導体素子１１から放熱板５５に伝導された熱を銅からなる部位を通じて冷却器２５へ効率的に伝導することができる。また、各第２埋設部５７ａ，５７ｂ，５７ｃは、放熱板５５の外縁に近いほど厚さ方向に長いため、放熱板５５の外縁では面方向の熱膨張を抑制することができる。したがって、放熱板５５の外縁の内側に位置する領域においても放熱板５５の面方向の熱膨張を抑制することができるため、結果的に放熱板５５全体としての面方向の熱膨張を抑制することができる。なお、その他の構成及び作用効果は実施例３と同じである。   In the outer peripheral region of the heat radiating plate 55, since the central region side is closer to the semiconductor element 11 than the outer edge side of the heat radiating plate 55, the heat of the semiconductor element 11 is easily conducted, and the temperature tends to be high. In this embodiment, the heat conduction of the semiconductor element 11 in the outer peripheral region of the heat sink 55 is long, and the length of the heat sink 55 made of copper is long in the thickness direction. The heat conducted to 55 can be efficiently conducted to the cooler 25 through the portion made of copper. Moreover, since each 2nd embedding part 57a, 57b, 57c is long in the thickness direction, so that it is near the outer edge of the heat sink 55, it can suppress the thermal expansion of a surface direction at the outer edge of the heat sink 55. Accordingly, since the thermal expansion in the surface direction of the heat radiating plate 55 can be suppressed even in the region located inside the outer edge of the heat radiating plate 55, the thermal expansion in the surface direction of the heat radiating plate 55 as a whole is consequently suppressed. Can do. Other configurations and operational effects are the same as those of the third embodiment.

実施例４では、放熱板５５に複数の第２埋設部５７ａ，５７ｂ，５７ｃが形成されていが、実施例４の変形例として、放熱板に１つの第２埋設部を形成することによっても、第２埋設部の厚さ方向の長さを放熱板の外縁に近いほど長い構成とすることができる。例えば、第２埋設部の下面を傾斜状としたり段差状としたりすることによって、放熱板の外縁ほど厚さ方向の長さを長くすることができる。   In the fourth embodiment, the plurality of second embedded portions 57a, 57b, 57c are formed on the heat radiating plate 55, but as a modification of the fourth embodiment, by forming one second embedded portion on the heat radiating plate, The length of the second embedded portion in the thickness direction can be increased as the length is closer to the outer edge of the heat sink. For example, by making the lower surface of the second embedded portion inclined or stepped, the outer edge of the heat sink can be made longer in the thickness direction.

（実施例５）
次に、図８を参照して実施例５の半導体装置６０を説明する。本実施例では、放熱板６１の母材としてアルミニウム（Ａｌ（１０００））を用いている。また、接合部１２と放熱板６１との間に、ＤＢＡ（Direct Brazed Aluminum）層６４が形成されている。また、放熱板６１が冷却器２５に直接接合している。これらの点が実施例１と異なっているが、その他の構成は、実施例１と同じであるため、同じ構成の部材については実施例１と同じ符号で示し、その説明を省略する。 (Example 5)
Next, a semiconductor device 60 of Example 5 will be described with reference to FIG. In this embodiment, aluminum (Al (1000)) is used as the base material of the heat sink 61. A DBA (Direct Brazed Aluminum) layer 64 is formed between the joint 12 and the heat sink 61. Further, the heat radiating plate 61 is directly joined to the cooler 25. Although these points differ from Example 1, since the other structure is the same as Example 1, the same code | symbol is shown about the member of the same structure as Example 1, and the description is abbreviate | omitted.

ＤＢＡ層６４は、アルミニウム（Ａｌ（４Ｎ））からなる第１層６５と、絶縁体である窒化アルミニウムからなる第２層６６と、アルミニウムから（Ａｌ（４Ｎ））なる第３層６７とが、ろう付けによって積層されている。放熱板６１の中央領域に第１埋設部６２が形成されているとともに、外周領域に第２埋設部６３が形成されている。第１埋設部６２及び第２埋設部６３の構成は、実施例１の第１埋設部１６及び第２埋設部１７と同じである。冷却器２５は、高強度のアルミニウム（Ａｌ（３０００））からなる。   The DBA layer 64 includes a first layer 65 made of aluminum (Al (4N)), a second layer 66 made of aluminum nitride as an insulator, and a third layer 67 made of aluminum (Al (4N)). Laminated by brazing. A first embedded portion 62 is formed in the central region of the heat radiating plate 61, and a second embedded portion 63 is formed in the outer peripheral region. The configurations of the first embedded unit 62 and the second embedded unit 63 are the same as those of the first embedded unit 16 and the second embedded unit 17 of the first embodiment. The cooler 25 is made of high-strength aluminum (Al (3000)).

表２に、アルミニウムの物性を示す。

Figure 2011159662
Table 2 shows the physical properties of aluminum.
Figure 2011159662

放熱板６１の母材であるアルミニウムの線膨張率は、２３［ｐｐｍ／Ｋ］であり、半導体素子１１を構成するシリコンよりも線膨張率大きく、第２埋設部６３の面方向の線膨張係数よりも大きい。また、アルミニウムのヤング率は６５［ＧＰａ］であり、アルミニウムの剛性は、第２埋設部６３の面方向の剛性よりも低い。また、第１埋設部１６の厚さ方向の熱伝導率は、アルミニウムの熱伝導率２３７［Ｗ／Ｋｍ］よりも高い。したがって、本実施例においても、実施例１と同様に、第１埋設部６２を通じて冷却器２５への伝導させることができる。また、放熱板６１の面方向の熱膨張を第２埋設部６３よって抑制して、接合部１２の劣化をより適切に抑制することができる。なお、その他の作用効果は、実施例１と同じである。   The linear expansion coefficient of aluminum which is the base material of the heat sink 61 is 23 [ppm / K], which is larger than that of silicon constituting the semiconductor element 11, and the linear expansion coefficient in the surface direction of the second embedded portion 63. Bigger than. Further, the Young's modulus of aluminum is 65 [GPa], and the rigidity of aluminum is lower than the rigidity in the surface direction of the second embedded portion 63. Moreover, the thermal conductivity in the thickness direction of the first embedded portion 16 is higher than the thermal conductivity 237 [W / Km] of aluminum. Therefore, also in the present embodiment, it is possible to conduct to the cooler 25 through the first embedded portion 62 as in the first embodiment. Moreover, the thermal expansion of the surface direction of the heat sink 61 can be suppressed by the 2nd embedding part 63, and deterioration of the junction part 12 can be suppressed more appropriately. Other functions and effects are the same as those of the first embodiment.

（実施例６）
次に、図９を参照して実施例６の半導体装置７０を説明する。本実施例では、半導体素子１１において、放熱板１５が積層されている面と反対側の面にも、基板としての電極７２が接合部７１を介して積層されている点が、上記各実施例と異なっている。その他の構成は、実施例１と同じであるため、同じ構成の部材については実施例１と同じ符号で示し、その説明を省略する。 (Example 6)
Next, a semiconductor device 70 of Example 6 will be described with reference to FIG. In the present embodiment, in the semiconductor element 11, the electrode 72 as a substrate is stacked on the surface opposite to the surface on which the heat dissipation plate 15 is stacked via the joint portion 71. Is different. Since the other configuration is the same as that of the first embodiment, members having the same configuration are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

半導体素子１１は、図示しないワイヤを介して電極７２に接続されている。半導体素子の表面に電極が露出している場合には、その表面電極と電極７２を導電性接合部（例えばはんだ）７１で接合してもよい。電極７２の母材は銅である。電極７２では、半導体素子１１の積層範囲である中央領域に、第１埋設部７３が形成されており、中央領域の周囲の外周領域に第２埋設部７４が形成されている。なお、図９に示す例では、電極７２の中心が半導体素子１１の中心に対して、紙面右側にずれているため、電極７２の中央領域は、電極７２の中心に対して紙面左側にずれている。半導体素子１１と電極７２とが積層されている方向を厚さ方向とし、その方向と直交する方向を面方向とする。第１埋設部７３は、グラファイトのｃ軸が面方向に揃っており、グラファイトのａｂ平面が厚さ方向（ｙｚ平面と平行）に伸びている。また、第２埋設部７４ではグラファイトのｃ軸が厚さ方向に揃っており、グラファイトのａｂ平面が半導体装置の面方向に伸びている。   The semiconductor element 11 is connected to the electrode 72 via a wire (not shown). When the electrode is exposed on the surface of the semiconductor element, the surface electrode and the electrode 72 may be joined by a conductive joint (for example, solder) 71. The base material of the electrode 72 is copper. In the electrode 72, a first embedded portion 73 is formed in a central region that is a stacking range of the semiconductor elements 11, and a second embedded portion 74 is formed in an outer peripheral region around the central region. In the example shown in FIG. 9, since the center of the electrode 72 is shifted to the right side of the drawing with respect to the center of the semiconductor element 11, the central region of the electrode 72 is shifted to the left side of the drawing with respect to the center of the electrode 72. Yes. A direction in which the semiconductor element 11 and the electrode 72 are stacked is a thickness direction, and a direction orthogonal to the direction is a plane direction. In the first embedded portion 73, the c-axis of graphite is aligned in the plane direction, and the ab plane of graphite extends in the thickness direction (parallel to the yz plane). In the second embedded portion 74, the c-axis of graphite is aligned in the thickness direction, and the ab plane of graphite extends in the surface direction of the semiconductor device.

本実施例では、半導体素子１１が作動して発熱すると、その熱が放熱板１５と電極７２との双方を通じて放熱される。電極７２では、第１埋設部７３を通じて熱が厚さ方向に伝導し、電極７２を通じて半導体素子１１の熱が放熱される。また、電極７２は、外周領域に第２埋設部７４が形成されているため、電極７２の面方向の熱膨張を適切に抑制することができ、接合部７１の劣化を抑制することができる。なお、その他の作用効果は実施例１と同じである。   In this embodiment, when the semiconductor element 11 operates to generate heat, the heat is radiated through both the heat radiating plate 15 and the electrode 72. In the electrode 72, heat is conducted in the thickness direction through the first embedded portion 73, and the heat of the semiconductor element 11 is radiated through the electrode 72. Further, since the electrode 72 has the second embedded portion 74 formed in the outer peripheral region, the thermal expansion in the surface direction of the electrode 72 can be appropriately suppressed, and the deterioration of the joint portion 71 can be suppressed. Other functions and effects are the same as those of the first embodiment.

（実施例７）
次に、図１０を参照して実施例７の半導体装置８０を説明する。図１０は、実施例７の半導体装置８０の平面視である。なお、図１０では、絶縁体層と冷却器を省略して示している。上記各実施例では、放熱板上に一つの半導体素子が積層されている例を説明したが、本実施例では、放熱板８５上に複数の半導体素子８１，８２が積層されている。図１０に示す例では、放熱板８５上に、２つのＩＧＢＴ８１と２つのダイオード８２が積層されている。各ＩＧＢＴ８１と放熱板８５との間には図示しない接合部が介在しているとともに、各ダイオード８２と放熱板８５との間には図示しない接合部が介在している。接合部は、はんだ等で構成されている。 (Example 7)
Next, a semiconductor device 80 of Example 7 will be described with reference to FIG. FIG. 10 is a plan view of the semiconductor device 80 according to the seventh embodiment. In FIG. 10, the insulator layer and the cooler are omitted. In each of the above-described embodiments, an example in which one semiconductor element is stacked on the heat dissipation plate has been described. However, in this embodiment, a plurality of semiconductor elements 81 and 82 are stacked on the heat dissipation plate 85. In the example shown in FIG. 10, two IGBTs 81 and two diodes 82 are stacked on the heat dissipation plate 85. A junction (not shown) is interposed between each IGBT 81 and the heat sink 85, and a joint (not shown) is interposed between each diode 82 and the heat sink 85. The joint is made of solder or the like.

放熱板８５には、各ＩＧＢＴ８１の積層範囲である第１中央領域にＩＧＢＴ８１放熱用の第１埋設部８６が形成されており、各ダイオード８２の積層範囲である第２中央領域にダイオード８２放熱用の第１埋設部８７が形成されている。放熱板８５の第１中央領域及び第２中央領域の周囲である外周領域には、第２埋設部８８が形成されている。第２埋設部８８は、平面視が４つの枠を有する枠形状に形成されており、それぞれの枠の内部に各第１埋設部８６，８７がそれぞれ収容されている。各第１埋設部８６，８７は、グラファイトのａｂ平面が厚さ方向（ｙｚ平面と平行）に伸びている。また、第２埋設部８８ではグラファイトのｃ軸が厚さ方向に揃っており、グラファイトのａｂ平面が面方向に伸びている。   The heat radiating plate 85 is formed with a first buried portion 86 for radiating the IGBT 81 in a first central region that is a stacking range of each IGBT 81, and for radiating the diode 82 in a second central region that is a stacking range of each diode 82. The first embedded portion 87 is formed. A second embedded portion 88 is formed in the outer peripheral region around the first central region and the second central region of the heat radiating plate 85. The second embedded portion 88 is formed in a frame shape having four frames in plan view, and the first embedded portions 86 and 87 are accommodated inside the respective frames. In each of the first embedded portions 86 and 87, the ab plane of graphite extends in the thickness direction (parallel to the yz plane). In the second embedded portion 88, the c-axis of graphite is aligned in the thickness direction, and the ab plane of graphite extends in the surface direction.

本実施例では、各ＩＧＢＴ８１及び各ダイオード８２が作動して発熱すると、その熱が第１埋設部８６，８７通じて熱が厚さ方向に伝導し、各ＩＧＢＴ８１及び各ダイオード８２で発生する熱が放熱される。また、外周領域に第２埋設部８８が形成されているため、放熱板８５が面方向の熱膨張を適切に抑制することができ、接合部が劣化することをより適切に抑制することができる。なお、その他の作用効果は実施例１と同じである。   In this embodiment, when each IGBT 81 and each diode 82 are activated to generate heat, the heat is conducted through the first embedded portions 86 and 87 in the thickness direction, and the heat generated in each IGBT 81 and each diode 82 is generated. Heat is dissipated. Moreover, since the 2nd embedding part 88 is formed in the outer periphery area | region, the heat sink 85 can suppress appropriately the thermal expansion of a surface direction, and can suppress more appropriately that a junction part deteriorates. . Other functions and effects are the same as those of the first embodiment.

（実施例８）
次に、図１１を参照して実施例８の半導体装置９０を説明する。図１１は、実施例８の半導体装置９０の平面視であり、絶縁体層と冷却器を省略して示している。本実施例では、実施例7と同様に、放熱板９５上に２つのＩＧＢＴ８１と２つのダイオード８２が積層されており、これらの半導体素子８１，８２は図示しない接合部を解して放熱板９５に接合されている。本実施例では、放熱板９５の構成が実施例７の放熱板８５と異なるが、その他の構成は実施例７と同じである。 (Example 8)
Next, a semiconductor device 90 of Example 8 will be described with reference to FIG. FIG. 11 is a plan view of the semiconductor device 90 according to the eighth embodiment, in which an insulator layer and a cooler are omitted. In the present embodiment, similarly to the seventh embodiment, two IGBTs 81 and two diodes 82 are stacked on the heat sink 95, and these semiconductor elements 81 and 82 are released from the heat sink 95 through a junction (not shown). It is joined to. In the present embodiment, the configuration of the heat sink 95 is different from the heat sink 85 of the seventh embodiment, but other configurations are the same as those of the seventh embodiment.

放熱板９５には、各ＩＧＢＴ８１の積層範囲である第１中央領域にＩＧＢＴ８１放熱用の第１埋設部９６が形成されており、各ダイオード８２の積層範囲である第２中央領域にダイオード８２放熱用の第１埋設部９７が形成されている。各第１埋設部９６，９７の構成は、実施例７の各第１埋設部８６，８７の構成と同じである。放熱板８５の第１中央領域及び第２中央領域の周囲である外周領域には、複数の第２埋設部９９が形成されている。本実施例では、第２埋設部９９の形成態様が実施例７と異なる。複数の第２埋設部９９は、平面視が略矩形状の直方体状である。第２埋設部９９は、第１埋設部９６，９７の厚さ方向に伸びる４つの各側面に対応して、第１埋設部９６，９７の周囲の４箇所に配置されている。第１埋設部９６，９７の厚さ方向に伸びる４つの各側面と第２埋設部９９の第１埋設部９６，９７側で厚さ方向に伸びる側面とは略同じ形状である。第１埋設部９６，９７の厚さ方向に伸びる４つの各側面と第２埋設部９９の第１埋設部９６，９７側で厚さ方向に伸びる側面とが、放熱板９５の母材である銅からなる部位を介して対向している。   The heat radiating plate 95 is formed with a first buried portion 96 for radiating the IGBT 81 in a first central region that is a stacking range of the IGBTs 81, and for radiating the diode 82 in a second central region that is a stacking range of the diodes 82. The first embedded portion 97 is formed. The configurations of the first embedded portions 96 and 97 are the same as the configurations of the first embedded portions 86 and 87 of the seventh embodiment. A plurality of second embedded portions 99 are formed in the outer peripheral region around the first central region and the second central region of the heat radiating plate 85. In the present embodiment, the formation mode of the second embedded portion 99 is different from that of the seventh embodiment. The plurality of second embedded portions 99 have a rectangular parallelepiped shape in plan view. The second embedded portions 99 are arranged at four locations around the first embedded portions 96 and 97 corresponding to the four side surfaces extending in the thickness direction of the first embedded portions 96 and 97. The four side surfaces extending in the thickness direction of the first embedded portions 96 and 97 and the side surfaces extending in the thickness direction on the first embedded portions 96 and 97 side of the second embedded portion 99 have substantially the same shape. The four side surfaces extending in the thickness direction of the first embedded portions 96 and 97 and the side surfaces extending in the thickness direction on the first embedded portions 96 and 97 side of the second embedded portion 99 are base materials of the heat radiating plate 95. It faces through a part made of copper.

本実施例では、各ＩＧＢＴ８１及び各ダイオード８２が作動して発熱すると、その熱が第１埋設部９６，９７通じて熱が厚さ方向に伝導し、各ＩＧＢＴ８１及び各ダイオード８２で発生する熱が放熱される。また、放熱板９５は、外周領域に第２埋設部９９が形成されているため、放熱板９５が面方向の熱膨張を適切に抑制することができ、接合部が劣化することをより適切に抑制することができる。なお、その他の作用効果は実施例１と同じである。   In this embodiment, when each IGBT 81 and each diode 82 are activated to generate heat, the heat is conducted through the first embedded portions 96 and 97 in the thickness direction, and the heat generated in each IGBT 81 and each diode 82 is generated. Heat is dissipated. Moreover, since the 2nd embedding part 99 is formed in the outer peripheral area | region of the heat sink 95, the heat sink 95 can suppress the thermal expansion of a surface direction appropriately, and it is more appropriate that a junction part deteriorates. Can be suppressed. Other functions and effects are the same as those of the first embodiment.

（実施例９）
次に、図１２を参照して実施例９の半導体装置１００を説明する。図１２は、実施例９の半導体装置１００の平面視であり、絶縁体層と冷却器を省略して示している。本実施例では、実施例7と同様に、放熱板１０５上に２つのＩＧＢＴ８１と２つのダイオード８２が積層されており、これらの半導体素子８１，８２は図示しない接合部を解して放熱板１０５に接合されている。本実施例では、放熱板１０５の構成が実施例７の放熱板８５と異なるが、その他の構成は実施例７と同じである。 Example 9
Next, the semiconductor device 100 of Example 9 will be described with reference to FIG. FIG. 12 is a plan view of the semiconductor device 100 according to the ninth embodiment, in which an insulator layer and a cooler are omitted. In the present embodiment, similarly to the seventh embodiment, two IGBTs 81 and two diodes 82 are laminated on the heat sink 105, and these semiconductor elements 81 and 82 are dissipated through a junction (not shown) to form the heat sink 105. It is joined to. In the present embodiment, the configuration of the heat radiating plate 105 is different from that of the heat radiating plate 85 of the seventh embodiment, but other configurations are the same as those of the seventh embodiment.

放熱板１０５には、第１埋設部１０６が、各ＩＧＢＴ８１の積層範囲である第１中央領域と、各ダイオード８２の積層範囲である第２中央領域とに亘ってｙ軸方向に伸びており、放熱板１０５の外周領域の一部にも形成されている。また、第２埋設部１０７は、放熱板１０５の外周領域において、第１埋設部１０６を挟むようにｙ軸方向に伸びている。第１埋設部１０６は、ｃ軸が面方向（ｘｙ平面のｙ軸方向）に揃っており、グラファイトのａｂ平面が厚さ方向（ｘｚ平面と平行）に伸びている。第２埋設部１０７は、グラファイトのｃ軸が厚さ方向に揃っており、グラファイトのａｂ平面が面方向に伸びている。したがって、第１埋設部１０６は、面方向のうちｘ軸方向については、線膨張係数が第２埋設部１０７の面方向の線膨張係数と同じである。そのため、半導体素子８１，８２の発熱時に、半導体素子８１，８２に対して第１埋設部１０６がｘ軸方向に大きく熱膨張することはない。なお、第１埋設部１０６は面方向のうちｙ軸方向の線膨張係数は大きい。しかしながら、第１埋設部１０６の両側には、面方向（ｘ軸方向及びｙ軸方向の双方）に線膨張係数が小さい第２埋設部１０７が形成されている。したがって、第１埋設部１０６が半導体素子８１，８２の発熱時にｙ軸方向に熱膨張しようとしても、その両側の第２埋設部１０７がｙ軸方向に熱膨張しにくいことから、第１埋設部１０６のｙ軸方向の熱膨張が抑制される。このように、本実施例では、第１埋設部１０６の全周囲を第２埋設部１０７で囲うことなく、放熱板１０５の熱膨張を抑制することができる。また、本実施例では、実施例７よりも第１埋設部１０６を大きく形成することができるため、半導体素子８１，８２の放熱をより効果的に行うことができる。   In the heat sink 105, the first embedded portion 106 extends in the y-axis direction across the first central region that is the stacking range of the IGBTs 81 and the second central region that is the stacking range of the diodes 82. It is also formed in a part of the outer peripheral area of the heat sink 105. The second embedded portion 107 extends in the y-axis direction so as to sandwich the first embedded portion 106 in the outer peripheral region of the heat radiating plate 105. In the first embedded portion 106, the c-axis is aligned in the plane direction (the y-axis direction of the xy plane), and the ab plane of graphite extends in the thickness direction (parallel to the xz plane). In the second embedded portion 107, the c-axis of graphite is aligned in the thickness direction, and the ab plane of graphite extends in the surface direction. Accordingly, the first embedded portion 106 has the same linear expansion coefficient as that of the second embedded portion 107 in the x-axis direction in the surface direction. Therefore, when the semiconductor elements 81 and 82 generate heat, the first embedded portion 106 does not greatly expand in the x-axis direction with respect to the semiconductor elements 81 and 82. The first embedded portion 106 has a large linear expansion coefficient in the y-axis direction in the surface direction. However, on both sides of the first embedded portion 106, the second embedded portion 107 having a small linear expansion coefficient in the surface direction (both the x-axis direction and the y-axis direction) is formed. Therefore, even if the first embedded portion 106 attempts to thermally expand in the y-axis direction when the semiconductor elements 81 and 82 generate heat, the second embedded portions 107 on both sides thereof are difficult to thermally expand in the y-axis direction. The thermal expansion of the y-axis direction of 106 is suppressed. As described above, in this embodiment, the thermal expansion of the heat radiating plate 105 can be suppressed without enclosing the entire periphery of the first embedded portion 106 with the second embedded portion 107. In the present embodiment, since the first embedded portion 106 can be formed larger than in the seventh embodiment, the semiconductor elements 81 and 82 can be radiated more effectively.

（その他の実施例）
上記各実施例では、第１埋設部及び第２埋設部の材料として、グラファイトを用いているが、第１埋設部及び第２埋設部の材料として、その他の材料を用いるようにしてもよい。また、上記各実施例では、第１埋設部の面方向において、ｘ軸方向とｙ軸方向の熱伝導率、線膨張係数、及びヤング率が異なっているが、第１埋設部は、面方向の全ての方向において熱伝導率、線膨張係数、及びヤング率が同じであってもよい。 (Other examples)
In each of the above embodiments, graphite is used as the material of the first embedded portion and the second embedded portion, but other materials may be used as the material of the first embedded portion and the second embedded portion. Moreover, in each said Example, although the thermal conductivity of a x-axis direction and a y-axis direction, a linear expansion coefficient, and a Young's modulus differ in the surface direction of a 1st embedding part, a 1st embedding part is a surface direction. The thermal conductivity, linear expansion coefficient, and Young's modulus may be the same in all directions.

以上、本明細書に開示される技術の具体例を詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時の請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は、複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 As mentioned above, although the specific example of the technique disclosed by this specification was demonstrated in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

１０，３０，４０，５０，６０，７０，８０，９０，１００：半導体装置
１１：半導体素子
１２，７１：接合部
１５，３５，４５，５５，６１，８５，９５：放熱板
１６，３６，４６，５６，６２，７３，８６，８７，９６，９７，１０６：第１埋設部
１７，３７，４７ａ，４７ｂ，４７ｃ，５７ａ，５７ｂ，５７ｃ，６３，７４，８８，９９，１０７：埋設部
１８：炭素原子
２０：絶縁体層
２５：冷却器
２６：冷却板
２７：フィン
６２：ＤＢＡ層
６５：第１層
６６：第２層
６７：第３層
７２：電極
８１：ＩＧＢＴ
８２：ダイオード 10, 30, 40, 50, 60, 70, 80, 90, 100: Semiconductor device 11: Semiconductor element 12, 71: Junction 15, 35, 45, 55, 61, 85, 95: Heat radiation plate 16, 36, 46, 56, 62, 73, 86, 87, 96, 97, 106: first embedded portion 17, 37, 47a, 47b, 47c, 57a, 57b, 57c, 63, 74, 88, 99, 107: embedded portion 18: carbon atom 20: insulator layer 25: cooler 26: cooling plate 27: fin 62: DBA layer 65: first layer 66: second layer 67: third layer 72: electrode 81: IGBT
82: Diode

Claims (6)

半導体素子と、その半導体素子に直接的又は間接的に積層されている基板と、その半導体素子とその基板との間に介在するとともに、その半導体素子とその基板との相対的な位置関係を固定する接合部とを備えており、
前記基板は、前記半導体素子の積層範囲に対応する中央領域と、その中央領域の周囲に伸びている外周領域を備えており、
前記半導体素子と前記基板とが積層されている方向を厚さ方向とし、その厚さ方向と直交する面に沿った方向を面方向とした場合に、
前記基板の前記中央領域に、厚さ方向の熱伝導率が面方向の熱伝導率及び前記基板の母材の熱伝導率よりも高い第１埋設部が形成されているとともに、前記基板の前記外周領域に、面方向の線膨張係数が前記第１埋設部の面方向の線膨張係数及び前記基板の母材の線膨張係数よりも小さく且つ面方向の剛性が前記第１埋設部の面方向の剛性及び前記基板の母材の剛性よりも高い第２埋設部が形成されていることを特徴とする半導体装置。 A semiconductor element, a substrate directly or indirectly stacked on the semiconductor element, and the semiconductor element and the substrate are interposed between the semiconductor element and the substrate, and the relative positional relationship between the semiconductor element and the substrate is fixed. And a joining portion to be
The substrate includes a central region corresponding to the stacking range of the semiconductor elements, and an outer peripheral region extending around the central region,
When the direction in which the semiconductor element and the substrate are stacked is the thickness direction, and the direction along the surface perpendicular to the thickness direction is the surface direction,
In the central region of the substrate, a first embedded portion having a thermal conductivity in the thickness direction higher than the thermal conductivity in the plane direction and the thermal conductivity of the base material of the substrate is formed, and the In the outer peripheral region, the linear expansion coefficient in the surface direction is smaller than the linear expansion coefficient in the surface direction of the first embedded portion and the linear expansion coefficient of the base material of the substrate, and the rigidity in the surface direction is the surface direction of the first embedded portion. And a second embedded portion higher than the rigidity of the base material of the substrate is formed. 前記第１埋設部及び第２埋設部が六方晶構造のグラファイトで構成されており、前記第１埋設部ではグラファイトのｃ軸が前記面方向に揃っており、前記第２埋設部ではグラファイトのｃ軸が前記厚さ方向に揃っていることを特徴とする請求項１に記載の半導体装置。   The first embedded portion and the second embedded portion are made of graphite having a hexagonal structure, and the c-axis of graphite is aligned in the plane direction in the first embedded portion, and the c of graphite is aligned in the second embedded portion. The semiconductor device according to claim 1, wherein axes are aligned in the thickness direction. 前記基板の全表面がその基板の母材からなり、前記第１埋設部及び前記第２埋設部が前記基板の表面に露出していないことを特徴とする請求項１又は２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the entire surface of the substrate is made of a base material of the substrate, and the first embedded portion and the second embedded portion are not exposed on the surface of the substrate. . 前記第１埋設部は、前記面内の少なくとも１方向における線膨張係数が前記基板の母材の線膨張係数よりも大きく、
前記基板の前記中央領域では、複数個の前記第１埋設部が、その第１埋設部と前記基板の母材からなる部位とが前記１方向に沿って交互に出現するように形成されていることを特徴とする請求項１から３のいずれか１項に記載の半導体装置。 The first embedded portion has a linear expansion coefficient in at least one direction in the plane larger than the linear expansion coefficient of the base material of the substrate,
In the central region of the substrate, a plurality of the first embedded portions are formed such that the first embedded portions and the portions made of the base material of the substrate appear alternately along the one direction. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 前記基板の前記半導体素子が積層されている側と反対側の面が冷却器に接合しており、
前記第２埋設部の面方向の熱伝導率が厚さ方向の熱伝導率よりも高いとともに、その厚さ方向の熱伝導率が前記基板の母材の熱伝導率よりも低く、
前記基板の前記外周領域に、複数個の前記第２埋設部が、その第２埋設部と前記基板の母材からなる部位とが面方向に交互に出現するように形成されていることを特徴とする請求項１から４のいずれか１項に記載の半導体装置。 The surface of the substrate opposite to the side where the semiconductor elements are stacked is bonded to a cooler,
The thermal conductivity in the surface direction of the second embedded portion is higher than the thermal conductivity in the thickness direction, and the thermal conductivity in the thickness direction is lower than the thermal conductivity of the base material of the substrate,
A plurality of the second embedded portions are formed in the outer peripheral region of the substrate such that the second embedded portions and the portions made of the base material of the substrate appear alternately in the surface direction. The semiconductor device according to any one of claims 1 to 4. 前記基板の前記半導体素子が積層されている側と反対側の面が冷却器に接合しており、
前記第２埋設部の面方向の熱伝導率が厚さ方向の熱伝導率よりも高いとともに、その厚さ方向の熱伝導率が前記基板の母材の熱伝導率よりも低く、
前記基板の外縁に近いほど前記第２埋設部の厚さ方向の長さが長いことを特徴とする請求項１から５のいずれか１項に記載の半導体装置。 The surface of the substrate opposite to the side where the semiconductor elements are stacked is bonded to a cooler,
The thermal conductivity in the surface direction of the second embedded portion is higher than the thermal conductivity in the thickness direction, and the thermal conductivity in the thickness direction is lower than the thermal conductivity of the base material of the substrate,
6. The semiconductor device according to claim 1, wherein a length of the second embedded portion in a thickness direction is longer as it is closer to an outer edge of the substrate.
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