JP2011151461A - Solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent leakage of charges to an OB area by a simple configuration. <P>SOLUTION: A light receiving part includes an exposure area, the OB area and a charge discharge area. The exposure area generates an image signal equivalent to an incident optical image, and the OB area generates a black pixel signal equivalent to the black of the optical image. The charge discharge area has a charge discharge pixel 20d, and the charge discharge pixel 20d includes a PD 21d, an FD 22d, a transfer transistor 23d, and a reset transistor 24d. The PD 21d and the FD 22d store the charges leaking out from the exposure area. The transfer transistor 23d transfers the charges stored in the PD 21d to the FD 22d. The reset transistor 24d discharges the charges stored in the FD 22d to a voltage source Vdd. The transfer transistor 23d and the reset transistor 24d are always maintained to be ON. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device capable of generating a black pixel signal corresponding to optical black with high accuracy with a simple configuration even when strong light is incident.

  The solid-state imaging device is provided with an exposure region and an optical black (OB) region. In the exposure area and the OB area, a plurality of pixels that generate charges according to the amount of received light are two-dimensionally arranged. The pixels in the OB region are shielded from light by the light shielding film.

  With such a configuration, an image signal corresponding to an optical image formed in the exposure region is generated by generating a pixel signal corresponding to the amount of received light by each pixel in the exposure region. In addition, a black pixel signal is generated by each pixel in the OB region in order to determine a reference for the signal intensity of the pixel signal corresponding to zero light reception amount in the exposure region.

  An image with high reproducibility can be created by adjusting the black reference of each pixel signal in the exposure region using the black pixel signal. Therefore, in order to adjust the black reference, a highly accurate black pixel signal is required.

  On the other hand, when high-intensity light enters an exposure area near the OB area, light leakage or blooming from the exposure area occurs. When such light leakage or blooming occurs, the signal intensity of the black pixel signal becomes larger than the original signal intensity even though the pixels in the OB area are shielded from light, and it is difficult to create a highly accurate image. It was.

  Thus, it has been proposed to detect the amount of light leakage and use a black pixel signal or an electrically generated reference signal according to the amount of leakage for black reference adjustment (see Patent Document 1). It has also been proposed to detect the amount of light leakage and change the number of black pixel signals used for black reference adjustment according to the amount of leakage (see Patent Document 2).

  However, in Patent Document 1, a circuit for switching between a black pixel signal and a reference signal is necessary, which causes a complicated manufacturing process and an increase in manufacturing cost. Further, in Patent Document 2, since the number of black pixel signals used for black reference adjustment decreases as the amount of light leakage increases, accurate black reference adjustment is difficult.

Japanese Patent Laid-Open No. 9-247552 JP 2007-158830 A

  Accordingly, an object of the present invention is to provide a solid-state imaging device capable of outputting a highly accurate black pixel signal with a simple configuration.

  The solid-state imaging device of the present invention has the same structure as the first pixel, and an exposure region in which first pixels that generate charges according to the amount of received light and output pixel signals based on the charges are two-dimensionally arranged. And a black region in which a second pixel that outputs a black pixel signal that serves as a black reference for the pixel signal and whose light-receiving surface is shielded is disposed, and is generated and exposed in the first pixel that is disposed between the exposure region and the black region. A discharge region for discharging the charge leaking from the region in a discharge period exceeding a predetermined ratio in the exposure period to the exposure region.

  Note that the first pixel has a first photoelectric conversion element that generates electric charge according to the amount of received light, and a third capacitor that stores electric charge leaking from the first pixel in the discharge region. It is preferable that the charge stored in the third capacitor in which the pixel is arranged is discharged during the discharge period.

  The third pixel is connected to the third capacitor and has a third reset transistor that discharges the electric charge accumulated in the third capacitor when the third pixel is turned on. The third reset transistor is turned on during the discharge period. It is preferred that the charge be discharged during the discharge period by maintaining.

  Alternatively, it is preferable that the charge accumulated in the third capacitor is discharged during the discharge period by directly connecting the third capacitor to the reference potential source.

  The first pixel has a first capacitor whose potential changes according to the charge transferred and accumulated from the first photoelectric conversion element, and a first amplification transistor that generates a pixel signal based on the potential of the first capacitor. And a first reset transistor that is connected to the first capacitor and discharges the electric charge accumulated in the first capacitor when turned on, and the second pixel has a light-receiving surface shielded and charges corresponding to the amount of light received Generating a black pixel signal based on the potential of the second capacitor and the second capacitor whose potential changes according to the charge transferred and accumulated from the second photoelectric conversion element And a second reset transistor that is connected to the second capacitor and discharges the electric charge accumulated in the second capacitor when turned on, and the third pixel corresponds to the amount of received light A third photoelectric conversion element for generating electric charge and a third amplification transistor for generating a discharge signal based on the potential of the third capacitor; the third capacitor is transferred from the third photoelectric conversion element and stored; It is preferable that the electric potential changes depending on the electric charge.

  In addition, it is preferable that the electric charge leaking from the first pixel is also accumulated in the third photoelectric conversion element, and the electric charge accumulated in the third photoelectric conversion element is transferred to the third capacitor during the discharging period.

  In addition, the third pixel has a third transfer transistor that transfers the charge from the third photoelectric conversion element to the third capacitor when the third pixel is ON, and the third transfer transistor is maintained ON during the discharge period. The charge is preferably transferred during the discharge period.

  Alternatively, it is preferable that the charge accumulated in the third photoelectric conversion element is transferred to the third capacitor during the discharge period by directly connecting the third photoelectric conversion element to the third capacitor.

  The first pixel has a first transfer transistor that transfers the electric charge from the first photoelectric conversion element to the first capacitor when the first pixel is ON, and the second pixel has a second transfer transistor when the second pixel is ON. It is preferable to have a second transfer transistor that transfers charges from the photoelectric conversion element to the second capacitor.

  The third photoelectric conversion element is preferably shielded from light.

  The discharge period is the entire period during which the solid-state image sensor is in operation, and it is preferable that the charge leaking from the exposure area is always discharged from the discharge area.

  According to the present invention, it is possible to prevent electric charges leaking from the exposed region to leak to the black region with a simple configuration, and it is possible to maintain high accuracy of the black pixel signal.

It is a block diagram which shows typically the whole structure of the CMOS image pick-up element to which one Embodiment of this invention is applied. It is a top view which shows the structure of a light-receiving part. It is a circuit diagram which shows the internal structure of an exposure pixel. It is a circuit diagram which shows the internal structure of an OB pixel. It is a circuit diagram which shows the internal structure of a charge discharge pixel. It is a graph which shows the signal intensity | strength of the signal produced | generated by each pixel when the high-intensity light injects with respect to the CMOS image sensor of the conventional structure. It is a graph which shows the signal intensity | strength of the signal produced | generated by each pixel when high-intensity light injects with respect to the CMOS image sensor of this embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a configuration diagram schematically showing the overall configuration of a CMOS image sensor to which an embodiment of the present invention is applied.

  The CMOS image sensor 10 includes a light receiving unit 11, a vertical shift register 12, a correlated double sampling / sample hold (CDS / SH) circuit 13, a horizontal shift register 14, and a horizontal output line 15. The light receiving unit 11 and the vertical shift register 12 are directly connected, and the horizontal output line 15 is connected to the light receiving unit 11 via the CDS / SH circuit 13.

  A plurality of pixels 20 are arranged in a matrix on the imaging surface of the light receiving unit 11. Signal charges are generated in the individual pixels 20. The image signal of the entire subject image is composed of a set of pixel signals corresponding to the signal charges of some pixels 20 on the imaging surface. The generated pixel signal is read out for each pixel 20. The pixel 20 to be read is selected directly or indirectly by the vertical shift register 12 and the horizontal shift register 14.

  A row of pixels 20 is selected by the vertical shift register 12. The pixel signal output from the selected pixel 20 is correlated double-sampled by the CDS / SH circuit 13 via a vertical output line (not shown in FIG. 1).

  Further, the pixel signal held in the CDS / SH circuit 13 is selected by the horizontal shift register 14 and output to the horizontal output line 15. The pixel signal output to the horizontal output line 15 is sent to, for example, a signal processing circuit (not shown) that performs signal processing, and is subjected to predetermined processing such as black reference adjustment to generate an image signal of the entire subject image. Generated.

  As shown in FIG. 2, an exposure area 11e, an optical black (OB) area 11b, and a charge discharge area 11d are formed on the rectangular light receiving surface 11. The exposure region 11e occupies most of the light receiving surface 11, and the OB region 11b is formed on the upper side and the left side of the light receiving surface. The charge discharge region 11d is formed so as to be sandwiched between the exposure region 11e and the OB region 11b.

  An exposure pixel (not shown in FIG. 2), an OB pixel (not shown in FIG. 2), and a charge discharge pixel (not shown in FIG. 2) are included in the exposure region 11e, the OB region 11b, and the charge discharge region 11d. Is provided.

  The configuration of the exposure pixel will be described in more detail. FIG. 3 is a circuit diagram showing a configuration of the exposure pixel 20e (first pixel). The exposed pixel 20e includes a photodiode (PD) 21e (first photoelectric conversion element), a floating diffusion (FD) 22e (first capacitor), a transfer transistor 23e (first transfer transistor), and a reset transistor 24e (first transistor). 1 transfer transistor), an amplification transistor 25e (first amplification transistor), and a row selection transistor 26e.

  The PD 21e is connected to the FD 22e via the transfer transistor 23e. The FD 22e is connected to the gate of the amplification transistor 25e. The source of the amplification transistor 25e is connected to the vertical output line 27 via the row selection transistor 26e.

  In the PD 21e, charges are generated according to the amount of light received for each exposure pixel 20e, and the generated charges are accumulated. When the transfer transistor 23e is turned on, the signal charge accumulated in the PD 21e is transferred to the FD 22e.

  Note that the potential of the FD 22e varies depending on the accumulated charge. By the amplification transistor 25e, a signal potential corresponding to the potential of the FD 22e can be output as a pixel signal. When the row selection transistor 26 e is turned on, the pixel signal that can be output by the amplification transistor 25 e is output to the vertical output line 27.

  The gates of transfer transistor 23e and row selection transistor 26e are connected to a transfer control line (not shown) and a row selection control line (not shown), respectively. A transfer signal Φt and a row selection signal Φsl for switching between HIGH and LOW are supplied from the vertical shift register 12 to the transfer control line and the row selection control line, respectively.

  A transfer control line and a row selection control line are provided for each row in which the exposure pixels 20e are arranged. The gates of the transfer transistor 23e and the row selection transistor 26e of the exposure pixel 20e arranged in the same row are connected to the same transfer control line and row selection control line, respectively, and are turned ON / OFF at the same timing.

  The FD 22e is connected to a voltage source Vdd (reference potential source) via a reset transistor 24e. When the reset transistor 24e is turned on, the charge accumulated in the FD 22e is swept out to the voltage source Vdd and reset. By resetting the FD 22e, the potential of the FD 22e is reset to a potential obtained by subtracting the threshold voltage of the reset transistor 25 from the potential of the voltage source Vdd.

  The gate of the reset transistor 24e is connected to a reset control line (not shown). A reset signal Φr for switching between HIGH and LOW is supplied from the vertical shift register 12 to the reset control line.

  The reset control line is provided for each row where the exposure pixels 20e are arranged. The gates of the reset transistors 24e of the exposure pixels 20e arranged in the same row are connected to the same reset control line, and are turned on / off at the same timing.

  The vertical output line 27 is a line extending vertically through the light receiving unit 11, and is connected to the row selection transistors 26e of the plurality of exposure pixels 20e in the same column. The vertical output line 27 is connected to the current source Iss above the light receiving surface. The vertical output lines 27 of each column are separately connected to the CDS / SH circuit 13 below the light receiving unit 11.

  The CDS / SH circuit 13 is provided with separate capacitors (not shown) that hold a reset pixel signal that is a pixel signal at the time of resetting and a mixed pixel signal that is a pixel signal at the time of signal charge accumulation.

  When the prehold signal Φshp input to the CDS / SH circuit 13 is HIGH, a pixel signal corresponding to the potential of the vertical output line 27 is held in a capacitor (not shown) that holds the reset pixel signal. When the data hold signal Φshd input to the CDS / SH circuit 13 is HIGH, a pixel signal corresponding to the potential of the vertical output line 28 is held in a capacitor (not shown) that holds the mixed pixel signal. The pre-hold signal Φshp and the data hold signal Φshd are output from the vertical shift register 12.

  A data pixel signal obtained by subtracting the reset pixel signal from the mixed pixel signal is output from the output terminal of the CDS / SH circuit 13. The output terminal of the CDS / SH circuit 13 is connected to the horizontal output line 15 via the column selection transistor 16. Therefore, when the column selection transistor 16 is turned on, the data pixel signal is output from the CMOS image sensor 10 via the horizontal output line 15.

  The gate of the column selection transistor 16 is connected to a column selection signal line (not shown). A column selection signal Φsc for switching between HIGH and LOW is connected to the column selection signal line. A column selection signal Φsc is supplied to each column selection transistor 16 at a timing determined from the horizontal shift register 14.

  Next, the configuration of the OB pixel will be described in more detail. FIG. 4 is a circuit diagram showing a configuration of the OB pixel (second pixel) 20b. The OB pixel 20b includes PD 21b (second photoelectric conversion element), FD 22b (second capacitor), transfer transistor 23b (second transfer transistor), reset transistor 24b (second reset transistor), and amplification transistor 25b (second transistor). 2 amplification transistors) and a row selection transistor 26b.

  The circuit configuration inside the OB pixel 20b is the same as that of the exposure pixel 20e except that the PD 21b is shielded from light.

  Note that the gate of the transfer transistor 23b of the OB pixel 20b is connected to a transfer control line connected to the transfer transistor 23e of the exposure pixel 20e arranged in the same row, and ON / OFF is switched at the same timing.

  Further, the gate of the row selection transistor 26b of the OB pixel 20b is connected to a transfer control line connected to the transfer transistor 26e of the exposure pixel 20e arranged in the same row, and ON / OFF is switched at the same timing.

  Further, the gate of the reset transistor 24b of the OB pixel 20b is connected to a reset control line connected to the reset transistor 24e of the exposure pixel 20e arranged in the same row, and ON / OFF is switched at the same timing.

  By forming the OB pixel 20b as described above and performing the correlated double sampling process in the CDS / SH circuit 13 as described above in the same manner as the exposure pixel 20e, the black pixel signal from which the pixel signal component at the time of reset is removed is obtained. Output from the CMOS image sensor 10. Since the PD 21b of the OB pixel 20b is shielded from light as described above, the signal intensity of the black pixel signal corresponds to optical black formed on the exposure pixel 20e.

  Next, the configuration of the charge discharge pixel 20d will be described in more detail. FIG. 5 is a circuit diagram showing the configuration of the charge discharging pixel 20d (third pixel). The charge discharge pixel 20d includes a PD 21d (third photoelectric conversion element), an FD 22d (third capacitor), a transfer transistor 23d (third transfer transistor), a reset transistor 24d (third transfer transistor), and an amplification transistor 25d. (Third amplification transistor) and a row selection transistor 26d are provided.

  The circuit configuration inside the charge discharge pixel 20d is the same as that of the OB pixel 20b, except that the gates of the transfer transistor 23d and the reset transistor 24d are not connected to the transfer control line and the reset control line connected to the exposure pixel 20e and the OB pixel 20b. The same.

  The gates of the transfer transistor 23d and the reset transistor 24d of the charge discharge pixel 20d are connected to a common discharge control line (not shown). A common signal Φc that is kept in a HIGH state is supplied to the discharge control line.

  Therefore, the transfer transistor 23d and the reset transistor 24d are always kept ON, the charge accumulated in the PD 21d is always transferred to the FD 23d, and the charge accumulated in the FD 23d is always swept out to the voltage source Vdd.

  Although a pixel signal based on the potential of the FD 23d can be generated in the discharge pixel 20d, it is not output from the CMOS image sensor 10 and is not used to create a received optical image.

  As described above, according to the CMOS image sensor 10 of the first embodiment, a black pixel signal with high accuracy can be generated even when a high-luminance subject image is incident as described below. Therefore, it is possible to create an image with high reproducibility.

  As described above, when high-luminance light is incident on the exposure region 11e, charges generated in the exposure pixel 20e leak to neighboring pixels.

  When high-intensity light is incident on an exposure region with respect to a CMOS image sensor that does not have a charge discharge region as in a conventional CMOS image sensor, an OB arranged near the exposure region as shown in FIG. The signal intensity of the black pixel signal of the pixel is greater than the signal intensity of the black pixel signal that should be output without charge leakage, that is, the signal intensity of the signal corresponding to optical black. Therefore, when the black pixel signal of the OB pixel from which charge is leaked is used, the black reference adjustment accuracy is deteriorated.

  On the other hand, according to the CMOS image sensor 10 of the present embodiment, as shown in FIG. 7, the charge leaked from the exposure region 11e is discharged by the charge discharge pixel 20d of the charge discharge region 11d before reaching the OB region 11b. Is done. Therefore, it is possible to output a black pixel signal having a signal intensity corresponding to optical black from the OB pixel 20b in the OB region 11b.

  In the present embodiment, the reset transistor 24d is provided in the discharge pixel 20d, but the FD 22d and the voltage source Vdd may be directly connected without providing the reset transistor 24d. Alternatively, any configuration in which the electric charge accumulated in the FD 23d is always discharged to the voltage source Vdd may be used.

  In the present embodiment, the transfer transistor 23d is provided in the discharge pixel 20d. However, the PD 21d and the FD 22d may be directly connected without providing the transfer transistor 23d. Alternatively, any configuration in which the charge accumulated in the PD 21d is always discharged to the voltage source Vdd may be used.

  In the present embodiment, the PD 21d of the discharge pixel 20d is shielded from light, but may not be shielded from light. However, if the light is not shielded, the charge is generated also in the PD 21d, so that it cannot be sufficiently discharged by the FD 22d, and the charge may leak to the OB region 11b. Therefore, as in this embodiment, it is preferable that the PD 21d of the discharge pixel 20d is also shielded from light.

  In the present embodiment, the transfer transistor 23d of the discharge pixel 20d is always turned on, but the transfer transistor 23d may not be always turned on. If the reset transistor 24d is always ON, the charge leaked to the discharge pixel 20d can be discharged to the voltage source Vdd. However, the area occupied by the PD 21d in the single discharge pixel 20d is large, and most of the charge leaking from the exposure area 11e is accumulated in the PD 21d. Therefore, charges may leak from the PD 21d to the OB region 11b while the transfer transistor 23d is OFF. Therefore, as in the present embodiment, it is preferable that the transfer transistor 23d is always kept ON, and the charge accumulated in the PD 21d is always discharged through the FD 22d.

  Further, in the present embodiment, the transfer transistor 23d and the reset transistor 24d of the discharge pixel 20d are always kept ON, but they may not always be kept ON. It is configured to be kept ON during a discharge period exceeding a predetermined ratio with respect to an exposure period to be exposed in the exposure area 11e for generating a single frame image signal, and charges are discharged from the PD 21d and the FD 22d. Also good. It should be noted that the discharge period may be determined so that the charge does not leak to the OB region 11b even if the charge cannot be discharged during the exposure period other than the discharge period.

  In the present embodiment, the PD 21d, the FD 22d, the amplification transistor 25d, and the row selection transistor 26d are provided in the discharge pixel 20d. The PD 21d, the FD 22d, the amplification transistor 25d, and the row selection transistor 26d may be omitted as long as the charges leaking from the exposure region 11e can be discharged. However, by forming the discharge pixel 20d so as to have a circuit configuration similar to that of the exposure pixel 20e and the OB pixel 20b, manufacturing can be simplified and manufacturing cost can be reduced.

  In the present embodiment, the solid-state imaging device is a CMOS imaging device, but may be another XY address type imaging device or a charge transfer type imaging device such as a CCD imaging device.

DESCRIPTION OF SYMBOLS 10 CMOS image sensor 11b Optical black (OB) area | region 11d Charge discharge | emission area | region 11e Exposure area | region 20b Optical black (OB) pixel 20d Charge discharge | emission pixel 20e Exposure pixel 20b, 20d, 20e Photodiode (PD)
21b, 21d, 21e Floating diffusion (FD)
22b, 22d, 22e Transfer transistor 24b, 24d, 24e Reset transistor 25b, 25d, 25e Amplification transistor 26b, 26d, 26e Row selection transistor

Claims (11)

An exposure region in which first pixels that generate charges according to the amount of received light and output pixel signals based on the charges are two-dimensionally arranged;
A black region having the same structure as the first pixel, in which a light receiving surface is shielded and a second pixel that outputs a black pixel signal serving as a black reference of the pixel signal is disposed;
Discharge that is arranged between the exposure area and the black area, and that discharges the charge generated in the first pixel and leaking from the exposure area in a discharge period that exceeds a predetermined ratio in the exposure period to the exposure area A solid-state imaging device. The first pixel includes a first photoelectric conversion element that generates an electric charge according to an amount of received light,
A third pixel having a third capacitor for storing the charge leaking from the first pixel is disposed in the discharge region, and the charge stored in the third capacitor is discharged during the discharge period. The solid-state imaging device according to claim 1, wherein:   The third pixel is connected to the third capacitor and has a third reset transistor that discharges the electric charge accumulated in the third capacitor when the third pixel is ON, and the third reset transistor is discharged. The solid-state imaging device according to claim 2, wherein the charge is discharged during the discharge period by being kept ON during the period.   3. The solid-state imaging device according to claim 2, wherein the charge accumulated in the third capacitor is discharged during the discharge period by directly connecting the third capacitor to a reference potential source. The first pixel generates a first capacitor whose potential changes according to the electric charge transferred and accumulated from the first photoelectric conversion element, and the pixel signal based on the potential of the first capacitor. A first amplification transistor; and a first reset transistor that is connected to the first capacitor and discharges the electric charge accumulated in the first capacitor when turned on.
The second pixel has a second photoelectric conversion element that generates a charge corresponding to an amount of received light with a light-receiving surface shielded, and a potential that changes according to the charge transferred and accumulated from the second photoelectric conversion element. A second capacitor; a second amplifying transistor that generates the black pixel signal based on the potential of the second capacitor; and the second capacitor that is connected to the second capacitor and is ON, and is stored in the second capacitor. And a second reset transistor for discharging the charge,
The third pixel includes a third photoelectric conversion element that generates a charge corresponding to the amount of received light, and a third amplification transistor that generates a discharge signal based on the potential of the third capacitor. 5. The solid-state imaging device according to claim 2, wherein a potential of the capacitor changes according to the charge transferred and accumulated from the third photoelectric conversion device. 6.   The electric charge leaking from the first pixel is also accumulated in the third photoelectric conversion element, and the electric charge accumulated in the third photoelectric conversion element is transferred to the third capacitor during the discharge period. The solid-state imaging device according to claim 5.   The third pixel has a third transfer transistor that transfers the electric charge from the third photoelectric conversion element to the third capacitor when the third pixel is ON, and the third transfer transistor is turned on in the discharge period. The solid-state imaging device according to claim 6, wherein the electric charge is transferred during the discharge period by maintaining the electric charge in a solid state.   The charge accumulated in the third photoelectric conversion element is transferred to the third capacitor during the discharge period by directly connecting the third photoelectric conversion element to the third capacitor. The solid-state imaging device according to claim 6. The first pixel includes a first transfer transistor that transfers the charge from the first photoelectric conversion element to the first capacitor when the first pixel is ON;
9. The second pixel according to claim 5, wherein the second pixel includes a second transfer transistor that transfers the electric charge from the second photoelectric conversion element to the second capacitor when the second pixel is ON. The solid-state image sensor of any one of Claims.   10. The solid-state imaging device according to claim 5, wherein the third photoelectric conversion element is shielded from light.   11. The discharge period according to claim 1, wherein the discharge period is an entire period during operation of the solid-state imaging device, and the charge leaking from the exposure area is always discharged from the discharge area. The solid-state imaging device according to item 1.

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