JP2011142204A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent breakage or the like of a gate oxide film caused by antenna effect, and to suppress operation delay of a semiconductor device. <P>SOLUTION: The semiconductor device includes an input transistor A3 having an input transistor gate electrode A9 connected to an output transistor A1 in a preceding stage through a metal wiring A2a, and a dummy transistor A5 connected to an input transistor gate electrode A9 through a resistive element A4. The resistive element A4 is arranged in a subsequent stage of the input transistor A3, and is connected to the metal wiring A2a. The resistive element A4 and the dummy transistor A5 are connected through a metal wiring A2b. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device that prevents element destruction due to an antenna effect and a manufacturing method thereof.

  A process using plasma discharge is frequently used in the manufacturing process of a semiconductor device. For example, in a sputtering process, electric charges generated by plasma discharge collide with a conductive film material, and knocked out atoms are deposited on a semiconductor substrate to form a conductive film. In the dry etching process, a plasma discharge charge collides with a conductor film that is not protected by a photoresist and is etched to form a pattern. In addition, plasma discharge is frequently used in a resist peeling process, an element surface cleaning process, and the like.

  However, in the process using plasma discharge, the electric charge existing in the plasma enters from the conductor part exposed on the surface of the semiconductor device, and enters a circuit element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed in the semiconductor device. Charge. When this conductor is a gate wiring layer connected to the gate electrode of the MOSFET, current flows from the gate electrode to the substrate through the gate oxide film, and the gate oxide film is damaged.

  That is, the MOSFET is regarded as a MOS capacitor element in which the gate electrode is one electrode, the gate oxide film below the gate electrode is a dielectric film, and the semiconductor substrate therebelow is the other electrode. If the charge flowing from the gate electrode is greater than or equal to the charge storage amount allowable in the MOS capacitor, the insulation of the MOS capacitor is broken.

  As described above, a phenomenon in which charges in plasma are collected on a conductor portion is called an antenna effect. When the gate oxide film is electrically damaged by the antenna effect, the gate oxide film is destroyed, resulting in an increase in standby leakage and a decrease in yield due to a malfunction of the function. In addition, other influences may include initial Vt (threshold voltage) variation, on-current variation, a decrease in operating frequency due to deterioration of on-current during circuit operation, operation failure, and the like.

  Note that the amount of charge flowing into the gate electrode due to the antenna effect is proportional to the conductor area exposed to plasma. The electrical damage of the gate oxide film is determined by the amount of charge that can be accumulated per unit area of the gate oxide film. The breakdown of the gate oxide film due to the antenna effect can be achieved by increasing the area of the gate oxide film or providing a diffusion layer so that the amount of charge storage allowed in the gate oxide film is equal to or greater than the charge amount charged on the surface conductor. This can be prevented by releasing the electric charge.

  The reference for preventing the gate oxide film from being destroyed by the antenna effect is used as the antenna reference. In addition, [area of the outermost conductor (accumulating charge)] ÷ [area of gate oxide film (channel area) of the gate electrode connected to the outermost conductor (accumulating charge)] Ratio. The larger the antenna ratio, the more charge is charged on the surface conductor. In order to satisfy the antenna standard, the antenna ratio needs to be smaller than a predetermined value.

  In recent years, the wiring between logic circuits has become longer due to multi-functionalization of semiconductor devices and the antenna ratio tends to increase. On the other hand, the gate oxide film thickness tends to be reduced due to miniaturization of the process, and the risk of destruction of the gate oxide film is increasing.

  Therefore, Patent Document 1 describes a semiconductor device that can prevent the gate oxide film from being broken even if the antenna ratio is increased. FIG. 12 is a diagram illustrating a planar pattern of the semiconductor device described in Patent Document 1. FIG. 13 is an equivalent circuit diagram of the semiconductor device shown in FIG.

  As shown in FIG. 12, an N-type diffusion layer 30 serving as a resistor and a diode is provided between the metal wiring 20 connected to the previous internal circuit 200 and the gate electrode layer 23 of the internal circuit 150. . N-type diffusion layer 30 and metal interconnection 20 are connected through contact hole 32. N-type diffusion layer 30 and gate electrode layer 23 are connected by metal interconnection 33 through contact holes 29 and 31.

  By providing the N-type diffusion layer 30 constituting the resistor and the diode as described above, plasma charged particles stored in the metal wiring 20 by plasma etching at the time of patterning the metal wiring 20 are absorbed by the N-type diffusion layer 30. Specifically, as shown in FIG. 13, when the metal wiring 20 is patterned, a GND potential is applied from the substrate to the metal wiring 20 through the N-type diffusion layer 30 constituting the diode, so that the metal wiring 20 is stored. Plasma charged particles disappear.

  The diode composed of the N-type diffusion layer 30 is particularly effective when negative plasma charged particles are accumulated in the metal wiring 20. Further, when plasma charged particles are suddenly accumulated in the metal wiring 20 due to plasma etching at the time of patterning the metal wiring 20, the peak value of the surge voltage can be reduced by the resistance formed by the N-type diffusion layer 30.

  However, Patent Document 1 has a problem that a load capacitance due to a diode affects circuit characteristics. That is, a PN junction capacitance exists as a parasitic capacitance between the N-type diffusion layer 30 and the P-type substrate in FIG. 12, and is connected to the gate electrode layer 23 from the previous internal circuit 200 via the parasitic capacitance. When a signal is transmitted from the previous internal circuit 200, the charge is accumulated in the channel portion 28 of the internal circuit 150, and before the internal circuit 150 is turned on, the charge is accumulated in the parasitic capacitance formed by the N-type diffusion layer 30. There is a delay in the time for the circuit 150 to turn on.

Japanese Patent No. 3450909

  As described above, the semiconductor device described in Patent Document 1 has a problem that a delay occurs in the operation of the semiconductor device when measures are taken to prevent destruction of the gate oxide film due to the antenna effect.

  A semiconductor device according to one embodiment of the present invention includes an input transistor having a gate electrode connected to a previous-stage output transistor via a metal wiring, and connected to the gate electrode via a resistance element, thereby preventing destruction of the input transistor And an antenna countermeasure element.

  Thus, by providing the antenna countermeasure element via the resistance element, the antenna countermeasure element is obtained by the effect of the resistance voltage division between the resistance from the previous stage output transistor to the input transistor and the resistance from the input transistor to the antenna countermeasure element. It is possible to reduce the influence of the additional capacity due to. As a result, the time for which the input transistor is turned on can be shortened.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein an input transistor having a gate electrode connected to a preceding output transistor via a metal wiring is provided, and a dummy transistor or a diode is connected to the gate electrode via a resistance element. The resistance value of the resistance element is calculated by calculating a total charge amount accumulated by the antenna effect in the metal wiring from a gate parasitic capacitance value of the dummy transistor or a resistance value of the diode, and calculating the resistance from the total charge amount. A current flowing through the element is calculated to calculate a gate voltage of the input transistor, and a determination is made based on a determination as to whether or not the gate voltage is less than or equal to the breakdown voltage of the gate oxide film of the input transistor.

  With such a configuration, by providing the antenna countermeasure element via the resistance element, it is possible to shorten the time for which the input transistor is turned on. In addition, by optimizing the resistance value of the resistance element, the output delay time of the input transistor can be further shortened.

  According to the present invention, it is possible to prevent the gate oxide film from being destroyed due to the antenna effect, and to suppress the delay in the operation of the semiconductor device.

1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. FIG. 1B is an equivalent circuit diagram of the semiconductor device shown in FIG. 1A. 3 is a flowchart showing a part of the method for manufacturing the semiconductor device according to the first embodiment. 3 is a timing chart for explaining the operation of the semiconductor device according to the first embodiment; FIG. 6 is a plan view showing a configuration of a semiconductor device according to a second embodiment. FIG. 6 is a plan view illustrating a configuration of a semiconductor device according to a third embodiment. FIG. 5B is an equivalent circuit diagram of the semiconductor device shown in FIG. 5A. 10 is a flowchart showing a part of the manufacturing method of the semiconductor device according to the third embodiment. FIG. 6 is a plan view showing a configuration of a semiconductor device according to a fourth embodiment. FIG. 10 is a plan view showing a configuration of a semiconductor device according to a fifth embodiment. FIG. 10 is a plan view showing a configuration of a semiconductor device according to a sixth embodiment. FIG. 10 is a plan view showing a configuration of a semiconductor device according to a seventh embodiment. FIG. 10 is a plan view showing a configuration of a semiconductor device according to an eighth embodiment. 10 is a plan view showing a configuration of a semiconductor device described in Patent Document 1. FIG. FIG. 13 is an equivalent circuit diagram of the semiconductor device shown in FIG. 12. 13 is a timing chart for explaining the operation of the semiconductor device shown in FIG.

Embodiment 1 FIG.
A semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIGS. 1A and 1B. FIG. 1A is a plan view showing the configuration of the semiconductor device according to the present embodiment. 1B is an equivalent circuit diagram of the semiconductor device shown in FIG. 1A.

  As shown in FIG. 1A, the semiconductor device according to the present embodiment includes a front-stage output transistor A1, metal wirings A2a and A2b, an input transistor A3, a resistance element A4, and a dummy transistor A5. The input transistor A3 includes an input transistor gate electrode A9, an input P-type transistor B31, and an input N-type transistor B32. The dummy transistor A has a dummy transistor gate electrode A12.

  The pre-stage output transistor A1 is connected to the metal wiring A2a. The metal wiring A2a is connected to the input transistor gate electrode A9 of the input transistor A3 via the input transistor gate contact A8. The metal wiring A2a is connected to one end of the resistance element A4 through the resistance element contact A10 after being connected to the input transistor gate electrode A9. That is, on the output side of the front-stage output transistor A1, the metal wiring A2a and the input transistor gate electrode A9 are connected on the front-stage side, and the metal wiring A2a and the resistance element A4 are connected on the rear-stage side.

  That is, one end of the metal wiring A2a is connected to the previous output transistor A1, and the other end is connected to one end of the resistance element A4. An intermediate portion of the metal wiring A2a is connected to the input transistor gate electrode A9. The resistance element A4 is provided to suppress a delay in signal potential change of the input transistor gate electrode A9 caused by the parasitic capacitance of the dummy transistor A5.

  The other end of the resistance element A4 is connected to one end of the metal wiring A2b via the resistance element contact A10. The other end of the metal wiring A2b is connected to the dummy transistor gate electrode A12 of the dummy transistor A5 via the dummy transistor gate contact A11. The dummy transistor A5 is an antenna countermeasure element provided as a countermeasure against destruction of the gate oxide film due to the antenna effect. As an example of the circuit configuration, the source diffusion layer of the input P-type transistor B31 is connected to the power supply potential, and the drain diffusion layer of the input N-type transistor B32 is connected to the GND potential.

  As shown in FIG. 1B, the front output transistor A1 is connected to the front output transistor input terminal B1. The front-stage output transistor output contact B2 of the front-stage output transistor A1 is connected to the input transistor gate input contact B3 of the input transistor A3 including the input P-type transistor B31 and the input N-type transistor B32 via the parasitic resistance of the metal wiring A2a. . The input transistor gate input contact B3 is connected to one end of the resistance element A4. The other end of the resistor element A4 is connected to the dummy transistor gate input contact B5.

  An input transistor output terminal B33 is connected to the drains of the input P-type transistor B31 and the input N-type transistor B32. Although not shown here, parasitic capacitance exists at all contacts of an actual semiconductor device.

  By changing the input of the previous stage output transistor A1, the gate of the input transistor A3 is charged / discharged through the metal wiring A2a. As a result, the output potential of the input transistor A3 changes. At this time, charge and discharge of the dummy transistor A5 connected to the input transistor A3 are performed.

  In the semiconductor device according to the present embodiment, a method for calculating the resistance value of the resistance element A4 disposed between the input transistor A3 and the dummy transistor A5 in order to prevent the gate oxide film from being destroyed due to the accumulation of electric charges of plasma discharge. This will be described with reference to FIG. FIG. 2 is a diagram showing a part of the manufacturing method of the semiconductor device according to the present embodiment.

As shown in FIG. 2, first, the total charge amount Q of the charges in the plasma collected by the antenna effect of the wiring in the semiconductor device according to the present embodiment is calculated (step L1). Assuming that the gate oxide film breakdown voltage of the input transistor A3 is V and the gate capacitance of the dummy transistor A5 required for preventing gate breakdown is Cmin, the total charge amount Q is as shown in Expression (1).
Q = Cmin × V (1)

Next, the current I flowing through the resistance element A4 is calculated when the charge in the plasma is collected on the conductor due to the antenna effect (step L2). The current I is expressed by the equation (2) depending on the total charge amount Q and the etching time Te.
I = Q ÷ Te (2)
The etching time Te is equal to the time from the start to the end of the plasma discharge.

Next, the resistance value of the resistance element A4 provided at the subsequent stage of the input transistor A3 is set to R (step L3). Then, the gate voltage V1 of the input transistor A3 when the resistance value of the resistance element A4 is set to R is calculated (step L4). When the gate capacitance of the dummy transistor A5 is C0, the gate voltage V1 of the input transistor A3 is as shown in Equation (3), where t is the time from the start of plasma discharge.
V1 = I × t ÷ C0 + I × R (3)

Finally, it is determined whether or not the gate voltage of the input transistor A3 is equal to or lower than the gate oxide film breakdown voltage (step L5). The gate voltage V1 of the input transistor A3 when the time t reaches the etching time Te is expressed as in Expression (4).
V1 = I × Te ÷ C0 + I × R (4)
Whether or not the gate voltage V1 of the input transistor A3 represented by the equation (4) is equal to or lower than the gate oxide film withstand voltage V is determined by the equation (5) (step L5).
V1 ≦ V (5)

  When the gate voltage V1 of the input transistor A3 is higher than the gate oxide breakdown voltage V (No in step L5), the resistance value R of the resistance element A4 is lowered to make the gate voltage V1 of the input transistor A3 less than the gate oxide breakdown voltage V. Repeat steps L3 to L5.

  The gate voltage V1 of the input transistor A3 increases as the resistance value of the resistance element A4 increases. On the other hand, the output delay of the input transistor A3 becomes smaller as the resistance value of the resistance element A4 becomes larger. For this reason, it is preferable that the resistance value of the resistance element A4 has a maximum value in a range where the gate voltage V1 is equal to or lower than the gate oxide film breakdown voltage V so that the input transistor A3 is not destroyed.

  Therefore, when the gate voltage V1 of the input transistor A3 is less than or equal to the gate oxide breakdown voltage V (step L5 Yes), it is preferable to check whether the equation (5) is satisfied even with a resistance value larger than the resistance value.

  In this way, it is possible to determine the maximum resistance value R of the resistance element A4 in which the gate oxide film is not destroyed by the charge accumulation due to the plasma discharge. Thus, by setting the resistance value R of the resistance element A4 and providing the dummy transistor A5, it is possible to prevent the gate oxide film from being destroyed by the antenna effect.

  Here, the operation of the semiconductor device shown in FIG. 1A will be described with reference to FIG. FIG. 3 is a timing chart showing an operation when the front-stage output transistor A1 and the input transistor A3 are inverters in the semiconductor device according to the present embodiment.

  t0 is an initial state, and the potential of the previous-stage output transistor input terminal B1 is set to the Low level. When the potential of the previous-stage output transistor input terminal B1 becomes High level at t1, the previous-stage output transistor output contact B2 becomes Low level. At this time, the discharge of the input transistor gate input contact B3 starts via the metal wiring A2a. Further, the discharge of the dummy transistor gate input contact B5 starts via the resistance element A4.

  Since the resistance element A4 is provided between the input transistor gate input contact B3 and the dummy transistor gate input contact B5, input is performed before the potential of the dummy transistor gate input contact B5 becomes completely low due to the voltage dividing effect. The transistor gate input contact B3 is at a low level. At t2, the potential of the input transistor output terminal B33 of the input transistor A3 becomes High.

  As shown in FIG. 1A, by arranging the dummy transistor A5 from the input transistor A3 through the resistance element A4, the parasitic resistance of the metal wiring A2a from the previous stage output transistor A1 to the input transistor gate electrode A9 of the input transistor A3, and the input The input transistor A3 is turned on before the charging of the dummy transistor gate electrode A12 of the dummy transistor A5 is completed by the voltage division of the resistance element A4 from the transistor A3 to the dummy transistor A5.

  Here, as a comparative example of the present embodiment, an operation in the case where the pre-stage internal circuit 200 and the internal circuit 150 are inverters in the semiconductor device described in Patent Document 1 will be described with reference to FIG. FIG. 14 is a timing chart for explaining the operation of the semiconductor device described in Patent Document 1.

  As shown in FIG. 14, when the output from the previous internal circuit 200 becomes High at t1, the metal wiring 20 connected to the output becomes Low level. At t1, the N-type diffusion layer 30 and the gate electrode layer 23 of the input transistor start to discharge. Since there is no resistance element between the gate electrode layer 23 and the N-type diffusion layer 30, the gate electrode layer 23 and the N-type diffusion layer 30 are simultaneously discharged. For this reason, the potential of the metal wiring 22 connected to the source / drain region 27 of the input transistor becomes High when the input transistor is turned ON, because the potential of the gate electrode layer 23 of the input transistor is lower than Vt of the transistor. Time t3 is reached.

  3 and 16, in the present embodiment, the time (t1 to t2) when the output transistor A1 of the previous stage is turned ON and the potential of the input transistor output terminal B33 becomes High is from the source / source of the comparative example. It can be said that the potential of the metal wiring 22 in the drain region 27 is not more than one-tenth of the time (t1 to t3) when the potential is high.

  Thus, in the semiconductor device according to the present embodiment, the input transistor A3, the resistance element A4, and the dummy transistor A5 are arranged in this order in the subsequent stage of the previous output transistor A1. For this reason, the input transistor A3 is charged / discharged faster than the dummy transistor A5 is charged / discharged by the resistance voltage division. As a result, the time for which the input transistor A3 is turned on is shortened. As a result, the influence of the load capacitance of the dummy transistor A5 is eliminated, the rise of the output waveform of the input transistor A3 can be accelerated, and high-speed operation can be realized.

Embodiment 2. FIG.
A semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 4 is a plan view showing the configuration of the semiconductor device according to the present embodiment. 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  In the present embodiment, one end of the metal wiring A2a is connected to the previous output transistor A1, and the other end of the metal wiring A2a is connected to the input transistor gate electrode A9 via the input transistor gate input contact E81. The input transistor gate electrode A9 is provided so as to extend in common on the channel regions of the input P-type transistor B31 and the input N-type transistor B32.

  The portion of the input transistor gate electrode A9 that has passed through the channel region of the input N-type transistor B32 is connected to one end of the metal wiring A2c through the input transistor gate lead-out contact E82. The other end of the metal wiring A2c is connected to one end of the resistance element A4. Similarly to the first embodiment, the dummy transistor A5 is connected to the subsequent stage of the resistance element A4 via the metal wiring A2b.

  In the semiconductor device according to the present embodiment, as in the first embodiment, the gate oxide film can be prevented from being destroyed due to the accumulation of the electric charge of the plasma discharge, and the rising of the input transistor A3 can be accelerated, and the high speed operation can be achieved. It can be realized.

  In the present embodiment, the parasitic resistance of the input transistor gate electrode A9 and the resistance element A4 are connected in series. Thereby, the input transistor gate electrode A9 can also serve as a part of the resistance necessary for the resistance element A4. In general, since the gate electrode has a higher resistance than the metal wiring, the resistance of the resistance element A4 can be reduced, and the expansion of the layout area can be suppressed.

Embodiment 3 FIG.
A semiconductor device according to Embodiment 3 of the present invention will be described with reference to FIGS. 5A and 5B. FIG. 5A is a plan view showing the configuration of the semiconductor device according to the present embodiment. FIG. 5B is an equivalent circuit diagram of the semiconductor device shown in FIG. 5A.

  The semiconductor device according to the present embodiment has a configuration in which the dummy transistor A5 shown in the first embodiment is replaced with a diode F5. The diode F5 has a diode diffusion layer F12. The diode F5 is an antenna countermeasure element provided as a countermeasure against destruction of the gate oxide film due to the antenna effect.

  Similar to the first embodiment, the metal wiring A2a is connected to the output of the previous stage output transistor A1. The metal wiring A2a is connected to the input transistor gate electrode A9 of the input transistor A3. In the subsequent stage, the metal wiring A2a is connected to one end of the resistance element A4 via the resistance element contact A10.

  The other end of the resistive element A4 is connected to the metal wiring A2b via the resistive element contact A10. The metal wiring A2b is connected to the diode diffusion layer F12 of the diode F5 through the diode contact F11.

  By providing the resistance element A4 between the input transistor A3 and the diode F5, the influence on the delay of the output time of the input transistor A3 due to the diffusion layer junction capacitance of the diode F5 can be suppressed as in the first embodiment. Is possible.

  Here, in the semiconductor device according to the present embodiment, calculation of the resistance value of the resistance element A4 disposed between the input transistor A3 and the diode F5 in order to prevent the gate oxide film from being destroyed due to the accumulation of plasma discharge charges. The method will be described with reference to FIG. FIG. 6 is a diagram showing a part of the manufacturing method of the semiconductor device according to the present embodiment.

As shown in FIG. 6, first, the current I flowing through the resistance element A4 is calculated during plasma etching (step M1). Assuming that the gate oxide breakdown voltage of the input transistor A3 is V and the minimum resistance value of the diode F5 required to prevent the gate from being destroyed by the antenna effect is Rdmin, the current I is as shown in equation (6).
I = V ÷ Rdmin (6)

Next, the resistance value R of the resistance element A4 provided between the input transistor A3 and the diode F5 is set (step M2). Then, the gate voltage of the input transistor when the resistance value of the resistance element A4 is set to R is calculated (step M3). When the resistance value of the actually arranged diode F5 is Rd, the gate voltage V1 of the input transistor A3 is as shown in Expression (7).
V1 = I × (R + Rd) (7)

Finally, it is determined by equation (8) whether the gate voltage V1 of the input transistor A3 is equal to or lower than the gate oxide film withstand voltage V (step M4).
V1 ≦ V (8)

  When the gate voltage V1 of the input transistor A3 is larger than the gate oxide film withstand voltage V (No in step M4), the resistance value R of the resistance element A4 is lowered so that the gate voltage V1 of the input transistor A3 becomes less than the gate oxide film withstand voltage V. Repeat steps L2 to L5. As described above, the gate voltage V1 of the input transistor A3 increases as the resistance value of the resistance element A4 increases. On the other hand, the output delay of the input transistor A3 becomes smaller as the resistance value of the resistance element A4 becomes larger.

  By repeating the above steps, it is possible to determine the maximum resistance value R of the resistance element A4 in which the gate oxide film is not destroyed by the accumulation of electric charges due to plasma discharge. Thus, by setting the resistance value R of the resistance element A4 and providing the diode F5, it is possible to prevent the gate oxide film from being destroyed due to the antenna effect.

  In general, there is a case where a countermeasure against gate oxide film destruction due to an antenna effect is implemented by providing a diode F5 and letting accumulated charges escape to the substrate. The present embodiment can also be applied to a case where the diode F5 is provided and antenna countermeasures are taken. Also in the present embodiment, as in the first embodiment, the influence of the diffusion layer junction capacitance of the diode F5 can be eliminated, the rise of the output waveform of the input transistor A3 can be accelerated, and high-speed operation can be realized. It becomes.

Embodiment 4 FIG.
The configuration of the semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a plan view showing the configuration of the semiconductor device according to the present embodiment. In the present embodiment, a diode F5 is provided as an antenna countermeasure element as in the third embodiment.

  In the present embodiment, one end of the metal wiring A2a is connected to the previous output transistor A1, and the other end of the metal wiring A2a is connected to the input transistor gate electrode A9 via the input transistor gate input contact E81. The input transistor gate electrode A9 is provided so as to extend in common on the channel regions of the input P-type transistor B31 and the input N-type transistor B32.

  The portion of the input transistor gate electrode A9 that has passed through the channel region of the input N-type transistor B32 is connected to one end of the metal wiring A2c through the input transistor gate lead-out contact E82. The other end of the metal wiring A2c is connected to one end of the resistance element A4. Similarly to the third embodiment, a diode F5 is connected to the subsequent stage of the resistance element A4 via the metal wiring A2b.

  As a result, as in the third embodiment, the gate oxide film can be prevented from being destroyed due to the antenna effect, and the rising of the input transistor A3 can be accelerated, thereby realizing high-speed operation. Similarly to the second embodiment, the input transistor gate electrode A9 can also serve as a part of the resistance necessary for the resistance element A4, the resistance of the resistance element A4 can be reduced, and the expansion of the layout area is suppressed. It becomes possible to do.

Embodiment 5 FIG.
The configuration of the semiconductor device according to the fifth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a plan view showing the configuration of the semiconductor device according to the present embodiment. In the present embodiment, a lead-out wiring N8 is provided in the middle of the metal wiring A2a that connects the previous stage output transistor A1 and the input transistor A3 of the first embodiment. The lead-out wiring N8 is connected to one end of the resistance element A4 via the resistance element contact A10.

  The other end of the resistive element A4 is connected to the metal wiring A2b via the resistive element contact A10. The metal wiring A2b is connected to the dummy transistor gate electrode A12 of the dummy transistor A5 through the dummy transistor gate contact A11. That is, the dummy transistor A5 is connected to the lead-out wiring N8 via the resistance element A4.

  Also in the present embodiment, the same effect as in the first embodiment can be obtained. Further, in this embodiment, since the resistance element, the lead wiring, and the dummy transistor A5 can be freely arranged in the empty area, it is effective for suppressing the layout area expansion.

Embodiment 6 FIG.
The configuration of the semiconductor device according to the sixth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a plan view showing the configuration of the semiconductor device according to the present embodiment. In the present embodiment, a lead-out wiring N8 is provided as in the fifth embodiment. The lead wiring N8 is connected to the dummy transistor A5 via the resistance element A4. Also in the present embodiment, the same effect as in the third embodiment can be obtained. Further, in the present embodiment, since the resistance element, the lead wiring, and the diode F5 can be freely arranged in the empty area, it is effective for suppressing the layout area expansion.

Embodiment 7 FIG.
The configuration of the semiconductor device according to the seventh embodiment of the present invention will be described with reference to FIG. FIG. 10 is a plan view showing the configuration of the semiconductor device according to the present embodiment. As shown in FIG. 10, the front-stage output transistor A1 has a front-stage output transistor drain diffusion layer A6. The lead-out wiring N8 is branched from one end of the metal wiring A2. The pre-stage output transistor drain diffusion layer A6 is connected to the lead-out wiring N8 via the drain contact A7.

  The lead-out wiring N8 is connected to the resistance element A4 via the resistance element contact A10. The dummy transistor A5 is connected to the lead-out wiring N8 via the resistance element A4. Also in the present embodiment, the same effect as in the first embodiment can be obtained. Further, in this embodiment, since the resistance element, the lead wiring, and the dummy transistor A5 can be freely arranged in the empty area, it is effective for suppressing the layout area expansion.

Embodiment 8 FIG.
The configuration of the semiconductor device according to the eighth embodiment of the present invention will be described with reference to FIG. FIG. 11 is a plan view showing the configuration of the semiconductor device according to the present embodiment. In the present embodiment, a lead-out wiring N8 is provided as in the seventh embodiment. The lead wiring N8 is connected to the diode F5 through the resistance element A4. Also in the present embodiment, the same effect as in the third embodiment can be obtained. Further, in the present embodiment, since the resistance element, the lead wiring, and the diode F5 can be freely arranged in the empty area, it is effective for suppressing the layout area expansion.

  As described above, according to the present invention, it is possible to reduce the signal delay from the previous stage output transistor A1 to the input transistor A3 due to the influence of the load capacitance of the dummy transistor A5 or the diode F5.

  For example, when the resistance from the previous stage output transistor output contact B2 to the input transistor gate input contact B3 is 20Ω, the resistance value (resistive element A4) from the input transistor gate input contact B3 to the dummy transistor A5 is set to 2 KΩ. The effect of the load capacitance of the dummy transistor A5 can be reduced to 1/100 by the effect of the voltage division.

  Further, the dummy transistor A5 and the diode F5 can be freely arranged in an empty area in the chip apart from the previous stage output transistor A1 and the input transistor A3. For this reason, it is possible to prevent the chip size from being increased by providing the dummy transistor A5 and the diode F5.

  Furthermore, by calculating the resistance value of the resistance element by the manufacturing method according to the present invention, it is possible to quantitatively set the resistance value of the resistance element so that the gate oxide film is not destroyed by the antenna effect.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

A1 Previous stage output transistor A2a, A2b, A2c Metal wiring A3 Input transistor A4 Resistance element A5 Dummy transistor A6 Previous stage output transistor drain diffusion layer A7 Drain contact A8 Input transistor gate contact A9 Input transistor gate electrode A10 Resistance element contact A11 Dummy transistor gate contact A12 Dummy transistor gate electrode B1 Previous stage output transistor input terminal B2 Previous stage output transistor output contact B3 Input transistor gate input contact B31 Input P type transistor B32 Input N type transistor B33 Input transistor output terminal B5 Dummy transistor gate input contact E81 Input transistor gate input contact E82 Input transistor gate lead-out contact F Diode F11 diode contact F12 diode diffusion layer I4 diffusion layer resistance element J7 parasitic diode N8 drawing wire

Claims (8)

An input transistor having a gate electrode connected to the previous stage output transistor via a metal wiring;
An anti-antenna element connected to the gate electrode via a resistance element and preventing destruction of the input transistor;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the resistance element is provided at a subsequent stage of the input transistor and is connected to the metal wiring.   The semiconductor device according to claim 1, wherein the resistance element is connected to the metal wiring via the gate electrode. A first lead wiring provided in an intermediate portion of the metal wiring;
The semiconductor device according to claim 1, wherein the resistance element is connected to the first lead wiring. A second lead wire drawn from a drain contact connected to the metal wire of the pre-stage output transistor;
The semiconductor device according to claim 1, wherein the resistance element is connected to the second lead wiring.   6. The semiconductor device according to claim 1, wherein the antenna countermeasure element is a dummy transistor or a diode.   The resistance value of the resistance element is calculated from the gate parasitic capacitance value of the dummy transistor or the resistance value of the diode, and the total charge amount accumulated by the antenna effect in the metal wiring is calculated and flows through the resistance element from the total charge amount. The semiconductor device according to claim 6, wherein a current is calculated to calculate a gate voltage of the input transistor, and the gate voltage is determined based on a determination whether or not the gate voltage is equal to or lower than a breakdown voltage of a gate oxide film of the input transistor. An input transistor having a gate electrode connected to the previous stage output transistor via a metal wiring is provided,
A dummy transistor or a diode is connected to the gate electrode via a resistance element;
The resistance value of the resistance element is
From the gate parasitic capacitance value of the dummy transistor or the resistance value of the diode, calculate the total amount of charge accumulated by the antenna effect in the metal wiring,
Calculate the current flowing through the resistance element from the total charge amount to calculate the gate voltage of the input transistor,
A method of manufacturing a semiconductor device, which is determined based on a determination as to whether or not the gate voltage is equal to or lower than a breakdown voltage of a gate oxide film of the input transistor.

Images