JP2011142136A - Field effect transistor and logical circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor (FET) improved in functionality, and a logical circuit using the transistor. <P>SOLUTION: The FET 100 includes a channel region 16 changeable in polarity, and a ferroelectric region 26 provided near the channel region 16 and changing the polarity of the channel region 16 based on the own polarization state. The FET 100 further includes a first control means 24 controlling the carrier density of the channel region 16, and a second control means 12 changing the polarization state of the ferroelectric region 26. The polarization state of the ferroelectric region 26 is changed by a control signal V<SB>c</SB>applied to the first control means 24, and as a result, the polarity of the channel region 16 can be changed. The polarity of the FET 100 can thereby be optionally changed, and the once changed polarity of the FET 100 can be maintained even after power-off. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a bipolar field effect transistor and a logic circuit using the transistor.

  A semiconductor logic circuit is configured by a combination of a plurality of circuit elements including a field effect transistor (FET). In recent years, there has been a limit to the miniaturization of semiconductor logic circuits due to problems such as limitations of processing technology and circuit heat generation. In view of this, attention has been paid to an approach in which elements constituting a circuit have a plurality of functions and the same function is realized with a small number of components.

  For example, an ambipolar field effect transistor that has both p-type and n-type polarities by configuring a channel region with a predetermined organic semiconductor material is known (see, for example, Patent Document 1).

JP 2006-303453 A

  In the bipolar field effect transistor, the polarity is determined depending on whether or not to perform boring (applying a predetermined voltage between the source and the gate) during manufacturing. The channel polarity once determined is always fixed and does not change during operation. That is, the bipolar field effect transistor described above actually operates only in either the p-type or n-type polarity, and it cannot be said that the both polarities are fully utilized.

  The present invention has been made in view of the above problems, and an object thereof is to provide a field effect transistor with improved functionality and a logic circuit using the transistor.

  This field effect transistor has a channel region whose polarity can be changed and a ferroelectric region which is provided near the channel region and changes the polarity of the channel region based on its polarization state. The field effect transistor further includes first control means for controlling the carrier concentration in the channel region and second control means for changing the polarization state of the ferroelectric region.

  This logic circuit has the above-described field effect transistor, an input terminal for inputting a signal to the first control means, and a control terminal for inputting a signal to the second control means. Further, a logic circuit in which a plurality of this logic circuit is combined has a plurality of the above logic circuits, and an address is assigned to at least one of the plurality of logic circuits. An arbitrary logic circuit is selected from the plurality of logic circuits according to the address, and a write voltage for changing the polarization state of the ferroelectric region in the field effect transistor is applied to the control terminal of the selected logic circuit.

  According to the present field effect transistor, the polarity can be arbitrarily changed, and the once changed polarity can be maintained even after the power is turned off. Further, according to the present logic circuit, the function can be arbitrarily changed and the once changed function can be maintained even after the power is turned off.

FIG. 1A is a diagram showing a configuration of an FET according to a comparative example, and FIG. 1B is a diagram showing its symbol. FIGS. 2A to 2B are diagrams illustrating the operation principle of the FET according to the comparative example. FIG. 3A is an example of a logic gate using bipolar FETs, and FIGS. 3B to 3C are truth tables showing the operation of this logic gate. FIG. 4A is a diagram illustrating the configuration of the FET according to the first embodiment, and FIG. 4B is a diagram illustrating the symbol thereof. FIGS. 5A to 5D are views (No. 1) illustrating the method for manufacturing the FET according to the first embodiment. 6A to 6D are diagrams (part 2) illustrating the method for manufacturing the FET according to the first embodiment. 7A to 7D are diagrams illustrating the operation principle of the FET according to the first embodiment. FIG. 8 is a graph illustrating the transfer characteristics of the FET according to the first embodiment. FIG. 9 is a diagram illustrating a configuration of an FET according to a modification of the first embodiment. FIG. 10A is a diagram illustrating the configuration of the logic gate according to the second embodiment, and FIG. 10B is a diagram illustrating the symbol thereof. FIG. 11 is a graph illustrating transfer characteristics of the logic gate according to the second embodiment. FIG. 12 is a timing chart illustrating the operation of the logic gate according to the second embodiment. FIG. 13 is a diagram illustrating a configuration of a logic gate according to a modification of the second embodiment. FIG. 14A is a diagram illustrating a configuration of a logic gate according to the third embodiment, and FIG. 14B is a diagram illustrating symbols thereof. FIG. 15 is a diagram showing a configuration of a binary decision graph logic circuit according to a conventional example. FIGS. 16A to 16D are diagrams illustrating a configuration of a logic circuit according to the fourth embodiment. FIG. 17 is a diagram illustrating the configuration of the logic circuit according to the fifth embodiment. FIG. 18 is a flowchart illustrating the operation of the logic circuit according to the fifth embodiment. FIG. 19 is a diagram illustrating a configuration of a logic circuit according to a modification of the fifth embodiment.

First, a field effect transistor according to a comparative example and a logic circuit using the same will be described.
(Comparative example)

  FIG. 1A is a schematic cross-sectional view of a field effect transistor (hereinafter, FET 80) according to a comparative example. A back gate electrode 12 is formed on a high-resistance silicon substrate 10. The silicon substrate 10 and the back gate electrode 12 are covered with a first insulating layer 14. On the first insulating layer 14, a channel region 16 is formed, and a source electrode 18 and a drain electrode 20 are formed across the channel region. The channel region 16, the source electrode 18 and the drain electrode 20 are covered with a second insulating layer 22. A top gate electrode 24 is formed on the second insulating layer 22.

  FIG. 1B is a diagram showing a symbol of the FET 80 in FIG. The FET 80 has two gate terminals (a first gate and a second gate) in addition to a source terminal and a drain terminal which are input / output terminals. The first gate located on the convex side of the transistor symbol corresponds to the top gate electrode 24, and the second gate located on the concave side of the transistor symbol corresponds to the back gate electrode 12. The first gate is a terminal for controlling the FET to be turned on or off by controlling the carrier concentration of the channel region 16 as in the case of a normal FET. The second gate is a terminal for changing the polarity of the FET to either n-type or p-type by changing the type of carriers induced in the channel region 16 as will be described below.

2A and 2B are diagrams for explaining the operation principle of the FET 80. FIG. A part of the substrate 10 and the second insulating layer 22 is omitted, and the channel region 16 and the back gate electrode 12 are illustrated in white. The channel region 16 is made of an organic semiconductor material having bipolar properties (for example, graphite or the like). The voltage V _c applied to the back gate electrode 12, the type of carrier induced in the channel region 16 is changed.

  In FIG. 2A, a positive voltage is applied to the back gate electrode 12, and negative carriers (electrons) are induced in the channel region 16. As a result, the polarity of the channel region 16 becomes n-type, and the FET 80 functions as an n-type transistor. In FIG. 2B, a negative voltage is applied to the back gate electrode 12, and positive carriers (holes) are induced in the channel region 16. As a result, the polarity of the channel region 16 becomes p-type, and the FET 80 functions as a p-type transistor. Thus, the polarity of the FET 80 can be changed by applying a predetermined voltage to the back gate electrode 12, and the FET 80 can be operated as an arbitrary FET of the n-type FET and the p-type FET.

  FIG. 3A is an example of a basic logic gate using a bipolar FET 80, and FIGS. 3B to 3C are truth tables showing the operation of this logic gate. As shown in FIG. 3A, in the logic gate 90, FETs 80A to 80C are connected in series between the power supply line Vdd and the ground line Vss. An FET 80D is connected in parallel with the FET 80C between the intermediate node of the FETs 80B and 80C and the ground line Vss.

The first input signal V _in1 to the logic gate 90 is input to the first gates of the FETs 80A and 80D, and the second input signal V _in2 is input to the first gates of the FETs 80B and 80C. The output signal V _out of the logic gate 90 is output from the intermediate node of the FET 80B and the FET 80C. The first control signal V _c1 to the logic gate 90 is input to the second gates of the FETs 80C and 80D, and the second control signal V _c2 to the logic gate 90 is input to the second gates of the FETs 80A and FET 80B. Yes.

FIG. 3B is a truth table when the first control signal V _c1 is at the H level and the second control signal V _c2 is at the L level. At this time, the FETs 80A and 80B operate as p-type, and the FETs 80C and 80D operate as n-type. If both the first input signal V _in1 and the second input signal V _in2 are at the L level, the output signal V _out is at the H level. In other cases, the output signal V _out is at the L level. That is, the logic gate 90 functions as a NOR type.

FIG. 3C is a truth table when the first control signal V _c1 is at the L level and the second control signal V _c2 is at the H level. At this time, the FETs 80A and 80B operate as n-type, and the FETs 80C and 80D operate as p-type. If both the first input signal V _in1 and the second input signal V _in2 are at the H level, the output signal V _out is at the H level. In other cases, the output signal V _out is at the L level. That is, the logic gate 90 functions as an AND type. In this way, by controlling the first control signal V _c1 and the second control signal V _c2 , the polarity of the FETs 80A to 80D can be changed, and the function of the logic gate 90 can be switched between the NOR type and the AND type.

  Since the polarity of the FET 80 according to the comparative example can be changed during operation, a plurality of functions can be realized by the same circuit element as in the example of the logic gate 90 described above. However, in order to maintain the polarity of the FET 80, a voltage must be continuously applied to the back gate electrode 12 as the second gate, and the polarity of the FET and the function of the logic gate are reset when the power is turned off. was there.

  In the following embodiments, a description will be given of a bipolar FET that can maintain a once-changed polarity even after power is turned off, and a logic circuit using such an FET.

  FIG. 4A is a diagram illustrating a configuration of a field effect transistor (hereinafter, FET 100) according to the first embodiment. Constituent elements common to the comparative example (FIG. 1A) are denoted by the same reference numerals, and detailed description thereof is omitted. In the FET 100, a ferroelectric region 26 is provided in a region between the back gate electrode 12 and the channel region 16 instead of the first insulating layer 14. Other configurations are the same as those of the FET 80 according to the comparative example.

  FIG. 4B is a diagram showing a symbol of the FET 100 in FIG. The FET 100 has a first gate corresponding to the top gate electrode 24 and a second gate corresponding to the back gate electrode 12, similarly to the FET 80 according to the comparative example. The symbol of the FET 100 is hatched in the channel portion to indicate that the ferroelectric region 26 is provided.

  FIG. 5A to FIG. 6D are diagrams illustrating a method for manufacturing the FET 100 according to the first embodiment. First, as shown in FIG. 5A, a back gate electrode is formed on the substrate 10, and a ferroelectric region 26 is formed thereon. For example, high-resistance silicon is used for the substrate 10 and the resistivity is set to 10 kΩ · cm, for example. For example, polysilicon is used for the back gate electrode 12, and the film thickness is set to 50 nm, for example. For the ferroelectric region 26, for example, lead zirconate titanate (PZT) is used, and its film thickness is, for example, 50 nm. The back gate electrode 12 and the ferroelectric region 26 are formed by, for example, a sputtering film forming method.

Next, as shown in FIG. 5 (b), the back gate electrode 12 and the ferroelectric region 26, which are formed at portions other than the portion that will later become the channel region, are removed, and the first insulating layer 14 is formed on the entire surface. To do. The back gate electrode 12 and the ferroelectric region 26 are removed by, for example, a photolithography process and an argon ion etching method. For the first insulating layer 14, for example, an insulating film containing silicon oxide (SiO ₂ ) is used, and the film is formed by, for example, spin coating.

  Next, as shown in FIG. 5C, the whole is flattened to expose the surface of the ferroelectric region 26. The planarization is performed by, for example, a CMP (Chemical Mechanical Polishing) method.

  Next, as shown in FIG. 5D, the channel region 16 is formed on the surface on the side where the ferroelectric region 26 is exposed. For the channel region 16, for example, a single layer or a multilayer (preferably at most about two layers) graphite thin film is used. In this case, a method may be used in which a graphite thin film is formed on another silicon substrate by a CVD (Chemical Vapor Deposition) method, and then peeled off and pasted on the ferroelectric region 26. After attaching the graphite thin film, the graphite thin film is selectively removed by, for example, a photolithography process and an oxygen ashing method to form the channel region 16.

  Next, as shown in FIG. 6A, the source electrode 18 and the drain electrode 20 are formed at both ends of the channel region 16. For example, titanium (Ti) and gold (Au) are used for the source electrode 18 and the drain electrode 20, respectively, and are formed with a thickness of, for example, 10 nm / 50 nm from the side close to the substrate 10. The source electrode 18 and the drain electrode 20 can be formed at desired positions by forming an electrode pattern using, for example, a photoresist and performing lift-off after depositing the electrode material.

Next, as shown in FIG. 6B, a second insulating layer 22 that becomes a gate insulating film is formed on the channel region 16, the source electrode 18, and the drain electrode 20. For example, hafnium oxide (HfO ₂ ) is used for the second insulating layer 22, and the film thickness thereof is, for example, 50 nm. The second insulating layer 22 is formed by, for example, an ALD (Atomic layer Deposition) method.

  Finally, a top gate electrode 24 is formed on the second insulating layer 22 as shown in FIG. The top gate electrode 24 is made of, for example, titanium (Ti) and gold (Au), and is formed with a film thickness of, for example, 10 nm / 50 nm from the side close to the substrate 10. Similar to the source electrode 18 and the drain electrode 20, the top gate electrode 24 can be formed at a desired position by forming an electrode pattern using, for example, a photoresist and performing lift-off after vapor deposition of the electrode material. Thereafter, the process proceeds to a wiring formation process in the same manner as a normal FET manufacturing method.

7A to 7D are diagrams for explaining the operation principle of the FET 100. FIG. A part of the substrate 10 and the second insulating layer 22 is omitted, and the channel region 16 and the back gate electrode 12 are illustrated in white. Similar to the comparative example, the channel region 16 is formed of an organic semiconductor material having both polarities. In Comparative Example (FIG. 2 (a) ~ (b) ), the voltage V _c applied to the back gate electrode 12 was configured to direct the channel region 16 carriers are induced. On the other hand, in the FET 100 according to the first embodiment, the polarization charge generated in the ferroelectric region 26 by the voltage application from the back gate electrode 12 induces positive or negative carriers in the channel region 16.

In FIG. 7A, a positive voltage V _c is applied to the back gate electrode 12. As a result, in the ferroelectric region 26, polarization occurs in which the substrate side is negative and the channel side is positive. Negative carriers (electrons) are induced in the channel region 16 due to positive polarization charges generated on the channel side of the ferroelectric region 26. As a result, the polarity of the channel region 16 becomes n-type, and the FET 100 functions as an n-type transistor. As shown in FIG. 7B, the polarization state of the ferroelectric region 26 is maintained even after the voltage application to the back gate electrode 12 is completed. Thereby, even after power is turned off, the polarity of the channel region 16 remains n-type, and the FET 100 continues to function as an n-type transistor.

In FIG. 7C, a negative voltage V _c is applied to the back gate electrode 12. As a result, in the ferroelectric region 26, polarization is generated in which the substrate side is positive and the channel side is negative. Positive carriers (holes) are induced in the channel region 16 due to negative polarization charges generated on the channel side of the ferroelectric region 26. Thereby, the polarity of the channel region 16 becomes p-type, and the FET 100 functions as a p-type transistor. As shown in FIG. 7D, the polarization state of the ferroelectric region 26 is maintained even after the voltage application to the back gate electrode 12 is completed. Thereby, even after power is turned off, the polarity of the channel region 16 remains p-type, and the FET 100 continues to function as a p-type transistor.

FIG. 8 is a graph showing the transfer characteristics of the FET 100. The horizontal axis represents the gate voltage, and the vertical axis represents the logarithmic value of the drain current. As shown in the figure, in the region where the gate voltage V _g is greater than V ₀ , the amount of current I _d increases as the voltage V _g increases. In the region where the gate voltage V _g is smaller than V ₀ , the amount of current I _d increases as the voltage V _g decreases. A characteristic in which the slope of the change in the drain current is reversed at a predetermined gate voltage V ₀ is called “bipolar”.

As described above, the ferroelectric region 26 changes the polarity of the channel region 16 based on its polarization state. In order to change (invert) the polarization state of the ferroelectric region 26, a voltage V _c having an absolute value larger than the coercive electric field of the ferroelectric region 26 is applied from the back gate electrode 12 to the ferroelectric region 26. . A region N in the graph indicates a region where the FET 100 operates as an n-type transistor, and a region P in the graph indicates a region where the FET 100 operates as a p-type transistor. That is, the back gate electrode 12 functions as a means (second control means) for changing the polarization state of the ferroelectric region 26 and the polarity of the FET 100.

Top gate electrode 24, the voltage signal V _in applied thereto controls the magnitude of current flowing through the channel region 16 within the range of the region N and the region P, and controls to turn on or off the FET 100. That is, the top gate electrode 24 functions as a means (first control means) for controlling the concentration of carriers induced in the channel region 16 and controlling the on / off of the FET 100.

  As described above, the FET 100 according to the first embodiment includes the channel region 16 whose polarity can be changed and the ferroelectric region 26 which is provided in the vicinity of the channel region 16 and changes the polarity of the channel region 16 based on its polarization state. And have. The FET 100 further includes a top gate electrode 24 as first control means for controlling the carrier concentration in the channel region 16 and a back gate electrode 12 as second control means for changing the polarization state of the ferroelectric region 26.

According to this configuration, a control signal V _c applied to the back gate electrode 12, and change the polarization state of the ferroelectric region 26, it is possible to change the polarity of the channel region 16 as a result. Thereby, the FET 100 can be operated as an arbitrary FET of p-type or n-type, and a plurality of functions can be realized by the same circuit element.

Further, the polarization state of the ferroelectric region 26 to be maintained without continued application of a control voltage V _c to the back gate electrode 12, it can be maintained even after the power supply dropping polarity FET100 changing once. In other words, the polarity of the FET 100 can be stored in a nonvolatile manner by the ferroelectric region 26. By using the FET 100 having such characteristics, it is possible to configure a logic circuit that can easily change and maintain functions. As a result, it is possible to realize, for example, higher functionality, lower power consumption, higher speed, smaller size, and lower cost of the integrated circuit.

  In the first embodiment, the top gate electrode 24 is used as the first control unit, and the back gate electrode 12 is used as the second control unit. However, the back gate electrode 12 is used as the first control unit, and the top gate electrode 24 is used as the second control unit. May be used. In this case, the ferroelectric region 26 is formed between the channel region 16 and the top gate electrode 24, and their positional relationship is opposite to that in the first embodiment.

  More generally, when the first control means and the second control means are realized by two upper and lower electrodes, the first gate electrode as the first control means is provided on the side opposite to the ferroelectric region 26 with respect to the channel region 16. Is provided. Then, a second gate electrode serving as second control means is provided on the opposite side of the ferroelectric region 26 from the channel region 16. Further, the first control means and the second control means may have other forms as long as they have the function described in the above paragraph 0037.

  In the first embodiment, the channel region 16 is formed of, for example, a graphite thin film. However, other materials may be used as long as the polarity can be changed as described above. For example, carbon nanotubes may be used instead of the graphite thin film. In the first embodiment, the ferroelectric region 26 is provided between the back gate electrode 12 and the channel region 16. However, the ferroelectric region 26 may be provided in the vicinity of the channel region 16. In this case, “near” means a positional relationship (distance) to the extent that the polarity of the channel region 16 can be changed by the polarization charge of the ferroelectric region 26.

  In the first embodiment, a space is provided between the top gate electrode 24 and the source electrode 18 as shown in FIG. 4, but other forms may be adopted.

  FIG. 9 is a schematic cross-sectional view of an FET 100a according to a modification of the first embodiment. The FET 100 a is a so-called full gate type FET in which no space is provided between the top gate electrode 24 and the source electrode 18. Other configurations are the same as those of the first embodiment (FIG. 4). Thereby, compared with FET100 of Example 1, the parasitic resistance between a source-gate can be suppressed. On the other hand, in the FET 100 of the first embodiment, parasitic capacitance can be suppressed as compared with the FET 100a of the modified example.

In Example 1, PZT was used as the material of the ferroelectric region 26. However, other than this, PLZT ((Pb, La) (Zr, Ti) O ₃ ), BaMgF ₄ , SBT (SrBi ₂ Ta ₂ O _9). ), BLT ((Bi, La) ₄ Ti ₃ O ₁₂ ), Sr ₂ (Ta, Nb) ₂ O ₇ , Pb ₅ Ge ₃ O _11, or the like can be used. Further, as a material for the first insulating layer 14 and the second insulating layer 22, Al ₂ O ₃ or the like can be used in addition to those described above.

  The manufacturing process of the FET 100 according to the first embodiment can coexist with the manufacturing process of a normal silicon FET. That is, the FET 100 may be formed on the same wafer as other silicon FETs. At this time, since there are steps that require high temperatures such as oxidation and diffusion in the process of silicon FET, it is preferable to perform the process of manufacturing the silicon FET first and then the process of manufacturing the FET 100. As a result, the channel region 16 made of a graphite thin film or the like that is susceptible to heat can be protected.

  Hereinafter, a logic circuit using the FET 100 according to the first embodiment will be described.

  The second embodiment is an example of a one-input one-output logic gate using the FET 100 according to the first embodiment.

FIG. 10A shows an example of a basic logic gate using the FET 100, and FIG. 10B shows a symbol of this logic gate. As shown in FIG. 10A, in the logic gate 110, the resistor R and the FET 100 are connected in series between the power supply line Vdd and the ground line Vss. The input signal V _in to the logic gate 110 is input to the first gate of the FET 100, and the output signal V _out of the logic gate 110 is output from the resistor R and the intermediate node of the FET 100. Further, the control signal V _c to the logic gate 110 is input to the second gate of the FET 100.

Hereinafter, the input signal V _in is input to the first gate of the FET 100 to control the on / off of the FET 100, and the control signal V is input to the second gate of the FET to change the polarity of the FET 100. _{Called c} . Also referred to the input terminal 30 a terminal for inputting an input signal V _in the logic gate 110, a terminal for inputting a control signal V _c to the logic gate 110 and the control terminal 32.

Figure 11 is a graph showing the transfer characteristic of the logic gate 110, an input signal _{V in} the horizontal axis, and taking the output signal _{V out} to the vertical axis. In the graph of “FET = n-type” in the figure, the polarization state of the ferroelectric region 26 is the same as in FIG. 7B, and the FET 100 functions as an n-type transistor. At this time, the output signal _{V out} of the logic gate 110 becomes smaller as the input signal _{V in} is high, the logic gate 110 functions as an inverter or NOT gate. In the graph of “FET = p-type” in the drawing, the polarization state of the ferroelectric region 26 is the same as that in FIG. 7D, and the FET 100 functions as a p-type transistor. At this time, the output signal V _out of the logic gate 110 becomes larger as the input signal V _in is high, the input signal to the logic gate 110 is directly output without being inverted.

FIG. 12 is a timing chart showing the operation of the logic gate 110. First, when a positive pulse is applied to the control terminal 32 and the control signal _Vc is at the H level for a predetermined period (A), the polarity of the FET 100 is changed to n-type. Thereafter, until the polarity of the FET100 is inverted (time X), the logic gate 110 serves as an inverter, for inverting and outputting an input signal _{V in.} Thereafter, the control terminal 32 negative pulse is applied to the control signal V _c in that the predetermined period L level (B), the polarity of the FET100 is changed to p-type. Thereafter, during (period Y) until the polarity is reversed for FET 100, the logic gate 110 is directly output without being inverted input signal _{V in.}

As described above, the logic gate 110 of the second embodiment includes an input terminal 30 for inputting an input signal V _in the first gate electrode as a first control means, the second gate electrode as a second control means and a control terminal 32 for inputting a control signal V _c to. According to this configuration, a control signal V _c which is input to the control terminal 32, it is possible to switch the function of the logic gate 110. As described in the first embodiment, since the polarity of the FET 100 is maintained even after the power is turned off, the function of the logic gate 110 once set can be maintained even after the power is turned off.

By using the logic gate 110 having the above characteristics, a logic circuit whose function can be easily changed and held can be configured. As a result, it is possible to realize, for example, higher functionality, lower power consumption, higher speed, smaller size, and lower cost of the integrated circuit. In Comparative Example (Fig. 3 (a)), in order to maintain the function of the logic gates 90, but had to be continuously applied to the control signal _{V c} to the second gate of FET80A～80D, Example In 2 it is not necessary. Therefore, the logic gate 110 of the second embodiment can reduce power consumption compared to the comparative example.

  The logic gate 110 is a resistive load type gate using a resistor R as a load element, but may instead be a complementary gate using FETs having different polarities as a load element.

FIG. 13 is a circuit diagram of a logic gate 110a according to a modification of the second embodiment. As illustrated, an FET 100A and an FET 100B are connected in series between the ground line Vss and the power supply line Vdd. An input signal V _in to the logic gate 110a is input to the first gates of the FET 100A and the FET 100B, and an output signal V _out of the logic gate 110a is output from an intermediate node of the FET 100A and the FET 100B. Also, the first control signal V _c1 to the logic gate 110a is input to the second gate of the FET 100B, and the second control signal V _c2 is input to the second gate of the FET 100A.

Here, the relationship between the first control signal V _c1 and the second control signal V _c2 is paired. If one is positive, the other is negative. When the first control signal V _c1 is positive and the second control signal is negative, the polarity of the FET 100A is n-type, the polarity of the FET 100B is p-type, and the logic gate 110a functions as an inverter (in FIG. 11, FET = n As with molds). Conversely, when the first control signal V _c1 is negative and the second control signal is positive, the polarity of the FET 100A is p-type, the polarity of the FET 100B is n-type, and the logic gate 110a remains as it is without inverting the input signal. Output (same as FET = p type in FIG. 11).

As described above, a complementary logic gate can be configured by using two bipolar FETs 100. The timing chart of the circuit in FIG. 13 is also the same as that in the second embodiment (FIG. 12). At this time, the waveform of the first control signal V _c1 in FIG. 13 and the waveform of the control signal V _c in FIG. 12 are the same, and the waveform of the second control signal V _c2 is the same as the inverted version thereof.

  The third embodiment is an example of a two-input one-output logic gate using the FET 100 according to the first embodiment.

  FIG. 14A shows an example of a basic logic gate using the FET 100, and FIG. 14B shows a symbol of this logic gate. As shown in FIG. 14A, in the logic gate 112, the resistor R and the FET 100A are connected in series between the power supply line Vdd and the ground line Vss. Further, the FET 100B is connected in parallel with the FET 100A between the resistor R and the intermediate node of the FET 100A and the ground line Vss.

The first input signal V _in1 to the logic gate 112 is input to the first gate of the FET 100B, and the second input signal V _in2 to the logic gate 112 is input to the first gate of the FET 100A. The output signal V _out of the logic gate 112 is output from the resistor R and the intermediate node of the FET 100A. Further, the first control signal V _c1 to the logic gate 112 is input to the second gate of the FET 100B, and the second control signal V _c2 to the logic gate 112 is input to the second gate of the FET 100A.

As shown in FIG. 14 (b), the logic gate 112 has an input terminal for inputting an input signal _{V in} to the first gate of the FET (30a, 30b), a control signal _{V c} to the second gate of the FET100 There are two control terminals (32a, 32b) for input.

The operation of the logic gate 112 is the same as that described in the comparative example (FIGS. 3B to 3C) (FETs 100A and 100B correspond to the FETs 80C and 80D of the comparative example, respectively). When the first control signal V _c1 and the second control signal V _c2 are set to the H level for a predetermined period, the FETs 100A and 100B subsequently function as n-type FETs. At this time, if both the first input signal V _in1 and the second input signal V _in2 are at the L level, the output signal V _out is at the H level. In other cases, the output signal V _out is at the L level. That is, the logic gate 112 functions as a NOR gate according to the truth table of FIG.

When the first control signal V _c1 and the second control signal V _c2 are set to L level for a predetermined period, both the FETs 100A and 100B function as p-type FETs thereafter. At this time, if both the first input signal V _in1 and the second input signal V _in2 are at the H level, the output signal V _out is at the H level, and otherwise, the output signal V _out is at the L level. That is, the logic gate 112 functions as an AND gate according to the truth table of FIG.

As described above, by controlling the first control signal V _c1 and the second control signal V _c2 , the polarity of the FETs 100A and 100B can be changed, and the function of the logic gate 112 can be switched between the NOR type and the AND type. In addition, the function of the logic gate once changed can be maintained even after power is turned off. As a result, as in the case of the second embodiment, it is possible to measure the higher functionality and lower power consumption of the integrated circuit.

The logic gate 112 is a resistive load type gate using a resistor R as a load element, but may be a complementary gate using FETs having different polarities as a load element as in the modification of the second embodiment. . This complementary gate is the same as that obtained by replacing the FETs 80A to 80D in the logic gate of the comparative example (FIG. 3A) with the FETs 100A to 100D of the first embodiment. By inputting a pair of signals to the first control signal V _c1 and the second control signal V _c2 , it is possible to function as a NOR type or AND type logic gate as in the third embodiment.

  The fourth embodiment is an example in which the binary decision graph is configured using the FET 100 according to the first embodiment.

FIG. 15 shows a conventional binary decision graph logic circuit. The logic circuit 92 receives two variable input signals V _A and V _B and two fixed input signals “0” and “1”, and outputs one output signal V _out . The logic circuit 92 includes a first transistor Tr1 to a fourth transistor Tr4 and intermediate nodes A and B. The first transistor Tr1 and the third transistor Tr3 are p-type transistors, and the second transistor Tr2 and the fourth transistor Tr4 are n-type transistors.

From the node A, the output V _out of the logic circuit 92 is output. A first transistor Tr1 is connected between the node A and the input “0”, and a second transistor Tr2 is connected between the node A and the node B. The third transistor Tr3 is connected between the node B and the input “0”, and the fourth transistor Tr4 is connected between the node B and the input “1”. The first input signal V _A is input to the gates of the first transistor Tr1 and the second transistor Tr2, and the second input signal V _B is input to the gates of the third transistor Tr3 and the fourth transistor Tr4.

When the first input signal _VA is at the H level, the first transistor Tr1 is turned off and the second transistor Tr2 is turned on. Here, when the second input signal _{V B} is at H level, the third transistor Tr3 is turned off, the fourth transistor Tr4 is turned on. As a result, the input “1” is connected to the output V _out, and the output of the logic circuit 92 becomes 1. In cases other than the above, the input “0” is connected to the output V _out and the output of the logic circuit 92 is zero. Thus, the output of the logic circuit 92 is the product (A · B) of the first input signal V _A and the second input signal V _B.

  In the conventional binary decision graph logic circuit 92, since the circuit elements are fixed, only one type of operation can be performed. Hereinafter, the binary decision graph logic circuit using the bipolar FET 100 according to the first embodiment will be described.

16A to 16D are circuit diagrams of the binary decision graph logic circuit according to the fourth embodiment. The logic circuit 114 is different from the conventional one in that the first transistor Tr1 to the fourth transistor Tr4 are configured by the FET 100 (FIG. 4B) of the first embodiment, and the connection relationship between the input / output terminals and the elements is as shown in FIG. It is the same. In the figure, the level of the control voltage V _c to be input to the second gate of the first transistor Tr1~ fourth transistor Tr4 indicated by "H" or "L" polarity n or p transistor which are determined thereby It shows with. The control voltage V _c is the transistor is p-type if L level, the transistor is n-type when V _c is at H level.

  In FIG. 16A, the first transistor Tr1 and the third transistor Tr3 are p-type transistors, and the second transistor Tr2 and the fourth transistor Tr4 are n-type transistors. Since this is the same as the circuit configuration shown in FIG. 15, the output of the logic circuit 114 is the product of “A” and “B”.

  In FIG. 16B, the first transistor Tr1 and the third transistor Tr3 are n-type transistors, and the second transistor Tr2 and the fourth transistor Tr4 are p-type transistors. Since all the polarities of the transistors are opposite to those in FIG. 16A, the logic circuit 114 outputs a product of “Negation of A” and “Negation of B”.

In FIG. 16C, the first transistor Tr1 and the fourth transistor Tr4 are p-type transistors, and the second transistor Tr2 and the third transistor Tr3 are n-type transistors. When the first input signal V _A is at the H level and the second input signal V _B is at the L level, “1” is output, and otherwise “0” is output. That is, the logic circuit 114 outputs the product of “A” and “Negation of B”.

  In FIG. 16D, the first transistor Tr1 and the fourth transistor Tr4 are n-type transistors, and the second transistor Tr2 and the third transistor Tr3 are p-type transistors. Since all the polarities of the transistors are opposite to those in FIG. 16C, the logic circuit 114 outputs a product of “Negation of A” and “B”.

  As described above, according to the logic circuit 114 of the fourth embodiment, the four logical operations shown in FIGS. 16A to 16D are executed without changing the configuration and connection relationship of the circuit elements. be able to. That is, one logic circuit can have a plurality of functions, and the function of the logic gate once changed can be maintained even after power is turned off. As a result, as in the case of the second to third embodiments, it is possible to measure the higher functionality and lower power consumption of the integrated circuit.

  The fifth embodiment is an example of a logic circuit in which a plurality of FETs according to the first embodiment and basic logic circuits according to the second to fourth embodiments are combined.

  FIG. 17 is a diagram illustrating the configuration of the logic circuit according to the fifth embodiment. The logic circuit 120 includes a plurality of logic gates 112A to 112F, a selection circuit 40, and a writing circuit 50.

The logic gates 112A to 112F are the same as the logic gate 112 according to the third embodiment, each having two input terminals (V _in1 , V _in2 ), two control terminals (V _c1 , V _c2 ), and one output. It has a terminal (V _out ). An address is assigned to each of the logic gates 112A to 112F, and an arbitrary logic gate can be selected from the logic gates 112A to 112F based on the address. The control terminals of the logic gates 112A to 112F are connected to the selection circuit 40 via signal lines, respectively.

  An address is input to the selection circuit 40 from the outside, and a predetermined write voltage is input from the write circuit 50. The write circuit 50 generates a write voltage for changing the polarity of the FET 100 included in the logic gates 112A to 112F. More specifically, the write voltage is a voltage for changing the polarization state of the ferroelectric region 26 in the FET 100 and has an absolute value larger than the coercive electric field of the ferroelectric region 26.

FIG. 18 is a flowchart showing the function changing operation of the logic circuit 120. First, the selection circuit 40 selects a logic gate designated by an address from the logic gates 112A to 112F included in the logic circuit 120 (step S10). Next, the selection circuit 40 applies the write voltage generated by the write circuit 50 to the control terminals (V _c1 , V _c2 ) of the logic gate selected in step S10 (step S12). As a result, the polarity of the FET 100 included in the selected logic gate is inverted, the function of the selected logic gate is changed, and the function of the entire logic circuit 120 is also changed.

  According to the logic circuit 120 according to the fifth embodiment, an address is allocated to each of the plurality of logic gates 112A to 112F, and an arbitrary logic gate can be selected based on the address. Then, by applying a write voltage to the selected logic gate, the functions of the logic gate and the entire logic circuit 120 are changed. As described above, even if the logic circuit is a combination of a plurality of basic logic circuits, a plurality of functions can be realized with the same circuit element by using the FET 100. In addition, the function of the logic gate once changed can be maintained even after the power is turned off. As a result, as in the case of the second to fourth embodiments, it is possible to measure the higher functionality and lower power consumption of the integrated circuit.

  In the above example, the example using the logic gate 112 according to the third embodiment has been described, but the components of the logic circuit 120 include the basic logic circuit described in the second to fourth embodiments and various other logics. A combination of circuits can be used. In the above example, the number of input terminals in each logic circuit is two, the number of control terminals is two, and the number of output terminals is one. However, the number of each terminal is not limited to this. . When there are two or more control terminals, an address may be assigned to each control terminal, or a common address may be used.

  In the fifth embodiment, the selection circuit 40 and the write circuit 50 are included in the logic circuit 120. However, these peripheral circuits may not necessarily be included. For example, only the selection circuit 40 among the peripheral circuits may be included, and the writing circuit 50 may not be included. In this case, the write voltage can be applied to an arbitrary logic gate from the outside. For example, when the product is shipped, a write voltage is applied from the outside to determine the function of the logic circuit 120.

  Further, the logic circuit 120 may be configured not to include both the selection circuit 40 and the writing circuit 50. In this case, an arbitrary logic circuit can be selected from the outside by some method (for example, providing a large number of control pins for circuit selection), and a write voltage can be applied to the selected logic circuit. Then, for example, when the product is shipped, a write voltage is applied from the outside, and the function of the logic circuit 120 is determined. Thus, by omitting the selection circuit 40 and the writing circuit 50, the size of the device can be reduced.

  In the fifth embodiment, addresses are allocated to all the logic gates 112A to 112F. However, it is sufficient that at least one logic gate among the logic gates included in the logic circuit 120 is allocated an address. That is, it is only necessary that one or more logic gates can be selected by the selection circuit 40.

  FIG. 19 is a circuit diagram illustrating a configuration of a logic circuit according to a modification of the fifth embodiment. The logic circuit 122 includes a first logic gate 112A to which an address is assigned and a second logic gate 112B to which an address is not assigned. The configuration of the first logic gate 112A and the second logic gate 112B is the same as that of the logic gate 112 of the third embodiment.

  The output of the first logic gate 112A is input to the switch unit 60. The switch unit 60 is provided between the write circuit 50 and the second logic gate 112B, and switches the write voltage applied from the write circuit 50 to the second logic gate 112B based on the output of the first logic gate 112A. That is, the switch unit 60 selectively applies either a positive voltage for changing the polarity of the FET 100 to n-type or a negative voltage for changing the polarity of the FET 100 to p-type to the control terminal of the second logic gate 112B. The

According to this configuration, changes on the basis of the output of the logic gate 112A allocated by the address among a plurality of logic gates 112a-112b, the write voltage applied to the control terminal V _c of the logic gates 112B unallocated the address Is done. In this way, even in a logic gate to which no address is assigned, its function can be changed during operation. Thereby, the freedom degree of circuit design can be raised.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Substrate 12 Back gate electrode 14 First insulating layer 16 Channel region 18 Source electrode 20 Drain electrode 22 Second insulating layer 24 Top gate electrode 26 Ferroelectric region 30 Input terminal 32 Control terminal 40 Select circuit 50 Write circuit 60 Switch unit 100 FET
110, 112 logic gate 114, 120 logic circuit

Claims (6)

A channel region whose polarity can be changed;
A ferroelectric region that is provided near the channel region and changes the polarity of the channel region based on its polarization state;
First control means for controlling the carrier concentration of the channel region;
Second control means for changing the polarization state of the ferroelectric region;
A field effect transistor. The first control means includes a first gate electrode provided on the opposite side of the ferroelectric region with respect to the channel region,
2. The field effect transistor according to claim 1, wherein the second control unit includes a second gate electrode provided on a side opposite to the channel region with respect to the ferroelectric region.   The field effect transistor according to claim 1, wherein the channel region includes a graphite thin film or a carbon nanotube. A field effect transistor according to any one of claims 1 to 3,
An input terminal for inputting a signal to the first control means;
A control terminal for inputting a signal to the second control means;
A logic circuit. A plurality of logic circuits according to claim 4,
An address is assigned to at least one of the plurality of logic circuits;
A logic circuit in which an arbitrary logic circuit is selected from the plurality of logic circuits according to the address, and a write voltage for changing a polarization state of the ferroelectric region is applied to the control terminal of the selected logic circuit. A write voltage applied to the control terminal of another logic circuit to which the address is not allocated among the plurality of logic circuits, based on the output of the one logic circuit to which the address is allocated among the plurality of logic circuits. 6. The logic circuit according to claim 5, wherein is changed.

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