JP2011014757A - Multilayer semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer semiconductor device for suppressing the occurrence of connection failures among semiconductor devices.SOLUTION: The multilayer semiconductor device 10 includes a first semiconductor device 20 and a second semiconductor device 30. The first semiconductor device 20 includes first solder balls 27, 27, and so on and is electrically connected to the second semiconductor device 30 via the first solder balls 27, 27, and so on. The second semiconductor device 30 includes second solder balls 37, 37, and so on and is electrically connected to a substrate 1 via the second solder balls 37, 37, and so on. The composition of each first solder ball 27 differs from that of the second solder ball 37.

Description

  The present invention relates to a stacked semiconductor device in which at least two semiconductor devices are stacked.

  In order to further reduce the size of electronic equipment, it is important to improve the mounting density of semiconductor devices in the electronic equipment. In mobile devices such as mobile phones, high-density mounting of semiconductor devices is possible by mounting stacked semiconductor devices (POP: Package On Package) in which multiple semiconductor devices (semiconductor packages) are stacked. Is realized.

  A manufacturing method of a semiconductor device in which a stacked semiconductor device is electrically connected to a printed circuit board (referred to as a “mounting structure” in this specification) is as follows. First, after manufacturing a plurality of semiconductor devices (for example, a BGA (Ball grid array) type semiconductor device), a pass / fail judgment is performed on each semiconductor device. Next, a mounting structure is manufactured according to a pre-stack method or an on-board stack method. In the prestack method, a plurality of semiconductor devices are stacked to manufacture a stacked semiconductor device, and then the manufactured stacked semiconductor device is electrically connected to a printed board. In the on-board stack method, semiconductor devices are sequentially mounted on a printed circuit board. In order to reduce the thickness of the stacked semiconductor device, the thickness of each semiconductor device constituting the stacked semiconductor device is reduced as much as possible. Specifically, the solder balls are arranged at positions different from the semiconductor elements in the thickness direction of the stacked semiconductor device.

  The configuration of a conventional mounting structure will be described with reference to FIG. FIG. 14 is a cross-sectional view of a conventional mounting structure.

  In the conventional mounting structure, the stacked semiconductor device 110 is electrically connected to the printed circuit board 101. In the stacked semiconductor device 110, the first semiconductor device 120 is provided on the second semiconductor device 130, and the first semiconductor device 120 and the second semiconductor device 130 are electrically connected to each other. ing.

  In the first semiconductor device 120, a first semiconductor element 123 is bonded to the center of the upper surface of the first wiring board 121, and the first semiconductor element 123 is connected to the first semiconductor element 123 via a wire (not shown). The wiring board 121 is electrically connected to a wiring pattern. .. Are provided on the peripheral edge of the lower surface of the first wiring board 121, and first solder balls 127 are provided on the lower surface of each first electrode portion 125. Yes. The first semiconductor element 123 and the wire are sealed with a resin 129.

  In the second semiconductor device 130, a second semiconductor element 133 is provided at the center of the upper surface of the second wiring board 131, and the second semiconductor element 133 is flip-chip connected to the second wiring board 131. ing. 2nd electrode part 135,135, ... is provided in the periphery of the upper surface of the 2nd wiring board 131, and each 2nd electrode part 135 is 1st electrode part via the 1st solder ball 127 125 is electrically connected. On the lower surface of the second wiring board 131, second solder balls 137, 137,.

  Generally, a semiconductor device in which a plurality of external connection terminals are arranged in a grid pattern on the lower surface of a wiring board is called an area array type semiconductor device, and a semiconductor device in which each external connection terminal is a solder ball is a BGA type. It is called a semiconductor device. That is, both the first semiconductor device 120 and the second semiconductor device 130 are BGA type semiconductor devices.

  By the way, in the BGA type semiconductor device in which the semiconductor element is flip-chip connected to the wiring board, the thermal expansion coefficient differs between the semiconductor element and the wiring board, and thus warpage occurs during the manufacture of the BGA type semiconductor device. Further, this warpage is more conspicuous in the BGA type semiconductor device that is thinned by optimizing the position of the solder ball than in the BGA type semiconductor device that is not thinned. Focusing on this point, Patent Document 1 discusses the bonding area of solder balls. Specifically, in a stacked semiconductor device in which the first semiconductor device is provided over the second semiconductor device, the upper surface of the second wiring substrate included in the second semiconductor device (the semiconductor element is provided). The bonding area between the surface and the solder ball is made smaller than the bonding area between the lower surface of the first wiring board (the surface where no semiconductor element is provided) of the first semiconductor device and the solder ball.

JP 2007-311643 A

  As described in Patent Document 1, in a BGA type semiconductor device in which a semiconductor element is flip-chip connected to a wiring board, the coefficient of thermal expansion differs between the semiconductor element and the wiring board. Warping occurs.

  Further, at the time of manufacturing the stacked semiconductor device, each of the plurality of semiconductor devices is warped by heating in the reflow process. This invites free deformation of each semiconductor device, thus obstructing the manufacture of the stacked semiconductor device. A case where a stacked semiconductor device including two semiconductor devices is manufactured will be described as an example. First, the reflow process is performed after the solder ball of the first semiconductor device is brought into contact with the upper surface of the electrode portion of the second semiconductor device. When the first semiconductor device and the second semiconductor device are greatly deformed by heating in the reflow process, the solder balls of the first semiconductor device are separated from the upper surfaces of the electrode portions of the second semiconductor device during the reflow process. Therefore, the first semiconductor device cannot be electrically connected to the second semiconductor device. This problem may occur even when the stacked semiconductor device is manufactured using the pre-stack method or when the mounting structure is manufactured using the on-board stack method.

  Furthermore, as a result of investigations by the inventors of the present application, it has been found that there are new factors other than the above two factors as factors that hinder the manufacture of the stacked semiconductor device.

  The present invention has been made in view of such a point, and provides a stacked semiconductor device in which the occurrence of poor connection between semiconductor devices is suppressed.

  In the stacked semiconductor device of the present invention, the first semiconductor device is disposed on the second semiconductor device, and the second semiconductor device is connected to the substrate. In the first semiconductor device, the first semiconductor element is provided on the upper surface of the first wiring board, and the first electrode portion and the first solder ball are provided on the lower surface of the first wiring board. It is provided in order. In the second semiconductor device, the second semiconductor element and the second electrode portion are provided on the upper surface of the second wiring substrate, and the second solder balls are provided on the lower surface of the second wiring substrate. Is provided. The second electrode portion is provided at a position on the upper surface of the second wiring substrate that is more peripheral than the portion where the second semiconductor element is provided and that faces the first electrode portion. The first solder ball electrically connects the first electrode portion and the second electrode portion. The composition of the first solder ball is different from the composition of the second solder ball. Specifically, the first solder ball contains Bi, while the second solder ball does not contain Bi. Thereby, since the wetting spread rate of the solder constituting the first solder ball can be increased, the occurrence of poor connection between the first semiconductor device and the second semiconductor device can be suppressed.

  The first solder ball preferably contains less than 10 wt% Bi, and more preferably contains less than 5 wt% Bi. Thereby, even when a large impact is applied to the stacked semiconductor device, it is possible to prevent the first solder ball from being peeled off from the upper surface of the second electrode portion.

  The upper surface of the second electrode part is preferably larger than the lower surface of the first electrode part. Thereby, the wetting force of the solder which comprises the 1st solder ball can be enlarged.

  In a preferred embodiment described later, the first semiconductor element is sealed with resin, and the second semiconductor element is flip-chip connected to the upper surface of the second wiring board.

  According to the present invention, it is possible to suppress the occurrence of poor connection between semiconductor devices.

(A) is the cross-sectional photograph which image | photographed the malfunction location in a well-known laminated semiconductor device, (b) is an enlarged photograph of IB area | region shown to Fig.1 (a). It is sectional drawing which showed typically the malfunction in a well-known laminated semiconductor device. It is sectional drawing of the mounting structure in one Embodiment of this invention. (A)-(d) is sectional drawing which shows the manufacturing method of the mounting structure in one Embodiment of this invention. (A) is sectional drawing of the state which has arrange | positioned the 1st semiconductor device on the 2nd semiconductor device, (b) is an expanded sectional view of the VB area | region shown to Fig.5 (a). (A) is sectional drawing of a laminated structure when the heating in a reflow process is performed, (b) is an expanded sectional view of VI area | region (described in FIG. 6 (a)) in the early stage of heating, (c) FIG. 5 is an enlarged cross-sectional view of the VI region after the first solder ball is melted. (A) is sectional drawing of the manufactured laminated semiconductor device, (b) is an expanded sectional view of the VIIB area | region shown to Fig.7 (a). (A) is sectional drawing which shows the connection state of the 1st solder ball and 2nd electrode part in case the 1st solder ball is not influenced by the curvature of the 1st and 2nd semiconductor device, FIG. 7B is a cross-sectional view showing a connection state between the first solder ball and the second electrode portion when the first solder ball is affected by warpage of the first and second semiconductor devices. It is the graph which showed the relationship between the content rate of Bi in solder, and the wetting spread rate of solder. It is drawing for demonstrating the calculation method of the wetting spread rate of a solder. It is a graph which shows the measurement result of the solid phase point ((double-circle)), liquid phase point ((square)), and solidification point ((triangle | delta)) of solder. It is a graph which shows the measurement result of the joint strength of a solder ball and an electrode part. It is a graph which shows the measurement result of the incidence rate of a destruction mode. It is sectional drawing of the conventional mounting structure.

  Before describing the embodiment of the present invention, what the inventors of the present application have considered in completing the present invention will be described with reference to FIGS. FIG. 1A is a cross-sectional photograph in which a defect portion in a known stacked semiconductor device is photographed, and FIG. 1B is an enlarged photograph of the VIIB region shown in FIG. FIG. 2 is a cross-sectional view schematically showing a defect in a known stacked semiconductor device.

  The inventors of the present application manufacture the first and second semiconductor devices while suppressing the occurrence of warpage, and the first semiconductor device while suppressing the occurrence of warpage in each of the first and second semiconductor devices. Was placed on the second semiconductor device to fabricate a stacked semiconductor device. In the stacked semiconductor device thus obtained, the contact state between the first solder ball included in the first semiconductor device and the second electrode portion included in the second semiconductor device was examined. Then, as shown in FIGS. 1A and 1B, in the obtained stacked semiconductor device, there are portions where the first solder balls 127 and the second electrode portions 135 are separated from each other. I found out. As the reason for this, the inventors of the present application focused on the solidification of the solder in the reflow process.

  In the reflow process, the solder is melted by heating and then cooled to room temperature. Due to the heating in the reflow process, a compressive force acts on the periphery of each of the first semiconductor device and the second semiconductor device, and a small tensile force occurs on the center of each of the first semiconductor device and the second semiconductor device. work. Thereafter, when the solder is melted, surface tension and contraction force act on the solder as the solder solidifies. The surface tension and the contraction force increase the magnitude of the tensile force. As a result, as shown in FIGS. 1A to 2, the contact failure between the first solder ball 127 and the second electrode portion 135 occurs. appear.

  The inventors of the present application have completed the present invention based on the above-described consideration. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to embodiment shown below.

  FIG. 3 is a cross-sectional view of the mounting structure in the embodiment of the present invention.

  In the mounting structure in the present embodiment, the stacked semiconductor device 10 is electrically connected to the upper surface of the printed circuit board 1. In the stacked semiconductor device 10, the first semiconductor device 20 is provided on the second semiconductor device 30, and the first semiconductor device 20 and the second semiconductor device 30 are electrically connected to each other. Yes.

  The first semiconductor device 20 includes a first wiring board 21, a first semiconductor element 23, first electrode portions 25, 25,..., First solder balls 27, 27,. Resin 29.

  The first wiring board 21 is a board on which a wiring pattern (not shown) is formed (such a board is generally called an interposer), and the wiring pattern has electrode terminals (not shown). A circuit (not shown) is formed in the center of the main surface (upper surface in FIG. 1) of the first semiconductor element 23, and an electrode terminal (not shown) is provided on the periphery thereof. This electrode terminal is connected to the electrode terminal of the first wiring board 21 via a wire (not shown), whereby the first wiring board 21 and the first semiconductor element 23 are electrically connected to each other. Is done. This wire and the first semiconductor element 23 are sealed with a sealing resin 29.

  The first electrode portions 25, 25,... Are provided in a lattice shape on the peripheral portion of the lower surface of the first wiring substrate 21, and thus the first semiconductor element 23 in the thickness direction of the first semiconductor device 20. It is arrange | positioned in the position different from. Therefore, the thickness of the first semiconductor device 20 can be reduced as compared with the case where the first electrode portion is provided at the same position as the first semiconductor element in the thickness direction of the first semiconductor device.

  The second semiconductor device 30 includes a second wiring substrate 31, a second semiconductor element 33, second electrode portions 35, 35,..., And second solder balls 37, 37,. ing.

  The second wiring board 31 is a board on which a wiring pattern (not shown) is formed. The second semiconductor element 33 is flip-chip connected to the central portion of the upper surface of the second wiring substrate 31. That is, the electrode terminal (not shown) included in the wiring pattern and the electrode terminal (not shown) included in the second semiconductor element 33 are electrically connected to each other via solder (not shown) or the like.

  The second electrode portions 35, 35,... Are provided on the periphery of the upper surface of the second wiring substrate 31 with respect to the portion where the second semiconductor element 33 is provided, and the first electrode portions 25, 25 are provided. , ... are facing. Therefore, since the second semiconductor element 33 and the second electrode portions 35, 35,... Are arranged at different positions in the thickness direction of the second semiconductor device 30, the thickness of the second semiconductor device 30 is reduced. Can be achieved. In addition, each second electrode portion 35 faces the first electrode portion 25 and is therefore electrically connected to the first electrode portion 25 via the first solder ball 27.

  Each of the second electrode portions 35 as described above may have been subjected to flux treatment at a predetermined position of the wiring pattern formed on the second wiring substrate 31, and may be a nickel plating layer and a gold plating layer. May be provided in order, a nickel plating layer, a palladium plating layer, and a gold plating layer may be provided in order, or a tin alloy plating layer (an alloy layer of tin and lead) In addition, an alloy layer of tin and lead, or an alloy layer of tin, silver, and copper) may be provided.

  The second solder balls 37, 37,... Are arranged on the lower surface of the second wiring board 31 in a grid pattern. Each second solder ball 37 is electrically connected to the second electrode portion 35 through a through electrode (an electrode penetrating in the thickness direction of the second wiring board 31, not shown).

  In such a stacked semiconductor device 10, the composition of the first solder balls 27, 27,... Is different from the composition of the second solder balls 37, 37,. Specifically, each of the first solder balls 27 and each of the second solder balls 37 contains Sn as a main component, and contains about 3 wt% Ag and about 0.5 wt% Cu with respect to Sn. Yes. Each first solder ball 27 contains less than 10% by weight (preferably less than 5% by weight) Bi, but each second solder ball 37 does not contain Bi.

  4A to 4D are cross-sectional views illustrating the method for manufacturing the mounting structure in this embodiment in the order of steps. In the following, a pre-stack method is taken as an example of a method for manufacturing a mounting structure, but the mounting structure may be manufactured using an on-board stack method.

  First, the first semiconductor device 20 and the second semiconductor device 30 are manufactured.

  Next, as shown in FIG. 4A, the flux 41 is transferred onto the surface of each first solder ball 27. A solder paste may be used instead of the flux.

  Subsequently, as shown in FIG. 4B, the first semiconductor device 20 is provided on the second semiconductor device 30. At this time, the first solder balls 27 are arranged on the upper surfaces of the second electrode portions 35, 35,.

  Thereafter, a reflow process is performed. Specifically, each first solder ball 27 is melted, and each melted first solder ball 27 wets and spreads on the upper surface of the second electrode portion 35. Thereby, as shown in FIG. 4C, the stacked semiconductor device 10 is manufactured.

  Then, as shown in FIG. 4D, the stacked semiconductor device 10 is mounted on the upper surface of the printed board 1. Thereby, the mounting structure in this embodiment can be produced.

  Hereinafter, the composition of each first solder ball 27 will be described while explaining the reason why Bi is contained in each first solder ball 27 in the present embodiment.

  As described above, warpage occurs in each of the first semiconductor device 20 and the second semiconductor device 30 during the manufacture of the stacked semiconductor device 10. This phenomenon will be described with reference to FIGS. FIG. 5A is a cross-sectional view of the first semiconductor device 20 disposed on the second semiconductor device 30, and FIG. 5B is an enlarged cross-sectional view of the VB region shown in FIG. 5A. It is. 6A is a cross-sectional view of the laminated structure when heating is performed in the reflow process, and FIG. 6B is an enlarged cross-sectional view of the VI region (described in FIG. 6A) in the initial stage of heating. FIG. 6C is an enlarged cross-sectional view of the VI region after the first solder ball 27 is melted. FIG. 7A is a cross-sectional view of the manufactured stacked semiconductor device, and FIG. 7B is an enlarged cross-sectional view of the VIIB region shown in FIG. 7A.

  When the first semiconductor device 20 is provided on the second semiconductor device 30, the first semiconductor device 20 protrudes downward because the first wiring board 21 and the sealing resin 29 have different thermal shrinkage rates. The second semiconductor device 30 is deformed upward because the second wiring board 31 and the second semiconductor element 33 have different thermal shrinkage rates. Therefore, as illustrated in FIGS. 5A and 5B, the stacked structure (the first semiconductor device 20 is provided on the second semiconductor device 30, and the first semiconductor device 20 and the second semiconductor device 20 are connected to each other). Of the semiconductor device 30 are not electrically connected to each other), the first solder balls 27, 27,... Are separated from the upper surfaces of the second electrode portions 35, 35,. .. Near the center of the body, the first solder balls 27, 27,... Compress the second electrode portions 35, 35,.

  When heating is performed in the reflow process after the first semiconductor device 20 is provided on the second semiconductor device 30, the large volume of the sealing resin 29 expands due to heat, so that the first semiconductor device 20 is placed upward. Since the second wiring substrate 31 having a large main surface is deformed to be convex and expands due to heat, the second semiconductor device 30 is deformed to be convex downward. At this time, at the initial stage of the heating process, the first solder balls 27, 27,... Have the upper surfaces of the second electrode portions 35, 35,. Are separated from the upper surface of the second electrode portions 35, 35,... Near the center of the laminated structure. In this state, the first solder balls 27, 27,... Melt. At this time, the melted first solder balls 27, 27,... Tend to wet and spread on the upper surfaces of the second electrode portions 35, 35,. Therefore, as shown in FIG. 6C, the first solder balls 27, 27,... Located near the center of the multilayer structure are the first solder balls 27, 27,. Compared to ..., it extends in the thickness direction of the laminated structure.

  Then, when cooled, the melted first solder balls 27, 27,... Solidify. At this time, since the surface tension and the contraction force act on the melted first solder balls 27, 27,..., The warping of the first semiconductor device 20 and the second semiconductor device 30 is alleviated, and FIG. The stacked semiconductor device 10 shown in (a) and (b) is formed.

  The cooling in the reflow process will be described in more detail with reference to FIGS. 8A shows the first solder balls 27 and the second electrode portions when the first solder balls 27, 27,... Are not affected by the warp of the first and second semiconductor devices 20, 30. FIG. It is sectional drawing which shows a connection state with 35. FIG. 8B shows the first solder balls 27 and the second electrode portions 35 when the first solder balls 27, 27,... Are affected by the warp of the first and second semiconductor devices 20, 30. It is sectional drawing which shows a connection state with.

  First, a case where the first solder balls 27, 27,... Are not affected by the warp of the first and second semiconductor devices 20, 30 will be described. The first solder balls 27, 27,... Are melted by heating in the reflow process. At this time, a force (solder wetting force) Fw that tends to get wet with the second electrode portions 35, 35,... And a surface tension Fs of the solder act on each first solder ball 27. When the solder wetting force Fw is greater than the surface tension Fs of the solder (Fw> Fs, as shown in FIG. 8A), the action of each first solder ball 27 acts, so that the first solder The ball 27 and the second electrode portion 35 are electrically connected to each other.

  On the other hand, when the first solder balls 27, 27,... Are affected by the warp of the first and second semiconductor devices 20, 30, each of the first solder balls 27 has a solder wetting force Fw and solder. In addition to the surface tension Fs, a tension Fp caused by warping works. If the solder wetting force Fw is equal to or greater than the resultant force of the solder surface tension Fs and the tension Fp caused by warpage (Fw ≧ (Fs + Fp)), the action of wetting of each first solder ball 27 works. On the other hand, when the solder wetting force Fw becomes larger than the resultant force of the solder surface tension Fs and the tension Fp caused by warpage (Fw <(Fs + Fp), as shown in FIG. 8B), each first solder ball Accordingly, the first solder ball 27 and the second electrode portion 35 cannot be electrically connected to each other.

  Further, as the warpage of the first and second semiconductor devices 20 and 30 increases, the tension Fp resulting from the warpage increases. Therefore, if the warpage of the first and second semiconductor devices 20 and 30 is increased, it is difficult to electrically connect the first solder balls 27 and the second electrode portions 35 to each other.

  From the above, if the solder wetting force Fw is increased, the solder wetting force Fw can be made equal to or greater than the resultant force of the solder surface tension Fs and the tension Fp caused by warpage. Also, if the solder wetting time is shortened, the solder wetting force Fw can be increased, and if the solder surface tension Fs is decreased, the solder wetting time can be shortened. That is, if the solder surface tension Fs is reduced, the solder wetting force Fw can be increased.

  Generally, solder having a melting point of about 220 ° C. (hereinafter referred to as “known solder”) is used as a solder used when semiconductor devices are connected to each other. The known solder contains Sn as a main component and contains about 3% by weight of Ag and about 0.5% by weight of Cu. In order to improve the wetting spread rate of the known solder (in order to increase the wetting force Fw of the known solder), various metals were added to the known solder and the wetting spread rate of the solder was measured. Then, when Bi was added to a known solder, the solder spreading rate increased. Further, when the relationship between the Bi content and the solder wetting spread rate was examined, as shown in FIG. 9, the solder wetting spread rate increased as the Bi content rate increased.

  Here, the wetting spread rate of the solder was calculated according to the following method. FIG. 10 is a diagram for explaining a method of calculating the solder spreading ratio.

  First, the solder 81 was applied on the upper surface of the substrate 80 made of electroless Ni / Pd / Au. And the diameter D (mm) of the solder 81 was measured.

  Next, a reflow process (temperature: 240 ° C., heating time: 40 seconds) was performed. Thereby, the solder 81 was melted. After cooling, the solder 81 solidified. Then, the height h (mm) of the solidified solder 82 was measured. The measured D and h were substituted into the following (Formula 1) to calculate the solder wetting spread rate S (%).

S = {(D−h) / D} × 100: (Formula 1)
As shown in FIG. 9, it has been found that if Bi is added to a known solder, the wet spreading rate of the solder can be increased, so the Bi content was optimized. Specifically, the solid point, liquid phase point, and freezing point of the solder to which Bi was added were measured using a reflow simulator. Furthermore, the joint strength between the solder ball to which Bi was added and the electrode part was measured by a shear test. Specifically, the shear rate of the solder ball added with Bi is assumed to be 10 mm / sec (assuming that a force is slowly applied to the solder ball added with Bi as in the reflow process). Was measured. In addition, a shear test was performed to determine the occurrence rate of the failure mode of the solder balls to which Bi was added. Specifically, a shear test is performed at a shear rate of 1000 mm / second (measured when a large force is applied to a solder ball to which Bi is added, such as an impact during a drop), and a failure mode occurs. The rate was determined.

  FIG. 11 is a graph showing the measurement results of the solid phase point (◇), the liquid phase point (□), and the freezing point (Δ) of the solder. FIG. 12 is a graph showing the measurement result of the bonding strength between the solder ball and the electrode part. FIG. 13 is a graph showing the measurement result of the occurrence rate of the fracture mode, where “A” in FIG. 13 indicates a mode in which the solder ball is broken, and “B” in FIG. FIG. 3 shows a mode in which a fracture occurs at the interface between the solder ball and the electrode part, that is, a mode in which the solder ball is peeled off from the upper surface of the electrode part.

  As shown in FIG. 11, as the Bi content increased, the solid phase point, liquid phase point, and freezing point all decreased.

  As shown in FIG. 12, when the Bi content is less than 5% by weight, increasing the Bi content increases the bonding strength between the solder ball and the electrode portion. On the other hand, when the Bi content is 5% by weight or more, even if the Bi content is increased, the bonding strength between the solder ball and the electrode portion does not increase so much.

  As shown in FIG. 13, as the Bi content increased, the incidence of the failure mode at the interface between the solder ball and the electrode portion increased.

  From the results shown in FIGS. 9 and 11 to 13, if the Bi content is less than 5% by weight, the wetting and spreading rate of the solder can be increased, and the bonding strength between the solder and the electrode portion can be ensured in the reflow process. In addition, even when a large external force is applied to the stacked semiconductor device, the breakage at the interface between the solder ball and the electrode portion can be suppressed.

  In summary, if each first solder ball 27 contains Bi, the solder wetting spread rate can be increased as compared to the case where Bi is not contained in the first solder ball. In other words, if Bi is contained in each first solder ball 27, the wetting force Fw of the solder can be increased as compared with the case where Bi is not contained in the first solder ball. Therefore, since the first solder ball 27 and the second electrode portion 35 can be electrically connected to each other, a connection failure occurs between the first semiconductor device 20 and the second semiconductor device 30. This can be suppressed.

  Further, if each first solder ball 27 contains Bi, the first solder ball 27 and the second electrode portion 35 can be joined as compared to the case where Bi is not contained in the first solder ball. The strength can be increased.

  Furthermore, if the Bi content is less than 5% by weight, the destruction at the interface between the first solder ball 27 and the second electrode part 35 is suppressed as compared with the case where the Bi content is 5% by weight or more. can do. Thus, a stacked semiconductor device with excellent reliability can be provided.

  On the other hand, the composition of each second solder ball 37 may be the same as that of a known solder.

  The present embodiment may have the following configuration.

  The stacked semiconductor device may include three or more semiconductor devices. In that case, the solder balls for connecting the semiconductor devices preferably contain Bi, the Bi content is preferably less than 10% by weight, and the Bi content is 5% by weight. If it is less than, it is more preferable.

  You may make the magnitude | size of the upper surface of a 2nd electrode part larger than the magnitude | size of the lower surface of a 1st electrode part. Thereby, compared with the case where the magnitude | size of the upper surface of a 2nd electrode part is below the magnitude | size of the lower surface of a 1st electrode part, the wetting force of solder can be enlarged.

  As described above, the present invention is useful for a stacked semiconductor device in which a plurality of semiconductor devices are stacked.

1 Printed circuit board (Board)
10 Stacked semiconductor devices
20 First semiconductor device
21 First wiring board
23 First semiconductor element
25 1st electrode part
27 First solder ball
29 Sealing resin
30 Second semiconductor device
31 Second wiring board
33 Second semiconductor element
35 Second electrode section
37 Second solder ball
41 Flux
80 substrates
81 solder

Claims (6)

A stacked semiconductor device in which a first semiconductor device is disposed on a second semiconductor device, and the second semiconductor device is connected to a substrate;
The first semiconductor device includes:
A first wiring board;
A first semiconductor element provided on an upper surface of the first wiring board;
A first electrode portion provided on a lower surface of the first wiring board;
A first solder ball provided on the lower surface of the first electrode portion,
The second semiconductor device includes:
A second wiring board;
A second semiconductor element provided on the upper surface of the second wiring board;
A second electrode portion provided at a position on the upper surface of the second wiring substrate at a position opposite to the first electrode portion at a periphery of a portion where the second semiconductor element is provided;
A second solder ball provided on the lower surface of the second wiring board,
The first solder ball electrically connects the first electrode portion and the second electrode portion,
A laminated semiconductor device in which the composition of the first solder balls is different from the composition of the second solder balls. The stacked semiconductor device according to claim 1,
The first solder ball contains Bi,
A stacked semiconductor device in which the second solder ball does not contain Bi. The stacked semiconductor device according to claim 2,
The first solder ball is a stacked semiconductor device containing less than 10 wt% Bi. The stacked semiconductor device according to claim 3,
The first solder ball is a stacked semiconductor device containing less than 5 wt% Bi. A stacked semiconductor device according to any one of claims 1 to 4, wherein
The stacked semiconductor device, wherein an upper surface of the second electrode portion is larger than a lower surface of the first electrode portion. A stacked semiconductor device according to any one of claims 1 to 5,
The first semiconductor element is sealed with a resin,
The second semiconductor element is a stacked semiconductor device that is flip-chip connected to an upper surface of a second wiring board.