JP2011091676A - Communication apparatus and network synchronizing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify the configuration of a communication apparatus by eliminating the need for a dedicated clock supply line which is used only for supplying a synchronizing clock. <P>SOLUTION: When a network-side signal of a predetermined frequency containing audio data is received from a digital line network, an interface means generates a synchronizing clock synchronized to the network-side signal, generates a multiplex signal by multiplexing the synchronizing clock and the audio data in the network-side signal, and outputs the multiplexing signal. A transmission line transmits the multiplex signal outputted from the interface means. When the multiplex signal is received via the transmission line, a processing means generates a system clock to be used for a communication apparatus synchronously with the synchronizing clock in the multiplex signal and processes the audio data in the multiplex signal synchronously with the synchronizing clock in the multiplex signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a communication device and a network synchronization method, and more particularly to a communication device and a network synchronization method connected to a digital line network.

  Patent Document 1 describes a communication device connected to an ISDN (Integrated Services Digital Network) network that is a digital communication network, specifically, a digital telephone exchange.

  This digital telephone exchange has a plurality of digital line interface circuits connected to the ISDN network. This digital telephone exchange selects any one of the network synchronization clocks (synchronization clocks) output from each digital line interface circuit, and uses the selected network synchronization clock as a master clock. This digital telephone exchange generates a system highway clock (system clock) for the digital telephone exchange synchronized with the master clock.

  FIG. 13 is a block diagram showing an outline of the digital telephone exchange described in Patent Document 1. In FIG.

  In FIG. 13, a digital telephone exchange includes a plurality of digital line interface circuits (hereinafter simply referred to as “interface circuits”) 101A to 101C, a system voice highway circuit (hereinafter simply referred to as “highway circuit”) 102, a main A CPU (Central Processing Unit) 103, a clock supply line 104, a control data highway 105, and an audio PCM (Pulse Code Modulation) highway 106 are included.

Each of the interface circuits 101A to 101C includes an ISDN line interface unit 11 ₁ , a network synchronization information control unit 13 ₁ , a network synchronization clock recovery unit 15 ₁ , and a PCM highway interface unit 16 shown in FIG. _{Contains 1} . The main CPU103 corresponds to the communication control CPU 12 ₁ shown in FIG. 2 of Patent Document 1.

  Each of the interface circuits 101A to 101C is connected to the ISDN network 201. Each of the interface circuits 101A to 101C receives a network side signal (for example, ISDN primary group speed interface signal) from the ISDN network 201.

  The network side signal is a signal synchronized with the network side clock used in the ISDN network 201, has a predetermined frequency (for example, 1.536 MHz), and includes voice data and communication control data.

  Each of the interface circuits 101A to 101C uses a network side signal to generate a network synchronization clock (synchronization clock) synchronized with the network side signal. Each of the interface circuits 101A to 101C outputs a network synchronization clock from the output terminal 101a. Each output terminal 101 a is connected to the highway circuit 102 via the clock supply line 104.

  Each of the interface circuits 101A to 101C extracts control data (control channel information: Dch) and voice data (call channel information: Bch) from the network side signal. Each of the interface circuits 101 A to 101 C outputs control data to the main CPU 103 via the control data highway 105. Each of the interface circuits 101A to 101C outputs audio data to the highway circuit 102 via the audio PCM highway 106.

  Note that the audio data is output in units of frames. Each frame of audio data is composed of a plurality of time slots.

  FIG. 14 is a diagram illustrating an example of the interface circuits 101A to 101C. In the following, an operation for extracting voice data from a network side signal and an operation for generating a network synchronization clock based on the network side signal will be described.

  In FIG. 14, in the interface circuit 101A, an ISDN basic interface LSI (Large Scale Integration) 101A1 receives a 192 kHz network side clock used at a point T of the ISDN basic interface as a network side signal.

  The ISDN basic interface LSI 101A1 extracts voice data from the network side signal, converts the voice data into a voice highway signal having a time interval of 125 μsec and 64 time slots, and outputs the voice highway signal to the voice PCM highway 106. To do.

  A PLL (Phase Locked Loop) circuit 101A2 in the ISDN basic interface LSI 101A1 outputs a 64 kHz signal synchronized with the network side signal. The 64 kHz signal is converted into an 8 kHz network synchronous clock by the frequency dividing circuit 101A3. When this network synchronization clock is selected by the output enable signal, it is output from the output enable circuit 101A4 as a master clock.

  In the interface circuit 101B, the ISDN basic interface LSI 101B1 receives a 320 kHz network clock used at the LI point of the ISDN basic interface as a network side signal.

  The ISDN basic interface LSI 101B1 extracts voice data from the network side signal, converts the voice data into a voice highway signal, and outputs the voice highway signal to the voice PCM highway 106.

  The PLL circuit 101B2 in the ISDN basic interface LSI 101B1 outputs an 8 kHz network synchronization clock synchronized with the network side signal. When this network synchronization clock is selected by the output enable signal, it is output from the output enable circuit 101B3 as a master clock.

  In the interface circuit 101C, the ISDN primary group interface LSI 101C1 receives a 1.544 MHz network clock used at the T point of the ISDN primary group interface as a network side signal.

  The ISDN primary group interface LSI 101 C 1 extracts voice data from the network side signal, converts the voice data into a voice highway signal, and outputs the voice highway signal to the voice PCM highway 106.

  The PLL circuit 101C2 in the ISDN primary group interface LSI 101C1 outputs an 8 kHz network synchronization clock synchronized with the network side signal. When the network synchronization clock is selected by the output enable signal, it is output from the output enable circuit 101C3 as a master clock.

JP-A-6-11574

  In the digital telephone exchange described in Patent Document 1, as shown in FIG. 13, a dedicated clock supply line is provided to supply a network synchronization clock (synchronization clock) from one of a plurality of interface circuits to a highway circuit. It was necessary. Each interface circuit and highway circuit also require a connector connected to the clock supply line.

  For this reason, the digital telephone exchange described in Patent Document 1 has a problem that the configuration is complicated by having a dedicated clock supply line and a connector connected to the clock supply line.

  The problem that the configuration is complicated by having a dedicated clock supply line and a connector connected to the clock supply line is not only a problem with a digital telephone exchange, but a digital line network such as an ISDN network. This is a problem common to communication devices connected to the.

  The objective of this invention is providing the communication apparatus and network synchronization method which can solve the subject mentioned above.

The communication device of the present invention is a communication device connected to a digital network,
When a network side signal having a predetermined frequency including voice data is received from the digital circuit network, a synchronization clock synchronized with the network side signal is generated, and the synchronization clock and the voice data in the network side signal are multiplexed. Interface means for generating a multiplexed signal and outputting the multiplexed signal;
A transmission line for transmitting the multiplexed signal output from the interface means;
When the multiplexed signal is received via the transmission line, a system clock used in the communication device is generated in synchronization with a synchronous clock in the multiplexed signal, and audio data in the multiplexed signal is generated in the multiplexed signal. And processing means for processing in synchronization with the synchronous clock.

The network synchronization method of the present invention is a network synchronization method in a communication apparatus connected to a digital circuit network,
When a network side signal having a predetermined frequency including voice data is received from the digital circuit network, a synchronization clock synchronized with the network side signal is generated, and the synchronization clock and the voice data in the network side signal are multiplexed. An output step of generating a multiplexed signal and outputting the multiplexed signal to a transmission line;
When the multiplexed signal is received via the transmission line, a system clock used in the communication device is generated in synchronization with a synchronous clock in the multiplexed signal, and audio data in the multiplexed signal is generated in the multiplexed signal. And a processing step for processing in synchronization with the synchronous clock.

  According to the present invention, a dedicated clock supply line used only for supplying a synchronous clock can be eliminated, and the configuration of the communication apparatus can be simplified.

1 is a block diagram showing a digital telephone exchange according to a first embodiment of the present invention. It is the figure which showed an example of interface circuits 11A-11C. It is the figure which showed the audio | voice highway signal. 2 is a block diagram showing a DPLL circuit 3. FIG. 3 is a circuit diagram showing a multiplexing circuit 4. FIG. It is explanatory drawing which showed an example of the audio | voice highway signal. It is the block diagram which showed the exchange 1A of 2nd Embodiment of this invention. It is explanatory drawing which showed an example of the audio | voice highway signal. It is a figure which shows the bit information of MC1-MC4. 2 is a block diagram showing a digital line interface circuit 5. FIG. 5 is a diagram illustrating an example of a multiplexing circuit 52. FIG. FIG. 6 is a diagram showing a selection circuit 6. 1 is a block diagram showing an outline of a digital telephone exchange described in Patent Document 1. FIG. It is a figure which shows an example of the interface circuits 101A-101C.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a digital telephone exchange (hereinafter simply referred to as “exchange”) which is a communication apparatus according to a first embodiment of the present invention.

  In FIG. 1, an exchange 1 is connected to an ISDN network 2 via a digital line.

  Here, the digital line indicates an ISDN basic interface, an ISDN primary group interface, a digital dedicated line, or the like. The digital line also includes a line used when behind-the-scene connection is made between digital telephone exchanges using the SDN interface function of ISDN.

  The ISDN network 2 can be generally called a digital circuit network. The ISDN network 2 outputs a network side signal (for example, ISDN primary group speed interface signal) to the exchange 1. The network side signal is a signal synchronized with the network side clock used in the ISDN network 2, has a predetermined frequency (for example, 1.536 MHz), and includes audio data.

  The exchange 1 includes a plurality of digital line interface circuits (hereinafter simply referred to as “interface circuits”) 11A to 11C, a voice PCM highway 12, a system voice highway circuit (hereinafter simply referred to as “highway circuit”) 13, A control data highway 14 and a main CPU 15 are included.

  Each of interface circuits 11A-11C can be generally referred to as interface means.

  When each of the interface circuits 11A to 11C receives a network side signal from the ISDN network 2, it extracts voice data from the network side signal.

  Each of the interface circuits 11 </ b> A to 11 </ b> C converts audio data into an audio highway signal having an interval of 125 μsec and 64 time slots, and outputs the audio highway signal to the audio PCM highway 12. The number of time slots of the audio highway signal is not limited to 64 and can be changed as appropriate.

  Further, when each of the interface circuits 11A to 11C receives a network side signal from the ISDN network 2, it uses the network side signal to generate a network synchronization clock synchronized with the network side signal. The network synchronization clock can be generally called a synchronization clock.

  Each of the interface circuits 11 </ b> A to 11 </ b> C outputs control data related to the network synchronization clock (for example, information indicating whether the network synchronization clock has been generated) to the main CPU 15 via the control data highway 14.

  Based on the control data from each of the interface circuits 11A to 11C, the main CPU 15 outputs an interface circuit (hereinafter referred to as “representative interface circuit”) 11 that outputs a network synchronization clock to any one of the interface circuits 11A to 11C. And the result of the selection is output to each of the interface circuits 11A to 11C.

  Each of the interface circuits 11A to 11C operates as a representative interface circuit when the selection result of the main CPU 15 indicates that its own circuit is selected as the representative interface circuit. The network synchronization clock generated by the representative interface circuit 11 is used as a master clock.

  The representative interface circuit 11 multiplexes a master clock (network synchronization clock) and audio data to generate a multiplexed signal. In the present embodiment, the representative interface circuit 11 generates a multiplexed signal by time division multiplexing the master clock and audio data. The representative interface circuit 11 may multiplex the master clock and the audio data by a method different from the time division multiplexing.

  The representative interface circuit 11 outputs the multiplexed signal to the audio PCM highway 12.

  Voice PCM highway 12 can generally be referred to as a transmission line. The voice PCM highway 12 connects each of the interface circuits 11A to 11C to the highway circuit 13.

  FIG. 2 is a diagram illustrating an example of the interface circuits 11A to 11C. FIG. 2 shows a configuration for generating multiple signals in the interface circuits 11A to 11C.

  In FIG. 2, an interface circuit 11A is an ISDN basic interface LSI (hereinafter simply referred to as “LSI”) 11A1, a frequency dividing circuit 11A2, and an audio / master clock multiplexing circuit (hereinafter simply referred to as “multiplexing circuit”). ) 11A3. The LSI 11A1 includes a PLL circuit 11A4.

  The interface circuit 11B includes an ISDN basic interface LSI (hereinafter simply referred to as “LSI”) 11B1 and an audio / master clock multiplexing circuit (hereinafter simply referred to as “multiplexing circuit”) 11B2. The LSI 11B1 includes a PLL circuit 11B3.

  The interface circuit 11C includes an ISDN primary group interface LSI (hereinafter simply referred to as “LSI”) 11C1 and an audio / master clock multiplexing circuit (hereinafter simply referred to as “multiplexing circuit”) 11C2. The LSI 11C1 includes a PLL circuit 11C3.

  In a situation where the interface circuit 11A is a representative interface circuit, the interface circuit 11A operates as follows.

  When receiving the 192 kHz network side clock used at the T point of the ISDN basic interface as a network side signal, the LSI 11A1 extracts voice data from the network side signal.

  The LSI 11A1 places the audio data in the 1st to 63rd time slots counted from the head among the audio highway signals having an interval of 125 μsec and 64 time slots. That is, the LSI 11A1 converts the audio data into an audio highway signal. The LSI 11A1 outputs an audio highway signal carrying audio data to the multiplexing circuit 11A3.

  The PLL circuit 11A4 uses the network side signal to output a 64 kHz signal synchronized with the network side signal. The 64 kHz signal is converted into an 8 kHz network synchronization clock by the frequency dividing circuit 11A2. The frequency dividing circuit 11A2 outputs the network synchronization clock as a master clock to the multiplexing circuit 11A3.

  When the multiplexing circuit 11A3 receives the audio highway signal carrying the audio data and the master clock, the multiplexing circuit 11A3 places the data representing the master clock in the 64th time slot of the audio highway signal. That is, the multiplexing circuit 11A3 time-division multiplexes the audio data and the master clock. The multiplexing circuit 11A3 outputs an audio highway signal carrying audio data and a master clock, that is, a multiplexed signal, to the audio PCM highway 12.

  In the situation where the interface circuit 11B is a representative interface circuit, the interface circuit 11B operates as follows.

  When the LSI 11B1 receives the network side clock of 320 kHz used at the LI point of the ISDN basic interface as a network side signal, the LSI 11B1 extracts voice data from the network side signal.

  The LSI 11B1 places the audio data in the 1st to 63rd time slots counted from the head of the audio highway signal. That is, the LSI 11B1 converts the audio data into an audio highway signal. The LSI 11B1 outputs an audio highway signal carrying audio data to the multiplexing circuit 11B2.

  The PLL circuit 11B3 uses the network side signal to generate an 8 kHz network synchronization clock synchronized with the network side signal, and outputs the network synchronization clock as a master clock to the multiplexing circuit 11B2.

  When the multiplexing circuit 11B2 receives the audio highway signal carrying the audio data and the master clock, the multiplexing circuit 11B2 places the data representing the master clock in the 64th time slot of the audio highway signal. That is, the multiplexing circuit 11B2 time-division multiplexes the audio data and the master clock. The multiplexing circuit 11B2 outputs an audio highway signal carrying audio data and a master clock, that is, a multiplexed signal, to the audio PCM highway 12.

  Further, in a situation where the interface circuit 11C is a representative interface circuit, the interface circuit 11C operates as follows.

  When the LSI 11C1 receives a 1.544 MHz network-side clock used at the point T of the ISDN primary group interface as a network-side signal, the LSI 11C1 extracts voice data from the network-side signal.

  The LSI 11C1 places the audio data in the 1st to 63rd time slots counted from the head of the audio highway signal. That is, the LSI 11C1 converts the audio data into an audio highway signal. The LSI 11C1 outputs an audio highway signal carrying audio data to the multiplexing circuit 11C2.

  The PLL circuit 11C3 uses the network side signal to generate an 8 kHz network synchronization clock synchronized with the network side signal, and outputs the network synchronization clock to the multiplexing circuit 11C2 as a master clock.

  When the multiplexing circuit 11C2 receives the audio highway signal carrying the audio data and the master clock, the multiplexing circuit 11C2 places the data representing the master clock in the 64th time slot of the audio highway signal. That is, the multiplexing circuit 11C2 time-division multiplexes the audio data and the master clock. The multiplexing circuit 11C2 outputs an audio highway signal carrying audio data and a master clock, that is, a multiplexed signal, to the audio PCM highway 12.

  In FIG. 3, audio data (Bch) is placed in the 1st to 63rd time slots (1ch to 63ch), and data representing the master clock (master clock data) is placed in the 64th time slot (64ch). It is the figure which showed the highway signal.

  Returning to FIG. 1, the voice PCM highway 12 can be generally referred to as a communication line. The voice PCM highway 12 connects each of the interface circuits 11A to 11C to the highway circuit 13.

  Highway circuit 13 can be generally referred to as processing means.

  When the highway circuit 13 receives a multiplexed signal (audio highway signal carrying audio data and a master clock) from the representative interface circuit via the audio PCM highway 12, the master clock is based on the master clock in the multiplexed signal. The system clock used in the exchange 1 is generated in synchronism with the voice signal, and the audio data in the multiplexed signal is processed in synchronization with the master clock in the multiplexed signal.

  The highway circuit 13 reads the master clock data from the audio highway signal. The PLL circuit 13a in the highway circuit 13 uses the master clock indicated by the data to generate a system highway clock synchronized with the master clock as a system clock.

  The highway circuit 13 supplies the system clock to, for example, the interface circuits 11A to 11C and the main CPU 15. Therefore, the operation timing based on the system clock in the exchange 1 can be synchronized with the operation timing based on the network side clock used in the ISDN network 2.

  FIG. 4 is a block diagram showing a DPLL (Digital Phase Locked Loop) circuit 3 that can be used as the PLL circuit 13a.

  4, a DPLL circuit 3 includes a D-FF (D-flip-flop) 31 that functions as a phase comparator, a shift register 32 that functions as a phase state storage unit, a counter reset value selector 33, and a counter frequency divider circuit. 34 and a crystal oscillator 35.

  The counter frequency dividing circuit 34 outputs an 8 kHz system clock by switching the output value between “1” and “0” every time a predetermined number of pulses from the crystal oscillator 35 are counted.

  The master clock (8 kHz) read from the audio highway signal is input to the D terminal of the D-FF 31. The system clock (8 kHz) output from the counter frequency dividing circuit 34 is input to the CK terminal of the D-FF 31.

  For this reason, when the phase of the system clock is ahead of the phase of the master clock, the output (phase comparison value) of the D-FF 31 is “0”, and the phase of the system clock is delayed from the phase of the master clock. If there is, the output (phase comparison value) of the D-FF 31 is “1”.

  The output (phase comparison value) of the D-FF 31 is held in the shift register 32 and then output to the counter reset value selector 33.

  When the output (phase comparison value) of the D-FF 31 is “0”, the counter reset value selector 33 adds 1 to the predetermined number used by the counter frequency dividing circuit 34 to switch the output value, and the cycle of the system clock Is lengthened by one pulse from the crystal oscillator 35.

  On the other hand, when the output (phase comparison value) of the D-FF 31 is “1”, the counter reset value selector 33 subtracts 1 from the predetermined number used by the counter frequency dividing circuit 34 to set the cycle of the system clock to the crystal It is shortened by one pulse from the oscillator 35.

  Therefore, in the stable operation region in which the DPLL circuit 3 is phase-locked (phase fixed), the phase comparison value for three frames is “1” → “0” → “1” → “0” or “0” → “1”. ⇒ Alternating with “0”, or “1” ⇒ “0” ⇒ “0” or “0” ⇒ “1” ⇒ “1”.

  The DPLL circuit 3 sets “0” or “1” to the correction timing (timing for correcting the predetermined value) once every 8 kHz or the phase comparison value twice consecutively by designing the synchronous range of the exchange 1. In the case of showing, it can be changed as appropriate, for example, correction to 4 kHz once.

  FIG. 5 is a circuit diagram showing a multiplexing circuit 4 that can be used as the multiplexing circuit 11A3, 11B2, or 11C2 shown in FIG.

  In FIG. 5, the multiplexing circuit 4 includes a D-FF 41 and a selector 42.

  A master clock is supplied to the D terminal of the D-FF 41. A system clock is supplied to the D terminal of the DFF 3a.

  The audio highway signal is input to the A terminal (input terminal) of the selector 42, and the output from the D-FF 41 is input to the B terminal (input terminal) of the selector 42. The switching signal shown in FIG. 3 is input to the S terminal (selector terminal) of the selector 42. The switching signal is “0” when the 1st to 63rd time slots of the audio highway signal are input to the A terminal, and “0” when the 64th time slot of the audio highway signal is input to the A terminal. 1 ".

  When the switching signal is “0”, the selector 42 outputs the audio highway signal input to the A terminal. On the other hand, when the switching signal is “1”, the selector 42 loads the output (master clock) of the D-FF 41 input to the B terminal into all 8 bits of the 64th time slot of the audio highway signal. Output.

  FIG. 6 is an explanatory diagram showing an example of the audio highway signal generated by the multiplexing circuit 4.

  Next, the operation will be described.

  Each of the interface circuits 11A to 11C receives a network side signal from the ISDN network 2 and performs an operation for generating a network synchronization signal synchronized with the network side signal. Each of the interface circuits 11 </ b> A to 11 </ b> C outputs control data related to the network synchronization clock to the main CPU 15 via the control data highway 14.

  The main CPU 15 selects any one of the interface circuits 11A to 11C as the representative interface circuit 11 based on the control data from each of the interface circuits 11A to 11C, and the result of the selection is selected as the interface circuits 11A to 11C. Output to each of. Since the representative interface circuit selection method is a known technique, a detailed description thereof will be omitted.

  The representative interface circuit 11 extracts the voice data from the network side signal, places the voice data in the 1st to 63rd time slots of the voice highway signal, and uses the information indicating the master clock as the 64th time of the voice highway signal. Put it in the slot.

  In the present embodiment, the master clock information indicates whether the phase of the master clock is advanced or delayed with respect to the rising timing of the system clock. The master clock information may indicate whether the phase of the master clock is advanced or delayed with respect to the falling timing of the system clock.

  Subsequently, the representative interface circuit 11 outputs an audio highway signal carrying audio data and a master clock, that is, a multiplexed signal, to the audio PCM highway 12.

  When the highway circuit 13 receives a multiplexed signal (audio highway signal carrying audio data and a master clock) from the representative interface circuit 11 via the audio PCM highway 12, the highway circuit 13 uses the master clock in the multiplexed signal to A system clock synchronized with the master clock is generated, and the audio data in the multiplexed signal is processed in synchronization with the master clock in the multiplexed signal.

  According to the present embodiment, the representative interface circuit 11 generates a multiplexed signal by multiplexing the master clock and the audio data, and outputs the multiplexed signal to the highway circuit 13 via the audio PCM highway 12. For this reason, the master clock is supplied to the highway circuit 13 via the audio PCM highway 12 for transmitting audio data.

  Therefore, a clock supply line dedicated for the master clock can be eliminated, and the configuration of the exchange can be simplified.

  Even in an exchange (communication device) composed of a plurality of interface circuits 11A to 11C, a voice PCM highway 12, and a highway circuit 13, a clock supply line dedicated to the master clock can be eliminated, and the configuration of the exchange can be simplified. Has the effect of becoming.

  According to the present embodiment, the representative interface circuit 11 generates a multiplexed signal by time division multiplexing the master clock and the audio data. In this case, the master clock and the audio data can be time-division multiplexed using the audio highway signal used in the exchange connected to the ISDN network.

(Second Embodiment)
Next, an exchange (for example, a digital telephone exchange) according to the second embodiment of the present invention will be described.

  In the exchange 1 of the first embodiment, the master clock information generated by the representative interface circuit 11 among the interface circuits 11A to 11C is described in the 64th time slot of the audio highway signal.

  On the other hand, in the exchange of the second embodiment, the number of time slots equal to the number of interface circuits (N: N is an integer of 2 or more) in the exchange among the 64 time slots of the voice highway signal, It is used not for audio data but for a network synchronization clock, and the time slot for the network synchronization clock is associated with the interface circuit on a one-to-one basis.

  FIG. 7 is a block diagram showing an exchange 1A according to the second embodiment of the present invention. In FIG. 7, the same components as those shown in FIG.

  In FIG. 7, the exchange 1A is connected to the ISDN network 2 via a digital line.

  The exchange 1A includes four (N = 4) digital line interface circuits (hereinafter simply referred to as “interface circuits”) 11AA, 11BA, 11CA and 11DA, a voice PCM highway 12, a system voice highway circuit (hereinafter simply referred to as “interface circuit”). 13A) (referred to as “highway circuit”), control data highway 14, and main CPU 15A. N is not limited to 4.

  Each of interface circuits 11AA, 11BA, 11CA and 11DA can be generally referred to as interface means.

  When each of the interface circuits 11AA, 11BA, 11CA, and 11DA receives a network side signal from the ISDN network 2, it extracts voice data from the network side signal.

  Each of the interface circuits 11AA, 11BA, 11CA, and 11DA converts the audio data into an audio highway signal having one frame interval of 125 μsec and 64 time slots, and outputs the audio highway signal to the audio PCM highway 12.

  Further, each of the interface circuits 11AA, 11BA, 11CA and 11DA, when receiving a network side signal from the ISDN network 2, generates a network synchronization clock synchronized with the network side signal.

  FIG. 8 shows 61ch (61st time slot), 62ch (62nd time slot), 63ch (63rd time slot) as time slots for the network synchronization clock in one frame (64 time slots) of the voice highway signal. It is the figure which showed the example in which four ch (time slot) of 64ch (64th time slot) exists.

  In this embodiment, interface circuits 11AA, 11BA, 11CA, and 11DA are assigned to 61ch, 62ch, 63ch, and 64ch, respectively.

  The interface circuit 11AA describes information (hereinafter referred to as “MC1”) on the network synchronization clock generated by the interface circuit 11AA in 61ch.

  The interface circuit 11BA describes information relating to the network synchronization clock generated by the interface circuit 11BA (hereinafter referred to as “MC2”) in 62ch.

  The interface circuit 11CA describes information regarding the network synchronization clock generated by the interface circuit 11CA (hereinafter referred to as “MC3”) in 63ch.

  The interface circuit 11DA describes information regarding the network synchronization clock generated by the interface circuit 11DA (hereinafter referred to as “MC4”) in 64ch.

  FIG. 9 is a diagram illustrating bit information of MC1 to MC4. Items of information described in MC1 to MC4 are common. For this reason, in order to avoid duplication of explanation, FIG. 9 shows MC4 bit information.

  MC4 is 8-bit information consisting of B7 to B0.

  B7 describes CK2 (the latest value of the network synchronization clock). B6 describes CK1 (the value of the network synchronization clock before one frame (125 μs)). B5 describes CK0 (the value of the network synchronization clock before one frame (250 μs)).

  In B4 to B2, I-TYPE (ISDN line type) is described. I-TYPE can be generally referred to as type information indicating the type of a digital line that supplies a network-side signal to an interface circuit.

  In this embodiment, I-TYPE = 000 indicates an ISDN basic interface, and I-TYPE = 001 indicates an ISDN primary group interface. I-TYPE = 010 indicates a TTC 2.048 MHz digital dedicated line, and I-TYPE = 011 indicates a TTC 1.511 MHz digital dedicated line. I-TYPE = 100, 101, and 110 indicate spare, and I-TYPE = 111 indicates no.

  B1 describes DK1 (current digital line synchronization state). DK1 = 1 indicates a synchronous state, and DK1 = 0 indicates an asynchronous state.

  In B0, DK0 (digital line synchronization state before one frame (125 μs)) is described. DK0 = 1 indicates a synchronous state, and DK0 = 0 indicates an asynchronous state.

  For this reason, the voice highway signal includes four network synchronization signals.

  FIG. 10 is a block diagram showing a digital line interface circuit (hereinafter simply referred to as “interface circuit”) 5 that can be used as the interface circuits 11AA, 11BA, 11CA, and 11DA.

  Interface circuit 5 includes an interface LSI (hereinafter simply referred to as “LSI”) 51 and a multiplexing circuit 52.

  When receiving the network side signal, the LSI 51 extracts voice data from the network side signal. The LSI 51 places the audio data in the 1st to 60th time slots counted from the top of the audio highway signal having an interval of 125 μsec and 64 time slots. That is, the LSI 51 converts audio data into an audio highway signal. The LSI 51 outputs an audio highway signal carrying audio data to the multiplexing circuit 52.

  Further, the LSI 51 generates an 8 kHz network synchronization clock synchronized with the network side signal, and outputs the network synchronization clock to the multiplexing circuit 52.

  Further, the LSI 51 determines whether or not the network synchronization clock is synchronized with the network side clock in synchronization with the system clock, and outputs the determination result to the multiplexing circuit 52 as a synchronization data signal.

  Further, I-TYPE (ISDN line type) is stored in advance in the LSI 51, and the LSI 51 outputs I-TYPE (ISDN line type) to the multiplexing circuit 52 as line type data.

  When the multiplexing circuit 52 receives the voice highway signal, the network synchronization clock, the synchronization data signal, and the line type data, the time slot (ch) assigned to the interface circuit including the time slot of the voice highway signal. The network high-speed signal in which the network synchronization clock, the synchronization data signal, and the line type data are described and the network synchronization clock, the synchronization data signal, and the line type data are described is output as a multiplexed signal.

  FIG. 11 is a diagram illustrating an example of the multiplexing circuit 52.

  The multiplexing circuit 52 includes D-FFs 52a to 52e, a shift register 52f, and a selector 52g.

  The synchronous data signal is input from the D-FF 52a to the D-FF 52b in synchronization with the system clock. The output of the D-FF 52b is input to the A terminal of the shift register 52f as DK0. The output of the D-FF 52a is also input to the B terminal of the shift register 52f as DK1.

  The line type data is input in 1-bit units to the C terminal, D terminal, and E terminal of the shift register 52f.

  The network synchronization clock is input from the D-FF 52c to the D-FF 52d and further to the D-FF 52e in synchronization with the system clock. The output of the D-FF 52e is input to the F terminal of the shift register 52f as CK0. The output of the D-FF 52d is also input to the G terminal of the shift register 52f as CK1. The output of the D-FF 52c is input to the H terminal of the shift register 52f as CK2.

  Based on the network synchronization clock data load pulse and the network synchronization clock data shift clock, the shift register 52f converts the input to the A terminal to the H terminal into the serial data shown in FIG. 9, and the serial data (MC: Network synchronization data) is output to the selector 52g.

  The selector 52g describes the serial data (MC) in the time slot (ch) assigned to the interface circuit including the selector among the time slots of the audio highway signal, and multiplexes the audio highway signal in which the MC is described. Output as a signal.

  Returning to FIG. 7, the highway circuit 13A includes a PLL circuit 13a and a selection circuit 13A1.

  The selection circuit 13A1 selects a master clock (that is, a synchronization clock for generating a system clock) from a plurality of network synchronization clocks described in the audio highway signal, for example, based on type information in the multiplexed signal, The master clock is output to the PLL circuit 13a.

  FIG. 12 is a diagram showing a selection circuit 6 that can be used as the selection circuit 13A1.

  The selection circuit 6 includes a serial-parallel conversion circuit 61, a CK2 extraction circuit 62, a line type data register 63, a synchronization data register 64, a monitoring circuit 65, a master clock selection circuit 66, and a selector 67. .

  The serial-parallel conversion circuit 61 transmits the network synchronization clock (CK2 to CK0), the synchronization data (DK1 to DK0) and the line type data (I-TYPE) described in the uplink voice highway signal for each time slot (for each interface circuit). ) To parallel data.

  The serial-parallel conversion circuit 61 outputs a plurality of CK2s described in the audio highway signal to the CK2 extraction circuit 62 for each time slot.

  The CK2 extraction circuit 62 outputs each CK2 to the selector 67 in parallel.

  Further, the serial-parallel conversion circuit 61 stores a plurality of line type data (I-TYPE) described in the audio highway signal in the line type data register 63 for each time slot.

  The serial-parallel conversion circuit 61 stores a plurality of synchronization data (DK1 to DK0) described in the audio highway signal in the synchronization data register 64 for each time slot.

  The serial-parallel conversion circuit 61 stores a plurality of network synchronization clocks (CK2 to CK0) described in the audio highway signal in the monitoring circuit 65 for each time slot.

  The master clock selection circuit 66 includes line type data (I-TYPE) in the line type data register 63, synchronization data (DK1 to DK0) in the synchronization data register 64, and network synchronization clocks (CK2 to CK2) in the monitoring circuit 65. Based on (CK0), a master clock source switching signal for selecting an output from the selector 67 is generated, and this master clock source switching signal is output to the selector 7.

  The master clock selection circuit 66 outputs a master clock source switching signal based on the selection conditions shown below.

  As essential elements for master clock selection, it is necessary that a digital line is connected and that the line synchronization state of the LSI is stable.

  The master clock selection circuit 66 determines the line synchronization state of each interface circuit with two bits DK0 and DK1. DK0 and DK1 indicate the synchronization state and become the master clock source only.

  Next, the master clock selection circuit 66 selects a synchronous clock for generating a system clock based on the line type of I-TYPE.

  In the present embodiment, the line types of I-TYPE are in the order of priority: TTC 2.048 MHz digital dedicated line → TTC 1.544 MHz dedicated line → ISDN primary group interface → ISDN basic interface.

  Once the system clock is synchronized with the master clock, as described with reference to FIG. 4, there is no case where all of the stable operation areas of the DPLL synchronized with the master clock are “1” or “0”. Therefore, when CK2 to CK0 all indicate “1” or all “0”, or when both DK0 and DK1 are displayed asynchronously, the master clock selection circuit 66 sets the master clock to the next priority. Automatic transition to the network synchronization clock of the rank

  According to the present embodiment, the highway circuit 13A selects a master clock for generating a system clock from N network synchronization clocks based on I-TYPE in the audio highway signal, and synchronizes with the master clock. Generated system clock.

  This eliminates the need for the main CPU 15A to control the switching of the master clock. Therefore, the load on the main CPU 15A can be reduced, and the control data used for switching the master clock between the main CPU 15A and each interface circuit can be made unnecessary.

  In this embodiment, since the master CPU 15A does not need to perform master clock switching control, it is possible to determine the master clock switching at every 8 kHz by using the complete hardware logic, and software control by the main CPU 15 is possible. The master clock switching time is faster than the master clock switching.

  When the master clock switching time is shortened, a data error called slip caused by the master clock switching can be shortened. Note that slip occurs due to a shift between the system clock frame and the network clock.

  In each of the above embodiments, a digital telephone exchange is used as a communication apparatus. However, the communication apparatus is not limited to a digital telephone exchange, and for example, a communication apparatus such as a button telephone that accommodates a digital line, a home telephone, or a FAX. But you can.

  In each embodiment described above, the illustrated configuration is merely an example, and the present invention is not limited to the configuration.

1, 1A exchange 11A-11C, 11AA, 11BA, 11CA, 11DA Digital circuit interface circuit 11A1, 11B1 ISDN basic interface LSI
11C1 ISDN primary group interface LSI
11A4, 11B3, 11C3, 13a PLL circuit 11A2 Frequency divider circuit 11A3, 11B2, 11C2 Audio / master clock multiplexing circuit 12 Audio PCM highway 13, 13A System audio highway circuit 13A1 Selection circuit 14 Control data highway 15, 15A Main CPU
2 ISDN network 3 DPLL circuit 31 D-FF
32 Shift register 33 Counter reset value selector 34 Counter frequency divider 35 Crystal oscillator 4 Multiplexer 41 D-FF
42 selector 5 digital circuit interface circuit 51 interface LSI
52 Multiplexing circuit 52a to 52e D-FF
52f shift register 52g selector 6 selection circuit 61 serial parallel conversion circuit 62 CK2 extraction circuit 63 line type data register 64 synchronous data register 65 monitoring circuit 66 master clock selection circuit 67 selector

Claims (5)

A communication device connected to a digital network,
When a network side signal having a predetermined frequency including voice data is received from the digital circuit network, a synchronization clock synchronized with the network side signal is generated, and the synchronization clock and the voice data in the network side signal are multiplexed. Interface means for generating a multiplexed signal and outputting the multiplexed signal;
A transmission line for transmitting the multiplexed signal output from the interface means;
When the multiplexed signal is received via the transmission line, a system clock used in the communication device is generated in synchronization with a synchronous clock in the multiplexed signal, and audio data in the multiplexed signal is generated in the multiplexed signal. Processing means for processing in synchronization with the synchronous clock. The communication device according to claim 1,
The communication unit is a communication device that generates the multiplexed signal by time-division multiplexing the synchronization clock and the audio data in the network-side signal. The communication device according to claim 1 or 2,
There are N (N is an integer of 2 or more) interface means,
Each of the interface means generates the multiplexed signal by multiplexing type information indicating the type of the digital line that has supplied the network side signal from the digital line network to the digital circuit network in addition to the synchronous clock and the audio data. ,
When the N multiplexing signals are received via the transmission line, the processing means receives a system clock from the synchronization clocks in the N multiplexed signals based on the type information in the N multiplexed signals. A communication apparatus that selects a generation synchronous clock and generates the system clock synchronized with the system clock generation synchronization clock. A network synchronization method in a communication device connected to a digital circuit network,
When a network side signal having a predetermined frequency including voice data is received from the digital circuit network, a synchronization clock synchronized with the network side signal is generated, and the synchronization clock and the voice data in the network side signal are multiplexed and multiplexed. An output step of generating a signal and outputting the multiplexed signal to a transmission line;
When the multiplexed signal is received via the transmission line, a system clock used in the communication device is generated in synchronization with a synchronous clock in the multiplexed signal, and audio data in the multiplexed signal is generated in the multiplexed signal. And a processing step of processing in synchronization with the synchronization clock of the network. The network synchronization method according to claim 4, wherein
In the output step, a network synchronization method for generating the multiplexed signal by time-division multiplexing the synchronization clock and the audio data in the network-side signal.

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