JP2011089025A - One-pack epoxy resin composition and method for production of wafer level chip size packaging semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a one-pack epoxy resin composition excellent in workability, and to provide a method for producing a wafer-level chip size packaging device using the same as an insulation coating film layer. <P>SOLUTION: This invention relates to a one-pack epoxy resin composition comprising (A) a liquid epoxy resin having an ICI viscosity at 25°C of 15 Pa s or lower, (B) a solid aliphatic amine, (C) an inorganic filler of a maximum particle diameter of 75 μm or smaller, and (D) carbon black, wherein component (C) is contained in an amount of 10-80 mass%. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a one-part epoxy resin composition excellent in workability and a method for manufacturing a semiconductor device for a wafer level chip size package having electrodes on a wiring surface using the composition as an insulating coating layer.

In recent years, electronic devices such as mobile phones, mobile computers, and home video cameras, and peripheral components have been increased in capacity, size, and weight. Along with these trends, miniaturization, thinning, weight reduction, and high-density mounting are regarded as important for semiconductor chips used in the electronic devices and the like. 2. Description of the Related Art Conventionally, it is common to provide an electrode on a semiconductor chip, connect the electrode and terminal leads arranged in the peripheral part by wire bonding, and seal (package) with resin.
DIP (Dual In-line Package) and QFP (Quad Flat Package), in which terminal leads are arranged around the package, are the main types of semiconductor packages, but with the recent progress of microfabrication technology, the electrodes of the semiconductor chip itself are becoming narrower. The pitch is advancing, and in such a form, there is a problem in that there is a limit to increasing the size and density of electronic component mounting.
In order to solve these problems, for example, there is a form of a semiconductor package called a ball grid array (BGA), and a large number of electrodes can be arranged two-dimensionally.
Along with this BGA, there is a semiconductor package technology called a wafer level chip size package (hereinafter sometimes abbreviated as “WL-CSP”), which has attracted attention as a technology that can greatly improve the mounting density compared to conventional semiconductor packages. It has become. Recently, since a thinner package is desired for card applications and the like, WL-CSP is also bonded to a glass epoxy resin laminate (FR-4) or the like, and a chip is provided by providing a through electrode on the wafer. A method of laminating is being studied. In general, when the ratio of the depth L to the diameter D of the through hole (L / D) increases, the process of forming the through hole increases the cost, so the wafer is thinned. It was easy to break due to its own strength reduction and warpage, and it was difficult to handle. In order to improve the handling of thin wafers, a method has been proposed in which two upper and lower wafers are bonded together in advance using an adhesive and then diced and separated individually (see, for example, Patent Document 1).

In addition, in order to provide a through electrode on the wafer, a resist layer having an opening is formed so as to expose a device terminal of a circuit formed on the wafer, and this opening is filled with a plating metal by electrolytic plating. The time required for plating takes several hours and the reliability of the electrodes is not sufficient. In order to improve this, it has been proposed to replace the connection terminal with a metal layer formed on the surface of a projection made of an insulator (see, for example, Patent Document 2).
Further, it has been proposed to expose a tip of an electrode after forming a resin layer with a sealing resin on a wafer surface on which a plurality of semiconductor elements provided with protruding electrodes are formed (for example, Patent Documents 3 and 4). See).
However, it has been difficult for any of the methods to obtain a wafer level chip size package having sufficient characteristics such as moisture resistance insulation.

JP 2000-277682 A JP 2001-298120 A JP-A-10-79362 JP 2000-299333 A

  An object of the present invention is to provide a one-part epoxy resin composition for use in a method for manufacturing a semiconductor device for a wafer level chip size package, which can easily form an electrode and has excellent moisture resistance insulation, and a wafer level having the above properties. This is to provide a semiconductor device for a chip size package.

  As a result of intensive studies to achieve the above object, the present inventors have found that an epoxy resin composition having a specific composition can be adapted to the object as a one-part epoxy resin, and a silicon wafer. A ball electrode is formed by wire bonding using a metal wire to the device terminal of the above circuit, and further, an insulating coating film is formed on the upper surface using the one-component epoxy resin composition. It has been found that a semiconductor device for a wafer level chip size package excellent in insulation can be easily obtained, and the present invention has been completed.

That is, the present invention
1. (A) a liquid epoxy resin having an ICI viscosity of 15 Pa · s or less at 25 ° C.,
(B) a solid aliphatic amine,
(C) an inorganic filler having a maximum particle size of 75 μm or less,
as well as,
(D) A one-component epoxy resin composition comprising carbon black and containing 10 to 80% by mass of component (C).
2. (A) A component is 15 Pa. 2. The liquid bisphenol A type epoxy resin of s or less, wherein the component (C) is a combination of spherical silica having an average particle size of 0.3 to 10 μm and fumed silica having a specific surface area of 100 m ² / g or more. One-part epoxy resin composition.
3. After forming a circuit on a silicon wafer, a ball electrode is formed with a metal wire on the pad portion of the device terminal, and a part of the ball electrode is exposed on the upper surface thereof, so that the one-component epoxy described in 1 or 2 above A method of manufacturing a semiconductor device for a wafer level chip size package, wherein an insulating coating layer is formed using a resin composition.
4). Bonding a metal wire having a diameter of 10 to 200 μm to a pad portion of a device terminal on a circuit of a silicon wafer at a temperature of 200 to 400 ° C., an ultrasonic frequency of 50 to 150 kHz, and a time of 10 to 100 ms to form a ball electrode, 3. Manufacturing of a semiconductor device for a wafer level chip size package according to 3 above, wherein an insulating coating layer is formed using the one-component epoxy resin composition according to 1 or 2 so that a part of the ball electrode is exposed on the upper surface thereof. Method.
5). 5. A semiconductor device for a wafer level chip size package manufactured by the manufacturing method according to 3 or 4 above.

  According to the present invention, a ball electrode is formed by wire bonding using a metal wire to a device terminal of a circuit on a silicon wafer, and a one-component epoxy resin composition having a specific composition is used on the upper surface thereof. By forming the insulating coating film, it is possible to easily obtain a semiconductor device for wafer level chip size package having excellent moisture resistance insulation.

It is a cross-sectional schematic diagram which shows an example of the semiconductor device before the dicing obtained by the manufacturing method of the semiconductor device of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device of this invention. It is a cross-sectional schematic diagram which shows the other example of the manufacturing process of the semiconductor device of this invention. It is a schematic perspective view of the silicon wafer in which the ball electrode obtained by the present invention became an external electrode. It is the wiring schematic which shows an example for the electrical conductivity and insulation test of a semiconductor device.

Embodiments of the semiconductor device of the present invention will be described below.
In the manufacturing process of the semiconductor device for wafer level chip size package of the present invention, as shown in the schematic cross-sectional view of FIG. 2, first, a wire bonding apparatus is applied to the pad 2 of the device terminal of the wiring circuit 21 formed on the silicon wafer 1. Using a metal wire having a diameter of about 10 to 200 μm, the diameter and length required by wire bonding under conditions of a temperature of about 200 to 400 ° C., an ultrasonic frequency of about 50 to 150 KHZ, and a time of about 10 to 100 ms. The ball electrode 3 is formed. At this time, in accordance with the thickness of the sealing resin to be sealed later, a so-called two-cardboard or three-cardboard may be used in which the ball is formed again on the ball.
As shown in FIG. 3, the semiconductor device in which the back surface pad 22 and the through electrode 5 are provided on the silicon wafer 1 can also be suitably used for use. A method of providing the back pad 22 and the through electrode 5 can be formed by a known method.

  After the ball electrode 3 is formed by the wire bonding method, the surface is covered with an insulating material. The coating method is a one-part liquid or paste epoxy resin composition, which is applied by dispensing or screen printing so as not to cover the electrode, and the resin is cured, or by using a liquid or paste resin. Or after screen-printing application | coating, the method of making it harden | cure by compression molding etc. are mentioned. With this compression molding method, if the amount of sealing resin is set to an appropriate amount, the electrode is not buried in the resin after compression molding, and the electrode head 31 can be exposed on the coating as an external electrode in one step. FIG. 4 is a schematic perspective view of the semiconductor device (wafer) before dicing obtained by the above method, and shows a state in which a large number of electrode heads 31 are exposed on the film of the silicon wafer 1.

Details of the insulating material that can be suitably used in the above-described method for manufacturing a semiconductor device will be described below.
The one-component epoxy resin composition that is an insulating material comprises (A) component: epoxy resin, (B) component: solid aliphatic amine, (C) component: inorganic filler, and (D) component: carbon black. Must be an essential ingredient.
The epoxy resin of component (A) to be used has an ICI viscosity of 15 Pa · s or less at 25 ° C., and so long as it has two or more epoxy groups in the molecule, liquid epoxy resin, solid epoxy resin, etc. are particularly limited. Can be used without.
Here, the ICI viscosity is a value measured using an ICI cone plate rotational viscometer.
Examples of the epoxy resin include bisphenol A diglycidyl ether, bisphenol F diglycidyl ether, novolac type epoxy resin, diglycidyl ester of polycarboxylic acid, epoxy resin obtained by epoxidation of siloxane derivatives, and the like. Alternatively, two or more kinds can be mixed and used.

In addition to this, a liquid monoepoxy compound, which is a reactive diluent, can be used as a combination component, if necessary. It is also possible to use an epoxy resin.
The solid aliphatic amine (B) preferably has a melting point or softening point of 70 to 150 ° C., specifically, “ADEKA HARDNER EH4070S” (melting point 80 ° C.) manufactured by ADEKA, which is a phenol salt, Examples thereof include “Fujicure FXR-1020” (softening point 120 ° C.) manufactured by Fuji Kasei Co., Ltd., which is a compound having an amide bond. When the melting point or the softening point is low or the liquid aliphatic amine is used, the floor life of the epoxy resin composition (usable time at room temperature) is extremely lowered, and the workability is remarkably deteriorated. Further, if the melting point or softening point is higher than the molding temperature, it does not contribute to the crosslinking reaction, so the molding temperature must be raised. However, if the molding temperature is too high, warping of the wafer after molding increases.

  Component (B) includes amine curing agents such as known dicyandiamide and aromatic diamine, phenol novolak resin, cresol novolak resin, bisphenol A type novolak resin, and triazine-modified phenol novolak resin as long as the object of the present invention is not adversely affected. Phenolic curing agents such as 2-ethyl-4-methylimidazole and 1-benzyl-2-methylimidazole, which are usually used as curing accelerators for epoxy resins, boron trifluoride amine complexes, It can be used in combination with triphenylphosphine or the like. Although this (B) component may be used individually by 1 type and may be used in combination of 2 or more types, the content is from a viewpoint regarding the sclerosis | hardenability of (A) component, and the other performance of hardened | cured material, (A) 5 mass parts or less are preferable with respect to 100 mass parts of component, and 2 mass parts or less are more preferable.

The component (C) is an inorganic filler having a maximum particle size of 75 μm or less. If the component exceeds the maximum particle size of 75 μm, there is a problem that the inorganic filler is exposed. A preferred maximum particle size is 45 μm or less. The particle size can be measured by a wet sieve. As this inorganic filler, fused spherical silica having an average particle diameter of 0.1 to 15 μm, preferably 0.3 to 10 μm, can be preferably used from the viewpoint of filling property and moisture resistance reliability. Specifically, “MSR-06” manufactured by Tatsumori, “SO-25R” manufactured by Admatechs, and the like can be mentioned.
Further, a specific surface area of 100 m ² / g or more, preferably improved sag characteristics capable of preventing a phenomenon that the resin is too flow after coating by combination fumed silica of 200 to 500 m ² / g. The content of the component (C) is 5 to 90% by mass, preferably 10 to 80% by mass, based on the total amount of the composition, from the viewpoint of the viscosity of the resin composition and the curing performance of the cured resin composition. .
Any carbon black (D) can be used as long as it has a small particle size, high coloring power, and low impurity contamination. Content of carbon black (D) is about 0.1-1.0 mass% normally based on the composition whole quantity, Preferably it is 0.2-0.8 mass%.

  When the resin composition is used in the form of a paste or liquid, the viscosity and thixotropy are appropriately adjusted depending on the coatability, spreadability, and film thickness. In the semiconductor device for wafer level chip size package of the present invention, an electronic component having double-sided electrodes is formed by forming external electrodes with the above-described ball electrodes of wire bonding and sealing them with an insulating material after forming through electrodes. Can also be obtained.

EXAMPLES Next, although an Example demonstrates this invention further more concretely, this invention is not limited at all by these examples.
The ICI viscosity at 25 ° C. of the liquid epoxy resin used in each example is a value measured using an ICI cone plate rotational viscometer [manufactured by Toki Sangyo Co., Ltd., model name “TV-22”].
[Example 1]
Prepare a test chip wafer (Phase 0: manufactured by Well Co., Ltd.) with a diameter of 6 inches and use a gold wire with a diameter of 50 μm using a Shinkawa bonder (SWB-FA-UTAC) at a temperature exceeding 380 ° C. Wire bonding was performed on the pad portion of the device terminal at a sound wave frequency of 60 kHz and a time of 50 ms to form a ball electrode having a height of 0.2 mm.
Next, a paste-like resin was manufactured at the composition ratio described in the sealing resin 1 of Table 1, and the resin composition for screen printing application was applied to the wafer with the electrode manufactured previously so that the film thickness was 200 μm. A 150 μm spacer was used on the circuit surface side, and a release film assisted compression molding was performed at 10 MPa and 150 ° C. for 10 minutes to form an insulating coating layer having a thickness of 150 μm. At this time, the 0.2 mm-high electrodes were crushed by compression molding, but as a result of examining the conduction state of each electrode on the surface of the insulating coating layer with the measuring instrument shown in FIG. 5, conduction was confirmed. . FIG. 5 shows an example of a measuring apparatus. As shown in the figure, the resin-sealed surfaces face each other and the heads of the ball electrodes are brought into contact with each other, and the connection wiring 6 and the measuring instrument (resistance) 7 are used. A circuit was formed to confirm the conduction state, and the insulation state of the insulating coating layer could be confirmed.
In addition, the content of the material used for the compounding composition shown in Table 1 is as follows.

Contents of materials used:
・ Bisphenol A type epoxy resin (25 ° C ICI viscosity 14Pa · s) …… "Epomic R-140" manufactured by Mitsui Chemicals, Inc.
・ Bisphenol A type epoxy resin (25 ℃ ICI viscosity 20Pa ・ s) …… “Epototo YD-128S” manufactured by Tohto Kasei Co., Ltd.
Aliphatic solid amine (SP120 ° C.): “Fujicure FXR-1020” manufactured by Fuji Kasei Co., Ltd.
・ Aliphatic solid amine (MP80 ° C): "ADEKA HARDNER EH4070S" manufactured by ADEKA
・ Aromatic solid amine (SP100 ° C): "TH-1000" manufactured by Tohto Kasei Co., Ltd.
・ Deformed aliphatic liquid amine: DIC's “Rakkamide WN-105”
・ Dicyandiamide: “DICY7” manufactured by Japan Epoxy Resin Co., Ltd.
・ Latent imidazole (containing 37% by mass of imidazole): “LH210” manufactured by Sanwa Chemical Co., Ltd.
・ Fine spherical silica powder (average particle size 7μm) …… “MSR-06” manufactured by Tatsumori
・ Fine spherical silica powder (average particle size 0.5 μm) …… “SO-25R” manufactured by Admatechs
・ Synthetic fumed silica powder (specific surface area 380 m ² / g) …… “Aerosil 380” manufactured by Nippon Aerosil Co., Ltd.
・ Carbon black …… Mitsubishi Chemical Corporation “Mitsubishi Carbon Black MA100”
・ Γ-Phenylaminopropyltrimethoxysilane …… “KBM-573” manufactured by Shin-Etsu Chemical Co., Ltd.

[Example 2]
The wire material was changed to an aluminum wire having a diameter of 100 μm, and a resin-encapsulated wafer having an insulating coating layer having a thickness of 400 μm and the sealing resin 1 shown in Table 1 was produced in the same manner as in Example 1. As a result of examining the conduction state of the electrode with a measuring instrument, conduction was confirmed.

[Example 3]
The wire material was changed to a copper wire having a diameter of 50 μm, and a resin-encapsulated wafer having an insulating coating layer having a thickness of 200 μm and the sealing resin 1 shown in Table 1 was produced in the same manner as in Example 1. As a result of examining the conduction state of the electrode with a measuring instrument, conduction was confirmed.

[Example 4]
A 6-inch diameter penetrating electrode test chip wafer (gold bump processing: manufactured by Well Co., Ltd.) was prepared, and a sealing resin 1 shown in Table 1 was used in the same manner as in Example 1 using a gold wire with a diameter of 25 μm. Was used to prepare a resin-encapsulated wafer having an insulating coating layer having a thickness of 100 μm and laminated to produce a stack package.
As a result of examining the conduction state of the electrode with a measuring instrument, conduction was confirmed. In addition, the evaluation of moisture resistance insulation (the time until the surface resistance value when applied with 500 V under an atmosphere of 85 ° C. and 85% RH is 1.0 × 10 ⁷ Ω / □ or less) was as good as 42 hours. It was.

[Example 5]
A stack package was produced in the same manner as in Example 4 except that the sealing resin 2 shown in Table 1 was used. As a result of examining the conduction state of the electrode with a measuring instrument, conduction was confirmed. Moreover, evaluation of moisture-proof insulation was as favorable as 40 hours.

[Comparative Example 1]
A stack package was produced in the same manner as in Example 4 except that the sealing resin 3 shown in Table 1 was used. As a result of examining the conduction state of the electrode with a measuring instrument, conduction was confirmed. However, the evaluation of moisture resistance insulation was poor at 5 hours.

[Comparative Example 2]
A stack package was produced in the same manner as in Example 4 except that the sealing resin 4 shown in Table 1 was used. However, since the fluidity of the material is remarkably poor, a blur occurs during screen printing, and the sealing cannot be completed completely.

[Comparative Example 3]
A stack package was produced in the same manner as in Example 4 except that the sealing resin 5 shown in Table 1 was used. However, the floor life was extremely short, and scumming was generated during screen printing, so that the sealing could not be completed completely.

[Comparative Example 4]
A stack package was produced in the same manner as in Example 4 except that the sealing resin 6 shown in Table 1 was used. However, the floor life was extremely short, and scumming was generated during screen printing, so that the sealing could not be completed completely.

DESCRIPTION OF SYMBOLS 1 ... Silicon wafer 2 ... Pad 21 ... Wiring circuit 3 ... Ball electrode 31 ... Electrode head 4 ... Insulating coating layer 5 ... Through electrode 6 ... Connection wiring 7 ... Measuring instrument

Claims (5)

(A) a liquid epoxy resin having an ICI viscosity of 15 Pa · s or less at 25 ° C.,
(B) a solid aliphatic amine,
(C) an inorganic filler having a maximum particle size of 75 μm or less,
as well as,
(D) A one-component epoxy resin composition comprising carbon black and containing 10 to 80% by mass of component (C). The component (A) is a liquid bisphenol A type epoxy resin having a viscosity of 15 Pa · s or less, and the component (C) is spherical silica having an average particle size of 0.3 to 10 μm and fumed silica having a specific surface area of 100 m ² / g or more. The one-component epoxy resin composition according to claim 1.   3. The one-component type according to claim 1 or 2, wherein after forming a circuit on the silicon wafer, a ball electrode is formed with a metal wire on a pad portion of the device terminal, and a part of the ball electrode is exposed on the upper surface thereof. A method of manufacturing a semiconductor device for a wafer level chip size package, comprising forming an insulating coating layer using an epoxy resin composition.   Bonding a metal wire having a diameter of 10 to 200 μm to a pad portion of a device terminal on a circuit of a silicon wafer at a temperature of 200 to 400 ° C., an ultrasonic frequency of 50 to 150 kHz, and a time of 10 to 100 ms to form a ball electrode, 4. The semiconductor device for a wafer level chip size package according to claim 3, wherein an insulating coating layer is formed using the one-component epoxy resin composition according to claim 1 or 2 so that a part of the ball electrode is exposed on the upper surface thereof. Manufacturing method.   A semiconductor device for a wafer level chip size package manufactured by the manufacturing method according to claim 3 or 4.

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