JP2011082380A - Thin-film transistor and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor whose off current and leakage current are suppressed, and a method of manufacturing the thin-film transistor in which the thin-film transistor can be manufactured in good yield. <P>SOLUTION: A metal film is formed on an Si(i) film 13 and an Si(n) film 14 formed successively on a gate electrode 12 via a gate insulating film 12, and etched using a photoresist pattern 22 as a mask to form a source electrode 15 and a drain electrode 16. Through processing using plasma containing oxygen, a side face of the photoresist pattern 22 is set back and an Al oxide coating 17 is formed on side faces and exposed upper surfaces of the source electrode 15 and the drain electrode 16. Parts of surfaces of the Si(n) film 14 and Si(i) film 13 of a channel part 18 are etched using the remaining photoresist pattern 22 and the Al oxide coating 17 as a mask. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a thin film transistor used for a liquid crystal display or the like and a manufacturing method thereof, and more particularly to a bottom gate thin film transistor having a single layer film of an aluminum alloy as a source electrode and a drain electrode and a manufacturing method thereof.

  A thin film transistor (abbreviation: TFT) used for a liquid crystal display is required to be reduced in cost, and therefore, the process needs to be simplified. For example, Patent Document 1 discloses a method for manufacturing an electro-optic element in which a bottom-gate thin film transistor in which a back channel is formed by etching is manufactured in five photolithography processes. “Back channel” refers to an exposed portion sandwiched between a source electrode and a drain electrode in a channel portion.

  In the electro-optical element manufacturing method disclosed in Patent Document 1, wet etching of the source electrode and drain electrode and dry etching of the underlying n-type silicon layer are performed using the photoresist pattern of the third photolithography process as a mask. Back channel etching is continuously performed to form a channel portion. However, when wet etching of the source electrode and drain electrode and back channel etching by dry etching are continuously performed, the n-type silicon layer is in the direction of carrier movement in the channel portion from the source electrode end and the drain electrode end. The shape extends in the channel direction. In other words, the n-type silicon layer has a shape protruding to the inside of the channel portion from the source electrode end and the drain electrode end.

  Thus, when the n-type silicon layer has a shape projecting inward of the channel portion from the source electrode end and the drain electrode end, the electric field concentrates on the electrode end portion, and the off-current in the high voltage region increases. When such a TFT is used as a switching element of a pixel of a liquid crystal display, there is a problem that charge retention characteristics are lowered, and contrast and crosstalk, which are important elements in display quality, are increased.

  As a technique for reducing the off-state current in the thin film transistor, for example, Patent Document 2 discloses that the edge portions on the channel side of the source electrode and the drain electrode are extended inward to form a ridge on the channel. As a method for forming this ridge, in Patent Document 2, after forming a source electrode and a drain electrode by anisotropic etching, a photoresist for patterning formed thereon is removed, and a back channel etching process is performed. Discloses a method for manufacturing a TFT array substrate in which the n-type silicon layer above the channel is removed by isotropic etching using the pattern of the source and drain electrodes as a direct mask.

  Further, for example, Patent Document 3 discloses a technique for obtaining a thin film transistor having excellent characteristics and reliability with respect to off-state current. In the method of manufacturing a thin film transistor disclosed in Patent Document 3, an impurity-containing amorphous film is formed after a source electrode and a drain electrode are formed by etching and before dry-etching an impurity-containing amorphous silicon layer that is an n-type silicon layer. A thin film transistor is fabricated by exposing the surface of the porous silicon layer to oxygen-containing plasma.

  In a conventional bottom gate thin film transistor, a wiring having a multilayer structure made of a low resistance material such as aluminum (Al) and a high melting point material such as chromium (Cr) is used for the source electrode and the drain electrode. In order to reduce the cost, a structure in which the source electrode and the drain electrode are formed of a single layer film of an Al alloy material has been adopted.

Japanese Patent Laid-Open No. 10-268353 Japanese Patent Laid-Open No. 11-154752 JP 2003-68755 A

  When an Al alloy material is used for the source electrode and the drain electrode, if the back channel etching is performed after removing the photoresist for patterning the source electrode and the drain electrode, the Al alloy material is used in the photoresist removal process and the subsequent cleaning process. Is eluted in the channel portion, becomes an etching inhibition layer, causes back channel etching failure, and decreases the yield. In addition, due to residual gas components after dry etching of the back channel, a deteriorated layer is generated on the surface of the Al alloy, and the reflectance between the contact with the pixel electrode formed on the upper portion and the portion that becomes the semi-transmissive electrode is lowered. There are problems such as.

  Further, when an Al alloy material is used for the source electrode and the drain electrode, if the photoresist is peeled off and washed with water after the back channel etching, there is a problem that an Al electrolyte or the like tends to adhere to the back channel etched surface. When the electrolyte adheres to the side walls of the source electrode and the drain electrode facing the back channel portion, current flows through the surface of the back channel via the electrolyte deposit, which causes an increase in leakage current when the transistor is off. In addition, problems such as a reduction in display quality due to a decrease in contrast and an increase in crosstalk are caused.

  In addition, when an Al alloy material is used for the source and drain electrodes, protrusions called hillocks are likely to occur. There is a problem that it is likely to occur. When a hillock occurs on the wiring side wall in the back channel portion, the hillock and the i-type silicon layer under the n-type silicon layer come into contact with each other, causing a problem that the leakage current of the transistor increases.

  An object of the present invention is to provide a thin film transistor in which off current and leakage current are suppressed, and a thin film transistor manufacturing method capable of manufacturing the thin film transistor with high yield.

  A thin film transistor of the present invention includes a gate electrode provided on an insulating substrate, a gate insulating film provided on the insulating substrate so as to cover the gate electrode, and a channel portion formed on the gate insulating film. An intrinsic silicon film, a conductive silicon film provided on the intrinsic silicon film and separated by the channel portion, and a source electrode and a drain electrode provided on the conductive silicon film and separated by the channel portion And an end portion of the source electrode and the drain electrode on the channel portion side is covered with an oxide film, and an end portion of the conductive silicon film on the channel portion side is formed of the source electrode and the drain electrode. It is formed on substantially the same plane as the end portion on the channel portion side.

  The method of manufacturing a thin film transistor of the present invention includes a step of forming a gate electrode on an insulating substrate, and a gate insulating film, an intrinsic silicon film, and a conductive silicon film on the surface of the insulating substrate on which the gate electrode is formed. And forming a photoresist pattern on the conductive silicon film, and etching the intrinsic silicon film and the conductive silicon film using the formed photoresist pattern as a mask to pattern the island pattern. A step of forming a metal film on the conductive silicon film patterned in an island shape, forming a photoresist pattern on the metal film, and etching the metal film using the formed photoresist pattern as a mask. Forming a source electrode and a drain electrode, the photoresist pattern, By treating the source electrode and the drain electrode with a plasma containing oxygen, the side surface of the photoresist pattern is retreated, and the side surface of the source electrode and the drain electrode is exposed by retreating the photoresist pattern. Etching at least the conductive silicon film at a portion to be a channel portion between the source electrode and the drain electrode, using the remaining photoresist pattern and the oxide film as a mask, forming an oxide film on the upper surface And a step of removing the remaining photoresist pattern.

  The thin film transistor manufacturing method of the present invention includes a step of forming a gate electrode on an insulating substrate, and a gate insulating film, an intrinsic silicon film, and conductive silicon on the surface of the insulating substrate on which the gate electrode is formed. A step of sequentially forming a film, a photoresist pattern is formed on the conductive silicon film, and the intrinsic silicon film and the conductive silicon film are etched using the formed photoresist pattern as a mask to pattern into an island shape. A step of forming a metal film on the island-patterned conductive silicon film, and forming a photoresist pattern on the metal film, and etching the metal film using the formed photoresist pattern as a mask. A step of forming a source electrode and a drain electrode, and the photoresist pattern, The step of removing the photoresist pattern by treating the source electrode and the drain electrode with plasma containing oxygen, and forming an oxide film over the entire surface of the source electrode and the drain electrode, and the oxide film Using as a mask, etching a conductive silicon film at least in a portion to be a channel portion between the source electrode and the drain electrode, forming a protective film on the oxide film, and forming on the protective film Forming a contact hole serving as a contact portion with the upper electrode so as to penetrate at least one of the source electrode and the drain electrode through the protective film and the oxide film. .

  The thin film transistor manufacturing method of the present invention includes a step of forming a gate electrode on an insulating substrate, and a gate insulating film, an intrinsic silicon film, and conductive silicon on the surface of the insulating substrate on which the gate electrode is formed. A step of sequentially forming a film and a metal film, and forming a photoresist pattern having portions with different thicknesses on the metal film, and using the formed photoresist pattern as a mask, the intrinsic silicon film and the conductive silicon film Etching the metal film and patterning the island pattern; treating the photoresist pattern with oxygen-containing plasma to recede the side of the photoresist pattern; and remaining photoresist The metal film is etched using the pattern as a mask to form a source electrode and a drain electrode And forming the remaining photoresist pattern, the source electrode, and the drain electrode with a plasma containing oxygen to recede the side surface of the photoresist pattern, and forming the source electrode and the drain electrode. A step of forming an oxide film on a side surface and an upper surface exposed by the receding of the photoresist pattern; and a channel portion between the source electrode and the drain electrode using the remaining photoresist pattern and the oxide film as a mask; And a step of etching at least the conductive silicon film in the portion to be formed, and a step of removing the remaining photoresist pattern.

  The thin film transistor manufacturing method of the present invention includes a step of forming a gate electrode on an insulating substrate, and a gate insulating film, an intrinsic silicon film, and conductive silicon on the surface of the insulating substrate on which the gate electrode is formed. A step of sequentially forming a film and a metal film, and forming a photoresist pattern having portions with different thicknesses on the metal film, and using the formed photoresist pattern as a mask, the intrinsic silicon film and the conductive silicon film Etching the metal film and patterning the island pattern; treating the photoresist pattern with oxygen-containing plasma to recede the side of the photoresist pattern; and remaining photoresist The metal film is etched using the pattern as a mask to form a source electrode and a drain electrode And forming the remaining photoresist pattern, the source electrode, and the drain electrode with a plasma containing oxygen to remove the photoresist pattern, and the entire surface of the source electrode and the drain electrode. A step of forming an oxide film, a step of etching at least a conductive silicon film in a channel portion between the source electrode and the drain electrode using the oxide film as a mask, and a protection on the oxide film A contact hole to be a contact portion between the step of forming a film and the upper electrode formed on the protective film, penetrating through the protective film and the oxide film, to at least one of the source electrode and the drain electrode And a step of forming it so as to reach.

  According to the thin film transistor of the present invention, the end portions of the source electrode and the drain electrode on the channel portion side are covered with the oxide film, and the source electrode and the drain electrode on the channel portion side end are substantially flush with the conductive layer. An end portion on the channel portion side of the conductive silicon film is formed. That is, the end of the conductive silicon film on the channel part side does not substantially protrude inside the channel part from the end part of the source and drain electrodes on the channel part side. Accordingly, concentration of the electric field at the end of the source electrode and the drain electrode on the channel portion side can be reduced, so that generation of a tunnel current when the thin film transistor is off can be prevented and off current can be reduced. it can.

  In addition, since the end portions on the channel portion side of the source electrode and the drain electrode are covered with the oxide film, generation of hillocks on the end portion side surfaces of the source electrode and the drain electrode on the channel portion side can be prevented. As a result, contact between the hillock and the intrinsic silicon film can be prevented, so that leakage current can be prevented. Accordingly, a thin film transistor in which off current and leakage current are suppressed can be realized.

  According to the method for manufacturing a thin film transistor of the present invention, the metal film on the conductive silicon film is etched using the photoresist pattern as a mask to form a source electrode and a drain electrode. The source electrode, the drain electrode, and the photoresist pattern are treated with plasma containing oxygen, and the side surface of the photoresist pattern recedes, and an oxide film is formed on the side surface and the exposed upper surface of the source electrode and the drain electrode. Then, using the remaining photoresist pattern and oxide film as a mask, at least the conductive silicon film in the portion to become the channel portion is etched.

  Thus, the end of the conductive silicon film on the channel part side can be formed on substantially the same plane as the end part of the source electrode and drain electrode on the channel part side. Accordingly, concentration of the electric field at the end of the source electrode and the drain electrode on the channel portion side can be reduced, so that generation of a tunnel current when the thin film transistor is off can be prevented and off current can be reduced. .

  In addition, since the end portions of the source and drain electrodes on the channel portion side are covered with an oxide film, the metal film material generated in the subsequent steps of etching the conductive silicon film and removing the photoresist pattern, etc. Elution can be prevented. As a result, the metal contamination on the back channel surface of the channel portion caused by the eluted metal solution and the off current flowing through the back channel interface resulting therefrom can be reduced, and the off current can be greatly reduced. Further, as described above, a thin film transistor in which off current and leakage current are suppressed can be manufactured with high yield.

  Further, according to the method of manufacturing a thin film transistor of the present invention, the metal film on the conductive silicon film is etched using the photoresist pattern as a mask to form a source electrode and a drain electrode. The source electrode, the drain electrode, and the photoresist pattern are treated with plasma containing oxygen to remove the photoresist pattern, and an oxide film is formed over the entire surface of the source electrode and the drain electrode. Using this oxide film as a mask, at least the conductive silicon film in the portion to become the channel portion is etched.

  Thus, the end of the conductive silicon film on the channel part side can be formed on substantially the same plane as the end part of the source electrode and drain electrode on the channel part side. Accordingly, concentration of the electric field at the end of the source electrode and the drain electrode on the channel portion side can be reduced, so that generation of a tunnel current when the thin film transistor is off can be prevented and off current can be reduced. .

  Moreover, since the surfaces of the source electrode and the drain electrode are covered with an oxide film, it is possible to prevent the elution of the metal film material generated in the subsequent step of etching the conductive silicon film and the step of removing the photoresist pattern. Can do. As a result, the metal contamination on the back channel surface of the channel portion caused by the eluted metal solution and the off current flowing through the back channel interface resulting therefrom can be reduced, and the off current can be greatly reduced. Further, as described above, a thin film transistor in which off current and leakage current are suppressed can be manufactured with high yield.

  In addition, a protective film is formed on the oxide film, and a contact hole that penetrates the protective film and the oxide film and reaches at least one of the source electrode and the drain electrode is formed. Connection failure between the electrode and at least one of the source electrode and the drain electrode can be prevented.

  In addition, according to the method of manufacturing a thin film transistor of the present invention, an intrinsic silicon film, a conductive silicon film, and a metal film are patterned in an island shape using a photoresist pattern having portions with different thicknesses as a mask, and then a plasma containing oxygen. The metal film is etched using the photoresist pattern whose side surface is receded as a mask, to form a source electrode and a drain electrode. Next, after processing with oxygen-containing plasma, the side surface of the photoresist pattern recedes and an oxide film is formed on the side surface and the exposed top surface of the source and drain electrodes, and then the remaining photoresist pattern and oxide film are masked. As a result, at least the conductive silicon film in the portion to become the channel portion is etched.

  Thus, the end of the conductive silicon film on the channel part side can be formed on substantially the same plane as the end part of the source electrode and drain electrode on the channel part side. Accordingly, concentration of the electric field at the end of the source electrode and the drain electrode on the channel portion side can be reduced, so that generation of a tunnel current when the thin film transistor is off can be prevented and off current can be reduced. .

  In addition, since the end portions of the source and drain electrodes on the channel portion side are covered with an oxide film, the metal film material generated in the subsequent steps of etching the conductive silicon film and removing the photoresist pattern, etc. Elution can be prevented. As a result, the metal contamination on the back channel surface of the channel portion caused by the eluted metal solution and the off current flowing through the back channel interface resulting therefrom can be reduced, and the off current can be greatly reduced. Further, as described above, a thin film transistor in which off current and leakage current are suppressed can be manufactured with high yield.

  The island patterning of the intrinsic silicon film, the conductive silicon film and the metal film and the etching of the metal film for forming the source electrode and the drain electrode are performed using one photoresist pattern having portions having different film thicknesses. Since it is performed, the photolithography process can be omitted once. As a result, an improvement in production capacity and a reduction in cost can be realized.

  In addition, according to the method of manufacturing a thin film transistor of the present invention, an intrinsic silicon film, a conductive silicon film, and a metal film are patterned in an island shape using a photoresist pattern having portions with different thicknesses as a mask, and then a plasma containing oxygen. The metal film is etched using the photoresist pattern whose side surface is receded as a mask, to form a source electrode and a drain electrode. Next, the photoresist pattern is removed by treatment with oxygen-containing plasma, and an oxide film is formed over the entire surface of the source electrode and the drain electrode. Using this oxide film as a mask, at least the conductive silicon film in the portion to become the channel portion is etched.

  Thus, the end of the conductive silicon film on the channel part side can be formed on substantially the same plane as the end part of the source electrode and drain electrode on the channel part side. Accordingly, concentration of the electric field at the end of the source electrode and the drain electrode on the channel portion side can be reduced, so that generation of a tunnel current when the thin film transistor is off can be prevented and off current can be reduced. .

  Moreover, since the surfaces of the source electrode and the drain electrode are covered with an oxide film, it is possible to prevent the elution of the metal film material generated in the subsequent step of etching the conductive silicon film and the step of removing the photoresist pattern. Can do. As a result, the metal contamination on the back channel surface of the channel portion caused by the eluted metal solution and the off current flowing through the back channel interface resulting therefrom can be reduced, and the off current can be greatly reduced. Further, as described above, a thin film transistor in which off current and leakage current are suppressed can be manufactured with high yield.

  The island patterning of the intrinsic silicon film, the conductive silicon film and the metal film and the etching of the metal film for forming the source electrode and the drain electrode are performed using one photoresist pattern having portions having different film thicknesses. Since it is performed, the photolithography process can be omitted once. As a result, an improvement in production capacity and a reduction in cost can be realized.

  In addition, a protective film is formed on the oxide film, and a contact hole that penetrates the protective film and the oxide film and reaches at least one of the source electrode and the drain electrode is formed. Connection failure between the electrode and at least one of the source electrode and the drain electrode can be prevented.

It is sectional drawing which shows the pixel main part of the TFT substrate 100 for liquid crystal display devices provided with TFT1 which is the 1st Embodiment of this invention. It is sectional drawing which shows the state of the stage which the formation of the gate electrode 11 was complete | finished. It is sectional drawing which shows the state in the stage where formation of the gate insulating film 19, Si (i) film | membrane 13, and Si (n) film | membrane 14 was complete | finished. It is sectional drawing which shows the state in the stage where formation of the source electrode 15 and the drain electrode 16 was complete | finished. It is sectional drawing which shows the state of the stage where formation of Al oxide film 17 was complete | finished. It is sectional drawing which shows the state of the stage which the formation of the channel part 18 was complete | finished. It is sectional drawing which shows the state of the stage which the removal of the photoresist pattern 22 was complete | finished. FIG. 6 is a cross-sectional view showing a state in which the formation of the pixel drain contact hole 20 is completed. FIG. 6 is a cross-sectional view showing a state at a stage where the formation of the pixel electrode 21 is completed. FIG. 6 is a cross-sectional view showing a state at a stage where the formation of the second metal film 23 is completed. It is sectional drawing which shows the state in the stage where formation of the photoresist pattern 24 was complete | finished. 6 is a cross-sectional view showing a state where a surface of a second metal film 23 is exposed. FIG. It is sectional drawing which shows the state of the stage which completed formation of the pattern of the source electrode 15 and the drain electrode 16. FIG. It is sectional drawing which shows the state of the stage where formation of Al oxide film 17 was complete | finished. It is sectional drawing which shows the state of the stage which the formation of the channel part 18 was complete | finished. It is sectional drawing which shows the state of the stage which the removal of the photoresist pattern 24 was complete | finished. It is sectional drawing which shows the state of the stage which manufacture of TFT substrate 100A was complete | finished. It is a figure which shows distribution of the hole current density in the thin-film transistor of this invention. It is a figure which shows distribution of the hole current density in the thin-film transistor of a prior art.

<First Embodiment>
FIG. 1 is a cross-sectional view showing a main part of a pixel of a TFT substrate 100 for a liquid crystal display device including the TFT 1 according to the first embodiment of the present invention. The TFT substrate 100 includes a transparent insulating substrate 10, a gate electrode 11, a gate insulating film 12, an i-type silicon (Si (i)) film 13, an n-type silicon (Si (n)) film 14, a source electrode 15, and a drain electrode. 16, a plasma oxide film 17, a protective insulating film 19, and a pixel electrode 21. The gate electrode 11, the gate insulating film 12, the Si (i) thin film 13, the Si (n) thin film 14, the source electrode 15, the drain electrode 16, the plasma oxide film 17, and the protective insulating film 19 are formed of TFT 1 that is an inverted staggered TFT. Constitute. The TFT 1 and the pixel electrode 21 are provided on one side in the thickness direction of the transparent insulating substrate 10.

  The transparent insulating substrate 10 is realized by a glass substrate, for example. The Si (i) film 13 and the Si (n) film 14 are realized by, for example, a single layer film of amorphous silicon or microcrystalline silicon, or a multilayer film of amorphous silicon and microcrystalline silicon. In the present embodiment, the Si (i) film 13 is realized by an i-type amorphous silicon thin film, specifically, a single-layer film of i-type amorphous silicon. The Si (n) film 14 is realized by an n-type amorphous silicon thin film, specifically, a single-layer film of n-type amorphous silicon. In the present embodiment, the Si (i) film 13 may be referred to as an i-type amorphous silicon thin film, and the Si (n) film 14 may be referred to as an n-type amorphous silicon thin film. The Si (i) film 13 corresponds to an intrinsic silicon film, and the Si (n) film 14 corresponds to a conductive silicon film.

  In this embodiment, the source electrode 15 and the drain electrode 16 are made of an aluminum (Al) -based metal film, specifically, an Al alloy single layer film. The plasma oxide film 17 is the aluminum oxide film 17 in the present embodiment, and is formed by oxidizing the Al-based metal film that becomes the source electrode 15 and the drain electrode 16. In the present embodiment, the plasma oxide film 17 may be referred to as an aluminum oxide film 17. The channel portion 18 of the TFT 1 is sandwiched between the source electrode 15 and the drain electrode 16, and a part of the surface of the Si (n) film 14 and the Si (i) film 13 is dug to form a recess. Is done. The Si (i) film 13 may not be dug.

  The ends of the Si (n) film 14 and the Si (i) film 13 on the channel portion 18 side are formed on substantially the same plane as the ends of the source electrode 15 and the drain electrode 16 on the channel portion 18 side. More specifically, the side surfaces of the source electrode 15 and the drain electrode 16 that face each other across the channel portion 18 are substantially the same as the side surfaces of the underlying Si (n) film 14 and Si (i) film 13 that are dug. It is formed on a plane. In FIG. 1, the ends of the Si (n) film 14 and the Si (i) film 13 on the channel part 18 side are equal to the film thickness of the aluminum oxide film 17 formed on the side surfaces of the source electrode 15 and the drain electrode 16. The source electrode 15 and the drain electrode 16 appear to protrude to the inside of the channel portion 18 from the ends on the channel portion 18 side. Actually, the film thickness of the aluminum oxide film 17 is as small as 0.1 μm or less. Therefore, the ends of the Si (n) film 14 and the Si (i) film 13 on the channel part 18 side, the source electrode 15, and the drain electrode 16. The end portion on the channel portion 18 side is located on substantially the same plane.

  In other words, the ends of the Si (n) film 14 and the Si (i) film 13 on the channel part 18 side are more inside the channel part 18 than the ends of the source electrode 15 and the drain electrode 16 on the channel part 18 side. Almost does not protrude. Specifically, at least the end portion of the Si (n) film 14 on the channel portion 18 side has an amount of protrusion to the inside of the channel portion 18 from the end portions on the channel portion 18 side of the source electrode 15 and the drain electrode 16, It is 0.1 μm or less. In the present embodiment, since the Si (i) film 13 is also dug in the same manner as the Si (n) film 14 to form the channel portion 18, the end of the Si (i) film 13 on the channel portion 18 side. In the portion, the amount of protrusion of the source electrode 15 and the drain electrode 16 from the ends on the channel portion 18 side toward the inside of the channel portion 18 is 0.1 μm or less.

  The protective insulating film 19 is formed on the entire TFT substrate 100 while protecting the channel portion 18. A pixel drain contact hole 20 is formed in the protective insulating film 19. The pixel drain contact hole 20 is formed through the protective insulating film 19 to the surface of the drain electrode 16 formed under the protective insulating film 19. The pixel electrode 21 is electrically connected to the drain electrode 16 formed below the protective insulating film 19 through the pixel drain contact hole 20. The pixel electrode 21 is composed of a transparent conductive film.

  Next, a method for manufacturing the TFT substrate 100 in the present embodiment will be described. In the manufacturing method of the TFT substrate 100 in the present embodiment, the TFT substrate 100 is manufactured using the manufacturing method of the TFT of the present invention. 2 to 9, as in FIG. 1, a portion corresponding to the main pixel portion of the TFT substrate 100 is shown. 2 to 9 are diagrams for explaining each step of the manufacturing method of the TFT substrate 100 according to the first embodiment of the present invention.

  FIG. 2 is a cross-sectional view showing a state where the formation of the gate electrode 11 is completed. First, after the transparent insulating substrate 10 such as a glass substrate is cleaned using a cleaning liquid or pure water, a first metal film that becomes the gate electrode 11 is formed on the surface of the transparent insulating substrate 10 on one side in the thickness direction. Film. As the material of the first metal film, for example, chromium (Cr), molybdenum (Mo), titanium (Ti), aluminum (Al), or an alloy obtained by adding a small amount of other substances to these metals is used. Of these, it is preferable to use Al-based metals such as Al and Al alloys. Since the Al-based metal has a lower specific resistance value than other metals such as Cr, Mo, and Ti, the wiring resistance can be lowered by using the Al-based metal. Therefore, Al-based metal is preferable for the use of the TFT substrate 100 for liquid crystal display devices.

  When an Al-based metal is used as the material of the first metal film, a projection called hillock that causes a pattern defect and a decrease in yield occurs on the upper surface of the wiring, that is, the surface on one side in the thickness direction of the first metal film. In order to prevent this, it is preferable to use an Al alloy obtained by adding another substance to Al. Other substances added to Al (hereinafter sometimes referred to as “additive elements”) include Group 8 transition elements such as iron (Fe), cobalt (Co) and nickel (Ni), and lanthanum (La), And rare earth elements such as neodymium (Nd), samarium (Sm), and gadolinium (Gd). The composition range of these additive elements is preferably atomic percentage (at%) and not less than 0.2 at% and not more than 6 at% of the entire Al alloy. If the composition range of the additive element is less than 0.2 at%, the effect of preventing the generation of hillocks on the upper surface of the wiring is insufficient, and if the composition range of the additive element exceeds 6 at%, the specific resistance value increases and Cr increases. This is because the superiority of low resistance to Mo and Ti is reduced.

  Specifically, as the first metal film, for example, an Al-3 at% Ni alloy film to which 3 at% Ni is added is formed to a thickness of 200 nm by sputtering using a known argon (Ar) gas. The film is formed.

  After forming the first metal film in this way, a photoresist pattern is formed on the first metal film in the first photolithography process. Using this photoresist pattern as a mask, the first metal film is wet-etched with a known etching solution, for example, a solution containing phosphoric acid, nitric acid and acetic acid, and then the photoresist pattern is removed to form gate electrode 11.

  FIG. 3 is a cross-sectional view showing a state where the formation of the gate insulating film 19, the Si (i) film 13, and the Si (n) film 14 has been completed. After the gate electrode 11 is formed as described above, the gate insulating film 12, the Si (i) film 13, and the Si (n) film 14 are formed on the surface of the gate electrode 11 and the transparent insulating substrate 10 on one side in the thickness direction. Films are sequentially formed. The Si (i) film 13 is an intrinsic semiconductor film made of i-type silicon Si (i) to which no impurity is added, and functions as a semiconductor active film serving as a channel. The Si (n) film 14 is an n-type semiconductor film made of n-type silicon Si (n) to which impurities are added. The Si (n) film 14 is in ohmic contact with the Si (i) film 13 and the source electrode 15 and drain electrode 16 in ohmic contact. It functions as a resistance film (hereinafter sometimes referred to as “ohmic contact film”).

  Specifically, for example, a silicon nitride (SiN) film, Si (Si) is used as the gate insulating film 12 under a substrate heating condition of about 300 ° C. using a chemical vapor deposition (abbreviation: CVD) method. i) A microcrystalline Si (i) film as a film 13 and a microcrystalline Si (n) film doped with phosphorus (P) as an impurity are sequentially formed as a film 13. Regarding the film thickness, for example, the film thickness of the gate insulating film 12 is 400 nm, the film thickness of the Si (i) film 13 is 150 nm, and the film thickness of the Si (n) film 14 is 50 nm.

  After the gate insulating film 12, the Si (i) film 13, and the Si (n) film 14 are thus formed, a photoresist pattern is formed on the surface of the Si (n) film 14 in the second photolithography process. . Using this photoresist pattern as a mask, the Si (i) film 13 and the Si (n) film 14 are etched and patterned in an island shape, for example, by dry etching using a known etching gas, for example, a fluorine-based gas. Thereafter, the photoresist pattern is removed to form island patterns of the semiconductor pattern of TFT1, that is, the Si (i) film 13 and the Si (n) film 14 which are the semiconductor films of TFT1.

  FIG. 4 is a cross-sectional view showing a state at the stage where the formation of the source electrode 15 and the drain electrode 16 is completed. After the Si (i) film 13 and the Si (n) film 14 are etched as described above, a second metal film is formed on the surfaces of the gate insulating film 12, the Si (i) film 13 and the Si (n) film 14. Form a film. Next, a photoresist pattern 22 is formed on the surface of the second metal film in the third photolithography process. Using this photoresist pattern 22 as a mask, the portion of the second metal film that becomes the channel portion 8 of the TFT 1 shown in FIG. 1 is etched to separate it into a source electrode 15 pattern and a drain electrode 16 pattern. At this time, the second metal film around the TFT 1 is also etched away.

  As a material of the second metal film, for example, Cr, Mo, Ti, Al, or an alloy obtained by adding a small amount of other substances to these metals can be used. Of these, Al-based metals such as Al and Al alloys have a lower specific resistance value than other metals such as Cr, Mo, and Ti, and therefore the wiring resistance can be lowered by using Al-based metals. Therefore, Al-based metal is preferable for the use of the TFT substrate 100 for liquid crystal display devices.

  When an Al-based metal is used as the material of the second metal film, an eutectic reaction between aluminum (Al) and silicon (Si) occurs at the interface with the Si (n) film 14 in contact with the lower layer in the case of Al alone. As a result, the contact characteristics may be deteriorated. Further, as a transparent conductive pixel electrode film constituting the pixel electrode 21 in contact with the upper layer, oxidation of indium tin oxide (abbreviation: ITO), indium zinc oxide (abbreviation: IZO) or the like is performed. When a physical conductive film is used, there is a risk that an oxidation reaction of Al occurs at the interface with the pixel electrode 21, resulting in poor contact characteristics. In order to prevent such poor contact characteristics, it is preferable to use an Al alloy as the material of the second metal film, and specifically, a Group 8 transition element such as at least Fe, Co, or Ni. It is preferable to use an Al alloy to which is added. The composition range of these Group 8 transition elements is preferably 0.2 at% or more and 6 at% or less of the entire Al alloy.

  Specifically, as the second metal film, for example, an Al-3 at% Ni alloy film to which 3 at% Ni is added has a thickness of 200 nm by a sputtering method using a known argon (Ar) gas. The film is formed as follows. Thereafter, as described above, a photoresist pattern 22 is formed on the surface of the second metal film in the third photolithography process, and using this photoresist pattern 22 as a mask, for example, a known etching solution such as phosphoric acid, The pattern of the source electrode 15 and the drain electrode 16 is formed by wet etching the second metal film with a solution containing nitric acid and acetic acid.

  In the etching process, even after so-called just etching in which the film to be etched is completely removed by etching, overetching is performed to extend the etching for a while in order to completely remove the minute etching residue remaining on the substrate. The overetching time is set to about 0.5 to 2 times the just etching time which is the time required for the just etching. For example, after the second metal film is just etched, overetching is performed until one time of the just etching time, that is, a time equal to the just etching time elapses.

  In the case of wet etching using a solution, since the etching reaction proceeds isotropically, the second metal film constituting the source electrode 15 and the drain electrode 16 is subjected to photoetching by overetching as shown in FIG. The resist pattern 22 is patterned into a shape whose end portion is recessed. Although it depends on the type of metal and the type of solution used, the receding amount (hereinafter sometimes referred to as “side etching amount”) sd of the second metal film constituting the source electrode 15 and the drain electrode 16 is, for example, It is 0.2 μm or more and 2 μm or less. In the case of wet etching using the above-described known solution containing phosphoric acid, nitric acid and acetic acid, the side etching amount sd is, for example, about 1 μm.

FIG. 5 is a cross-sectional view showing a state where the formation of the Al oxide film 17 has been completed. After forming the source electrode 15 and the drain electrode 16 as described above, one side in the thickness direction of the transparent insulating substrate 10 is formed on the substrate surface, that is, the surface of each film exposed on one side in the thickness direction of the transparent insulating substrate 10. Then, treatment is performed by irradiating plasma containing oxygen (O ₂ ) (hereinafter sometimes referred to as “oxygen plasma”). By processing with oxygen plasma in this way, the photoresist pattern 22 is ashed to reduce the film thickness, and the end portion, at least the side surface of the photoresist pattern 22 is retracted. In addition, the upper surface and side surfaces of the source electrode 15 and the drain electrode 16 whose surfaces are exposed as the end portions of the photoresist pattern 22 recede are processed by being irradiated with oxygen plasma. As a result, the second metal film constituting the source electrode 15 and the drain electrode 16 is oxidized, and a plasma oxide film 17 is formed on portions of the source electrode 15 and the drain electrode 16 that are not covered with the photoresist pattern 22. In the present embodiment, the Al-based metal film that is the second metal film is oxidized, and an Al oxide film is formed as the plasma oxide film 17.

  The receding amount rd1 of the photoresist pattern 22 in this step may be a value at which the surfaces of the source electrode 15 and the drain electrode 16 are completely covered with the photoresist pattern 22 and the Al oxide film 17, Optional. However, if the Al oxide film 17 is present in a portion where the pixel drain contact hole 20 where the drain electrode 16 is in contact with the upper pixel electrode 21 is formed, the contact resistance is increased. Therefore, the receding amount rd1 of the photoresist pattern 22 is preferably in a range where the Al oxide film 17 is not formed on the surface of the drain electrode 16 where the pixel drain contact hole 20 is formed. Specifically, the oxygen plasma irradiation is performed until the receding amount rd1 of the photoresist pattern 22 is about 2 μm, for example.

  FIG. 6 is a cross-sectional view showing a state where the formation of the channel portion 18 is completed. FIG. 7 is a cross-sectional view showing a state where the removal of the photoresist pattern 22 is completed. After the Al oxide film 17 is formed as described above, the remaining photoresist pattern 22 and the Al oxide film 17 at the ends of the source electrode 15 and the drain electrode 18 are used as masks for the portion where the channel portion 18 is formed. So-called back channel etching, in which the Si (n) film 14 is removed by etching, is performed. At this time, in this embodiment, part of the surface of the Si (i) film 13 is also removed by etching. Thereafter, the photoresist pattern 22 is completely removed to form the channel portion 18 of the TFT 1 as shown in FIG.

  Specifically, the Si (n) film 14 in the portion where the channel portion 18 is formed is etched and removed by dry etching using a known etching gas, for example, a gas containing chlorine. Further, after digging a part of the surface of the Si (i) film 13 where the channel portion 18 is to be formed, the photoresist pattern 22 is removed to form the channel portion 18 of the TFT 1.

  As described above, in this embodiment, the channel portion 18 uses the pattern of the source electrode 15 and the drain electrode 16 as a direct mask, and performs dry etching on a part of the surface of the Si (n) film 14 and the Si (i) film 13. It is formed by removing by. Therefore, the end portions of the Si (n) film 14 and Si (i) film 13 on the channel portion 18 side are on the channel portion 18 side of the source electrode 15 and the drain electrode 16 serving as upper layer masks as shown in FIG. It is formed on substantially the same plane as the end. More specifically, the side surfaces of the Si (n) film 14 and the Si (i) film 13 of the channel portion 18 are formed on substantially the same plane as the side surfaces of the source electrode 15 and the drain electrode 16.

  The ends of the Si (n) film 14 and the Si (i) film 13 on the channel part 18 side are separated from the source electrode 15 and the drain electrode 16 depending on the overetching time of the Si (n) film 14 and the Si (i) film 13. In some cases, the source electrode 15 and the drain electrode 16 are slightly deviated from the plane on which the end portions of the source electrode 15 and the drain electrode 16 are formed so as to recede in the direction away from the channel portion 18 from the end portion of the channel portion 18 side. Even in this case, the amount of deviation is small, and the virtual plane including the ends of the Si (n) film 14 and the Si (i) film 13 on the channel part 18 side, and the channel part 18 side of the source electrode 15 and the drain electrode 16 side. Are arranged on substantially the same plane.

  FIG. 8 is a cross-sectional view showing a state where the formation of the pixel drain contact hole 20 has been completed. After forming the channel portion 18 as described above, the protective insulating film 19 is formed on the surface of each film exposed on one side in the thickness direction of the transparent insulating substrate 10. As the protective insulating film 19, for example, a silicon nitride (SiN) film is formed to have a thickness of 300 nm under a substrate heating condition of about 300 ° C. by using a CVD method.

  Thereafter, in the fourth photolithography process, a photoresist pattern is formed on the surface of the protective insulating film 19, and the protective insulating film 19 is formed using a dry etching method using a known etching gas, for example, a fluorine-based gas. After the etching, the photoresist pattern is removed to form the pixel drain contact hole 20. The pixel drain contact hole 20 is formed so as to penetrate at least the surface of the drain electrode 16. In the present embodiment, the pixel drain contact hole 20 is formed so as to penetrate the protective insulating film 19 and reach the surface of the drain electrode 16. The pixel drain contact hole 20 is not limited to this, and may be formed to penetrate to the inside of the drain electrode 16, for example.

FIG. 9 is a cross-sectional view showing a state in which the formation of the pixel electrode 21 is completed. After the pixel drain contact hole 20 is formed as described above, a transparent conductive film to be the pixel electrode 21 is formed on the surface of each film exposed on one side in the thickness direction of the transparent insulating substrate 10. As the transparent conductive film, for example, IZO made of indium oxide (In ₂ O ₃ ) and zinc oxide ZnO is formed to a thickness of 100 nm by a sputtering method using a known Ar gas.

  Next, a photoresist pattern is formed on the surface of the transparent conductive film in the fifth photolithography process, and the transparent conductive film is wet etched with a known etching solution, for example, an oxalic acid-based solution, using this photoresist pattern as a mask. Thereafter, by removing the photoresist pattern, a pixel electrode 21 made of a transparent conductive film is formed as a pixel electrode pattern for liquid crystal display. As a result, the TFT substrate 100 for the liquid crystal display device according to the first embodiment of the present invention shown in FIG. 1 is obtained.

  As described above, according to the present embodiment, as shown in FIG. 5, after the pattern of the source electrode 15 and the drain electrode 16 is formed, the substrate is irradiated with oxygen plasma to retract the photoresist pattern 22, An Al oxide film 17 is formed on the end portions of the source electrode 15 and the drain electrode 16. Then, the Si (n) film 14 and the Si (i) film 13 are etched using the photoresist pattern 22 and the Al oxide film 17 as a mask. As a result, as shown in FIG. 6, the ends of the Si (n) film 14 and Si (i) film 13 on the channel portion 18 side are substantially the same as the ends of the source electrode 15 and the drain electrode 16 on the channel portion 18 side. They can be formed on the same plane.

  As shown in FIG. 4 described above, when the source electrode 15, the drain electrode 16 and the channel portion 18 are formed in the third photolithography process, after the Al alloy film constituting the source electrode 15 and the drain electrode 16 is wet-etched. The end portion of the source electrode 15 and the drain electrode 16 on the side where the channel portion 18 is formed is separated from the portion where the channel portion 18 is formed rather than the end portion of the photoresist pattern 22 by overetching. Retreating. Therefore, in the case of the conventional process of forming the channel portion 18 by dry etching the Si (n) film 14 which is the semiconductor film of the TFT using the photoresist pattern 22 as it is, the Si (n) film 14 The end portion on the channel portion 18 side extends in the channel direction from the end portions of the source electrode 15 and the drain electrode 16, and protrudes to the inside of the channel portion 18.

  Thus, the end of the Si (n) film 14 on the side of the channel portion 18 protrudes more inside the channel portion 18 than the ends of the source electrode 15 and the drain electrode 16, that is, the semiconductor film of the TFT is outside the electrode. When it protrudes, the electric field concentrates at the end of the electrode, and a tunneling current (hereinafter sometimes referred to as “tunnel current”) is generated at the interface between the n-type silicon and the i-type silicon. It will rise. In particular, when the semiconductor film of the TFT is formed of amorphous silicon, even if the amorphous silicon is n-type, the conductivity is two orders of magnitude smaller than that of crystalline silicon. Therefore, at the interface between the n-type amorphous silicon and the i-type amorphous silicon. Tunnel current is likely to occur, and off current is likely to increase.

  On the other hand, in the present embodiment, as described above, in the step shown in FIG. 5, the substrate is irradiated with oxygen plasma to retract the photoresist pattern 22 on the source electrode 15 and the drain electrode 16, and A plasma oxide film 17, specifically, an aluminum oxide film 17 is formed on the source electrode 15 and the drain electrode 16. That is, the protrusion of the end portion of the photoresist pattern 22 after the source electrode 15 and the drain electrode 16 are formed is removed by irradiating oxygen plasma.

  Then, using the photoresist pattern 22 and the aluminum oxide film 17 that have been receded as a direct mask, as shown in FIG. 6, for example, by dry etching using a chlorine-based gas, the Si (n) film 14 and Si ( i) A part of the surface of the film 13 is etched and dug to form the channel portion 18. At this time, the portions of the source electrode 15 and the drain electrode 16 whose surfaces are exposed due to the receding of the photoresist pattern 22 are covered with the aluminum oxide film 17 which is a plasma oxide film, and therefore are subject to corrosion by chlorine-based gas. There is no.

  Therefore, the end portions of the Si (n) film 14 and the Si (i) film 13 on the channel portion 18 side are formed on substantially the same plane as the end portions of the source electrode 15 and the drain electrode 16 on the channel portion 18 side. become. Accordingly, the concentration of the electric field at the end portions of the source electrode 15 and the drain electrode 16 can be relaxed, so that the generation of a tunnel current when the TFT 1 is off can be prevented, and the off current can be reduced.

  This effect is remarkable when a single-layer film of microcrystalline silicon or a multilayer film of amorphous silicon and microcrystalline silicon is used as the Si (i) film 13. Since microcrystalline silicon has a band gap of about 1.4 eV, which is smaller than 1.7 eV, which is the band gap of amorphous silicon, a tunnel current is easily generated. In the present embodiment, as described above, the ends of the Si (n) film 14 and the Si (i) film 13 on the channel portion 18 side are substantially the same as the ends of the source electrode 15 and the drain electrode 16 on the channel portion 18 side. Even when a single-layer film of microcrystalline silicon or a multilayer film of amorphous silicon and microcrystalline silicon is used as the Si (i) film 13, the source electrode 15 and the drain electrode 15 can be formed on the same plane. The concentration of the electric field at the end of 16 can be reduced. As described above, according to the present embodiment, when a single-layer film of microcrystalline silicon or a multilayer film of amorphous silicon and microcrystalline silicon is used as the Si (i) film 13, it is greatly effective in suppressing off current. An effect can be obtained.

  In the present embodiment, the end of the Si (n) film 14 on the channel part 18 side has an amount of protrusion from the ends of the source electrode 15 and the drain electrode 16 on the channel part 18 side to the inside of the channel part 18. , 0.1 μm or less. As a result, generation of a tunnel current when the TFT 1 is off can be prevented more reliably, and the off current can be more reliably reduced.

  Further, in the TFT substrate 100 in the present embodiment, as the second metal film constituting the source electrode 15 and the drain electrode 16, an alloy film in which at least a Group 8 transition element such as Fe, Co, Ni or the like is added to Al, specifically Specifically, an AlNi alloy film in which at least Ni is added to Al is used. As a result, eutectic reaction with the lower Si (n) film 14 can be prevented, and good contact characteristics with the pixel electrode 21 made of the upper oxide transparent conductive film can be obtained. Therefore, it is possible to apply a low resistance Al-based alloy, which has been impossible in the past, to the source electrode 15 and the drain electrode 16 of the TFT 1 for a liquid crystal display device as a single layer film.

  In addition, Al alloys such as AlNi alloys have low resistance and excellent hillock prevention properties to the upper surface, but have the disadvantage that hillocks are likely to occur on the side surfaces of the wiring due to the orientation of the crystal orientation. In the manufacturing method of TFT 1 of the present embodiment, since aluminum oxide film 17 is formed on the wiring side surface, that is, the end portion on the channel portion 18 side including the side surfaces of source electrode 15 and drain electrode 16, hillocks are generated on the side surface portion. Can be prevented. As a result, it is possible to prevent the occurrence of leakage current due to the contact between the source electrode 15 and the drain electrode 16 and the Si (i) film 14 underneath.

  In addition, since the aluminum oxide film 17 is formed on at least the side surfaces of the source electrode 15 and the drain electrode 16 on the channel part 18 side, the source electrode 15 is removed in the back channel etching process and the process of removing the photoresist pattern 22. 15 and the Al-based metal film constituting the drain electrode 16 can be prevented from eluting. As a result, it is possible to prevent the eluted metal solution from adhering to the surfaces of the semiconductor films 13 and 14 of the channel portion 18, and thus adhere to the surfaces of the semiconductor films 13 and 14 of the channel portion 18 after the back channel etching. Leakage current caused by the electrolyte etc. can be reduced. That is, it is possible to reduce metal contamination on the back channel surface of the channel portion caused by the eluted metal solution and off current flowing through the back channel interface due to the contamination. Accordingly, off-state current can be significantly reduced. Further, as described above, a thin film transistor in which off current and leakage current are suppressed can be manufactured with high yield.

  Further, by forming the aluminum oxide film 17 on at least the side surfaces of the source electrode 15 and the drain electrode 16, damage to the Al alloy surface due to the chlorine-based gas during back channel etching can be prevented, so that the resistance increases. Disconnection and a decrease in reflectance can be suppressed. Thus, for example, the drain electrode 16 can be applied to a reflective pixel electrode that reflects light and displays an image.

  In addition, in the source electrode 15 and the drain electrode 16, the aluminum oxide film 17, which is a plasma oxide film, does not exist in the portion covered with the photoresist pattern 22 at the time of etching for forming the channel portion 18. Therefore, electrical continuity with the pixel electrode 21 and the like existing above can be easily ensured through the contact hole 20.

  In this embodiment, the Si (i) film 13 and the Si (n) film 14 are interposed between the source electrode 15 and the gate insulating film 12 over the entire surface of the source electrode 15. As a result, the parasitic capacitance of the source electrode 15 can be reduced, so that when it is used for a liquid crystal display or the like, display defects that occur can be reduced. Further, since the Al oxide film 17 which is a plasma oxide film is formed only at the ends of the source electrode 15 and the drain electrode 16, it increases the wiring resistance and the contact resistance with the pixel electrode 21 which is the upper electrode. Can be prevented.

  As described above, according to the present embodiment, even when an Al alloy film is used for the source electrode 15 and the drain electrode 16, the off current and the leakage current can be suppressed. A resistive Al alloy film can be used. Further, according to the present embodiment, it is possible to manufacture the TFT 1 in which such off current and leakage current are suppressed with high yield. Therefore, it is possible to manufacture a TFT 1 for a liquid crystal display at a low cost and with a high yield by using a low resistance Al alloy film for the source electrode 15 and the drain electrode 16.

<Modification of the first embodiment>
In the first embodiment of the present invention described above, in the step shown in FIG. 5, the substrate is irradiated with oxygen plasma, thereby reducing the film thickness of the photoresist pattern 22 and forming the end portion of the channel portion 18. However, the photoresist pattern 22 may be completely removed. In this case, the entire surface of the source electrode 15 and the drain electrode 16 is covered with the Al oxide film 17. The Si (n) film 14 and the Si (i) film 13 are dry-etched using the pattern of the source electrode 15 and the drain electrode 16 whose entire surface is covered with the Al oxide film 17 as a direct mask. n) The feature that the end portions of the film 14 and the Si (i) film 13 on the channel portion 18 side are formed on substantially the same plane as the end portions of the source electrode 15 and the drain electrode 16 on the channel portion 18 side is This is the same as the first embodiment.

  However, in this modification, since the Al oxide film 17 is also formed on the surface of the drain electrode 16 where the contact hole 20 that is in contact with the upper pixel electrode 21 is formed, the drain that is in contact with the pixel electrode 21 The Al oxide film 17 formed on the surface of the electrode 16 is preferably removed.

  According to this modification, the remaining portion of the second metal film except the contact portion connected to the pixel electrode 21 is protected by the Al oxide film 17 throughout. Accordingly, generation of hillocks in the upper surface direction of the source electrode 15 and the drain electrode 16 can be prevented, and wiring disconnection due to generation of hillocks can be prevented. Further, since generation of hillocks in the side surface direction of the source electrode 15 and the drain electrode 16 can be prevented, leakage current due to contact between the hillock generated in the side surface direction and the Si (i) film 13 can be prevented. it can. Further, process damage and corrosion to the source electrode 15 and the drain electrode 16 after the step of etching the Si (n) film 14 can be significantly suppressed.

<Second Embodiment>
10 to 17 are diagrams for explaining each step of the manufacturing method of the TFT substrate 100A for the liquid crystal display device according to the second embodiment of the present invention. 10 to 17, as in FIGS. 2 to 9, a portion corresponding to the main pixel portion of the TFT substrate 100 </ b> A is shown. In the manufacturing method of TFT substrate 100A in the present embodiment, TFT substrate 100A is manufactured using the manufacturing method of TFT of the present invention. The manufacturing method of the TFT substrate 100A in the present embodiment is similar to the manufacturing method of the TFT substrate 100 in the first embodiment described above, and therefore, different points will be described and are common to the first embodiment. Description of the portion is omitted. In this embodiment, the second and third photolithography processes in the first embodiment are combined into one photolithography process, so that the TFT substrate can be obtained in a total of four photolithography processes. The point which manufactures 100A differs from 1st Embodiment.

  FIG. 10 is a cross-sectional view showing a state where the formation of the second metal film 23 has been completed. First, similarly to the first embodiment, after forming the gate electrode 11 on the surface of one side in the thickness direction of the transparent insulating substrate 10 such as a glass substrate, the gate insulating film 12 and the Si (i) film 13 are formed. The Si (n) film 14 and the second metal film 23 are sequentially formed. The gate electrode 11 is made of, for example, an Al-3 at% Ni alloy film. The gate insulating film 12 is made of, for example, SiN. The second metal film 23 is made of, for example, Al-3 at% Ni.

  FIG. 11 is a cross-sectional view showing a state where the formation of the photoresist pattern 24 is completed. After forming the gate electrode 11, the gate insulating film 12, the Si (i) film 13, the Si (n) film 14 and the second metal film 23 as described above, in the second photolithography process, A photoresist pattern 24 is formed on the surface of the second metal film 23. The photoresist pattern 24 is formed so that the film thickness of the portion corresponding to the channel portion 18 of the TFT 1 is thinner than the film thickness of other portions. The second metal film 23, the Si (n) film 14, and the Si (i) film 13 are sequentially etched using the photoresist pattern 24 having portions having different thicknesses as a mask.

  The photoresist pattern 24 is formed as follows, for example. First, as a photoresist, for example, a novolac positive photosensitive organic resin film is formed to a thickness of, for example, about 1.6 μm by using a known spin coating method. Thereafter, a first exposure is performed using a first photomask by a photoengraving exposure machine. The first exposure is performed with an exposure amount at which the photoresist photosensitive agent is completely exposed. Next, using a second photomask, the portion corresponding to the channel portion 18 of the TFT 1 is exposed with an intensity of about 30 to 60% of the exposure amount in the first exposure. Thereafter, the photoresist is developed using a developing solution to form a photoresist pattern 24 in which the film thickness of the portion corresponding to the channel portion 18 of the TFT 1 is smaller than the film thickness of the other portions. The photoresist pattern 24 is formed so that the film thickness of the portion corresponding to the channel portion 18 is, for example, about 0.8 μm.

  Etching using the photoresist pattern 24 as a mask is performed, for example, as follows. Using the photoresist pattern 24 as a mask, the second metal film 24 is wet etched using a known etching solution. When the second metal film 23 is made of Al-3 at% Ni, for example, a solution containing phosphoric acid, nitric acid and acetic acid is used as the etching solution. Subsequently, the Si (n) film 14 and the Si (i) film 13 are sequentially etched and patterned into islands by a dry etching method using a known etching gas, for example, a fluorine-based gas.

  FIG. 12 is a cross-sectional view showing a state where the surface of the second metal film 23 is exposed. After etching is performed as described above, the photoresist pattern 24 is ashed to reduce the film thickness by irradiating the substrate surface with oxygen plasma, and the film thickness corresponding to the channel portion 18 of the TFT 1 is thin. The photoresist is removed to expose the surface of the lower second metal film 23.

  FIG. 13 is a cross-sectional view showing a state where the formation of the pattern of the source electrode 15 and the drain electrode 16 is completed. Using the photoresist pattern 24 remaining after ashing shown in FIG. 12 as a mask, the portion of the second metal film 23 that becomes the channel portion 18 of the TFT 1 is etched, and the pattern of the source electrode 15 and the pattern of the drain electrode 16 are determined. To separate.

  Specifically, the pattern of the source electrode 15 and the drain electrode 16 is formed by wet etching the second metal film 23 using a known etching solution. At this time, the end portion of the source electrode 15 and the drain electrode 16 on the side where the channel portion 18 is formed is closer to the portion where the channel portion 18 is formed than the end portion of the photoresist pattern 24 by side etching by overetching. Retreat in the direction of separation. For example, when the second metal film 23 is made of Al-3 at% Ni, a phosphoric acid-nitric acid-acetic acid-based solution containing phosphoric acid, nitric acid and acetic acid is used as the etching solution, and the source electrode 15 and the drain electrode 16 are formed. The end portion on the side where the channel portion 18 is formed recedes by about 1 μm from the end portion of the photoresist pattern 24 in a direction away from the portion where the channel portion 18 is formed.

  FIG. 14 is a cross-sectional view showing a state in which the formation of the Al oxide film 17 has been completed. After etching the second metal film 23 as described above, the surface of the substrate is irradiated with oxygen plasma and processed to ash the photoresist pattern 24 again to reduce the film thickness. The end portions are set back from the end portions of the source electrode 15 and the drain electrode 16 in a direction away from the portion where the channel portion 18 is formed. Further, the Al oxide film 17 is formed by irradiating the surface and side surfaces of the source electrode 15 and the drain electrode 16 whose surfaces are exposed along with the receding edge of the photoresist pattern 24 by irradiating oxygen plasma.

  The receding amount rd2 of the photoresist pattern 24 at this time may be a value that allows the surfaces of the source electrode 15 and the drain electrode 16 to be completely covered with the photoresist pattern 24 and the Al oxide film 17, Optional. However, if the Al oxide film 17 is present in a portion where the pixel drain contact hole 20 where the drain electrode 16 is in contact with the upper pixel electrode 21 is formed, the contact resistance is increased. Therefore, the receding amount rd2 of the photoresist pattern 24 is preferably in a range where the Al oxide film 17 is not formed on the surface of the drain electrode 16 where the pixel drain contact hole 20 is formed. The oxygen plasma irradiation is performed, for example, until the receding amount rd2 of the photoresist pattern 24 is about 2 μm.

  FIG. 15 is a cross-sectional view showing a state in which the formation of the channel portion 18 has been completed. FIG. 16 is a cross-sectional view showing a state where the removal of the photoresist pattern 24 is completed. After the Al oxide film 17 is formed as described above, the channel portion 18 is formed using the remaining photoresist pattern 24 and the Al oxide film 17 at the ends of the source electrode 15 and the drain electrode 16 as a mask. The so-called back channel etching, in which the Si (n) film 14 is removed by etching, is performed. At this time, also in this embodiment, part of the surface of the Si (i) film 13 is also removed by etching. Thereafter, the photoresist pattern 24 is completely removed, and the channel portion 18 of the TFT 1 is formed as shown in FIG.

  The back channel etching is performed as follows, for example. First, the Si (n) film 14 in the portion where the channel portion 18 is formed is removed by dry etching using a known etching gas, for example, a gas containing chlorine. Further, a part of the surface of the Si (i) film 13 where the channel portion 18 is formed is dug. Thereafter, the photoresist pattern 24 is removed, and the channel portion 18 of the TFT 1 is formed.

  In this back channel etching, the channel portion 18 uses the pattern of the source electrode 15 and the drain electrode 16 as a direct mask to remove a part of the surface of the Si (n) film 14 and the Si (i) film 13 by dry etching. Will be formed. Therefore, the end portions of the Si (n) film 14 and Si (i) film 13 on the channel portion 18 side are substantially flush with the end portions on the channel portion 18 side of the source electrode 15 and the drain electrode 16 serving as upper layer masks. Will be formed.

  FIG. 17 is a cross-sectional view showing a state where the manufacture of the TFT substrate 100A is completed. After the channel portion 18 is formed as described above, the protective insulating film 19, the pixel drain contact hole 20, and the manufacturing process shown in FIGS. 7 to 9 in the first embodiment are performed. By forming the pixel electrode 21, a TFT substrate 100A for a liquid crystal display device according to the second embodiment of the present invention is obtained. In the present embodiment, since the Si (i) film 13 and the Si (n) film 14 are formed up to the lower layer of the drain electrode 16 where the pixel drain contact hole 20 is formed, the pixel electrode 21 is formed of Si. (I) The film 13, the Si (n) film 14 and the drain electrode 16 are stacked.

  The thus obtained TFT substrate 100A for a liquid crystal display device according to the second embodiment of the present invention can obtain the same effect as the TFT substrate 100 of the first embodiment described above. is there.

  Furthermore, according to the present embodiment, the photolithography process is less than that in the first embodiment, and the TFT substrate 100A for a liquid crystal display device can be manufactured by four photolithography processes. . Therefore, as compared with the first embodiment, it is possible to further improve the production capacity and reduce the cost.

  Also in this embodiment, as in the modification of the first embodiment described above, in the step shown in FIG. 14, instead of reducing the film thickness of the photoresist pattern 24 and receding the end, The resist pattern 24 may be completely removed. In this case, the Si (n) film 14 and the Si (i) film 13 are dry-etched using the pattern of the source electrode 15 and the drain electrode 16 whose entire surface is covered with the Al oxide film 17 as a direct mask. The feature that the end portions of the Si (n) film 14 and the Si (i) film 13 on the channel portion 18 side are formed on substantially the same plane as the end portions of the source electrode 15 and the drain electrode 16 on the channel portion 18 side. This is the same as in the second embodiment.

  In this case, since the Al oxide film 17 is also formed on the surface of the drain electrode 16 in the portion where the contact hole 20 in contact with the pixel electrode 21 is formed, as in the modification of the first embodiment described above, It is preferable to remove the Al oxide film 17 formed on the surface of the drain electrode 16 in contact with the pixel electrode 21.

  In the second embodiment, when the same modification as that of the first embodiment is performed, the remaining portion of the second metal film excluding the contact portion connected to the pixel electrode 21 is entirely. It is protected by the Al oxide film 17 over the entire area. Accordingly, generation of hillocks in the upper surface direction of the source electrode 15 and the drain electrode 16 can be prevented, and wiring disconnection due to generation of hillocks can be prevented. Further, since generation of hillocks in the side surface direction of the source electrode 15 and the drain electrode 16 can be prevented, leakage current due to contact between the hillock generated in the side surface direction and the Si (i) film 13 can be prevented. it can. Further, process damage and corrosion to the source electrode 15 and the drain electrode 16 after the step of etching the Si (n) film 14 can be significantly suppressed.

  In the first and second embodiments described above, the case where the Si (i) film 13 and the Si (n) film 14 that are amorphous Si films are applied as the semiconductor film of the TFT is exemplified. However, the same effect can be obtained even when a polycrystalline or microcrystalline Si film is applied. Further, even when an organic semiconductor film or an oxide semiconductor film is used as the semiconductor film of the TFT, it is formed in a process including an ohmic contact film with the source electrode 15 and the drain electrode 16 and including back channel etching of the ohmic contact film. Similar effects can be obtained with a TFT structure.

  In the first and second embodiments described above, the case where the TFT manufacturing method of the present invention is applied to the manufacture of TFT substrates 100 and 100A for a liquid crystal display device is exemplified. However, the present invention is not limited to the liquid crystal display device. In addition, the present invention can also be applied to a TFT substrate of a self-luminous display device using an electro-luminescence (Electro-Luminescence; abbreviation: EL) element and other semiconductor devices including a TFT having the same structure.

  FIG. 18 is a graph showing the distribution of hole current density in the thin film transistor of the present invention. FIG. 19 is a diagram showing a distribution of hole current density in a conventional thin film transistor. FIGS. 18 and 19 are distribution diagrams showing the results of calculating the hole current that causes the off current in the thin film transistor (TFT) when the gate voltage is −15 V and the drain voltage is 10 V. FIG. FIG. 18 is a distribution diagram related to the inverted staggered TFT 1 of the first embodiment described above. Further, FIG. 19 shows that, as a conventional TFT, one end portion on the channel portion side of the Si (n) film and the Si (i) film, which are Si layers, is more in the channel direction than the end portion on the channel portion side of the drain electrode. 2 shows a distribution diagram relating to an inverted staggered TFT having a shape extending inward and projecting inside the channel portion. In each of the two diagrams shown in FIGS. 18 and 19, only the hole current inside the Si layer is shown, and the hole current in the film other than the Si layer such as the source electrode, the drain electrode, the gate electrode, and the gate insulating film is shown. Not. 18 and 19, it is shown that the hole current density is higher as the concentration is higher.

  In the TFT 1 of the first embodiment exhibiting the distribution chart shown in FIG. 18, the gate electrode 11 has an Al-3 at% Ni alloy film as the first metal film, and the thickness becomes 200 nm by sputtering using Ar gas. After forming the film in this way, it was formed by wet etching with a solution containing phosphoric acid, nitric acid and acetic acid. A silicon nitride (SiN) film is added as the gate insulating film 12, a microcrystalline Si (i) film is added as the Si (i) film 13, and phosphorus (P) is added as an impurity as the Si (n) film 14. Crystalline Si (n) films were sequentially formed under a substrate heating condition of about 300 ° C. using a CVD method. The thickness of the gate insulating film 12 was 400 nm, the thickness of the Si (i) film 13 was 150 nm, and the thickness of the Si (n) film 14 was 50 nm. Etching of the Si (i) film 13 and the Si (n) film 14 was performed by dry etching using a fluorine-based gas.

The source electrode 15 and the drain electrode 16 are formed by forming an Al-3 at% Ni alloy film as a second metal film to a thickness of 200 nm by sputtering using Ar gas, and then adding phosphoric acid, nitric acid, and acetic acid. A pattern was formed by wet etching with the solution containing the solution. In the wet etching, overetching was performed until a time equal to the just etching time passed. At this time, the side etching amount sd of the second metal film was about 1 μm. The O ₂ plasma irradiation after the formation of the source electrode 15 and the drain electrode 16 was performed until the receding amount rd1 of the photoresist pattern 22 was about 2 μm. Etching of the Si (n) film 14 and the Si (i) film 13 when forming the channel portion 18 was performed by dry etching using a gas containing chlorine.

  As the protective insulating film 19, a silicon nitride (SiN) film was formed to a thickness of 300 nm under the substrate heating condition of about 300 ° C. by using the CVD method. For etching the protective insulating film 19 when forming the pixel drain contact hole 20, a dry etching method using a fluorine-based gas was used. As a transparent conductive film to be the pixel electrode 21, IZO was formed to a thickness of 100 nm by a sputtering method using Ar gas. Etching of the transparent conductive film was performed by wet etching using an oxalic acid-based solution. Each of the films in the prior art TFT that exhibits the distribution diagram shown in FIG. 19 has one end on the channel part side of the Si (n) film and the Si (i) film than the end part on the channel part side of the drain electrode. Except for projecting to the inside of the channel portion, it has the same shape as each film in the TFT 1 of the first embodiment.

  In the distribution diagrams shown in FIGS. 18 and 19, the recessed portion corresponds to a channel portion. In the distribution diagram of the prior art shown in FIG. 19, the hole current that causes the off-current is concentrated on the silicon extension portion at the drain electrode end on the right side toward the paper surface, and the hole current from this portion is dominant. It can be seen that it is.

  The cause is considered as follows. In an inverted staggered TFT, the profile of impurities such as phosphorus at the interface between n-type silicon and i-type silicon is steep, so that the electric field at the drain electrode 16 side, particularly at the drain electrode end that is the end of the drain electrode 16, Concentration occurs. For example, since the conductivity of n-type amorphous silicon used for TFT is as small as about 1.0 S / m, the concentration of the electric field generated at the end of the drain electrode cannot be sufficiently relaxed. The electric field at the interface with silicon increases. Due to the concentration of the electric field at the end of the drain electrode, a tunnel current is generated between the valence band and the conduction band, and this becomes a hole current. Accordingly, in the conventional TFT, as shown in FIG. 19, the hole current from the silicon extension portion at the drain electrode end is dominant.

  On the other hand, in the distribution diagram relating to the TFT 1 of the first embodiment shown in FIG. 18, the hole current is not concentrated except for the vicinity of the right drain electrode end toward the paper surface, and the hole current is reduced. You can see that

  In the present embodiment, as described above, the ends of the Si (n) film 14 and Si (i) film 13 that are Si layers on the channel part 18 side are connected to the channel part 18 side of the source electrode 15 and the drain electrode 16. It can be formed on substantially the same plane as the end portion, and the extending portion of the Si layer from the end portions of the source electrode 15 and the drain electrode 16 to the inside of the channel portion 18 can be eliminated. As a result, the concentration of the electric field moves from the end of the drain electrode 16 to the outer protective insulating film 19, so that the electric field at the interface between the n-type silicon and the i-type silicon is reduced, and the tunnel current becomes a hole current. Is suppressed. Therefore, as shown in FIG. 18, the concentration of the hole current is alleviated and the hole current is reduced.

  As described above, according to the present embodiment, the end portions of the Si (n) film 14 and the Si (i) film 13 on the channel portion 18 side are the end portions of the source electrode 15 and the drain electrode 16 on the channel portion 18 side. Therefore, off current can be reduced in a high electric field region of the thin film transistor. In particular, a thin film transistor for driving a liquid crystal display is applied with a high voltage alternately between the source electrode and the drain electrode because of its driving method, so that a low off-state current is required in both cases of source grounding and drain grounding. . Therefore, as in this embodiment, on either side of the source electrode 15 and the drain electrode 16, the end of the Si (n) film 14 and the Si (i) film 13 on the channel portion 18 side is the source electrode 15. And the structure which does not protrude inside the channel part 18 rather than the edge part by the side of the channel part 18 of the drain electrode 16 is required.

  DESCRIPTION OF SYMBOLS 1 Thin film transistor (TFT), 10 Transparent insulating board | substrate, 11 Gate electrode, 12 Gate insulating film, 13 i-type amorphous silicon thin film, 14 n-type amorphous silicon thin film, 15 Source electrode, 16 Drain electrode, 17 Aluminum oxide film, 18 channels Part, 19 protective insulating film, 20 pixel drain contact hole, 21 pixel electrode, 22, 24 photoresist pattern, 23 second metal film, 100, 100A thin film transistor (TFT) substrate.

Claims (10)

A gate electrode provided on an insulating substrate;
A gate insulating film covering the gate electrode and provided on the insulating substrate;
An intrinsic silicon film provided on the gate insulating film and having a channel portion formed thereon;
A conductive silicon film provided on the intrinsic silicon film and separated by the channel portion;
A source electrode and a drain electrode provided on the conductive silicon film and separated by the channel portion;
The channel electrode side ends of the source electrode and the drain electrode are covered with an oxide film,
The channel part side end of the conductive silicon film is formed on substantially the same plane as the channel part side ends of the source electrode and the drain electrode.   2. The remaining part of the upper surfaces of the source electrode and the drain electrode, except for the part in contact with the upper electrode provided on the source electrode and the drain electrode, is entirely covered with an oxide film. A thin film transistor according to 1.   3. The thin film transistor according to claim 1, wherein the intrinsic silicon film and the conductive silicon film are interposed between the source electrode and the gate insulating film over the entire surface of the source electrode.   4. The thin film transistor according to claim 1, wherein the intrinsic silicon film is formed of a single layer film of microcrystalline silicon or a multilayer film of amorphous silicon and microcrystalline silicon.   The amount of protrusion of the conductive silicon film on the channel portion side from the ends on the channel portion side of the source electrode and the drain electrode to the inside of the channel portion is 0.1 μm or less. The thin film transistor according to claim 1, wherein the thin film transistor is a thin film transistor. Forming a gate electrode on an insulating substrate;
Sequentially forming a gate insulating film, an intrinsic silicon film and a conductive silicon film on the surface of the insulating substrate on which the gate electrode is formed;
Forming a photoresist pattern on the conductive silicon film, etching the intrinsic silicon film and the conductive silicon film using the formed photoresist pattern as a mask, and patterning the island pattern;
Forming a metal film on the conductive silicon film patterned in an island shape;
Forming a photoresist pattern on the metal film, etching the metal film using the formed photoresist pattern as a mask, and forming a source electrode and a drain electrode;
The photoresist pattern, the source electrode, and the drain electrode are treated with plasma containing oxygen to recede the side surface of the photoresist pattern, and the side surface of the source electrode and the drain electrode, and the photoresist pattern. Forming an oxide film on the upper surface exposed by retreating,
Etching at least the conductive silicon film at a portion to be a channel portion between the source electrode and the drain electrode, using the remaining photoresist pattern and the oxide film as a mask;
And a step of removing the remaining photoresist pattern. Forming a gate electrode on an insulating substrate;
Sequentially forming a gate insulating film, an intrinsic silicon film and a conductive silicon film on the surface of the insulating substrate on which the gate electrode is formed;
Forming a photoresist pattern on the conductive silicon film, etching the intrinsic silicon film and the conductive silicon film using the formed photoresist pattern as a mask, and patterning the island pattern;
Forming a metal film on the conductive silicon film patterned in an island shape;
Forming a photoresist pattern on the metal film, etching the metal film using the formed photoresist pattern as a mask, and forming a source electrode and a drain electrode;
The step of removing the photoresist pattern by treating the photoresist pattern, the source electrode and the drain electrode with plasma containing oxygen, and forming an oxide film over the entire surface of the source electrode and the drain electrode When,
Etching at least a conductive silicon film at a portion to be a channel portion between the source electrode and the drain electrode using the oxide film as a mask;
Forming a protective film on the oxide film;
Forming a contact hole serving as a contact portion with the upper electrode formed on the protective film so as to penetrate through the protective film and the oxide film and reach at least one of the source electrode and the drain electrode; A method for producing a thin film transistor, comprising: Forming a gate electrode on an insulating substrate;
Sequentially forming a gate insulating film, an intrinsic silicon film, a conductive silicon film, and a metal film on the surface of the insulating substrate on which the gate electrode is formed;
A photoresist pattern having portions with different thicknesses is formed on the metal film, and the intrinsic silicon film, the conductive silicon film, and the metal film are etched using the formed photoresist pattern as a mask to form an island shape. Patterning into
Retreating the side surface of the photoresist pattern by treating the photoresist pattern with a plasma containing oxygen; and
Etching the metal film using the remaining photoresist pattern as a mask to form a source electrode and a drain electrode;
The remaining photoresist pattern, the source electrode, and the drain electrode are treated with oxygen-containing plasma so that the side surface of the photoresist pattern is retreated, the side surface of the source electrode and the drain electrode, and the photo Forming an oxide film on the upper surface exposed by the receding resist pattern;
Etching at least a conductive silicon film at a portion to be a channel portion between the source electrode and the drain electrode using the remaining photoresist pattern and the oxide film as a mask;
And a step of removing the remaining photoresist pattern. Forming a gate electrode on an insulating substrate;
Sequentially forming a gate insulating film, an intrinsic silicon film, a conductive silicon film, and a metal film on the surface of the insulating substrate on which the gate electrode is formed;
A photoresist pattern having portions with different thicknesses is formed on the metal film, and the intrinsic silicon film, the conductive silicon film, and the metal film are etched using the formed photoresist pattern as a mask to form an island shape. Patterning into
Retreating the side surface of the photoresist pattern by treating the photoresist pattern with a plasma containing oxygen; and
Etching the metal film using the remaining photoresist pattern as a mask to form a source electrode and a drain electrode;
The remaining photoresist pattern, the source electrode and the drain electrode are treated with plasma containing oxygen to remove the photoresist pattern and form an oxide film over the entire surface of the source electrode and the drain electrode. And a process of
Etching at least a conductive silicon film at a portion to be a channel portion between the source electrode and the drain electrode using the oxide film as a mask;
Forming a protective film on the oxide film;
Forming a contact hole serving as a contact portion with the upper electrode formed on the protective film so as to penetrate through the protective film and the oxide film and reach at least one of the source electrode and the drain electrode; A method for producing a thin film transistor, comprising:   The method of manufacturing a thin film transistor according to claim 6, wherein the intrinsic silicon film is formed of a single layer film of microcrystalline silicon or a multilayer film of amorphous silicon and microcrystalline silicon. .