JP2011067038A - Charge pump - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge pump for selecting two kinds of voltages, namely, a high voltage and a low voltage enabling generation, and smooth transition from an operation state which outputs the high voltage to an operation state which outputs the low voltage. <P>SOLUTION: When a step-down command is given in a high-voltage output mode, transition to a relay mode is once performed. In the relay mode, since two kinds of operation, namely, a smoothing operation for separating an input power supply from first and second capacitors for output and a flying capacitor to connect the flying capacitor and the first capacitor for output in parallel, and a flying operation for separating the flying capacitor from the first capacitor for output and connecting to the second capacitor for output in parallel, are repeated, the charge voltage of each capacitor is lowered, while the voltage values are maintained to be equal. Then, transition to a low-voltage output mode is performed, after the charge voltage of the capacitor lowers is awaited. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a charge pump that generates a power supply voltage having positive and negative polarities using a single input power supply.

  The charge pump is a DC / DC converter that generates a voltage having a desired polarity and magnitude by moving charges between a plurality of capacitors. In addition, this kind of charge pump is disclosed by patent document 1, for example.

JP-A-6-165482

  By the way, depending on the application of the charge pump, two types of voltage, high voltage and low voltage, are selected and generated. While generating this output voltage, the output voltage is switched from the low voltage to the high voltage according to the boost command. There is a case where a function for switching the output voltage from a high voltage to a low voltage is required in accordance with a command. Here, in order to generate the former high voltage, the operation of applying the output voltage of the input power supply to one capacitor and the charge charge of this capacitor are redistributed to the output capacitor connected to the power supply terminal of the load. The operation to be repeated may be repeated. In order to generate the latter low voltage, the operation of applying the output voltage of the input power supply to two capacitors connected in series, and the operation of one capacitor out of the two capacitors connected in series. What is necessary is just to repeat the operation of redistributing the charge to the output capacitor connected to the power supply terminal of the load. However, one problem arises when the charge pump is transitioned from an operating state that outputs a high voltage to an operating state that outputs a low voltage. That is, when the operation state for outputting a high voltage ends, a voltage equal to the output voltage of the input power supply remains in the capacitor. Therefore, when the operation state for outputting a low voltage starts, the input power supply is charged. A capacitor in which the voltage remains and another capacitor are connected in series, and an excessive voltage is generated in the voltage output portion of the input power supply, which may cause an abnormal operation of the charge pump.

  The present invention has been made in view of the circumstances described above, and can be generated by selecting two types of voltages, a high voltage and a low voltage, and a low voltage can be generated from an operating state that outputs a high voltage. An object of the present invention is to provide a charge pump capable of smoothly transitioning to an output operating state.

The present invention is a charge pump comprising first and second output capacitors, a flying capacitor, a switch circuit interposed between input power supplies, and a control unit for controlling the switch circuit,
The charge pump has a high voltage output mode, a low voltage output mode, and a relay mode as operation modes, and the control unit is configured to operate the flying capacitor and the first output in the high voltage output mode. A first charging operation for applying an output voltage of the input power source to each of the capacitors; and a flying operation for separating the flying capacitor from the first output capacitor and connecting the flying capacitor in parallel to the second output capacitor; Are repeatedly executed by the switch circuit to output positive and negative voltages from the first and second output capacitors. In the low voltage output mode, the flying capacitor and the first output capacitor are The flying capacitor connected in series and the first output capacitor connected in series A second charge operation for applying the output voltage of the input power source to the input device, a smoothing operation for connecting the flying capacitor and the first output capacitor in parallel, and the flying capacitor for the first output. A positive and negative voltage lower than that output in the high voltage output mode by causing the switch circuit to repeatedly perform a flying operation of separating from the capacitor and connecting in parallel to the second output capacitor. Are output from the first and second output capacitors, and in the relay mode, the input power source is separated from the first and second output capacitors and the flying capacitor, and the flying capacitor and the first capacitor are separated from each other. Smoothing operation of connecting output capacitors in parallel, and the flying capacity A period in which the switch circuit repeatedly executes a flying operation in which the switch is disconnected from the first output capacitor and connected in parallel to the second output capacitor, and the operation mode of the charge pump is the low voltage output mode When the step-up command is given, the operation mode of the switch circuit is changed from the low-voltage output mode to the high-voltage output mode, and during the period when the operation mode of the charge pump is the high-voltage output mode, When a command is given, a charge pump is provided, wherein the operation mode is changed from the high voltage output mode to the relay mode, and then is changed to the low voltage output mode.

  According to this invention, when the transition from the high-voltage output mode to the low-voltage output mode is made, the relay mode is passed, so that the first and second output capacitors and the flying are obtained through the operation in the relay mode. The charging voltage of the capacitor can be lowered, and the transition to the low voltage output mode can be made smoothly.

1 is a circuit diagram showing a configuration of a power amplifier circuit including a charge pump 1 according to an embodiment of the present invention. It is a circuit diagram which shows the structural example of the output state detection part 3 in the same embodiment. It is a figure which shows the state transition in the high voltage output mode of the charge pump 1 in the embodiment. It is a figure which shows the state transition in the low voltage output mode of the charge pump 1 in the embodiment. It is a figure which shows the state transition in the relay mode of the charge pump 1 in the embodiment. It is a figure which shows the aspect of the transition between the modes of the charge pump 1 in the embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a circuit diagram showing a configuration of a power amplifier circuit including a charge pump 1 according to an embodiment of the present invention. The power amplifier circuit includes a charge pump 1 as a power supply circuit, a load driving unit 2, and an output state detection unit 3. Here, the charge pump 1 is a power supply circuit that generates positive and negative power supply voltages to be supplied to the load driving unit 2. The load driving unit 2 is an amplifier that receives supply of positive and negative power supply voltages from the charge pump 1, amplifies an input signal AMPI given from a preceding circuit (not shown), and gives the output signal AMPO to a load (not shown). The output state detection unit 3 monitors the output state of the load driving unit 2 and whether the level of the output signal AMPO of the load driving unit 2 exceeds a predetermined limit with respect to the power supply voltage supplied to the load driving unit 2 This is a circuit for outputting an output state detection signal DETO indicating whether or not.

  As illustrated, the charge pump 1 includes a control unit 10, a switch circuit 20, and terminals CPVDD, CP, GND, CN, and CPVSS. The terminal CPVDD is connected to the positive power supply terminal of the load driving unit 2, and the terminal CPVSS is connected to the negative power supply terminal of the load driving unit 2. The terminal GND is grounded, the output capacitor C1 is between the terminal CPVDD and the ground line, the output capacitor C2 is between the terminal CPVSS and the ground line, and the flying capacitor C3 is between the terminals CP and CN. Is inserted. The output capacitor C1, the output capacitor C2, and the flying capacitor C3 ideally have the same capacitance value. In the following, for convenience of explanation, the voltage generated at the terminal CPVDD is the voltage CPVDD, the voltage generated at the terminal CP is the voltage CP, the voltage generated at the terminal GND is the voltage GND, and the voltage generated at the terminal CN is the voltage CN. The voltage generated at the terminal CPVSS may be expressed as a voltage CPVSS.

  The switch circuit 20 includes P-channel field effect transistors (hereinafter simply referred to as transistors) P1 to P5 and N-channel transistors N1 to N3. Here, the P-channel transistor P1 is between the power supply HPVDD and the terminal CP, the P-channel transistor P2 is between the power supply HPVDD and the terminal CPVDD, the P-channel transistor P3 is between the terminals CPVDD and CP, and the P-channel transistor P4 is at the terminal CPVDD and The P channel transistor P5 is inserted between the power supply SPVDD and the terminal CP. The voltage value of the power supply HPVDD is, for example, 1.8V. The voltage value of the power supply SPVDD is larger than the voltage value of the power supply HPVDD, for example, 3.6V. The N channel transistor N1 is inserted between the terminal CP and the terminal GND, the N channel transistor N2 is inserted between the terminal CN and the terminal GND, and the N channel transistor N3 is inserted between the terminal CN and the terminal CPVSS.

  The charge pump 1 in the present embodiment has a high voltage output mode, a low voltage output mode, a relay mode, and a high power mode as operation modes.

  The high voltage output mode is an operation mode in which a positive voltage CPVDD (= HPVDD) and a negative voltage CPVSS (= −HPVDD) having the same magnitude as the power supply voltage HPVDD are output from the terminals CPVDD and CPVSS. The low voltage output mode is an operation mode in which a positive voltage CPVDD (= HPVDD / 2) and a negative voltage CPVSS (= −HPVDD / 2), which are 1/2 the magnitude of the power supply voltage HPVDD, are output from the terminals CPVDD and CPVSS. is there. The relay mode is an operation mode provided in order to smoothly transition from the high voltage output mode to the low voltage output mode. In the high voltage output mode, the low voltage output mode, and the relay mode, only the power supply HPVDD is used, and the power supply SPVDD is not used. The high power mode is an operation mode in which a positive voltage CPVDD (= HPVDD) having the same magnitude as the power supply voltage HPVDD and a negative voltage CPVSS having an arbitrary magnitude are output from the terminals CPVDD and CPVSS. In this high power mode, the power supply SPVDD is used in addition to the power supply HPVDD, and a negative voltage CPVSS having a voltage value larger than the power supply voltage HPVDD can be generated within a range within the power supply voltage SPVDD.

  The control unit 10 is a circuit that controls transition between the above operation modes and controls the switch circuit 20 in each operation mode. The control unit 10 synchronizes with the clock CLK having a predetermined frequency and switches the gate voltage applied to the gates of the P-channel transistors P1 to P5 and the N-channel transistors N1 to N3 according to a procedure determined for each operation mode, thereby Each operation mode is realized. Details of control of the switch circuit 20 for realizing the high voltage output mode, the low voltage output mode, and the relay mode will be described later. The high power mode has a weak relationship with the features of the present invention, and thus the details thereof will be omitted.

  In the present embodiment, the transition between the low voltage output mode and the high voltage output mode is performed based on the output state of the load driving unit 2. The output state detection unit 3 is a circuit that generates information that triggers the mode transition. More specifically, the output state detection unit 3 monitors the output state of the load drive unit 2 and supplies power supply voltages (specifically, a positive power supply voltage CPVDD and a negative power supply voltage CPVSS) supplied to the load drive unit 2. Is a circuit that outputs an output state detection signal DETO indicating whether or not the level of the output signal AMPO of the load driving unit 2 has approached beyond a predetermined limit.

  FIGS. 2A to 2C are circuit diagrams illustrating various configuration examples of the output state detection unit 3. In the output state detector 3A shown in FIG. 2A, the resistor 31 and the constant current source 32 constitute a circuit that generates a reference level REFP from each common connection point. Here, the resistor 31 is interposed between the power supply CPVDD and the constant current source 32, and the current of the constant current source 32 flows. Therefore, when the current value of the constant current source 32 is I0 and the resistance value of the resistor 31 is R0, the reference level REFP obtained from the common connection point of the resistor 31 and the constant current source 32 is CPVDD−I0 · R0. The resistor 33 and the constant current source 34 constitute a circuit that generates a reference level REFM from each common connection point. Here, the resistor 33 is inserted between the power source CPVSS and the constant current source 34, and the current of the constant current source 34 flows. Therefore, when the current value of the constant current source 34 is I0 as in the constant current source 32 and the resistance value of the resistor 33 is R0 as in the resistor 31, the reference obtained from the common connection point of the resistor 33 and the constant current source 34 is obtained. The level REFM is CPVSS + I0 · R0. The comparator 35 outputs a signal that becomes H level when the output signal AMPO of the load driving unit 2 is higher than the reference level REFP, and becomes L level in other cases. The comparator 36 outputs a signal that is H level when the output signal AMPO of the load driving unit 2 is lower than the reference level REFM, and is L level otherwise. The OR gate 37 sets the output state detection signal DETO to L level when both output signals of the comparators 35 and 36 are at L level, and when at least one of the output signals of the comparators 35 and 36 is at H level. The output state detection signal DETO is set to H level. Accordingly, the output state detection signal DETO becomes L level when the output signal AMPO of the load driving unit 2 is within the range between the reference level REFP and the reference level REFM, and the output signal AMPO exceeds the predetermined limit and the power supply is detected. When the voltage approaches CPVDD or CPVSS, specifically, when the output signal AMPO becomes higher than the reference level REFP, or becomes lower than the reference level REFM, the H level is set.

  The output state detection unit 3B shown in FIG. 2B is obtained by changing the circuit that generates the reference levels REFP and REFM in the output state detection unit 3A shown in FIG. The circuit configuration of the part including the comparators 35 and 36 and the OR gate 37 is the same as that shown in FIG. In the output state detection unit 3B, a circuit that generates the reference levels REFP and REFM is configured by resistors 41, 42, and 43 having the same resistance value, an N-channel transistor 44, and an operational amplifier 45. Here, the resistors 41, 42, and 43 are inserted in series between a voltage source that generates a constant reference level REFV, such as a band gap reference circuit, and the drain of the N-channel transistor 44. The N-channel transistor 44 has a source connected to the power supply CPVSS. The operational amplifier 45 has a positive phase input terminal (+ terminal) grounded and a negative phase input terminal (− terminal) connected to a common connection point of the resistors 42 and 43. According to this configuration, negative feedback to the operational amplifier 45 is performed via the common connection point of the resistors 42 and 43, and the operational amplifier 45 has an N channel so that the potential at the common connection point of the resistors 42 and 43 becomes the ground potential. A gate voltage is output to the transistor 44. Therefore, the reference level REFP obtained from the common connection point of the resistors 41 and 42 is REFV / 2, and the reference level REFM obtained from the drain of the N-channel transistor 44 is −REFV / 2.

  The output state detection unit 3C shown in FIG. 2C is a circuit that detects a current flowing through a transistor in the output stage of the load driving unit 2 and outputs an output state detection signal DETO based on the detection result. In the example shown in FIG. 2C, the load driving unit 2 has a P-channel transistor 21 and an N-channel transistor 22 inserted in series between the power supplies CPVDD and CPVSS, and the drains of these two transistors are connected to each other. The output signal AMPO is output from the connection point. In the load driving unit 2, the gate voltage applied to the P-channel transistor 21 is adjusted, the drain current passed through the P-channel transistor 21 is increased, the output signal AMPO is increased, and the gate voltage applied to the N-channel transistor 22 is adjusted. The output signal AMPO is lowered by increasing the drain current flowing through the N-channel transistor 22. In the output state detection unit 3C shown in FIG. 2C, the drain currents flowing in the P-channel transistor 21 and the N-channel transistor 22 of the load driving unit 2 are detected, and based on the detection result, the load driving unit 2 It is determined whether the output signal AMPO has approached the power supply voltages CPVDD and CPVSS beyond a certain limit. Further details are as follows.

  First, the source of the P-channel transistor 51 is fixed to the power supply voltage CPVDD, and the gate voltage that is the same as that applied to the P-channel transistor 21 of the load driving unit 2 is applied to the gate. Together with the current mirror. Therefore, a drain current of k1 times the drain current of the P channel transistor 21 (k1 is a coefficient determined by the ratio of the transistor size of the P channel transistor 21 and the transistor size of the P channel transistor 51) flows through the P channel transistor 51. A constant current source 52 is connected to the drain of the P-channel transistor 51. The current value of the constant current source 52 is a P-channel transistor when the level of the output signal AMPO of the load driving unit 2 reaches a certain upper limit level (a level corresponding to the reference level REFP in FIG. 2A or 2B). 21 is a value obtained by multiplying the drain current value of 21 by k1. Therefore, when the level of the output signal AMPO of the load driving unit 2 is lower than the upper limit level, the drain current value of the P-channel transistor 51 becomes smaller than the current value of the constant current source 52, and the drain voltage of the P-channel transistor 51 Becomes L level, which is a voltage value greatly reduced from the power supply voltage CPVDD. On the other hand, when the level of the output signal AMPO of the load driving unit 2 is higher than the upper limit level, the drain current value of the P-channel transistor 51 becomes larger than the current value of the constant current source 52, and the drain voltage of the P-channel transistor 51 Becomes H level, which is a voltage value close to the power supply voltage CPVDD. The drain voltage of P channel transistor 51 is applied to OR gate 58 through inverters 55 and 56.

  Next, the source of the N-channel transistor 53 is fixed to the power supply voltage CPVSS, and the gate voltage that is the same as that applied to the N-channel transistor 22 of the load driving unit 2 is applied to the gate. 22 constitutes a current mirror. Therefore, the drain current of k2 times the drain current of the N channel transistor 22 (k2 is a coefficient determined by the ratio of the transistor size of the N channel transistor 22 and the transistor size of the N channel transistor 53) flows through the N channel transistor 53. A constant current source 54 is connected to the drain of the N-channel transistor 53. The current value of the constant current source 54 is an N-channel transistor when the level of the output signal AMPO of the load driving unit 2 reaches a certain lower limit level (a level corresponding to the reference level REFM in FIG. 2A or 2B). This is a value obtained by multiplying the drain current value of 22 by k2. Therefore, when the level of the output signal AMPO of the load driving unit 2 is higher than the lower limit level, the drain current value of the N-channel transistor 53 becomes smaller than the current value of the constant current source 54, and the drain voltage of the N-channel transistor 53 Becomes an H level that is a voltage value greatly increased from the power supply voltage CPVSS. On the other hand, when the level of the output signal AMPO of the load driving unit 2 is lower than the lower limit level, the drain current value of the N-channel transistor 53 becomes larger than the current value of the constant current source 54, and the drain voltage of the N-channel transistor 53 Becomes an L level which is a voltage value close to the power supply voltage CPVSS. The drain voltage of the N-channel transistor 53 is inverted in level through the inverter 57 and applied to the OR gate 58.

  The OR gate 58 sets the output state detection signal DETO to L level when both output signals of the inverters 56 and 57 are at L level, and when at least one of the output signals of the inverters 56 and 57 is at H level, that is, When the level of the output signal AMPO of the load driving unit 2 is higher than the upper limit level or lower than the lower limit level, the output state detection signal DETO is set to H level.

  Next, details of each operation mode of the charge pump 1 will be described. FIG. 3 is a diagram showing a state transition of the charge pump 1 in the high voltage output mode. As shown in FIG. 3, in the high voltage output mode, the charge pump 1 alternately performs a charge operation (see FIG. 3A) and a flying operation (see FIG. 3C) in synchronization with the clock CLK. repeat.

  First, in the charging operation (see FIG. 3A), the control unit 10 turns on the P-channel transistors P1, P2 and the N-channel transistor N2 of the switch circuit 20, and turns off the other transistors. As a result, as shown in the figure, the output capacitor C1 is charged through the path of power supply HPVDD → P channel transistor P2 → output capacitor C1 → ground line, and the power supply voltage HPVDD is applied to the output capacitor C1. . Further, as shown in the figure, the flying capacitor C3 is charged through a path of power supply HPVDD → P channel transistor P1 → flying capacitor C3 → N channel transistor N2 → ground line, and the power supply voltage HPVDD is applied to the flying capacitor C3. The In this case, the flying capacitor C3 is in a state where the electrode on the terminal CP side is charged with positive charges and the electrode on the terminal CN side is charged with negative charges.

  If the charging operation (see FIG. 3A) is performed for a certain period, then the flying operation (see FIG. 3C) is performed for a certain period. In this flying operation (see FIG. 3C), the control unit 10 turns on the P-channel transistor P2 and the N-channel transistors N1 and N3 of the switch circuit 20, and turns off the other transistors. As a result, as shown in the figure, the output capacitor C1 is charged through the path of power supply HPVDD → P channel transistor P2 → output capacitor C1 → ground line, and the power supply voltage HPVDD is applied to the output capacitor C1. . Further, as shown in the drawing, a path of the ground line → N channel transistor N1 → flying capacitor C3 → N channel transistor N3 → output capacitor C2 → ground line is formed. The flying capacitor C3 grounds the electrode on the terminal CP side charged with positive charges via the N-channel transistor N1, and connects the electrode on the terminal CN side charged with negative charges via the N-channel transistor N3. It is connected to the terminal CPVSS and connected in parallel with the output capacitor C2. In this way, the charging voltage HPVDD of the flying capacitor C3 has a reverse polarity and is applied to the output capacitor C2, and the charging voltage CPVSS of the output capacitor C2 becomes −HPVDD.

  Thereafter, similarly, the charging operation and the flying operation are repeated, and the power supply voltage CPVDD = HPVDD from the terminal CPVDD to the positive power supply terminal of the load driving unit 2 and the power supply voltage CPVSS = − from the terminal CPVSS to the negative power supply terminal of the load driving unit 2. HPVDD is supplied.

  FIG. 4 is a diagram showing state transition of the charge pump 1 in the low voltage output mode. As shown in FIG. 4, in the low voltage output mode, the charge pump 1 synchronizes with the clock CLK, the charge operation (see FIG. 4A), the smoothing operation (see FIG. 4B), The flying operation (see FIG. 4C) is repeated sequentially and cyclically.

  First, in the charging operation (see FIG. 4A), the control unit 10 turns on the P-channel transistors P1 and P4 of the switch circuit 20 and turns off the other transistors. As a result, as shown in the figure, a path of power supply HPVDD → P channel transistor P1 → flying capacitor C3 → P channel transistor P4 → output capacitor C1 → ground line is formed. In this way, the flying capacitor C3 and the output capacitor C1 are charged with the flying capacitor C3 and the output capacitor C1 connected in series between the power supply HPVDD and the ground line. In this case, the flying capacitor C3 and the output capacitor C1 are in a state of being vertically stacked between the power supply HPVDD and the ground line, and a voltage is applied by HPVDD / 2. In this case, the flying capacitor C3 is in a state where the electrode on the terminal CP side is charged with positive charges and the electrode on the terminal CN side is charged with negative charges.

  If the charging operation (see FIG. 4A) is performed for a certain period, then the smoothing operation (see FIG. 4B) is performed for a certain period. In the smoothing operation (see FIG. 4B), the control unit 10 turns on the P-channel transistor P3 and the N-channel transistor N2 of the switch circuit 20, and turns off the other transistors. As a result, as shown in the figure, a path of the ground line → N channel transistor N2 → flying capacitor C3 → P channel transistor P3 → output capacitor C1 → ground line is formed. As a result, the flying capacitor C3 grounds the electrode on the terminal CN side charged with negative charges via the N-channel transistor N2, and the electrode on the terminal CP side charged with positive charges via the P-channel transistor P3. And connected in parallel to the output capacitor C1. As a result, the charging voltage of the output capacitor C1 and the charging voltage of the flying capacitor C3 become the same, and the charging voltage CPVDD of the output capacitor C1 becomes HPVDD / 2.

  If the smoothing operation (see FIG. 4B) is performed for a certain period, then the flying operation (see FIG. 4C) is performed for a certain period. In this flying operation (see FIG. 4C), the control unit 10 turns on the N-channel transistors N1 and N3 of the switch circuit 20 and turns off the other transistors. As a result, as shown in the drawing, a path of the ground line → N channel transistor N1 → flying capacitor C3 → N channel transistor N3 → output capacitor C2 → ground line is formed. As a result, the flying capacitor C3 grounds the electrode on the terminal CP side charged with positive charge via the N-channel transistor N1, and the electrode on the terminal CN side charged with negative charge via the N-channel transistor N3. To the terminal CPVSS and connected in parallel with the output capacitor C2. In this way, the charging voltage HPVDD / 2 of the flying capacitor C3 has a reverse polarity and is applied to the output capacitor C2, and the charging voltage CPVSS of the output capacitor C2 becomes −HPVDD / 2.

  Thereafter, similarly, the charging operation, the smoothing operation, and the flying operation are sequentially and cyclically repeated so that the power supply voltage CPVDD = HPVDD / 2 is transferred from the terminal CPVDD to the positive power supply terminal of the load driving unit 2 and the load driving unit from the terminal CPVSS. The power supply voltage CPVSS = −HPVDD / 2 is supplied to the two negative power supply terminals.

  FIG. 5 is a diagram showing state transition of the charge pump 1 in the relay mode. As shown in FIG. 5, in the relay mode, the charge pump 1 synchronizes with the clock CLK, the all-OFF operation (see FIG. 5A), the smoothing operation (see FIG. 5B), the flying The operation (see FIG. 5C) is repeated sequentially and cyclically.

  First, in the all-OFF operation (see FIG. 5A), the control unit 10 turns off all the transistors of the switch circuit 20. While this all-OFF operation continues, the flying capacitor C3 maintains the same charging voltage. The output capacitors C1 and C2 are connected to the positive power supply terminal and the negative power supply terminal of the load driving unit 2, respectively. For this reason, the charge charges of the output capacitors C1 and C2 are consumed by the load driving unit 2, and the magnitudes of the charge voltages of the output capacitors C1 and C2 gradually decrease.

  If the all-OFF operation (see FIG. 5A) is performed for a certain period, then the smoothing operation (see FIG. 5B) is performed for a certain period. In this smoothing operation (see FIG. 5B), the control unit 10 turns on the P-channel transistor P3 and the N-channel transistor N2 of the switch circuit 20 as in the case of the smoothing operation in the low-voltage output mode. Turn off the other transistors. As a result, the charging voltage of the output capacitor C1 and the charging voltage of the flying capacitor C3 are the same.

  If the smoothing operation (see FIG. 5B) is performed for a certain period, then the flying operation (see FIG. 5C) is performed for a certain period. In this flying operation (see FIG. 5C), the control unit 10 turns on the N-channel transistors N1 and N3 of the switch circuit 20 and turns off the other transistors as in the case of the flying operation in the low voltage output mode. And As a result, the flying capacitor C3 is connected in parallel to the output capacitor C2 with the electrode on the terminal CP side grounded, and the charging voltage of the output capacitor C2 is a negative voltage having the same magnitude as the charging voltage of the flying capacitor C3. It becomes.

  Thereafter, similarly, the charging operation, the smoothing operation, and the flying operation are sequentially and cyclically repeated. During this time, the charging charge of the output capacitor C1 and the charging charge of the output capacitor C2 are consumed by the load driving unit 2, so that the charging voltages of the output capacitors C1 and C2 and the flying capacitor C3 are becoming the same voltage value. It will gradually decline.

  FIG. 6 is a diagram illustrating a mode transition mode of the charge pump 1 according to the present embodiment. In the present embodiment, the change from the L level to the H level of the output state detection signal DETO output by the output state detection unit 3 becomes a boost command to the charge pump 1. Further, a change from the H level to the L level of the output state detection signal DETO becomes a step-down command for the charge pump 1. The transition between modes of the charge pump 1 is performed by using a change in the output state detection signal DETO as such a step-up command or step-down command as a trigger. First, when the charge pump 1 is operating in the low voltage output mode, the level of the output signal AMPO of the load driving unit 2 exceeds a predetermined limit with respect to the power supply voltages CPVDD and CPVSS supplied to the load driving unit 2. Assume that the output state detection signal DETO becomes H level. In this case, the control unit 10 immediately changes the operation mode of the charge pump 1 from the low voltage output mode to the high voltage output mode. In this case, since the charging voltages of the output capacitors C1 and C2 and the flying capacitor C3 before the mode transition are about HPVDD / 2, the operation mode of the charge pump 1 is immediately shifted from the low voltage output mode to the high voltage output mode. But no problem arises.

  On the other hand, when the charge pump 1 is operating in the high voltage output mode, the amplitude of the output signal AMPO decreases, and the output signal of the load driving unit 2 with respect to the power supply voltages CPVDD and CPVSS supplied to the load driving unit 2 Assume that the level of AMPO is no longer approaching beyond a predetermined limit, and the output state detection signal DETO becomes L level. Here, during the operation in the high voltage output mode, the charging voltages of the output capacitors C1 and C2 and the flying capacitor C3 are about HPVDD. Accordingly, when the charge pump 1 is immediately shifted from the high voltage output mode to the low voltage output mode in response to the output state detection signal DETO becoming L level, the power supply HPVDD is used in the charge operation in the low voltage output mode. The flying capacitor C3 and the output capacitor C1 are vertically stacked between the ground line and the grounding line (see FIG. 4A), and the charging voltage as a whole of the vertically stacked flying capacitor C3 and output capacitor C1 is 2HPVDD. Since the voltage is in the vicinity, the operation of the charge pump 1 may be abnormal.

  Therefore, in the present embodiment, when the output state detection signal DETO becomes L level, the control unit 10 changes the operation mode of the charge pump 1 from the high voltage output mode to the relay mode, for example, the output capacitor C1. The charging voltage CPVDD is monitored. In this relay mode, the all-OFF operation, the smoothing operation, and the flying operation are repeated while the charge driving unit 2 consumes the charge of the output capacitors C1 and C2 (see FIGS. 5A to 5C). The charging voltages of the output capacitors C1 and C2 and the flying capacitor C3 gradually decrease while becoming the same voltage. Then, when the output state detection signal DETO is at the L level, the control unit 10 sets the charge pump 1 when the charge voltage CPVDD of the output capacitor C1 becomes a sufficiently low voltage, more specifically, αHPVDD or less. The operation mode is changed from the high voltage output mode to the low voltage output mode.

  In the present embodiment, α is 0.55. The reason why α is set to 0.55 is as follows. First, the power amplifier circuit shown in FIG. 1 is formed on a P-type semiconductor substrate doped with a low-concentration P-type impurity. In this power amplifier circuit, each P-channel transistor is formed on the P-type semiconductor substrate at a low concentration. It is formed in an N well which is an isolated region formed by doping the N-type impurity. When operating in the high voltage output mode, the low voltage output mode, and the relay mode, the power supply voltage HPVDD is applied to each N well to which each of the P channel transistors P1, P2, P3, and P4 shown in FIG. 1 belongs. It has become. When transitioning from the high voltage output mode to the low voltage output mode via the relay mode, the flying capacitor C3 and the output capacitor C1 are vertically stacked between the power supply HPVDD and the ground line in the charge operation of the low voltage output mode after the transition. It will be in the state. If the voltage across the flying capacitor C3 and the output capacitor C1 that are vertically stacked is higher than the power supply voltage HPVDD by a predetermined voltage or more, it is interposed between the drain of the P channel transistor P1 and the N well to which the P channel transistor P1 belongs. There is a possibility that current flows through the parasitic diode, causing an abnormality in the operation of the charge pump 1. However, in the present embodiment, when the charging voltages of the output capacitors C1 and C2 and the flying capacitor C3 become αHPVDD = 0.55HPVDD or less, the transition from the relay mode to the low voltage output mode is performed. For this reason, in the charge operation in the low voltage output mode, the voltage across the flying capacitor C3 and the output capacitor C1 that are vertically stacked is 1.1HPVDD, and when HPVDD = 1.8V, the excess from the power supply voltage HPVDD is 0.1HPVDD = 0.18V or so. If the voltage exceeds this level, there is no fear that the parasitic diode described above will be turned on, and the operation of the charge pump 1 will not be abnormal. The above is the reason why α is set to 0.55.

  In addition to the above, there is the following advantage in passing through the relay mode at the time of transition from the high voltage output mode to the low voltage output mode in the present embodiment. That is, it is an advantage that stable transition between modes is realized. For example, when the amplitude of the output signal AMPO of the load driving unit 2 increases slowly, the following inconvenience arises if the relay mode is not passed during the transition from the high voltage output mode to the low voltage output mode. First, when the output signal AMP approaches the power supply voltage supplied to the load driving unit 2 beyond a certain limit, the output state detection signal DETO goes to H level, which causes the charge pump 2 to change from the low voltage output mode to the high level. Transition to voltage output mode. Here, when the output state detection unit 3A shown in FIG. 2A, for example, is employed as the output state detection unit 3, the reference level REFP increases and the reference level with the transition from the low voltage output mode to the high voltage output mode. When the decrease in REFM occurs and the increase in the amplitude of the output signal AMPO is slow, the output state detection signal DETO that has become the H level immediately returns to the L level. For this reason, assuming that the relay mode is not passed during the transition from the high voltage output mode to the low voltage output mode, the operation mode is immediately changed to the low voltage output mode in response to the change of the output state detection signal DETO to the L level. It will be transitioned. However, when the mode returns to the low voltage output mode, the reference level REFP decreases and the reference level REFM increases accordingly, so that the output state detection signal DETO becomes H level again, and the low voltage output mode changes to the high voltage output mode. Transition occurs. As described above, when the amplitude of the output signal AMPO of the load driving unit 2 increases slowly, there is a possibility that the mode transition between the low voltage output mode and the high voltage output mode occurs frequently.

  However, in the present embodiment, for example, when the amplitude of the output signal AMPO of the load driving unit 2 increases slowly and there is a transition from the low voltage output mode to the high voltage output mode, the output state detection signal DETO is thereafter detected. Is changed from the high voltage output mode to the relay mode. If the output state detection signal DETO becomes H level again during the operation in the relay mode, the operation mode returns from the relay mode to the high voltage output mode. As described above, in the present embodiment, when the amplitude of the output signal AMPO of the load driving unit 2 is slowly increased, frequent transition between modes between the low voltage output mode and the high voltage output mode is prevented. In addition, the operation of the charge pump 1 and the operation of the load driving unit 2 that receives power from the charge pump 1 can be stabilized.

  As described above, the power amplifier circuit according to the present embodiment monitors the output state of the load driving unit, and the level of the output signal of the load driving unit exceeds a predetermined limit with respect to the power supply voltage supplied to the load driving unit. When it is detected that the power supply voltage is approached, the power supply voltage supplied to the load drive unit is switched to a higher power supply voltage, so it is easier to design than the configuration that switches the power supply voltage based on the input signal. Yes, the power supply voltage can be switched stably and at an appropriate timing.

  In addition, according to the present embodiment, a charge pump having a high voltage output mode, a low voltage output mode, and a relay mode is adopted as the power supply circuit, and the control unit of the charge pump is operated in the low voltage output mode. When it is detected that the level of the output signal of the load drive unit has approached the power supply voltage beyond the predetermined limit, the operation mode of the charge pump is immediately changed from the low voltage output mode to the high voltage output mode to drive the load. When it is detected that the output signal level of the unit is not approaching the power supply voltage beyond a predetermined limit, the operation mode of the charge pump is changed from the high voltage output mode to the relay mode, and then the low voltage output Since the mode is shifted to the mode, the first and second output capacitors and the flying cap are operated during the operation in the high voltage output mode. The charge charged in the jitter can be reduced by going through the operation in the relay mode, and after the transition to the low voltage output mode, in the charge operation, the both ends of the flying capacitor and the first output capacitor connected in series are connected. The voltage can be prevented from becoming abnormally large, and smooth transition between modes can be realized.

  Further, according to the present embodiment, when it is detected that the level of the output signal of the load driving unit is not approaching the power supply voltage beyond a predetermined limit, a transition is made from the high voltage output mode to the relay mode, After that, since the transition to the low voltage output mode is made, for example, when the rate of increase in the level of the output signal of the load driving unit is slow, the transition between the modes between the low voltage output mode and the high voltage output mode is performed. It is possible to prevent the occurrence of frequent abnormality, and to stabilize the operation of the charge pump and the load driving unit.

  In the present embodiment, the smoothing operation is repeated in the relay mode. Therefore, when it is detected that the level of the output signal of the load driving unit has not approached the power supply voltage beyond the predetermined limit and the transition is made from the high voltage output mode to the relay mode, The charging voltages of the first and second output capacitors and the flying capacitor gradually decrease while maintaining the same magnitude. Therefore, in order to obtain the transition timing from the relay mode to the low voltage output mode, it is only necessary to monitor the charging voltage of one of the first output capacitor, the second output capacitor, or the flying capacitor, There is an advantage that only one circuit for monitoring the charging voltage of the capacitor is required.

<Other embodiments>
As mentioned above, although embodiment of this invention was described, various other embodiment can be considered to this invention. For example:

(1) In the relay mode, the all-OFF operation may be omitted, and the smoothing operation and the flying operation may be alternately repeated.

(2) In the above embodiment, in the relay mode, the charging voltage CPVDD of the first output capacitor C1 is monitored, and the transition to the low voltage output mode is performed when the voltage CPVDD becomes equal to or lower than αHPVDD. However, the charging voltage of the second output capacitor C2 or the flying capacitor C3 may be monitored.

(3) In the above embodiment, the transition from the relay mode to the low voltage output mode may be performed when the relay mode continues for a predetermined time or more while the output state detection signal DETO remains at the L level. When the relationship between the elapsed time after the transition to the relay mode and the charging voltages of the first output capacitor C1, the second output capacitor C2, and the flying capacitor C3 is stable, such a simple operation is possible. In the method, the same effect as the above embodiment can be obtained.

(4) In the above embodiment, the charge pump 1 that is a power supply circuit generates the positive power supply voltage CPVDD and the negative power supply voltage CPVSS around the ground level (the level of the terminal GND). A positive power supply voltage CPVDD and a negative power supply voltage CPVSS may be generated around the level.

(5) In the above embodiment, the charge pump 1 that is the power supply circuit generates the positive power supply voltage CPVDD and the negative power supply voltage CPVSS using the positive input power supplies HPVDD and SPVDD. A configuration may be employed in which positive power supply voltage CPVDD and negative power supply voltage CPVSS are generated.

(6) Although the field effect transistor is used as the switching element constituting the switch circuit 20 in the above embodiment, other types of switching elements such as bipolar transistors may be used.

(7) In the above embodiment, the charge pump 1 is used as the power supply circuit of the power amplifier circuit. However, the charge pump according to the present invention is applicable to uses other than the power amplifier circuit.

DESCRIPTION OF SYMBOLS 1 ... Charge pump, 2 ... Load drive part, C1 ... 1st output capacitor, C2 ... 2nd output capacitor, C3 ... Flying capacitor, 3, 3A, 3B, 3C ... Output state Detection unit, 10... Control unit, 20... Switch circuit, P1 to P5... P channel transistor, N1 to N3.

Claims (2)

A switch circuit interposed between the first and second output capacitors, the flying capacitor, and the input power supply;
A charge pump comprising a control unit for controlling the switch circuit,
The charge pump has a high voltage output mode, a low voltage output mode, and a relay mode as operation modes,
In the high voltage output mode, the control unit applies a first charge operation for applying an output voltage of the input power source to each of the flying capacitor and the first output capacitor, and the flying capacitor is used as the first capacitor. By causing the switch circuit to repeatedly perform a flying operation that is disconnected from one output capacitor and connected in parallel to the second output capacitor, positive and negative voltages are generated from the first and second output capacitors. Output
In the low voltage output mode, the flying capacitor and the first output capacitor are connected in series, and the output voltage of the input power supply is applied to the flying capacitor and the first output capacitor connected in series. A second charge operation; a smoothing operation in which the flying capacitor and the first output capacitor are connected in parallel; and the flying capacitor is separated from the first output capacitor and parallel to the second output capacitor. By causing the switch circuit to repeatedly execute a flying operation to be connected, positive and negative voltages lower than those output in the high voltage output mode are output from the first and second output capacitors. Let
In the relay mode, a smoothing operation of disconnecting the input power source from the first and second output capacitors and the flying capacitor, and connecting the flying capacitor and the first output capacitor in parallel; and the flying Causing the switch circuit to repeatedly perform a flying operation in which a capacitor is disconnected from the first output capacitor and connected in parallel to the second output capacitor;
When a boost command is given during a period in which the operation mode of the charge pump is the low voltage output mode, the operation mode of the switch circuit is changed from the low voltage output mode to the high voltage output mode,
When a step-down command is given during a period in which the operation mode of the charge pump is the high voltage output mode, the operation mode is changed from the high voltage output mode to the relay mode, and then the low voltage output mode is entered. A charge pump characterized by making a transition.   When the step-down command is given during the period in which the operation mode is the high voltage output mode, the control unit transitions the operation mode from the high voltage output mode to the relay mode, and then the first mode When the charging voltage of at least one of the output capacitor, the second output capacitor, or the flying capacitor falls below a predetermined threshold, the operation mode of the charge pump is changed from the relay mode to the low voltage output mode. 3. The charge pump according to claim 2, wherein transition is performed.

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