[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP2011066122A - Circuit board - Google Patents

Circuit board Download PDF

Info

Publication number
JP2011066122A
JP2011066122A JP2009214381A JP2009214381A JP2011066122A JP 2011066122 A JP2011066122 A JP 2011066122A JP 2009214381 A JP2009214381 A JP 2009214381A JP 2009214381 A JP2009214381 A JP 2009214381A JP 2011066122 A JP2011066122 A JP 2011066122A
Authority
JP
Japan
Prior art keywords
terminal electrode
electrode layer
support substrate
layer
resist layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009214381A
Other languages
Japanese (ja)
Inventor
Shunsuke Chisaka
俊介 千阪
Minoru Hatase
稔 畑瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2009214381A priority Critical patent/JP2011066122A/en
Publication of JP2011066122A publication Critical patent/JP2011066122A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To securely prevent peeling and damages such as cracking of a terminal electrode layer provided to a support substrate. <P>SOLUTION: The peripheral part 31 of the terminal electrode layer 3 provided to one principal surface of the support substrate 9 is continuously covered with a resist layer 2 except a part thereof to reinforce bonding between the terminal electrode layer 3 and support substrate 9, thereby preventing peeling of the terminal electrode layer 3 from the support substrate 9. Further, when coefficients of thermal expansion of the support substrate 9, terminal electrode layer 3 and resist layer 2 are greatly different from one another, for example, even when the support substrate 9, terminal electrode layer 3 and resist layer 2 are heated and expanded, and stress is produced, during a reflow treatment, since the produced stress is released through the part of the terminal electrode layer peripheral part 31, which is not covered with the resist layer 2, the terminal electrode layer 3 is prevented from peeling from the support substrate 9 or cracking. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

本発明は、支持基板の少なくとも一方の主面に端子電極層のパターンが形成された回路基板に関する。   The present invention relates to a circuit board in which a pattern of a terminal electrode layer is formed on at least one main surface of a support substrate.

従来、マザー基板に搭載される回路基板は、その支持基板の少なくとも一方の主面にランドやパッドなどの端子電極層のパターンが形成される。そして、端子電極層は銅箔などの電極材料により形成され、支持基板は樹脂やセラミックなどの絶縁材料を用いた単層、多層の構成である。そして、端子電極層を形成する材料と、支持基板を形成する材料とは異なる材質であり、機械的な摩擦や温度変化等の影響を受けてはがれるおそれがあるため、端子電極層と支持基板との接合を補強する種々の試みが行われている。例えば、支持基板の少なくとも一方の主面に設けられた端子電極層の周部を、絶縁材(レジスト)で覆って端子電極層を支持基板に押えつけ、端子電極層と支持基板との接合を補強することが提案されている(特許文献1,2参照)。   Conventionally, a circuit board mounted on a mother board has a pattern of terminal electrode layers such as lands and pads formed on at least one main surface of the support board. The terminal electrode layer is made of an electrode material such as copper foil, and the support substrate has a single layer or multilayer structure using an insulating material such as resin or ceramic. Since the material for forming the terminal electrode layer and the material for forming the support substrate are different materials and may be peeled off due to mechanical friction or temperature change, the terminal electrode layer and the support substrate Various attempts have been made to reinforce the bonding. For example, the peripheral portion of the terminal electrode layer provided on at least one main surface of the support substrate is covered with an insulating material (resist) so that the terminal electrode layer is pressed against the support substrate, and the terminal electrode layer and the support substrate are bonded. It has been proposed to reinforce (see Patent Documents 1 and 2).

図7(a),(b)に示すように、特許文献1に記載の回路基板300では、導体パッド301からなる端子電極層の外周部301aが全周に渡ってオーバーコート材302により被覆されている。一方、図8に示すように、特許文献2に記載の回路基板400では、導体401からなる端子電極層の2ヶ所が保護ガラス402により開口部403を挟んで被覆されることにより、導体ランド401aが形成されている。なお、図7(a),(b)はそれぞれ回路基板の断面図および平面図であり、図8は回路基板の平面図である。   As shown in FIGS. 7A and 7B, in the circuit board 300 described in Patent Document 1, the outer peripheral portion 301 a of the terminal electrode layer formed of the conductor pad 301 is covered with the overcoat material 302 over the entire periphery. ing. On the other hand, as shown in FIG. 8, in the circuit board 400 described in Patent Document 2, two portions of the terminal electrode layer made of the conductor 401 are covered with the protective glass 402 with the opening 403 sandwiched therebetween, whereby the conductor land 401a. Is formed. 7A and 7B are a sectional view and a plan view of the circuit board, respectively, and FIG. 8 is a plan view of the circuit board.

特開2002−198637号公報(段落[0018],[0020],[0021]、図1、要約書など)JP 2002-198637 (paragraphs [0018], [0020], [0021], FIG. 1, abstract, etc.) 特開平9−213881号公報(段落[0010],[0012]、図1など)Japanese Patent Laid-Open No. 9-213881 (paragraphs [0010], [0012], FIG. 1, etc.)

図7(a),(b)に示す回路基板300では、導体パッド301の外周部301aが全周に渡ってオーバーコート材302で被覆されて基板に押しつけられるため、支持基板303と導体パッド301との接合がオーバーコート材302により補強される。しかしながら、はんだリフローなどの際に支持基板303、オーバーコート材302および導体パッド301が加熱されると、それらの熱膨張係数の相違等に基づき、オーバーコート材302によって導体パッド301が外周部側から中心側に押されて、導体パッド301が浮き上がって支持基板303から剥離するおそれがあり、また、導体パッド301にひびが生じるおそれもある。   In the circuit board 300 shown in FIGS. 7A and 7B, the outer peripheral portion 301a of the conductor pad 301 is covered with the overcoat material 302 over the entire periphery and pressed against the substrate. The overcoat material 302 reinforces the bonding with the. However, when the support substrate 303, the overcoat material 302, and the conductor pad 301 are heated at the time of solder reflow or the like, the conductor pad 301 is moved from the outer peripheral side by the overcoat material 302 based on the difference in coefficient of thermal expansion. When pressed toward the center, the conductor pad 301 may be lifted and peeled off from the support substrate 303, and the conductor pad 301 may be cracked.

一方、図8に示す回路基板400では、導体401の2ヶ所が開口部403を挟んで保護ガラス402により被覆されて基板に押付けられる。この場合、導体401は保護ガラス402により周部の2ヶ所のみが部分的に被覆されるため、保護ガラス402が導体401を支持基板に押しつける力は、図7の回路基板300の例と比較して小さく、支持基板と導体401との接合が十分に補強されないおそれがある。   On the other hand, in the circuit board 400 shown in FIG. 8, two portions of the conductor 401 are covered with the protective glass 402 with the opening 403 interposed therebetween and pressed against the board. In this case, since the conductor 401 is partially covered with the protective glass 402 only at the two peripheral portions, the force of the protective glass 402 pressing the conductor 401 against the support substrate is compared with the example of the circuit board 300 in FIG. The connection between the support substrate and the conductor 401 may not be sufficiently reinforced.

また、複数の導体ランド401aは隣接して配置されるが、隣接する導体ランド401a間に保護ガラス402が設けられていないため、溶融したはんだなどの接合部材により導体ランド401a間が短絡するおそれもある。   Further, although the plurality of conductor lands 401a are disposed adjacent to each other, since the protective glass 402 is not provided between the adjacent conductor lands 401a, the conductor lands 401a may be short-circuited by a joining member such as molten solder. is there.

本発明は、支持基板に設けられた端子電極層の剥離やひび割れ等の損傷を確実に防止することを第1の目的とし、また、支持基板に島状に複数の端子電極層が設けられた場合には、併せて、それらの層間が溶融したはんだ等で短絡することを防止することを第2の目的とする。   The first object of the present invention is to reliably prevent damage such as peeling and cracking of the terminal electrode layer provided on the support substrate, and the support substrate is provided with a plurality of terminal electrode layers in an island shape. In some cases, the second object is to prevent short-circuiting between the layers with molten solder or the like.

上記した第1の目的を達成するために、本発明の回路基板は、支持基板と、前記支持基板の少なくとも一方の主面に設けられた端子電極層と、前記端子電極層を部分的に被覆するレジスト層とを備え、前記レジスト層は、前記端子電極層の周部のうち、前記支持基板の少なくとも一の端縁側を除く前記周部を連続的に覆うように設けられていることを特徴としている(請求項1)。   In order to achieve the first object described above, a circuit board according to the present invention includes a support substrate, a terminal electrode layer provided on at least one main surface of the support substrate, and partially covering the terminal electrode layer. A resist layer, and the resist layer is provided so as to continuously cover the peripheral portion of the terminal electrode layer excluding at least one edge side of the support substrate. (Claim 1).

また、本発明の回路基板の前記レジスト層は、前記レジスト層は、前記端子電極層と当該レジスト層との重合部分が、前記周部を除く前記端子電極層上の1点を原点とするX−Y座標軸のX軸、Y軸それぞれと前記端子電極層の周端との交点のうち少なくとも3点を含むことを特徴としている(請求項2)。   Further, the resist layer of the circuit board according to the present invention is such that the resist layer has a point where the overlapping portion of the terminal electrode layer and the resist layer is one point on the terminal electrode layer excluding the peripheral portion. It includes at least three points of intersections between the X-axis and Y-axis of the −Y coordinate axis and the peripheral edge of the terminal electrode layer (claim 2).

また、上記した第2の目的を達成するために、本発明の回路基板は、複数の前記端子電極層が前記主面の端縁に沿って島状に設けられ、前記レジスト層は、前記主面の前記各端子電極層間および前記主面の中央部分を覆うように設けられていることを特徴としている(請求項3)。   In order to achieve the second object, the circuit board of the present invention includes a plurality of the terminal electrode layers provided in an island shape along an edge of the main surface, and the resist layer includes the main layer. It is characterized by being provided so as to cover each terminal electrode layer of the surface and the central portion of the main surface (Claim 3).

また、本発明の回路基板は、前記レジスト層は、前記端子電極層の全ての隅部を覆うように設けられていることを特徴としている(請求項4)。   In the circuit board according to the present invention, the resist layer is provided so as to cover all corners of the terminal electrode layer.

請求項1の発明によれば、レジスト層は、支持基板の端縁側を除く端子電極層の周部を連続的に覆うように設けられているため、端子電極層はレジスト層により支持基板に押しつけられて、端子電極層と支持基板との接合が十分に補強される。この場合、機械的な衝撃が加えられても端子電極層は支持基板から容易に剥離することがない。   According to the invention of claim 1, since the resist layer is provided so as to continuously cover the peripheral portion of the terminal electrode layer excluding the edge side of the support substrate, the terminal electrode layer is pressed against the support substrate by the resist layer. Thus, the bonding between the terminal electrode layer and the support substrate is sufficiently reinforced. In this case, even if a mechanical impact is applied, the terminal electrode layer does not easily peel from the support substrate.

また、端子電極層の周部の一部がレジスト層により被覆されないため、例えばはんだリフローの際に、支持基板、端子電極層、レジスト層が加熱され、それらの熱膨張係数の差により生じる端子電極層を浮き上がらせようとする力は、端子電極層周部のレジスト層により被覆されない部分から逃がされ、端子電極層が支持基板から剥離したり、ひび割れたりすることがない。   In addition, since a part of the peripheral portion of the terminal electrode layer is not covered with the resist layer, for example, when the solder reflow is performed, the support substrate, the terminal electrode layer, and the resist layer are heated, and the terminal electrode is generated due to a difference in thermal expansion coefficient between them. The force to lift the layer is released from the portion not covered by the resist layer around the terminal electrode layer, and the terminal electrode layer is not peeled off from the support substrate or cracked.

また、はんだリフローなどの際に支持基板、端子電極層、レジスト層が加熱されて膨張しても、端子電極層を浮き上がらせようとする力(歪み)は、端子電極層の周部のレジスト層により被覆されない部分から支持基板の端縁側に逃がされて、支持基板の他の部分に影響を与えることがない。したがって、機械的な衝撃や加熱による端子電極層の破損を確実に防止することができ、回路基板の信頼性が向上する。   In addition, even when the support substrate, terminal electrode layer, and resist layer are heated and expanded during solder reflow, the force (strain) that causes the terminal electrode layer to lift up is affected by the resist layer around the terminal electrode layer. Therefore, the portion that is not covered with the base plate is released to the edge of the support substrate, and the other portions of the support substrate are not affected. Therefore, damage to the terminal electrode layer due to mechanical impact or heating can be reliably prevented, and the reliability of the circuit board is improved.

請求項2の発明によれば、レジスト層は、支持基板の少なくとも一方の主面に設けられた端子電極層の周部をその一部を除き連続的に覆い、かつ、端子電極層と当該レジスト層との重合部分が、周部を除く端子電極層上の1点を原点とするX−Y座標軸のX軸、Y軸それぞれと端子電極層の周端との交点のうち少なくとも3点を含むように設けられているため、端子電極層はレジスト層により3方向から支持基板に効率よく押え込まれて、端子電極層と支持基板との接合が十分に補強される。この場合、機械的な衝撃が加えられても端子電極層は支持基板から容易に剥離することがない。したがって、より確実に端子電極層の破損を防止することができる。   According to the invention of claim 2, the resist layer continuously covers a peripheral portion of the terminal electrode layer provided on at least one main surface of the support substrate except for a part thereof, and the terminal electrode layer and the resist The overlapping portion with the layer includes at least three points among the intersections of the X-axis and Y-axis of the XY coordinate axis and the peripheral edge of the terminal electrode layer with one point on the terminal electrode layer excluding the peripheral portion as the origin. Thus, the terminal electrode layer is efficiently pressed into the support substrate from three directions by the resist layer, and the bonding between the terminal electrode layer and the support substrate is sufficiently reinforced. In this case, even if a mechanical impact is applied, the terminal electrode layer does not easily peel from the support substrate. Therefore, damage to the terminal electrode layer can be prevented more reliably.

請求項3の発明によれば、複数の端子電極層が支持基板の主面の端縁に沿って島状に設けられ、レジスト層は、端子電極層が設けられた支持基板の主面の各端子電極層間および中央部分を覆うように設けられているため、各端子電極層間に設けられたレジスト層により、例えば溶融したはんだが端子電極層どうしを短絡するおそれがなく、支持基板に島状に設けられた複数の端子電極層間が短絡することも併せて確実に防止できる。   According to the invention of claim 3, the plurality of terminal electrode layers are provided in an island shape along the edge of the main surface of the support substrate, and the resist layer is provided on each of the main surfaces of the support substrate on which the terminal electrode layer is provided. Since it is provided so as to cover the terminal electrode layers and the central portion, the resist layer provided between the terminal electrode layers prevents, for example, molten solder from short-circuiting the terminal electrode layers, so that the support substrate has an island shape. A short circuit between a plurality of provided terminal electrode layers can also be reliably prevented.

請求項4の発明によれば、レジスト層は、端子電極層の全ての隅部を覆うように設けられているため、支持基板からの剥離が生じやすい端子電極層の角の部分である隅部が全てレジスト層により支持基板に押しつけられるため、端子電極層が支持基板から剥離することをさらに一層確実に防止できる。   According to the invention of claim 4, since the resist layer is provided so as to cover all the corners of the terminal electrode layer, the corner that is a corner portion of the terminal electrode layer that is likely to be peeled off from the support substrate. Are all pressed against the support substrate by the resist layer, so that the terminal electrode layer can be more reliably prevented from peeling from the support substrate.

本発明の回路基板を備える部品内蔵モジュールの第1実施形態を示す断面図である。It is sectional drawing which shows 1st Embodiment of a component built-in module provided with the circuit board of this invention. 図1の底面図である。It is a bottom view of FIG. 図1の部品内蔵モジュールの第2実施形態を示す底面図である。It is a bottom view which shows 2nd Embodiment of the component built-in module of FIG. 図1の部品内蔵モジュールの変形例を示す底面図である。It is a bottom view which shows the modification of the component built-in module of FIG. 図1の部品内蔵モジュールの変形例を示す底面図である。It is a bottom view which shows the modification of the component built-in module of FIG. (a)〜(c)は端子電極層の変形例を示す図である。(A)-(c) is a figure which shows the modification of a terminal electrode layer. 従来の回路基板の一例を示す図であって、(a)は断面図、(b)は平面図である。It is a figure which shows an example of the conventional circuit board, Comprising: (a) is sectional drawing, (b) is a top view. 従来の回路基板の一例を示す平面図である。It is a top view which shows an example of the conventional circuit board.

<第1実施形態>
本発明の回路基板を備える部品内蔵モジュール1の第1実施形態について、図1および図2を参照して説明する。
<First Embodiment>
1st Embodiment of the component built-in module 1 provided with the circuit board of this invention is described with reference to FIG. 1 and FIG.

図1は本発明の回路基板10を備える部品内蔵モジュール1の第1実施形態を示す断面図である。図1に示すように、部品内蔵モジュール1は、レジスト層2と、端子電極層3と、接続層4と、部品内蔵層5と、配線層6,8と、コア基板7とが積層され一体化されて形成されている。また、配線層8と電子部品ICの端子電極tICとが接続されることにより、部品内蔵モジュール1には電子部品ICが搭載されている。   FIG. 1 is a cross-sectional view showing a first embodiment of a component built-in module 1 including a circuit board 10 of the present invention. As shown in FIG. 1, the component built-in module 1 includes a resist layer 2, a terminal electrode layer 3, a connection layer 4, a component built-in layer 5, wiring layers 6 and 8, and a core substrate 7 laminated together. It is formed. Further, the electronic component IC is mounted on the component built-in module 1 by connecting the wiring layer 8 and the terminal electrode tIC of the electronic component IC.

部品内蔵層5は、封止用の樹脂層51に、部品52,53などの部品が設けられて形成されている。また、部品内蔵層5には必要に応じて導電性ペーストの充填、ビアフィルめっき等により形成された層間接続導体(ビア導体)54が設けられている。   The component built-in layer 5 is formed by providing components such as components 52 and 53 on a sealing resin layer 51. The component built-in layer 5 is provided with an interlayer connection conductor (via conductor) 54 formed by filling with a conductive paste, via fill plating, or the like as necessary.

樹脂層51は例えば熱硬化性の樹脂により形成されている。また、部品52,53などの各部品はコンデンサ、コイル、トランジスタなどの電子回路素子のチップであり左右端部に電極(外部電極)521,531を有している。熱硬化性の樹脂としては、エポキシ樹脂、フェノール樹脂、シアネート樹脂などがある。   The resin layer 51 is made of, for example, a thermosetting resin. Each component such as the components 52 and 53 is a chip of an electronic circuit element such as a capacitor, a coil, or a transistor, and has electrodes (external electrodes) 521 and 531 at the left and right ends. Examples of the thermosetting resin include an epoxy resin, a phenol resin, and a cyanate resin.

接続層4は、樹脂層51と同様の樹脂層41を有し、樹脂層41の必要な箇所にビア構造の層間接続導体42を設けて形成され、硬化した部品内蔵層5に接続層4を介して端子電極層3が貼り付けられる。また、コア基板7は、樹脂やセラミックなどで形成されており、必要な箇所にビア構造の層間接続導体71が設けられて形成されている。   The connection layer 4 includes a resin layer 41 similar to the resin layer 51, and is formed by providing an interlayer connection conductor 42 having a via structure at a necessary portion of the resin layer 41. The connection layer 4 is formed on the cured component built-in layer 5. The terminal electrode layer 3 is affixed. The core substrate 7 is formed of resin, ceramic, or the like, and is formed by providing an interlayer connection conductor 71 having a via structure at a necessary location.

配線層6,8は、例えば銅箔を配線パターンにしたがってレーザ加工やエッチング加工などして形成される。また、端子電極層3は、接続層4の一方の主面に設けられ、例えば銅箔を配線パターンにしたがってレーザ加工やエッチング加工などして形成される。そして、配線層6,8および端子電極層3として形成されたランドやパッドなどに層間接続導体42,54,71の端面が、合金や金属間化合物を形成することによって、あるいは、物理的に接触することによって接合することにより、配線層6,8および端子電極層3が接続される。   The wiring layers 6 and 8 are formed by, for example, laser processing or etching processing of copper foil according to a wiring pattern. The terminal electrode layer 3 is provided on one main surface of the connection layer 4, and is formed by, for example, laser processing or etching processing of a copper foil according to a wiring pattern. Then, the end faces of the interlayer connection conductors 42, 54, 71 are formed on the lands or pads formed as the wiring layers 6, 8 and the terminal electrode layer 3 by forming an alloy or an intermetallic compound, or in physical contact. As a result, the wiring layers 6 and 8 and the terminal electrode layer 3 are connected.

レジスト層2は、端子電極層3のはんだ付けが必要な部分を露出させて、端子電極層3を部分的に被覆するように設けられている。また、レジスト層2は、端子電極層3のはんだ付けが不要な部分を覆うことにより、端子電極層3に無駄なはんだが付着しないように、例えば熱硬化性エポキシ樹脂により形成されている。なお、レジスト層2を形成する材質としては、上記した材質に限られず、端子電極層3が設けられる接続層4(支持基板9)の種類に応じて、例えばガラスにより形成するなど、種々変更することができる。   The resist layer 2 is provided so as to partially cover the terminal electrode layer 3 by exposing a portion of the terminal electrode layer 3 that needs to be soldered. Further, the resist layer 2 is formed of, for example, a thermosetting epoxy resin so as to prevent unnecessary solder from adhering to the terminal electrode layer 3 by covering a portion of the terminal electrode layer 3 that does not require soldering. In addition, the material for forming the resist layer 2 is not limited to the above-described material, and various changes are made, for example, by using glass according to the type of the connection layer 4 (support substrate 9) on which the terminal electrode layer 3 is provided. be able to.

次に、図1の部品内蔵モジュール1の製造方法の一例についてその概略を説明する。まず、両面に配線層6,8を設けたコア基板7に部品52,53が実装される。そして、部品52,53が埋まるように未硬化の樹脂層51が充填されて加熱硬化された後、硬化した樹脂層51にビア孔が形成される。   Next, an outline of an example of a method for manufacturing the component built-in module 1 of FIG. 1 will be described. First, the components 52 and 53 are mounted on the core substrate 7 provided with the wiring layers 6 and 8 on both sides. Then, after filling the uncured resin layer 51 so as to fill the parts 52 and 53 and heat-curing, via holes are formed in the cured resin layer 51.

次に、未硬化の接続層4が用意され、接続層4にもビア孔が形成される。そして、樹脂層51(部品内蔵層5)および接続層4のビア孔に導電性ペーストが充填されたり、ビアフィルめっきが施されたりして層間接続導体42,54が形成される。   Next, an uncured connection layer 4 is prepared, and via holes are also formed in the connection layer 4. Then, the via holes in the resin layer 51 (component built-in layer 5) and the connection layer 4 are filled with a conductive paste or subjected to via fill plating to form the interlayer connection conductors 42 and 54.

続いて、接続層4に銅箔が貼り付けられ、エッチング加工などによって端子電極層3が形成される。そして、接続層4の一方の主面に形成された端子電極層3の周部を一部を除いて覆うように接続層4上にレジスト層2が形成される。   Subsequently, a copper foil is attached to the connection layer 4, and the terminal electrode layer 3 is formed by etching or the like. Then, resist layer 2 is formed on connection layer 4 so as to cover the peripheral portion of terminal electrode layer 3 formed on one main surface of connection layer 4 except for a part thereof.

その後、コア基板7の配線層8にはんだバンプなどを介して電子部品ICが実装されることにより、部品内蔵モジュール1が完成する。   Thereafter, the electronic component IC is mounted on the wiring layer 8 of the core substrate 7 via solder bumps, whereby the component built-in module 1 is completed.

以上のようにして、接続層4および部品内蔵層5を有する支持基板9が形成され、レジスト層2、端子電極層3、支持基板9および配線層6により回路基板10が構成されている。なお、端子電極層3は、回路基板10をマザー基板に接続する外部電極を構成する。   As described above, the support substrate 9 having the connection layer 4 and the component built-in layer 5 is formed, and the circuit substrate 10 is constituted by the resist layer 2, the terminal electrode layer 3, the support substrate 9 and the wiring layer 6. The terminal electrode layer 3 constitutes an external electrode that connects the circuit board 10 to the mother board.

次に、図2を参照して、レジスト層2が端子電極層3の周部31を被覆する構成について説明する。図2は、図1の底面図であって、レジスト層2が端子電極層3の周部31を被覆する様子を示す図である。   Next, a configuration in which the resist layer 2 covers the peripheral portion 31 of the terminal electrode layer 3 will be described with reference to FIG. FIG. 2 is a bottom view of FIG. 1 and shows a state in which the resist layer 2 covers the peripheral portion 31 of the terminal electrode layer 3.

図2に示すように、レジスト層2は、矩形状の端子電極層3の周部31のうち、支持基板9の一の端縁91に平行な一部を除いた部分を連続的に覆うように設けられている。そして、レジスト層2は、端子電極層3と当該レジスト層2との重合部分21が、周部31を除く端子電極層3上の1点を原点とするX−Y座標軸のX軸、Y軸それぞれと端子電極層3の周端33との交点のうち少なくとも3点を含むように設けられている。さらに、レジスト層2は、端子電極層3の全ての隅部32を覆うように設けられている。   As shown in FIG. 2, the resist layer 2 continuously covers a portion of the peripheral portion 31 of the rectangular terminal electrode layer 3 except for a portion parallel to one edge 91 of the support substrate 9. Is provided. The resist layer 2 has an X- and Y-axis of the XY coordinate axis where the overlapping portion 21 of the terminal electrode layer 3 and the resist layer 2 has one point on the terminal electrode layer 3 excluding the peripheral portion 31 as an origin. It is provided so as to include at least three of the intersections between each and the peripheral end 33 of the terminal electrode layer 3. Further, the resist layer 2 is provided so as to cover all the corners 32 of the terminal electrode layer 3.

したがって、この実施形態によれば、支持基板9の一方の主面に設けられた端子電極層3の周部31がその一部を除きレジスト層2により連続的に覆われており、かつ、端子電極層3と当該レジスト層2との重合部分21が、周部31を除く端子電極層3上の1点を原点とするX−Y座標軸のX軸、Y軸それぞれと端子電極層3の周端33との交点のうち少なくとも3点を含むようにレジスト層2が設けられているため、端子電極層3はレジスト層2により支持基板9に効率よく押え込まれて、端子電極層3と支持基板9との接合が補強され、例えば部品内蔵モジュール1に機械的な衝撃が加えられたときに端子電極層3が支持基板9から剥離することが防止される。   Therefore, according to this embodiment, the peripheral portion 31 of the terminal electrode layer 3 provided on one main surface of the support substrate 9 is continuously covered with the resist layer 2 except for a part thereof, and the terminal The overlapping portion 21 of the electrode layer 3 and the resist layer 2 has an X- and Y-axis axes of the X-Y coordinate axis and the periphery of the terminal electrode layer 3 with one point on the terminal electrode layer 3 excluding the peripheral portion 31 as the origin. Since the resist layer 2 is provided so as to include at least three of the intersections with the end 33, the terminal electrode layer 3 is efficiently pressed into the support substrate 9 by the resist layer 2, and the terminal electrode layer 3 is supported. The bonding with the substrate 9 is reinforced, and for example, the terminal electrode layer 3 is prevented from being peeled from the support substrate 9 when a mechanical impact is applied to the component built-in module 1.

また、支持基板9、端子電極層3およびレジスト層2のそれぞれの熱膨張係数が大きく異なるときに、例えばリフローの際に支持基板9、端子電極層3およびレジスト層2が加熱されて膨張することにより応力が生じても、端子電極層3の周部31の一部がレジスト層2により被覆されていないため、生じた応力は、端子電極層周部31のレジスト層2により被覆されない部分から逃げる。したがって、リフローの際の加熱などに起因して回路基板10を破損するおそれのある応力が生じても、端子電極層3が支持基板9から剥離したり、ひび割れたりすることが防止される。そのため、機械的な衝撃が部品内蔵モジュール1に加えられたり、部品内蔵モジュール1が加熱されたりしたときに、支持基板9に設けられた端子電極層3が破損することが防止されて、部品内蔵モジュール1(回路基板10)の信頼性が向上する。   Further, when the thermal expansion coefficients of the support substrate 9, the terminal electrode layer 3 and the resist layer 2 are greatly different, for example, the support substrate 9, the terminal electrode layer 3 and the resist layer 2 are heated and expanded during reflow. Even if stress is generated by the above, a part of the peripheral portion 31 of the terminal electrode layer 3 is not covered with the resist layer 2, so that the generated stress escapes from the portion of the terminal electrode layer peripheral portion 31 that is not covered with the resist layer 2. . Therefore, even if a stress that may damage the circuit board 10 due to heating during reflow or the like occurs, the terminal electrode layer 3 is prevented from being peeled off or cracked from the support substrate 9. Therefore, when a mechanical shock is applied to the component built-in module 1 or the component built-in module 1 is heated, the terminal electrode layer 3 provided on the support substrate 9 is prevented from being damaged, and the component built-in is prevented. The reliability of the module 1 (circuit board 10) is improved.

また、支持基板9の端縁91の側を除く端子電極層3の周部31がレジスト層2により連続的に覆われているため、例えばリフローの際に回路基板10が加熱されて、支持基板9、端子電極層3およびレジスト層2が膨張することにより回路基板10を破損するおそれのある応力が生じても、生じた応力は、端子電極層3の周部31がレジスト層102により被覆されない支持基板9の端縁91側から逃げることとなる。したがって、支持基板9、端子電極層103およびレジスト層102を形成する各材料が膨張することにより生じた応力(歪み)などが支持基板9の端縁91から支持基板9の外へと逃げる構造であるため、支持基板9に設けられた端子電極層3の破損を防止することができる。   Further, since the peripheral portion 31 of the terminal electrode layer 3 excluding the edge 91 side of the support substrate 9 is continuously covered with the resist layer 2, the circuit substrate 10 is heated at the time of reflow, for example. 9. Even if stress that may damage the circuit board 10 due to expansion of the terminal electrode layer 3 and the resist layer 2 occurs, the peripheral portion 31 of the terminal electrode layer 3 is not covered with the resist layer 102. It will escape from the edge 91 side of the support substrate 9. Therefore, a structure in which stress (strain) generated by expansion of each material forming the support substrate 9, the terminal electrode layer 103 and the resist layer 102 escapes from the edge 91 of the support substrate 9 to the outside of the support substrate 9. Therefore, damage to the terminal electrode layer 3 provided on the support substrate 9 can be prevented.

また、端子電極層3の全ての隅部32がレジスト層2により覆われているため、支持基板9からの剥離が生じやすい端子電極層3の角の部分である隅部32がレジスト層2により支持基板9に確実に押しつけられて、端子電極層3が支持基板9から剥離するのをさらに確実に防止できる。   In addition, since all the corners 32 of the terminal electrode layer 3 are covered with the resist layer 2, the corners 32 that are corner portions of the terminal electrode layer 3 that easily peel off from the support substrate 9 are covered with the resist layer 2. It is possible to further reliably prevent the terminal electrode layer 3 from being peeled from the support substrate 9 by being surely pressed against the support substrate 9.

<第2実施形態>
次に、図3を参照して部品内蔵モジュール1の第2実施形態について説明する。図3は図1の部品内蔵モジュール1の第2実施形態を示す底面図である。
Second Embodiment
Next, a second embodiment of the component built-in module 1 will be described with reference to FIG. FIG. 3 is a bottom view showing a second embodiment of the component built-in module 1 of FIG.

この第2実施形態が、上記した第1実施形態と異なる点は、図3に示すように、複数の端子電極層103が支持基板9の一方の主面の端縁91に沿って島状に設けられている点である。そして、レジスト層102は、支持基板9の主面の各端子電極層103間および主面の中央部分を覆うように設けられている。また、レジスト層2は、全周部のうち、支持基板9の端縁91側を除く端子電極層103の周部を覆うように設けられている。その他の構成は上記した第1実施形態と同様であるため、その構成の説明は同一符号を付すことにより省略する。   The second embodiment is different from the first embodiment described above in that a plurality of terminal electrode layers 103 are formed in an island shape along the edge 91 of one main surface of the support substrate 9 as shown in FIG. It is a point provided. The resist layer 102 is provided so as to cover between the terminal electrode layers 103 on the main surface of the support substrate 9 and the central portion of the main surface. The resist layer 2 is provided so as to cover the peripheral portion of the terminal electrode layer 103 excluding the end 91 side of the support substrate 9 among the entire peripheral portion. Since the other configuration is the same as that of the first embodiment described above, the description of the configuration is omitted by attaching the same reference numerals.

この第2実施形態によれば、上記した第1実施形態と同様の効果を奏することができるとともに、以下のような効果を奏することができる。すなわち、複数の端子電極層103が支持基板9の主面の端縁91に沿って島状に設けられており、端子電極層103が設けられた支持基板9の主面の各端子電極層103間および中央部分がレジスト層102により被覆されている。したがって、例えばリフローの際に、各端子電極層103間に設けられたレジスト層102により溶融したはんだが端子電極層103どうしを短絡するおそれがなく、支持基板9に島状に設けられた複数の端子電極層103間が短絡するのを確実に防止できる。   According to the second embodiment, the same effects as those of the first embodiment described above can be obtained, and the following effects can be obtained. That is, a plurality of terminal electrode layers 103 are provided in an island shape along the edge 91 of the main surface of the support substrate 9, and each terminal electrode layer 103 on the main surface of the support substrate 9 on which the terminal electrode layer 103 is provided. The middle and middle portions are covered with a resist layer 102. Therefore, for example, at the time of reflow, there is no possibility that the solder melted by the resist layer 102 provided between the terminal electrode layers 103 short-circuits the terminal electrode layers 103, and a plurality of island electrodes are provided on the support substrate 9. A short circuit between the terminal electrode layers 103 can be reliably prevented.

<第1変形例>
次に、図4を参照して部品内蔵モジュール1の第1変形例について説明する。図4は図1の部品内蔵モジュール1の第1変形例を示す底面図である。
<First Modification>
Next, a first modification of the component built-in module 1 will be described with reference to FIG. FIG. 4 is a bottom view showing a first modification of the component built-in module 1 of FIG.

この第1変形例が、上記した第2実施形態と異なる点は、図4に示すように、レジスト層112が、端子電極層113の支持基板9の端縁91側の境界と揃うようにして、支持基板9の主面の各端子電極層113間および主面の中央部分を覆うように設けられている点である。その他の構成は上記した第2実施形態と同様であるため、その構成の説明は同一符号を付すことにより省略する。   This first modification differs from the second embodiment described above in that the resist layer 112 is aligned with the boundary of the terminal electrode layer 113 on the edge 91 side of the support substrate 9 as shown in FIG. Further, it is provided so as to cover between the terminal electrode layers 113 on the main surface of the support substrate 9 and the central portion of the main surface. Since the other configuration is the same as that of the second embodiment described above, description of the configuration is omitted by attaching the same reference numerals.

この第1変形例によれば、上記した第1および第2実施形態と同様の効果を奏することができる。   According to this first modification, the same effects as those of the first and second embodiments described above can be obtained.

<第2変形例>
次に、図5を参照して部品内蔵モジュール1の第2変形例について説明する。図5は図1の部品内蔵モジュール1の第2変形例を示す底面図である。
<Second Modification>
Next, a second modification of the component built-in module 1 will be described with reference to FIG. FIG. 5 is a bottom view showing a second modification of the component built-in module 1 of FIG.

この第2変形例が、上記した第2実施形態と異なる点は、図5に示すように、端子電極層123の境界が、支持基板9の端縁91と揃うように端子電極層123が支持基板9に設けられている点である。そして、レジスト層122が、支持基板9の端縁91まで覆うようにして、支持基板9の主面の各端子電極層123間および主面の中央部分を覆うように設けられている。その他の構成は上記した第2実施形態と同様であるため、その構成の説明は同一符号を付すことにより省略する。   The second modification differs from the second embodiment described above in that the terminal electrode layer 123 is supported so that the boundary of the terminal electrode layer 123 is aligned with the edge 91 of the support substrate 9 as shown in FIG. This is a point provided on the substrate 9. Then, the resist layer 122 is provided so as to cover up to the edge 91 of the support substrate 9 so as to cover between the terminal electrode layers 123 on the main surface of the support substrate 9 and the central portion of the main surface. Since the other configuration is the same as that of the second embodiment described above, description of the configuration is omitted by attaching the same reference numerals.

この第2変形例によれば、上記した第1および第2実施形態と同様の効果を奏することができる。   According to the second modification, the same effects as those of the first and second embodiments described above can be obtained.

<端子電極層の変形例>
次に、図6を参照して端子電極層3,103,113,123の変形例について説明する。図6(a)〜(b)は端子電極層3,103,113,123の変形例を示す図である。
<Modification of terminal electrode layer>
Next, a modified example of the terminal electrode layers 3, 103, 113, 123 will be described with reference to FIG. FIGS. 6A to 6B are diagrams showing modifications of the terminal electrode layers 3, 103, 113, and 123.

図6(a)に示すように、端子電極層133は円形状に形成されている。そして、レジスト層132が、端子電極層133と当該レジスト層132との重合部分が、周部を除く端子電極層133上の1点を原点とするX−Y座標軸のX軸、Y軸それぞれと端子電極層133の周端との交点のうち少なくとも3点を含むように設けられている。   As shown in FIG. 6A, the terminal electrode layer 133 is formed in a circular shape. Then, the resist layer 132 is such that the overlapping portion of the terminal electrode layer 133 and the resist layer 132 has an X-Y coordinate axis and a Y-axis with one point on the terminal electrode layer 133 excluding the peripheral portion as the origin. The terminal electrode layer 133 is provided so as to include at least three of the intersections with the peripheral edge.

図6(b)に示すように、端子電極層143は円形の一部を切欠いた形状に形成されている。そして、レジスト層142が、端子電極層143と当該レジスト層142との重合部分が、周部を除く端子電極層143上の1点を原点とするX−Y座標軸のX軸、Y軸それぞれと端子電極層143の周端との交点のうち少なくとも3点を含むように設けられている。さらに、レジスト層142は、端子電極層143の全ての隅部を覆うように設けられている。   As shown in FIG. 6B, the terminal electrode layer 143 is formed in a circular shape with a part cut away. Then, the resist layer 142 is such that the overlapping portion of the terminal electrode layer 143 and the resist layer 142 has a point on the terminal electrode layer 143 excluding the peripheral portion as the origin, the X axis of the XY coordinate axis, and the Y axis respectively. The terminal electrode layer 143 is provided so as to include at least three of the intersections with the peripheral edge. Further, the resist layer 142 is provided so as to cover all corners of the terminal electrode layer 143.

図6(c)に示すように、端子電極層153はライン状に形成されている。そして、レジスト層152が、端子電極層153と当該レジスト層152との重合部分が、周部を除く端子電極層153上の1点を原点とするX−Y座標軸のX軸、Y軸それぞれと端子電極層153の周端との交点のうち少なくとも3点を含むように設けられている。   As shown in FIG. 6C, the terminal electrode layer 153 is formed in a line shape. Then, the resist layer 152 has a portion where the terminal electrode layer 153 and the resist layer 152 overlap with each other on the X- and Y-axes of the XY coordinate axes with one point on the terminal electrode layer 153 excluding the peripheral portion as the origin. The terminal electrode layer 153 is provided so as to include at least three of the intersections with the peripheral edge.

<その他>
なお、本発明は上記した実施形態に限定されるものではなく、その趣旨を逸脱しない限りにおいて、上記したもの以外に種々の変更を行なうことが可能であり、例えば、端子電極層3,103,113,123,133,143、153の周部のうち、レジスト層2,102,112,122,132,142,152により覆われない部分は、支持基板9の端縁91側に限られない。また、端子電極層3,103,113,123,133,143、153の全ての隅部がレジスト層2,102,112,122,132,142,152により覆われる必要はない。
<Others>
The present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit thereof, for example, the terminal electrode layers 3, 103, Of the peripheral portions of 113, 123, 133, 143, and 153, the portions that are not covered by the resist layers 2, 102, 112, 122, 132, 142, and 152 are not limited to the edge 91 side of the support substrate 9. Further, it is not necessary that all corner portions of the terminal electrode layers 3, 103, 113, 123, 133, 143, and 153 are covered with the resist layers 2, 102, 112, 122, 132, 142, and 152.

また、部品内蔵層5の各部品はどのような形状、大きさのものであってもよく、その個数などもどのようであってもよい。また、樹脂層51などは光硬化性樹脂などで形成されていてもよい。さらに、支持基板9は樹脂やセラミックの単層、多層の基板であってもよく、支持基板9の両面に端子電極層3,103,113,123,133,143、153を設けてもよい。そして、本発明は、種々の回路基板に適用することができる。   Further, each component of the component built-in layer 5 may have any shape and size, and the number thereof may be any. Further, the resin layer 51 and the like may be formed of a photocurable resin or the like. Further, the support substrate 9 may be a single layer or multilayer substrate of resin or ceramic, and the terminal electrode layers 3, 103, 113, 123, 133, 143, and 153 may be provided on both surfaces of the support substrate 9. The present invention can be applied to various circuit boards.

2,102,112,122,132,142,152 レジスト層
21 重合部分
3,103,113,123,133,143、153 端子電極層
31 周部
32 隅部
33 周端
9 支持基板
10 回路基板
2,102,112,122,132,142,152 Resist layer 21 Polymerized portion 3,103,113,123,133,143,153 Terminal electrode layer 31 Peripheral part 32 Corner part 33 Peripheral end 9 Support substrate 10 Circuit board

Claims (4)

支持基板と、
前記支持基板の少なくとも一方の主面に設けられた端子電極層と、
前記端子電極層を部分的に被覆するレジスト層とを備え、
前記レジスト層は、前記端子電極層の周部のうち、前記支持基板の少なくとも一の端縁側を除く前記周部を連続的に覆うように設けられていることを特徴とする回路基板。
A support substrate;
A terminal electrode layer provided on at least one main surface of the support substrate;
A resist layer partially covering the terminal electrode layer,
The circuit board, wherein the resist layer is provided so as to continuously cover the peripheral portion of the peripheral portion of the terminal electrode layer excluding at least one end side of the support substrate.
前記レジスト層は、前記端子電極層と当該レジスト層との重合部分が、前記周部を除く前記端子電極層上の1点を原点とするX−Y座標軸のX軸、Y軸それぞれと前記端子電極層の周端との交点のうち少なくとも3点を含む請求項1に記載の回路基板。   In the resist layer, the terminal portion of the terminal electrode layer and the resist layer is an X- and Y-axis axes of the X- and Y-coordinate axes with one point on the terminal electrode layer excluding the peripheral portion as the origin, and the terminal The circuit board according to claim 1, comprising at least three points of intersections with the peripheral edge of the electrode layer. 複数の前記端子電極層が前記主面の端縁に沿って島状に設けられ、
前記レジスト層は、前記主面の前記各端子電極層間および前記主面の中央部分を覆うように設けられている請求項1に記載の回路基板。
A plurality of the terminal electrode layers are provided in an island shape along an edge of the main surface,
The circuit board according to claim 1, wherein the resist layer is provided so as to cover the terminal electrode layers of the main surface and a central portion of the main surface.
前記レジスト層は、前記端子電極層の全ての隅部を覆うように設けられている請求項1ないし3のいずれかに記載の回路基板。   The circuit board according to claim 1, wherein the resist layer is provided so as to cover all corners of the terminal electrode layer.
JP2009214381A 2009-09-16 2009-09-16 Circuit board Pending JP2011066122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009214381A JP2011066122A (en) 2009-09-16 2009-09-16 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009214381A JP2011066122A (en) 2009-09-16 2009-09-16 Circuit board

Publications (1)

Publication Number Publication Date
JP2011066122A true JP2011066122A (en) 2011-03-31

Family

ID=43952089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009214381A Pending JP2011066122A (en) 2009-09-16 2009-09-16 Circuit board

Country Status (1)

Country Link
JP (1) JP2011066122A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013041647A (en) * 2011-08-17 2013-02-28 Dainippon Printing Co Ltd Suspension substrate
WO2022059455A1 (en) * 2020-09-17 2022-03-24 株式会社村田製作所 Electronic component

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001230513A (en) * 2000-02-15 2001-08-24 Denso Corp Printed board and its manufacturing method
JP2003249746A (en) * 2002-02-25 2003-09-05 Hitachi Ltd Printed wiring board
JP2005051240A (en) * 2003-07-29 2005-02-24 Samsung Electronics Co Ltd Semiconductor package having improved solder ball land structure
JP2006024858A (en) * 2004-07-09 2006-01-26 Audio Technica Corp Printed-wiring board and method for manufacturing the same
JP2009182330A (en) * 2008-01-30 2009-08-13 Samsung Electronics Co Ltd Printed circuit board, semiconductor package, card, and electronic system
JP2010086987A (en) * 2008-09-29 2010-04-15 Fujitsu Media Device Kk Electronic component module

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001230513A (en) * 2000-02-15 2001-08-24 Denso Corp Printed board and its manufacturing method
JP2003249746A (en) * 2002-02-25 2003-09-05 Hitachi Ltd Printed wiring board
JP2005051240A (en) * 2003-07-29 2005-02-24 Samsung Electronics Co Ltd Semiconductor package having improved solder ball land structure
JP2006024858A (en) * 2004-07-09 2006-01-26 Audio Technica Corp Printed-wiring board and method for manufacturing the same
JP2009182330A (en) * 2008-01-30 2009-08-13 Samsung Electronics Co Ltd Printed circuit board, semiconductor package, card, and electronic system
JP2010086987A (en) * 2008-09-29 2010-04-15 Fujitsu Media Device Kk Electronic component module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013041647A (en) * 2011-08-17 2013-02-28 Dainippon Printing Co Ltd Suspension substrate
WO2022059455A1 (en) * 2020-09-17 2022-03-24 株式会社村田製作所 Electronic component

Similar Documents

Publication Publication Date Title
US7884484B2 (en) Wiring board and method of manufacturing the same
JP4424449B2 (en) Component built-in module and manufacturing method thereof
JP4766049B2 (en) Manufacturing method of component built-in module and component built-in module
TWI387409B (en) Printed wiring board having a built-in semiconductor device and production process thereof
JP5195422B2 (en) Wiring board, mounting board, and electronic device
JP2768650B2 (en) Printed circuit board having solder ball mounting groove and ball grid array package using the same
JP2008226945A (en) Semiconductor device and its manufacturing method
JP4265607B2 (en) Laminated electronic component and mounting structure of laminated electronic component
JP2016063130A (en) Printed wiring board and semiconductor package
JP2005191156A (en) Wiring plate containing electric component, and its manufacturing method
US8507805B2 (en) Wiring board for semiconductor devices, semiconductor device, electronic device, and motherboard
US20190254164A1 (en) Circuit board, method of manufacturing circuit board, and electronic device
JP2008181977A (en) Package, manufacturing method thereof, semiconductor device using the same, and manufacturing method of semiconductor device using the same
JP2006134912A (en) Semiconductor module and its manufacturing method, and film interposer
JP2009135391A (en) Electronic device and method of manufacturing the same
JP4312148B2 (en) Relay board and three-dimensional wiring structure
JP6639934B2 (en) Wiring board, semiconductor device, and method of manufacturing wiring board
JP2011066122A (en) Circuit board
KR101483874B1 (en) Printed Circuit Board
US20120175158A1 (en) Circuit board
JP2009070898A (en) Component mounting substrate, electronic device, and component mounting method
JP4654971B2 (en) Multilayer semiconductor device
JP2009010201A (en) Printed circuit board and electronic apparatus
JP2004266271A (en) Electronic part mounting body and method for manufacturing the same
JP2001358445A (en) Mount structure of electronic component

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120619

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130620

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130625

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130821

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140304