JP2011050159A - Method of controlling single phase/three phase direct conversion devices - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of controlling single phase/three phase direct conversion devices wherein pulsation in an average DC voltage Vc can be reduced even with use of a non-linear capacitor circuit. <P>SOLUTION: The following processing is carried out in each predetermined period ts represented by the sum of first to third periods trec, tc, tz: in the first period trec, a current is passed through a single-phase diode rectifier 3 and in the third period tz, an inverter 5 is caused to carry out an operation using a zero-voltage vector as the voltage vector. In each of the predetermined periods, the following processing is carried out depending on single-phase AC voltage: when the absolute value of the single-phase AC voltage is lower than a predetermined value, capacitors C41, C42 are connected in parallel with each other in a second period tc; and when the absolute value of the single-phase AC voltage is higher than the predetermined value, a current is passed through the capacitors C41, C42 connected in series with each other in a second period tc. The maximum value in the second period tc obtained when the absolute value of the single-phase AC voltage is higher than the predetermined value is larger than the maximum value in the second period tc obtained when the absolute value of the single-phase AC voltage is lower than the predetermined value. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for controlling a single-phase / three-phase direct conversion device.

  Non-Patent Document 1 shows an example of a single-phase / three-phase direct conversion device. In such a single-phase / three-phase direct conversion device, a snubber circuit is provided on two DC power supply lines (DC links) that connect the single-phase diode rectifier and the inverter. This snubber circuit has a diode and a capacitor connected in series with each other, and a switch element connected in parallel with the diode. The diode is arranged with its anode facing the high potential side of the DC link and its cathode facing the low potential side.

  Non-Patent Document 1 discloses a technique for eliminating the power pulsation of a DC link caused by a single-phase diode rectifier by controlling such a switch element and an inverter.

  Note that Patent Documents 1 to 4 and Non-Patent Document 2 are disclosed as techniques related to the present application.

Patent No. 4049189 Patent No. 4238935 Japanese Patent No. 4135026 US Pat. No. 6,999,992

Yoshiya Onuma and Shinichi Ito, “Capacitor Reduction Method and Basic Verification Using a New Single-Phase Three-Phase Power Converter”, IEEJ Semiconductor Power Conversion Research Institute, SPC-08-162 (2008) Yota Yamashita et al., “Examination of application of single-phase / three-phase matrix converters to railway vehicles”, 2008 IEEJ Industrial Application Conference, 1-22

  Non-patent document 1 employs a snubber circuit having a switch element in a DC link. When the switch element becomes conductive and the capacitor is discharged, the voltage across the capacitor is applied to the input side of the inverter. At this time, a switching loss corresponding to the voltage across the capacitor occurs in the inverter.

  In order to reduce the switching loss, it is conceivable to employ a nonlinear capacitor circuit instead of the snubber circuit. The non-linear capacitor circuit has a plurality of capacitors and switch elements, and currents flow from the high potential side DC power supply line to the low potential side DC power supply line in series with each other through the plurality of capacitors. Current is passed through the plurality of capacitors in parallel with each other from the DC power supply line on the potential side to the DC power supply line on the high potential side.

  By employing such a non-linear capacitor circuit, the voltage applied to the inverter can be reduced when the capacitor is connected to the inverter in a parallel state, so that the switching loss generated in the inverter can be reduced.

  Consider a case where the control shown in Non-Patent Document 1 is executed for a single-phase / three-phase direct conversion device having such a configuration. However, the voltage across the nonlinear capacitor circuit varies greatly between discharging and charging. Therefore, when the control shown in Non-Patent Document 1 is simply applied and executed, the average of the voltage between the DC links with respect to the power supply cycle is not constant but pulsates. Such pulsation is not preferable, and it has been desired to suppress the average fluctuation of the DC voltage caused by the pulsation, especially the decrease in the average.

  Therefore, the present invention provides a control method for a single-phase / three-phase direct conversion device that can suppress a decrease in the average of DC voltage due to pulsation while providing a nonlinear capacitor circuit in the DC link.

  A first aspect of the control method of the single-phase / three-phase direct conversion device according to the present invention is connected to a single-phase diode rectifier (3) to which a single-phase AC voltage is input and an output side of the single-phase diode rectifier. A first power supply line (LH), a second power supply line (LL) connected to the output side of the single-phase diode rectifier and applied with a potential lower than that of the first power supply line, and the first power supply line (LL). And N (N is a natural number of 2 or more) capacitors (C41 to C43) provided between the second power supply lines, and the first power supply line to the second power supply line. The current flowing through the N capacitors flows through the N capacitors connected in series with each other, and the current flowing from the second power supply line to the first power supply line passes through the N capacitors connected in parallel with each other. A flowing non-linear capacitor circuit (4) and said first and front A method for controlling a single-phase / three-phase direct conversion device including an inverter (5) that receives a voltage between second power supply lines and operates based on a voltage vector, the first to third periods In each of the predetermined predetermined periods (ts) represented by the sum of (trec, tc, tz), a current is passed through the single-phase diode rectifier during the first period, and the voltage vector is supplied to the inverter during the third period. In the second period, the N capacitors are connected in parallel when the absolute value of the single-phase AC voltage is lower than a predetermined value in each of the predetermined periods. When the absolute value of the single-phase AC voltage is higher than the predetermined value, a current is passed through the N capacitors connected in series in the second period, and the absolute value of the single-phase AC voltage is Maximum value of the second period of time serial lower than a predetermined value is larger than the maximum value of the second period when the absolute value of the single-phase AC voltage is higher than the predetermined value.

  A second aspect of the method for controlling a single-phase / three-phase direct conversion apparatus according to the present invention is a method for controlling a single-phase / three-phase direct conversion apparatus according to the first aspect, wherein the absolute value of the single-phase AC voltage is The maximum value of the second period (tc) when the value is lower than the predetermined value is (2N−1) of the maximum value of the second period when the absolute value of the single-phase AC voltage is higher than the predetermined value. ) Smaller than twice.

  A third aspect of the method for controlling a single-phase / three-phase direct conversion apparatus according to the present invention is a method for controlling a single-phase / three-phase direct conversion apparatus according to the first aspect, wherein the absolute value of the single-phase AC voltage is The maximum value of the second period (tc) when the value is lower than the predetermined value is N times the maximum value of the second period when the absolute value of the single-phase AC voltage is higher than the predetermined value. .

  A fourth aspect of the method for controlling a single-phase / three-phase direct conversion apparatus according to the present invention is a method for controlling a single-phase / three-phase direct conversion apparatus according to any one of the first to third aspects, The N capacitors are charged in advance so that the voltage across each of the N capacitors (C41 to C43) is equal to or higher than the predetermined value.

  A fifth aspect of the method for controlling a single-phase / three-phase direct conversion apparatus according to the present invention is a method for controlling a single-phase / three-phase direct conversion apparatus according to any one of the first to fourth aspects, The nonlinear capacitor circuit (4) is provided between the N capacitors (C41 to C43), and has an anode as the first power line (LH) and a cathode as the second power line (LL). First to (N-1) th charging diodes (D41, D44) connected in series with the Nth capacitor toward each other, and each of the first to (N-1) th charging diodes. Between the anode and the capacitor provided adjacent to the anode and between the second power line and the anode on the second power line side and the cathode on the first power line side (N 1) between the first discharging diodes (D43, D46), the cathodes of the first to (N-1) th charging diodes, and the capacitor provided adjacent to the cathode; And (N-1) second power sources arranged between the first power source line and an anode facing the second power source line side and a cathode facing the first power source line side, respectively. The discharge diodes (D42, D45), the (N-1) first discharge diodes, and the (N-1) second discharge diodes 2 (N-1) directly connected to the discharge diodes (D42, D45), respectively. ) Switches (S41 to S44).

  A sixth aspect of the method for controlling a single-phase / three-phase direct conversion apparatus according to the present invention is a method for controlling a single-phase / three-phase direct conversion apparatus according to any one of the first to fourth aspects, The non-linear capacitor circuit (4) is provided between the N capacitors with the anode facing the first power line (LH) and the cathode facing the second power line (LL), respectively. Thru (N-1) charging diode (D41), and between each of the anodes of the first to (N-1) charging diodes and the capacitor provided adjacent to the anode, (N-1) first discharges provided between the second power line and having an anode facing the second power line and a cathode facing the first power line, respectively. Diode (D43) and the second to Nth diodes Between each cathode of the power diode and the capacitor provided adjacent to the cathode and between the first power supply lines, an anode is provided on the second power supply line side and a cathode is provided on the first power supply line side. (N-1) second discharge diodes (D42) disposed toward the respective power supply line sides, anodes of the (N-1) first discharge diodes, and the second A switch element (S47) provided between the power supply lines or between the cathodes of the (N-1) second discharge diodes and the first power supply line, and an anode serving as the first power supply line And an Nth charging diode (D47) connected in parallel with the switch element with the cathode directed toward the second power supply line.

  According to the first aspect of the control method of the single-phase / three-phase direct conversion device according to the present invention, the first and second power lines in the second period when the absolute value of the single-phase AC voltage is higher than the predetermined value. Is equal to the sum of the voltages across the N capacitors. If a current flows through N capacitors connected in parallel from the second power supply line to the first power supply line in the second period when the absolute value of the single-phase AC voltage is lower than the predetermined value, the first And the voltage between the second power supply lines is equal to each of the voltages across the N capacitors.

  Further, the maximum value of the second period when the absolute value of the single-phase AC voltage is higher than the predetermined value is larger than the maximum value of the second period when the absolute value of the single-phase AC voltage is lower than the predetermined value. As a result, the average of the voltages between the first and second power supply lines by the N capacitors when the absolute value of the single-phase AC voltage is low is obtained by calculating the N capacitors when the absolute value of the single-phase AC voltage is high. It is possible to approach the average of the voltage between the first and second power supply lines.

  Therefore, it is possible to suppress a decrease in voltage of the first and second power supply lines due to the use of the nonlinear capacitor circuit.

  Moreover, since the maximum value of the second period when the absolute value of the single-phase AC voltage is low is increased, the third period at this time can be reduced. In the third period, when the inverter performs an operation using the zero voltage vector as the voltage vector, the third period can be reduced, so the ratio of the average output voltage of the inverter to the average DC voltage (voltage utilization rate). ) Can be increased.

  According to the second aspect of the control method of the single-phase / three-phase direct conversion device according to the present invention, it is possible to suppress an increase in the voltage of the first and second power supply lines due to the use of the nonlinear capacitor circuit. it can.

  According to the third aspect of the method for controlling the single-phase / three-phase direct conversion device according to the present invention, the pulsation of the voltage of the first and second power supply lines due to the use of the nonlinear capacitor circuit is most suppressed. Can do.

  According to the fourth aspect of the control method of the single-phase / three-phase direct conversion device according to the present invention, when the absolute value of the single-phase AC voltage is lower than the predetermined value, the voltage across the capacitor is equal to or higher than the single-phase AC voltage. Therefore, when the absolute value of the single-phase AC voltage is lower than a predetermined value, the current can be surely passed by the N capacitors connected in parallel from the second power supply line to the first power supply line. it can.

  According to the fifth aspect of the control method of the single-phase / three-phase direct conversion device according to the present invention, it contributes to the realization of the single-phase / three-phase direct conversion device according to claims 1 to 4.

  According to the sixth aspect of the control method of the single-phase / three-phase direct conversion device according to the present invention, the function of the non-linear capacitor circuit can be realized by one switch element, so that compared to the case where a plurality of switch elements are provided Manufacturing cost can be reduced.

It is a figure which shows an example of a notional structure of a single phase / three phase direct conversion circuit. It is a figure which shows the equivalent circuit of a single phase / three phase direct conversion circuit. It is a graph which shows an example of a current distribution rate. It is a figure which shows an example of the timing chart in an equivalent circuit. It is a figure which shows a voltage vector. It is a figure which shows an example of the timing chart of an inverter. It is a graph which shows an example of the average of DC voltage. It is a figure which shows DC voltage, input line current, output line current, output line voltage, and the average of output line voltage. It is a figure which shows an example of a notional structure of a control part. It is a graph which shows an example of the timing chart of an equivalent circuit and an inverter. It is a graph which shows an example of a current distribution rate. It is a graph which shows an example of the average of DC voltage. It is a figure which shows DC voltage, input line current, output line current, output line voltage, and the average of output line voltage. It is a graph which shows an example of the average of DC voltage. It is a figure which shows an example of a notional structure of a single phase / three phase direct conversion apparatus. It is a figure which shows an example of a notional structure of a nonlinear capacitor circuit. It is a figure which shows an example of a notional structure of a nonlinear capacitor circuit. It is a graph which shows an example of a current distribution rate. It is a graph which shows an example of the average of DC voltage.

First embodiment.
<Configuration of single-phase / three-phase direct conversion device>
As shown in FIG. 1, the single-phase / three-phase direct conversion apparatus includes a single-phase diode rectifier 3, a nonlinear capacitor circuit 4, and an inverter 5.

  The single-phase diode rectifier 3 is connected to the single-phase AC power source 1 via, for example, a filter 2. The filter 2 includes a reactor L2 and a capacitor C2. The reactor L <b> 2 is provided between one of the two output terminals of the single-phase AC power source 1 and the single-phase diode rectifier 3. The capacitor C2 is provided between the two output terminals of the single-phase AC power source 1. The filter 2 removes the high frequency component of the current.

  The single-phase diode rectifier 3 includes diodes D31 to D34. The diodes D31 to D34 constitute a bridge circuit, which rectifies the single-phase AC voltage input from the single-phase AC power supply 1 and converts it to a DC voltage, and outputs this between the DC power supply lines LH and LL. A higher potential than the DC power supply line LL is applied to the DC power supply line LH.

  The non-linear capacitor circuit 4 has N (N is a natural number of 2 or more) capacitors provided between the DC power supply lines LH and LL, and flows through the N capacitors from the DC power supply line LH to the DC power supply line LL. The current flows through N capacitors connected in series with each other, and the current flowing from the DC power supply line LL to the DC power supply line LH flows through the N capacitors connected in parallel with each other. In the illustration of FIG. 1, the nonlinear capacitor circuit 4 includes two capacitors C41 and C42, diodes D41 to D43, and switching elements S41 and S42.

  The diode D41 is provided between the DC power supply lines LH and LL with the anode directed toward the DC power supply line LH and the cathode directed toward the DC power supply line LL. Capacitors C41 and C42 are provided on the DC power supply lines LH and LL, respectively, with respect to the diode D41, and are connected in series with the diode D41.

  The switching element S41 and the diode D42 are provided in series with each other between a point between the cathode of the diode D41 and the capacitor C42 and the DC power supply line LH. The switching element S42 and the diode D43 are provided in series with each other between the point between the anode of the diode D41 and the capacitor C41 and the DC power supply line LL. The diodes D42 and D43 are arranged with their anodes facing the DC power supply line LL and their cathodes facing the DC power supply line LH. The switching elements S41 and S42 are transistors, for example, and are arranged with their emitter terminals facing the DC power supply line LH and their collector terminals facing the DC power supply line LL.

  According to the nonlinear capacitor circuit 4, current flows from the DC power supply line LH to the DC power supply line LL side via the capacitors C41 and C42 and the diode D41, so that the capacitors C41 and C42 flow in series with each other. . Further, due to the conduction of the switching elements S41 and S42, the capacitors C41 and C42 flow in current from the DC power supply line LL to the DC power supply line LH in a parallel state.

  The inverter 5 converts the DC voltage between the DC power supply lines LH and LL into an AC voltage and outputs it to the output terminals Pu, Pv and Pw. The inverter 5 includes six switching elements Sup, Svp, Swp, Sun, Svn, and Swn. The switching elements Sup, Svp, Swp are respectively connected between the output terminals Pu, Pv, Pw and the DC power supply line LH, and the switching elements Sun, Svn, Swn are respectively connected to the output terminals Pu, Pv, Pw and the DC power supply line LL. Connected between. The inverter 5 constitutes a so-called voltage source inverter and includes six diodes Dup, Dvp, Dwp, Dun, Dvn, Dwn.

  The diodes Dup, Dvp, Dwp, Dun, Dvn, and Dwn are all arranged with the cathode facing the DC power supply line LH and the anode facing the DC power supply line LL. The diode Dup is connected in parallel with the switching element Sup between the output terminal Pu and the DC power supply line LH. Similarly, the diodes Dvp, Dwp, Dun, Dvn, Dwn are connected in parallel with the switching elements Svp, Swp, Sun, Svn, Swn, respectively.

  For example, IGBTs (insulated gate bipolar transistors, hereinafter simply referred to as IGBTs) are employed as the switching elements Sup, Svp, Swp, Sun, Svn, and Swn.

  The inductive load 6 is, for example, a rotating machine, and is illustrated by an equivalent circuit indicating that it is an inductive load. Specifically, the reactor Lu and the resistor Ru are serially connected to each other, and one end of the serial body is connected to the output end Pu. The same applies to reactors Lv and Lw and resistors Ru and Rw. The other ends of these series bodies are connected to each other.

<Control method of single-phase / three-phase direct conversion device>
In this single-phase / three-phase direct conversion device, a single-phase AC power source 1 and a single-phase diode rectifier 3 are used. Therefore, the power supplied to the DC power supply lines LH and LL pulsates with a frequency twice the frequency of the single-phase AC voltage, if the subsequent elements including the nonlinear capacitor circuit 4 are ignored. Here, a control method for reducing such power pulsation will be described.

  According to the equivalent circuit (FIG. 2) of the circuit shown in FIG. 1, the current Idc input to the inverter includes the current Ic flowing through the capacitors C41 and C42, the current Irec flowing through the single-phase diode rectifier 3, and the inverter 5 Is distributed to the current Iz flowing during the period of operation with the zero voltage vector. According to the equivalent circuit, the currents Ic, Irec, and Iz flow through the conduction of the switches Sc, Srec, and Sz, respectively. Each switch Srec, Sc, Sz is controlled so that only one of them is always conducted. Although details will be described later, there is a period in which the inverter 5 operates with a zero voltage vector even in a period in which the switches Srec and Sc are conductive. Here, the current Iz excludes a period in which the inverter 5 operates with a zero voltage vector in a period in which the switches Srec and Sc are conductive.

  If the current distribution ratios for the currents Irec, Ic, and Iz are drec, dc, and dz, respectively, the following equations are derived. Each current distribution rate drec, dc, dz can also be grasped as a ratio of the conduction period of the switches Srec, Sc, Sz to a predetermined period.

  Since the sum of the currents Irec, Ic, and Iz is equal to the current Idc from the continuity of the current, the following equation is established.

  First, the current distribution ratio drec is considered under the condition that the input current is a sine wave. In order to make the input current a sine wave, the current Irec should satisfy the following equation.

  Here, Im indicates the amplitude of the input current input to the single-phase diode rectifier 3. ωt indicates the phase of the single-phase AC voltage input to the single-phase diode rectifier 3. From equation (1) and equation (3), the current distribution ratio drec is expressed by the following equation.

  Furthermore, the current distribution ratio dc is considered under the condition of reducing power pulsation. The electric power P1 output from the single-phase diode rectifier 3 is expressed by the following equation.

  Here, Vm represents the amplitude of the single-phase AC voltage. In Equation (5), the second item on the right side indicates power pulsation. In order to cancel such power pulsation, the non-linear capacitor circuit 4 may output the power P2 having the same value as that of the second item and having a different polarity. Such electric power P2 is expressed by the following equation.

  The electric power P2 output from the nonlinear capacitor circuit 4 can take a positive or negative value from the equation (6). Specifically, when the phase ωt of the single-phase AC voltage is 0 or more and π / 4 or less, 3π / 4 or more, 5π / 4 or less, or 7π / 4 or more and 2π or less, a positive value is taken. Take a negative value.

  Since the single-phase AC voltage is expressed by Vm · sin (ωt), in other words, when the absolute value of the single-phase AC voltage is lower than 1 / √2 times the amplitude Vm, the nonlinear capacitor It can be understood that the circuit 4 outputs positive power and outputs negative power when the value is higher than 1 / √2 times the amplitude Vm.

  In order to output such positive and negative power, the direction of the current Ic flowing through the nonlinear capacitor circuit 4 may be changed. Specifically, for example, the following control may be performed to change the direction of the current Ic. That is, if each of the voltages at both ends of the capacitors C41 and C42 is higher than the absolute value of the single-phase AC voltage, a positive current Ic flows through the capacitors C41 and C42 by turning on the switching elements S41 and S42. In other words, the capacitors C41 and C42 are discharged. Also, a negative voltage Ic flows in the capacitors C41 and C42 by outputting a reverse voltage vector, which will be described later, by switching control of the inverter 5 and thereby causing a regenerative current to flow from the inverter 5 side to the nonlinear capacitor circuit 4. In other words, the capacitors C41 and C42 are charged. Therefore, if the respective charging voltages of the capacitors C41 and C42 are set to Vm / √2 or more in advance, the above-described positive and negative power can be output.

  Capacitors C41 and C42 discharge in parallel with each other. Therefore, at the time of discharge (that is, 0 ≦ ωt ≦ π / 4, 3π / 4 ≦ ωt ≦ 5π / 4, 7π / 4 ≦ ωt ≦ 2π, in other words, the absolute value of the single-phase AC voltage is from Vm / √2. When it is small), the nonlinear capacitor circuit 4 outputs a half value of the voltage Vc obtained by summing the voltages at both ends of the capacitors C41 and C42.

  Capacitors C41 and C42 are charged in series with each other. Therefore, at the time of charging (that is, when π / 4 ≦ ωt ≦ 3π / 4, 5π / 4 ≦ ωt ≦ 7π / 4, in other words, when the absolute value of the single-phase AC voltage is larger than Vm / √2), The non-linear capacitor circuit 4 outputs a voltage Vc that is the sum of both-end voltages written by the capacitors C41 and C42.

  Therefore, the electric power P2 output from the non-linear capacitor circuit 4 is divided into the electric power P2 at the time of charging and the electric power P2 at the time of discharging, and is expressed by the following equations, respectively.

  When the equation (6) and the equation (7) are modified, and the equation (6) and the equation (8) are modified, the current Ic flowing through the capacitors C41 and C42 during charging and the capacitor C41 during discharging. , C42, the following equations are derived for the current Ic flowing through C42.

  Since the direction of the current Ic can be controlled as described above, the current distribution ratio dc can be considered as a positive value. Therefore, the current distribution ratio dc for the capacitors C41 and C42 during charging and the current distribution ratio dc for the capacitors C41 and C42 during discharging are obtained by Expressions (1) and (9) and Expressions (1) and (10). Are represented by the following equations.

  As can be understood from the equations (4), (11), and (12), each of the current distribution ratios drec and dc is a sine wave having the same frequency as the frequency of the single-phase power supply voltage and a frequency that is twice as high. It has the same shape as the absolute value of, and only its amplitude is not determined.

  Further, the parameter Im / Idc is considered under the condition that the voltage utilization rate is maximized. The voltage utilization rate here is, for example, the ratio of the voltage output by the inverter 5 to the DC voltage between the DC power supply lines LH and LL. Since the inverter 5 does not output a voltage during the period in which the inverter 5 outputs the zero voltage vector, it is desirable that the period is short in order to improve the voltage utilization rate. However, as can be understood from the equations (2), (4), (11), and (12), the current distribution ratio dz cannot always be zero. The current distribution ratios drec, dc, and dz are all positive numbers. Therefore, if the minimum value of the current distribution ratio dz is 0, the overall voltage utilization rate can be maximized. In other words, dz = 0 may be set when the sum of the current distribution ratios drec and dc is maximized, that is, when ωt = π / 2.

  For example, substituting ωt = π / 2 and dz = 0 into Equation (2), Equation (4), and Equation (11) respectively leads to the following equation.

  For example, substituting ωt = π / 2 and dz = 0 into Equation (2), Equation (4), and Equation (12) respectively leads to the following equation.

  When Expression (13) is substituted into Expression (4) and Expression (11), current distribution ratios drec and dc during charging are expressed by the following expressions.

  When Expression (14) is substituted into Expressions (4) and (12), current distribution ratios drec and dc at the time of discharge are expressed by the following expressions.

  FIG. 3 shows an example of such current distribution rates drec, dc, and dz. In FIG. 3, the amplitude Vm and the voltage Vc are set to the same value. The current distribution rates drec, dc, and dz all have a voltage phase angle and a period of 180 degrees. The current distribution rate drec has a shape along a positive sine wave having a voltage phase angle of 180 degrees as a half cycle. However, the amplitude of the sine wave along the current distribution ratio drec during charging is larger than the amplitude of the sine wave along the current distribution ratio drec during discharging. Further, in order to eliminate the discontinuity between the current distribution ratio drec during charging and the current distribution ratio drec during discharge, these are appropriately connected by, for example, a straight line having a predetermined slope. This is because if there is discontinuity, the waveform of the input current is distorted. The current distribution ratio dc has a shape along a positive sine wave having a voltage phase angle of 90 degrees as a half cycle. However, the amplitude of the sine wave along which the current distribution ratio dc during discharging is larger than the amplitude of the sine wave along with the current distribution ratio dc during charging.

  By using such current distribution ratios drec, dc, and dz as command values and comparing them with a predetermined carrier, the periods trec, tc, and tz for conducting the switches Srec, Sc, and Sz, respectively, are obtained in a certain predetermined period ts. Can do. The predetermined period ts is a period sufficiently short with respect to the cycle of the single-phase AC voltage.

  Such periods trec, tc, and tz can be obtained by comparing the carrier C with the current distribution ratio drec, the sum of the current distribution ratios drec and dz (= 1-dc), as shown in FIG. The carrier C has a periodic waveform having a minimum value of 0 and a maximum value of 1, for example, a triangular wave, and an isosceles triangular wave is illustrated in FIG.

  The switch Srec is turned on during a period trec in which the carrier C is equal to or less than the current distribution ratio drec. The switch Sc is conductive during a period tc in which the carrier C is equal to or greater than the sum of the current distribution ratios drec and dz. The switch Sz is turned on during a period tz in which the carrier C is equal to or greater than the current distribution ratio drec and equal to or less than the sum drec + dz of the current distribution ratio. Accordingly, the ratios of the periods trec, tc, and tz with respect to the predetermined period ts can be matched with the current distribution ratios drec, dc, and dz, respectively. Note that since the carrier C is an isosceles triangular wave and neither the current distribution ratio drec nor the sum of current distribution ratios drec + dz takes the minimum value or the maximum value of the carrier C, the period tz is equal to two in the predetermined period ts. Divided equally and appears as two periods tz / 2.

  Note that the switches Srec, Sc, and Sz are not actually provided in the single-phase / three-phase direct conversion device shown in FIG. The switches Srec, Sc, Sz on the equivalent circuit shown in FIG. 2 are equivalently controlled by switching of the nonlinear capacitor circuit 4 and the inverter 5. In order to explain a method for equivalently controlling the switches Srec, Sc, Sz, first, general control of the inverter will be explained.

  The pair of switching elements Sup and Sun, the pair of switching elements Svp and Svn, and the pair of switching elements Swp and Swn are controlled exclusively with each other. Therefore, there are the following eight patterns as the switch pattern of each switching element. Here, a switch state in which the upper switching element is conductive and the lower switching element is non-conductive is expressed by “1”, and a switch state in which the upper switching element is non-conductive and the lower switching element is conductive is “0”. It expresses with. When the switch states for each phase are arranged in this order, the switch pattern is (0, 0, 0) (0, 0, 1) (0, 1, 0) (0, 1, 1) (1, 0 , 0) (1, 0, 1) (1, 1, 0) (1, 1, 1).

  When the inverter realizes each switch pattern described above, a voltage vector corresponding to the switching pattern is output to the output terminals Pu, Pv, and Pw. The voltage vectors output by each switch pattern are expressed as voltage vectors V0 to V7, respectively, by adopting numbers that represent the above three numbers of the switch patterns in decimal numbers. For example, the voltage vector V4 is output by the switch pattern (1, 0, 0).

  FIG. 5 shows a voltage vector diagram. The voltage vectors V1 to V6 are arranged such that their start points coincide with the center point and their end points are radially directed outward. When the end points of the voltage vectors V1 to V6 are connected, a regular hexagon is formed. Since the output terminals Pu, Pv, and Pw are short-circuited in the voltage vectors V0 and V7, the voltage vectors V0 and V7 have no magnitude. Therefore, the voltage vectors V0 and V7 are arranged at the center point. Such voltage vectors V0 and V7 are referred to as zero voltage vectors. In addition, the equilateral triangle area | region comprised by two adjacent among each voltage vector V1-V6 and each voltage vector V0, V7 is each called S1-S6.

  For example, according to the two-phase modulation method, the two voltage vectors Vi, Vj (i, j = 1 to 6, 6) constituting the regions S1 to S6 according to the regions S1 to S6 where the voltage command vector V * is located. i ≠ j) and the voltage vector V0 (or voltage vector V7) are output. The voltage vectors Vi and Vj and the voltage vector V0 (or voltage vector V7) are output so that their combined voltage vector matches the voltage command vector V *. Hereinafter, an example of outputting the voltage vector V0 as a zero voltage vector will be described.

  For example, when the voltage command vector V * is located in the region S1, for example, the voltage vectors V0, V4, and V6 are output in the periods t0, t4, and t6 (ts = t0 + t4 + t6) in the predetermined period ts, respectively.

  The combined voltage vector in the predetermined period ts is expressed as t0 / ts · V0 + t4 / ts · V4 + t6 / ts · V6. The voltage vectors V0, V4, V4, V4, t4 / t, and V6 are equal to the voltage command vector V *. V6 is output. In other words, the periods t0, t4, and t6 are obtained so that the combined voltage vector matches the voltage command vector V *, and the voltage vectors V0, V4, and V6 are output in the periods t0, t4, and t6, respectively.

  A voltage vector V7 may be output instead of the voltage vector V0.

  As described above, the voltage vectors Vi, Vj, and V0 (V7) are output in the regions S1 to S6, and the inverter 5 outputs an alternating voltage.

  Now, the switches Srec, Sc, Sz on the equivalent circuit shown in FIG. 2 are equivalently controlled by the switching of the nonlinear capacitor circuit 4 and the inverter 5 as follows.

  A period tz in which the switch Sz is conductive is a period in which the inverter 5 outputs a zero voltage vector. Therefore, the switch Sz is equivalently controlled by making all of the switching elements Sup, Svp, Swp conductive in the period tz, or by making all the switching elements Sun, Svn, Swn conductive.

  The period tc during which the switch Sc is conductive is a period during which the switching elements S41 and S42 are conductive during discharging and the inverter 5 outputs a desired voltage vector. That is, when discharging, the switching elements S41 and S42 are made conductive and the inverter 5 outputs a desired voltage vector, whereby the switch Sc during discharging is controlled equivalently. However, since the desired voltage vector is output to the inverter 5 in the period tc, the zero voltage vector can be output also in the period tc. In actuality, no current flows through the capacitors C41 and C42 during the period of the zero voltage vector. However, here, the period during which the zero voltage vector is output in the period tc is treated on the assumption that the current Ic flows. In order to reduce errors due to such assumptions, it is preferable to increase the amplitude of the AC voltage output from the inverter 5 (the magnitude of the voltage vector V). This is because the period during which the zero voltage vector is output in the period tc can be shortened.

  The period tc during which the switch Sc is conductive is a period during which the inverter 5 outputs a reverse voltage vector whose direction is opposite to the desired voltage vector during charging. For example, after the desired voltage vectors V0, V4, V6, V4 and V0 are output, the reverse voltage vectors V1, V3, V7, V3 and V1 are output.

  In the voltage vector V4, the switching elements Sup, Svn, and Swn are conducted, and a positive u-phase current, a negative v-phase current, and a w-phase current flow. The u-phase current, the v-phase current, and the w-phase current here are currents that flow through the output terminals Pu, Pv, and Pw, and the current that flows from the inverter 5 to the inductive load 6 is positive. Next, when the switching element Sun is turned on to output the voltage vector V0, the diode Dun is turned on to maintain the positive u-phase current, the negative v-phase current, and the w-phase current. Next, when the switching element Swp is turned on to output the voltage vector V1, the diode Dwp is turned on to maintain the positive u-phase current, the negative v-phase current, and the w-phase current. At this time, a regenerative current flows to the capacitors C41 and C42 via the diode Dwp. When the voltage vector is output in the period trec during charging, the single-phase AC voltage is large and the inductive energy stored in the inductive load 2 is large. Therefore, a regenerative current flows in the period tc.

  As described above, the switch Sc during charging is equivalently controlled by causing the inverter 5 to output the reverse voltage vector. Similarly, the switch Sc is equivalently controlled so that the current Ic flows during the period in which the inverter 5 outputs the zero voltage vector in the period tc. Note that the conduction / non-conduction of the switching elements S41, 42 is not questioned during charging. This is because the regenerative current flows in the charging period tc, so that the capacitors C41 and C42 are not discharged regardless of the conduction / non-conduction of the switching elements S41 and S42.

  The period trec in which the switch Srec is conducted is inevitably determined by controlling the switches Sz and Sc. In the period trec, the inverter 5 outputs a desired voltage vector. Thereby, the switch Srec is controlled equivalently. Similarly, when the zero voltage vector is output in the period trec, the switch Srec is equivalently controlled so that the current Irec flows even in the period in which the inverter 5 outputs the zero voltage vector in the period trec.

  The inverter 5 outputs each voltage vector V0 (V7), Vi, Vj in the predetermined period ts, and it is desirable to distribute each output period at a ratio equal to the periods trec and tc. In other words, at the time of discharging, the ratio of each output period of each voltage vector V0 (V7), Vi, Vj to the period trec, and the ratio of each output period of each voltage vector V0 (V7), Vi, Vj to the period tc Are preferably equal. Similarly, at the time of charging, the ratio of the output period of each voltage vector V0 (V7), Vi, Vj to the period trec, and each voltage vector V0 (V7), Vi ′, Vj ′ (Vi ′, Vj ′) to the period tc are It is desirable that the output period ratios of the reverse voltage vectors Vi and Vj are equal to each other. Thereby, the distortion of the waveform of the input current input to the single-phase diode rectifier 3 can be reduced.

  Hereinafter, a timing chart on the side of the inverter 5 at the time of charging will be described with reference to an example of FIG. In FIG. 6, conduction / non-conduction of the switching elements Sun, Svn, Swn controlled exclusively with the switching elements Sup, Svp, Swp, respectively, is not shown.

  The conduction period of each switching element included in the inverter 5 can also be obtained using the same carrier C as the carrier used to derive the conduction periods trec, tc, tz of the switches Srec, Sc, Sz.

  In each of the two periods trec and tc, the two command values obtained by internally dividing the phase voltage command value Vu * by the ratio of the periods trec and tc are compared with the magnitude of the carrier C, respectively. The four command values obtained by internally dividing the values Vv * and Vw * by the ratio of the periods trec and tc are respectively compared with the magnitude of the carrier C. However, in the period tc, command values Vu **, Vv **, and Vw ** obtained by subtracting the phase voltage command values Vu *, Vv *, and Vw * from 1 are used to output a reverse voltage vector. Hereinafter, a case where the phase voltage command values Vu *, Vv *, and Vw * increase in this order will be exemplified, and in particular, a case where Vw * = 1 will be described as an example.

  In the period trec, the switching element Sup is turned on when the carrier C is drec · (1−Vu *) or less, and the switching element Svp is turned on when the carrier C is drec · (1−Vv *) or less. When C is less than drec · (1-Vw *), the switching element Swp is turned on.

  Thus, for example, voltage vectors V0, V4, V6, V4, and V0 are output in this order during the period trec. In the period tc, the carrier C has a triangular shape that takes the maximum value. In the period trec, the carrier C has an inverted triangular shape that flips upside down and takes the minimum value. Therefore, in the period trec, the phase voltage command values Vu *, Vv *, and Vw * are subtracted from 1 in accordance with the inverted triangular shape.

  In the period tc, phase voltage command values Vu **, Vv **, and Vw ** obtained by subtracting the phase voltage command values Vu *, Vv *, and Vw * from 1, respectively, are used to output a reverse voltage vector. In the period tc, the phase voltage command values Vu *, Vv *, and Vw * are subtracted from 1, respectively. In the period tc, the carrier C has a triangular shape. Therefore, the reverse voltage vector is output in the period tc as follows.

  In the period tc, the switching element Sup is turned on when the carrier C is greater than or equal to drec + dz + dc · Vu **, and the switching element Tuv is turned on when the carrier C is greater than or equal to drec + dz + dc · Vv **. At the above time, the switching element Tuw is turned on.

  Thereby, for example, voltage vectors V1, V3, V7, V3, and V1 are output in the period tc. Referring to FIG. 5, voltage vectors V1 and V3 are reverse voltage vectors with respect to voltage vectors V6 and V4, respectively. In such a period tc, the inductive energy stored in the inductive load 6 is regenerated to the DC power supply lines LH and LL, so that a negative current Ic flows through the capacitors C41 and C42.

  Further, the switches Sup, Svp, and Swp are non-conducting in the period tz sandwiched between the periods trec and tc by the control of each switching element in the periods trec and tc described above. Thereby, the voltage vector V0 is output as a zero voltage vector in the period tz.

  The timing chart of the inverter 5 during discharging can be described with reference to FIG. That is, the phase voltage command values Vu *, Vv *, and Vw * are used instead of the command values Vu **, Vv **, and Vw ** in the period tc, and the switching elements S41 and S42 are made conductive in the period tc. . Thereby, the inverter 5 outputs a desired voltage vector in the period tc, and a positive current Ic flows in the capacitors C41 and C42 in the period tc.

  It is desirable that switching between the switching elements S41 and S42 is performed during a period in which the inverter 5 outputs a zero voltage vector. This is because no switching loss occurs because no current flows through the switching elements S41 and S42. Therefore, it is preferable that the switching elements S41 and S42 are turned on in the period tc and the period tz and switched at the boundary between the periods trec and tz and turned off in the period trec. This is because in the above example, the voltage vector output at the end of the period trec is the zero voltage vector (voltage vector V0), and the zero voltage vector is output at the boundary between the periods trec and tz.

  Further, at the time of charging, the switching elements S41 and S42 may be non-conducting in the period tc, but switching the switching state of the switching elements S41 and S42 in the period tc is controlled by distinguishing between charging and discharging. Make it complicated. On the other hand, at the time of charging, even if the switching elements S41 and S42 are turned on, the charging operation is not hindered. Therefore, it is preferable that the switching elements S41 and S42 are turned on during the period tc regardless of whether they are charged or discharged. In other words, in the example of FIG. 6, it is desirable that the switching elements S41 and S42 are conducted in a period in which the carrier C is equal to or higher than the current distribution ratio drec.

  With the control described above, the DC voltage Vdc input to the inverter 5 alternately adopts the DC voltage Vrec from the single-phase diode rectifier 3 and the voltage Vc1 from the nonlinear capacitor circuit 4. The voltages Vrec and Vc1 are expressed by the following equations.

  However, since the current is regenerated during the charging period, the voltage Vc1 is considered negative. The average of the DC voltage Vdc is considered as the sum of the voltages Vrec and Vc1. An average of the voltages Vrec and Vc1 and the DC voltage Vdc input to the inverter 5 is shown in FIG.

  For comparison, consider the case where the control of Non-Patent Document 1 is executed in the single-phase / three-phase direct conversion circuit of FIG. FIG. 18 shows a ratio (hereinafter also referred to as a current distribution ratio) drec1 for a current flowing through a single-phase diode rectifier, a current distribution ratio dc1 of a current flowing through a capacitor, and an inverter that outputs a zero voltage vector to the inverter. The current distribution ratio dz1 of the current is shown.

  FIG. 19 shows the voltage that can be instantaneously taken by the DC link and the average of these when the control is performed using the current distribution ratios drec1, dc1, and dz1. As shown in FIG. 19, the average DC voltage is not constant but pulsates. Such pulsation is not preferable, and it has been desired to suppress a decrease in the average DC voltage due to pulsation.

  As shown in FIG. 7, although the average of the DC voltage Vdc varies, it can be seen from the comparison with FIG. 19 that the average decrease in the DC voltage Vdc can be suppressed. Specifically, in FIG. 19, the average minimum of the DC voltage Vdc at the time of discharge is 0.5 times the average of the DC voltage Vdc at the time of charge, and in FIG. 7, the average value of the DC voltage Vdc at the time of discharge is The minimum is 0.84 times the average of the DC voltage Vdc during discharge.

  The point at which the average decrease in the DC voltage Vdc can be suppressed in this way is that when the DC voltage Vdc by the capacitors C41 and C42 at the time of discharge is half the voltage Vc, the maximum value of the current distribution ratio dc at the time of discharge is This is because it is larger than the maximum value of the current distribution ratio dc during charging.

  Further, in the control method according to the first embodiment, although the decrease in the average value of the DC voltage Vdc can be suppressed, pulsation still remains. Therefore, it is desirable to correct such pulsation on the inverter 5 side. Specifically, the correction coefficient may be multiplied by the phase voltage command values Vu *, Vv *, and Vw *. Such a correction coefficient is expressed, for example, by the inverse of the average of the DC voltage Vdc shown in FIG.

  Further, since the maximum of the current distribution ratio dc at the time of discharging is higher than the maximum of the current distribution ratio dc at the time of charging, the current distribution ratio dz at the time of discharging can be lowered (for example, comparison between FIG. 3 and FIG. 18). . Since the current distribution ratio dz is a ratio at which a zero voltage vector is output, the ratio decreases, so that the voltage utilization ratio can be increased. That is, the inductive load 6 can be controlled more efficiently.

  A simulation result by the control of such a single-phase / three-phase direct conversion apparatus is shown in FIG. 8, for example. As the simulation conditions, the amplitude of the single-phase AC voltage Vm = √2 × 200 V, the frequency of the single-phase AC voltage 50 Hz, the sum of the voltages across the capacitors C41 and C42 Vc = 600 V, and the amplitude modulation of the output voltage after multiplying by the correction coefficient Ratio (ratio of output voltage when the average maximum of DC voltage Vdc is 1) 0.84, frequency 150 Hz, inductive load 6 resistance value 2.25Ω, reactance 1.16 mH, power factor = 0.9, A frequency of 10 kHz for carrier C was employed. As shown in FIG. 8, the maximum of DC voltage Vdc at the time of discharging is half the voltage Vc, and the maximum of DC voltage Vdc at the time of charging is voltage Vc. Further, as shown in FIG. 8, the input current can be a sine wave, and the output line currents at the output terminals Pu, Pv, and Pw can be output as a three-phase alternating current. Further, FIG. 8 shows, for example, the output line voltage output between the output terminals Pu and Pv. The maximum of the output line voltage at the time of discharging is the maximum half value between the output lines at the time of charging, and the reverse voltage vector is output at the time of charging. The average of the output line voltage is an AC voltage.

  The switching loss that occurs in each switching element of the inverter 5 increases as the voltage applied to each switching element increases. As shown in FIG. 8, since the DC voltage Vdc at the time of discharging is lower than that at the time of discharging, the switching loss generated in the inverter 5 at the time of discharging can be reduced.

<Configuration of control unit>
Next, the configuration of the control unit 10 that controls the single-phase / three-phase direct conversion device will be described with reference to FIG. The control unit 10 includes a current distribution rate generation unit 11, a modulation rate correction unit 21, a polarity inversion unit 22, a carrier generation unit 23, an output voltage command value generation unit 31, correction units 32 and 33, and a comparator 12. , 34, 35 and a logical sum / logical product unit 36.

  The current distribution ratio generation unit 11 receives the amplitude Vm of the single-phase AC voltage, the angular velocity ω of the single-phase AC voltage, and the sum Vc of the voltages at both ends of the capacitors C41 and C42. The amplitude Vm and the angular velocity ω are detected by a detection unit (not shown) as a single-phase AC voltage and input to the current distribution ratio generation unit 11. The sum Vc is input as a set value by, for example, an external CPU. The current distribution ratio generation unit 11 generates the current distribution ratios drec, dc, dz based on, for example, Expression (2), Expression (15) to Expression (18).

  The comparator 12 compares the current distribution ratio drec with the carrier C from the carrier generation unit 23, and supplies the switch signal SS to the switching elements S41 and S42. For example, referring to FIG. 6, the comparator 12 outputs the switch signal SS activated in a period in which the carrier C is equal to or higher than the current distribution ratio drec. Thereby, the switching elements S41 and S42 are turned on in the periods tc and tz.

  The modulation factor correction unit 21 generates a correction coefficient for correcting the average pulsation of the DC voltage Vdc and outputs the correction coefficient to the output voltage command value generation unit 31. For example, the reciprocal of the average value of the DC voltage Vdc is calculated from the current distribution ratios drec, dc, the amplitude Vm, the sum Vc, and the angular velocity ω, and this is output as a correction coefficient.

  The output voltage command value generation unit 31 receives, for example, command values for the amplitude and angular velocity for the output voltage from an external CPU, for example. The output voltage command value generation unit 31 calculates the phase voltage command values Vu *, Vv *, Vw * from the amplitude and angular velocity, for example, and multiplies them by a correction coefficient to obtain the phase voltage command values Vu *, Vv *, Vw *. This is generated and output to the correction units 32 and 33.

  The polarity inversion unit 22 determines whether it is charging or discharging and outputs it to the correction unit 32. For example, the polarity inversion unit 22 receives the angular velocity ω from the current distribution ratio generation unit 11 and notifies the correction unit 32 of whether charging or discharging.

  The correction unit 32 generates phase voltage command values Vu **, Vv **, and Vw ** by subtracting the phase voltage command values Vu *, Vv *, and Vw * from 1, respectively, during charging. After multiplying by the rate dc, a value obtained by adding the current distribution rates drec and dz is output to the comparator 34. When discharging, the correction unit 32 multiplies the phase voltage command values Vu *, Vv *, and Vw * by the current distribution ratio dc and outputs a value obtained by adding the current distribution ratios drec and dz to the comparator 34. .

  The correction unit 33 subtracts the phase voltage command values Vu *, Vv *, Vw * from 1 and outputs a value obtained by multiplying each by the current distribution ratio drec to the comparator 35.

  The comparators 34 and 35 output the comparison result between the input value and the carrier C to the logical sum / logical product unit 36, respectively. For example, the comparators 34 and 35 output a signal activated in a period in which the inputted value is equal to or greater than the carrier C.

  The logical sum / logical product unit 36 appropriately performs a logical sum operation and a logical product operation on the comparison result to make the switching elements Sup, Svp, Swp conductive as described with reference to FIG. 6, so that the switch signals SuSp, SSvp, SSwp, SSun , SSvn, SSwn are output. Hereinafter, the switch signals SSup and SSun will be described representatively. The comparator 34 outputs the activated signal SS1 when the carrier C is lower than the value drec + dz + dc · Vu **, and the comparator 35 is activated when the carrier C is lower than the value drec · (1−Vu *). The signal SS2 is output. Referring to FIG. 6, switching signal SSup of switching element Sup is obtained by inverting signal SS1 and calculating a logical sum with signal SS2. The switching signal SSun of the switching element Sun is obtained by inverting the signal SS2 and calculating a logical product with the signal SS1.

<Variation of carrier>
As shown in FIG. 10, a sawtooth carrier C1 may be used as the carrier. In the illustration of FIG. 10, the inverter 5 is controlled according to the three-phase modulation method. Although there are carrier differences and modulation method differences, the same control as described above may be performed. That is, in the period trec, the switching element Sup is turned on when the carrier C is drec · (1-Vu *) or less, and the switching element Svp is turned on when the carrier C is drec · (1-Vv *) or less. When the carrier C is not more than drec · (1-Vw *), the switching element Swp is made conductive. In the period tc, phase voltage command values Vu **, Vv **, and Vw ** obtained by subtracting the phase voltage command values Vu *, Vv *, and Vw * from 1 are used to output a reverse voltage vector. In the period tc, the phase voltage command values Vu *, Vv *, and Vw * are reduced from 1, respectively. In the period tc, the carrier C has a triangular shape that takes the maximum value. Therefore, the reverse voltage vector is output in the period tc. In the period tc, a negative current Ic flows through the capacitors C41 and C42.

  Although a timing chart of the inverter 5 at the time of charging is omitted, it can be described with reference to FIG. That is, the phase voltage command values Vu *, Vv *, and Vw * are used instead of the command values Vu **, Vv **, and Vw ** in the period tc, and the switching elements S41 and S42 are made conductive in the period tc. . Thereby, the inverter 5 outputs a desired voltage vector in the period tc, and a positive current Ic flows in the capacitors C41 and C42 in the period tc.

Second embodiment.
The current distribution ratios drec, dc, dz in the second embodiment are different from the current distribution ratios drec, dc, dz in the first embodiment.

  When Expression (13) is substituted into Expression (12), the current distribution ratio dc during discharge is expressed by the following expression.

  In the third embodiment, Equations (15) and (16) are adopted as current distribution rates drec and dc at the time of charging, respectively, and Equations (15) and Equations are used as current distribution rates drec and dc at the time of discharging, respectively. (21) is adopted. Note that the current distribution ratio dz is calculated from the equation (2).

  Such current distribution ratios drec, dc, and dz are shown in FIG. All of the current distribution ratios drec, dc, and dz have a cycle of 180 degrees in voltage phase angle. The current distribution rate drec has a shape along a positive sine wave having a voltage phase angle of 180 degrees as a half cycle. Unlike the first embodiment, the sine wave along which the current distribution ratio drec at the time of charging is the same as the sine wave along which the current distribution ratio drec at the time of discharging is the same. The current distribution ratio dc has a shape along a positive sine wave having a voltage phase angle of 90 degrees as a half cycle. However, the amplitude of the sine wave along which the current distribution ratio dc during discharge is twice the amplitude of the sine wave along with the current distribution ratio dc during charging.

  By controlling the nonlinear capacitor circuit 4 and the inverter 5 using the current distribution ratios drec, dc, and dz as in the first embodiment, the average of the DC voltage Vdc becomes constant as shown in FIG. As described above, the average pulsation of the DC voltage Vdc can be reduced most.

  In addition, since the average of the DC voltage Vdc can be made constant, it is not necessary to perform correction on the inverter 5 side. For example, the modulation rate correction unit 21 in FIG. 9 can be omitted. Therefore, the control can be simplified.

  FIG. 13 shows a simulation result in which the single-phase / three-phase direct conversion device is controlled as in the first embodiment without correction by the modulation factor correction unit 21. The simulation conditions of the result shown in FIG. 13 are the same as the simulation conditions of the result shown in FIG. However, since the correction is not performed, the amplitude modulation factor of the output voltage is 0.84.

Third embodiment.
In the second embodiment, the maximum value of the voltage distribution ratio dc during discharging is set to twice the maximum value of the current pressure distribution ratio dc during charging, and the average pulsation (variation) of the DC voltage Vdc is reduced most. is doing. However, in view of reducing the average fluctuation of the DC voltage Vdc from the DC voltage Vdc shown in FIG. 19, the maximum value of the voltage distribution ratio dc during discharging is the maximum value of the current pressure distribution ratio dc during charging. It may exceed twice. Here, the upper limit of the maximum value of the current distribution ratio dc at the time of discharge is defined to reduce the average fluctuation of the DC voltage Vdc shown in FIG.

  In the second embodiment, the maximum value of the current distribution ratio dc during discharging is set lower than three times the maximum value of the current distribution ratio dc during charging. More specifically, the current distribution ratio dc during discharge is set lower than the following equation.

  In the following, when Equation (22) is adopted as the current distribution ratio dc at the time of discharge, it is assumed that the average fluctuation width (also referred to as pulsation amplitude) of the DC voltage Vdc matches the fluctuation width shown in FIG. Show. FIG. 14 shows the average Vdc1 of the DC voltage Vdc when the equation (22) is adopted as the current distribution ratio dc during discharge.

  Now, as described in the first embodiment, the average Vdc1 of the DC voltage Vdc is represented by the sum of the voltages Vrec and Vc1. Equations (15) and (16) are adopted as current distribution rates drec and dc during charging, equations (15) and (22) are adopted as current distribution rates drec and dc during discharging, and equations When it is noted that the voltage Vdc at the time of discharge in (20) is a half value, the average Vdc1 at the time of charging and the average Vdc1 at the time of discharging are respectively expressed by the following equations.

  From equation (23), the average Vdc1 during charging is constant. From the equation (24), the average Vdc1 during discharge is charged with the minimum value at both ends (ωt = 3 / 4π, 5 / 4π) of the discharge period (for example, ωt is 3 / 4π or more and 5 / 4π or less). It coincides with the average Vdc of the hour, and the center of the period (for example, ωt = π) has a maximum value (see FIG. 14). When the average Vdc1 at the time of discharging takes the maximum value, that is, for example, when ωt = π, the fluctuation range ΔV that is the difference between the average Vdc1 at the time of discharging and the average Vdc1 at the time of charging takes the maximum. Therefore, subtracting equation (23) and equation (24) and substituting ωt = π leads to the maximum value ΔVmax of the fluctuation range ΔV.

  The difference Vdc1 between discharging and charging of the average Vdc1 of the DC voltage Vdc shown in FIG. 19 is similarly considered. In FIG. 18, Expression (15) and Expression (16) are respectively employed as the current distribution ratios drec and dc regardless of whether they are charged or discharged. The average Vdc1 at the time of charging is expressed by Expression (23), and the average Vdc1 at the time of discharging is expressed by the following expression.

  From the equation (26) and FIG. 8, the average Vdc1 during discharge is the maximum value at both ends (ωt = 3 / 4π, 5 / 4π) of the discharge period (for example, ωt is 3 / 4π or more and 5 / 4π or less). Is equal to the average Vdc at the time of charging, and the center (for example, ωt = π) has a minimum value (see FIG. 19). When the average Vdc1 at the time of discharging takes a minimum value, that is, when ωt = π, for example, the fluctuation range ΔV of the average Vdc1 at the time of discharging and the average Vdc1 at the time of charging takes the maximum. Therefore, subtracting equation (23) and equation (26) and substituting ωt = π leads to the maximum value ΔVmax of the fluctuation range ΔV.

  As can be understood from the comparison between the formula (25) and the formula (27), the maximum value ΔVmax when the formula (22) is used as the current distribution ratio dc at the time of discharge and the conventional current distribution ratio dc are used. Is the same as the maximum value ΔVmax.

  Further, as described in the second embodiment, when the maximum value of the current distribution ratio dc during discharging exceeds twice the maximum value of the current distribution ratio dc during charging, the fluctuation range of the average Vdc1 is more efficient. Can be reduced. In a range exceeding this double, the fluctuation range of the average Vdc1 increases as the maximum value of the current distribution ratio dc during discharge increases. Therefore, the maximum value ΔVmax of the fluctuation range ΔV of the average Vdc1 is compared with the conventional control by setting the maximum value of the current distribution ratio dc at the time of discharging to be lower than three times the maximum value of the current distribution ratio dc at the time of charging. And can be suppressed.

Fourth embodiment.
In the fourth embodiment, a method of initially charging the capacitors C41 and C42 will be described.

  As described in the first embodiment, when the absolute value of the single-phase AC voltage is lower than 1 / √2 times the amplitude Vm (during charging), the switching elements S41 and S42 are turned on during the period tc. To discharge the capacitors C41 and C42. However, if the voltage across the capacitors C41 and C42 is lower than 1 / √2 times the amplitude Vm, there is a period during which the single-phase AC voltage exceeds the voltage across the capacitors C41 and C42 during the discharge period tc. In this case, the capacitors C41 and C42 cannot be discharged.

  For example, in the single-phase / three-phase direct conversion circuit of FIG. 1, before controlling the switching of the nonlinear capacitor circuit 4 and the inverter 5, each of the capacitors C41 and C42 is charged with a half value of the amplitude Vm of the single-phase AC voltage. The Therefore, when the control of the switching of the nonlinear capacitor circuit 4 and the inverter 5 is started, there is a period during which the capacitors C41 and C42 cannot be discharged when the discharge occurs first.

  Therefore, in the fourth embodiment, prior to switching control of the nonlinear capacitor circuit 4 and the inverter 5, the voltage across the capacitors C41 and C42 is preliminarily set so as to be 1 / √2 times or more of the amplitude Vm. C41 and C42 are charged.

  For example, as shown in FIG. 15, this single-phase / three-phase direct conversion device further includes an initial charging switch S7 as compared with the single-phase / three-phase direct conversion devices of the first to third embodiments. Yes. One end of the switch S7 is connected between the diodes D31 and D32 or between the diodes D33 and D34. The other end is connected between the capacitors C41 and C42. In the illustration of FIG. 15, the switch S7 is provided with one end connected between the diodes D33 and D34 and the other end connected between the diode D41 and the capacitor C42.

  In such a three-phase / single-phase direct conversion device, the switch S7 is turned on prior to the switching of the nonlinear capacitor circuit 4 and the inverter 5. The diodes D31 and D34 and the capacitors C41 and C42 constitute a voltage doubler rectifier circuit by the conduction of the switch S7. Therefore, the conduction of the switch S7 charges the capacitors C41 and C42 such that each of the voltages across the capacitors C41 and C42 has the amplitude Vm.

  Therefore, when the switching control of the nonlinear capacitor circuit 4 and the inverter 5 is started, the capacitors C41 and C42 can be reliably discharged even if the discharge time comes first.

Fifth embodiment.
In the first to fourth embodiments, the mode in which the nonlinear capacitor circuit 4 includes the two capacitors C41 and C42 has been described. As illustrated in FIG. 16, the nonlinear capacitor circuit 4 according to the fifth embodiment includes three capacitors C41 to C43. Note that the number of capacitors is not limited to three and may be four or more. In the non-linear capacitor circuit 4, the current flowing through the capacitors C41 to C43 from the DC power supply line LH to the DC power supply line LL flows through the capacitors C41 to C43 connected in series, and flows from the DC power supply line LL to the DC power supply line LH. The current flows through capacitors C41 to C43 connected in parallel with each other.

  In the illustration of FIG. 16, the nonlinear capacitor circuit 4 includes diodes D41 to D46 and switching elements S41 to S44. The two diodes D41 and D44 are provided between the three capacitors C41 to C43. All of the diodes D41 and D44 are connected in series with capacitors C41 to C43 with the anode directed to the DC power supply line LH and the cathode directed to the DC power supply line LL.

  The switching element S44 and the diode D46 are connected in series with each other between the anode of the diode D41, the capacitor C41 provided adjacent to the anode, and the DC power supply line LL. The switching element S42 and the diode D43 are provided between the anode of the diode D44, the capacitor C42 provided adjacent to the anode, and the DC power supply line LL.

  The switching element S43 and the diode D45 are connected in series with each other between the cathode of the diode D44, the capacitor C43 provided adjacent to the cathode, and the DC power supply line LH. The switching element S41 and the diode D42 are provided between the cathode of the diode D41 and the capacitor C42 provided adjacent to the cathode, and between the DC power supply line LH.

  All of the diodes D42, D43, D45, and D46 are arranged with the anode facing the DC power supply line LL and the cathode facing the DC power supply line LH.

  According to the nonlinear capacitor circuit 4, current flows from the DC power supply line LH to the DC power supply line LL side via the capacitors C41 to C43 and the diodes D41 and D44, so that the capacitors C41 to C43 are in series with each other. Flows. Further, due to the conduction of the switching elements S41 to S44, currents flow in the capacitors C41 to C43 in parallel with each other.

  Therefore, according to the nonlinear capacitor circuit 4, the DC voltage Vdc generated by the capacitors C41 to C43 during discharging is one third of the DC voltage Vdc generated by the capacitors C41 to C43 during charging.

  Also in the fifth embodiment, as in the first embodiment, the maximum value of the current distribution ratio dc during discharging is set higher than the maximum value of the current distribution ratio dc during charging, so that the DC voltage Vdc A decrease can be suppressed.

  Similarly to the second embodiment, the maximum value of the current distribution ratio dc at the time of discharging is set to 3 (= the number of capacitors) times the maximum value of the current distribution ratio dc at the time of charging. The amplitude of fluctuation of Vdc can be further suppressed. More specifically, it is desirable to adopt the formula (22) as the current distribution ratio dc during discharge.

  Similarly to the third embodiment, the maximum value of the current distribution ratio dc during discharging is set lower than 5 (= 2 × the number of capacitors−1) times the maximum value of the current distribution ratio dc during charging. As a result, the average pulsation of the DC voltage Vdc can be reduced.

Sixth embodiment.
In the first to fifth embodiments, the nonlinear capacitor circuit 4 having a plurality of switching elements has been exemplified. In the sixth embodiment, as illustrated in FIG. 17, the non-linear capacitor circuit 4 includes one switching element S47. In the illustration of FIG. 17, the nonlinear capacitor circuit 4 includes two capacitors C41 and C42 and diodes D41 to D43.

  The diode D41 is provided between the DC power supply lines LH and LL with the anode directed toward the DC power supply line LH and the cathode directed toward the DC power supply line LL. Capacitors C41 and C42 are provided on the DC power supply lines LH and LL, respectively, with respect to the diode D41, and are connected in series with the diode D41.

  The diode D42 is provided between a point between the cathode of the diode D41 and the capacitor C42 and the DC power supply line LH. The diode D43 is provided between a point between the anode of the diode D41 and the capacitor C41 and the DC power supply line LL. The diodes D42 and D43 are arranged with their anodes facing the DC power supply line LL and their cathodes facing the DC power supply line LH.

  The switching element S47 is provided between the cathode of the diode D42 and the DC power supply line LH. More specifically, the switching element S47 has one end connected in common with the cathode of the diode D42 and the capacitor C41, and the other end connected to the DC power supply line LH.

  The diode D47 is connected in parallel with the switching element S47 with the anode directed toward the DC power supply line LH and the cathode directed toward the DC power supply line LL.

  According to the nonlinear capacitor circuit 4, current flows from the DC power supply line LH to the DC power supply line LL side via the capacitors C41 and C42 and the diodes D41 and D47, so that the capacitors C41 and C42 are in series with each other. Current flows. Further, due to the conduction of the switching element S47, current flows in the capacitors C41 and C42 in parallel with each other. In addition, since the selection function of the nonlinear capacitor circuit 4 can be realized by only one switching element S47 as compared with the first to fifth embodiments, the manufacturing cost can be reduced.

  Note that the switching element S47 may be provided between the anode of the diode D43 and the DC power supply line LL. More specifically, one end of the switching element S47 may be commonly connected to the anode of the diode D43 and the capacitor C42, and the other end may be connected to the DC power supply line LL. At this time, the cathode of the diode D42 is connected to the DC power supply line LH.

  Further, the number of capacitors is not limited to the number of capacitors included in the nonlinear capacitor circuit 4, and only one switching element is required. For example, in FIG. 16, instead of the switching elements S41 to S44, one end of one switching element may be connected to the cathodes of the diodes D42 and D45 and the capacitor C41, and the other end may be connected to the DC power supply line LH. One end of one switching element may be commonly connected to the cathodes of the diodes D43 and D46 and the capacitor C43, and the other end may be connected to the DC power supply line LL.

  Similarly to the fourth embodiment, if the switch S7 is provided between the diodes D31 and D32 or between the diodes D33 and D34 and between the capacitors C41 and C42, both ends of the capacitors C41 and C42 are initially set. It can be charged so that the voltage has an amplitude Vm.

3 Single-phase diode rectifier 4 Non-linear capacitor circuit 5 Inverter C41 to C43 Capacitor D41 to D47 Diode LH, LL DC power supply line S41 to S44, S47 Switching element ts, trec, tc, tz Period

Claims (6)

A single-phase diode rectifier (3) to which a single-phase AC voltage is input;
A first power line (LH) connected to the output side of the single-phase diode rectifier;
A second power supply line (LL) connected to the output side of the single-phase diode rectifier and applied with a lower potential than the first power supply line;
There are N (N is a natural number of 2 or more) capacitors (C41 to C43) provided between the first and second power lines, and the first power line to the second power line. The current flowing through the N capacitors flows through the N capacitors connected in series with each other, and the current flowing from the second power supply line to the first power supply line flows through the N capacitors connected in parallel with each other. A non-linear capacitor circuit (4) flowing through the capacitor;
A method for controlling a single-phase / three-phase direct conversion device including an inverter (5) that receives a voltage between the first and second power lines and operates based on a voltage vector,
In each of the predetermined predetermined periods (ts) represented by the sum of the first to third periods (trec, tc, tz), a current is passed through the single-phase diode rectifier during the first period, and the third period Causing the inverter to perform an operation employing a zero voltage vector as the voltage vector,
In each of the predetermined periods, when the absolute value of the single-phase AC voltage is lower than a predetermined value, the N capacitors are connected in parallel in the second period, and the absolute value of the single-phase AC voltage is the predetermined value. Current is passed through the N capacitors connected in series with each other in the second period,
The maximum value of the second period when the absolute value of the single-phase AC voltage is lower than the predetermined value is greater than the maximum value of the second period when the absolute value of the single-phase AC voltage is higher than the predetermined value. Control method for single-phase / three-phase direct conversion devices.   The maximum value of the second period (tc) when the absolute value of the single-phase AC voltage is lower than the predetermined value is the maximum value of the second period when the absolute value of the single-phase AC voltage is higher than the predetermined value. The method for controlling a single-phase / three-phase direct conversion device according to claim 1, wherein the control method is smaller than (2N-1) times the maximum value.   The maximum value of the second period (tc) when the absolute value of the single-phase AC voltage is lower than the predetermined value is the maximum value of the second period when the absolute value of the single-phase AC voltage is higher than the predetermined value. The method for controlling a single-phase / three-phase direct conversion device according to claim 1, wherein the control method is N times the maximum value.   4. The single-phase / single-phase according to claim 1, wherein the N capacitors are charged in advance so that a voltage across each of the N capacitors (C41 to C43) is equal to or higher than the predetermined value. Control method for three-phase direct conversion device. The nonlinear capacitor circuit (4)
The N capacitors (C41 to C43) are provided between the N capacitors with the anode facing the first power line (LH) and the cathode facing the second power line (LL). First to (N-1) charging diodes (D41, D44) connected in series with each other;
Each of the first to (N-1) charging diodes is provided between the anode and the capacitor provided adjacent to the anode, and between the second power supply line, (N-1) first discharge diodes (D43, D46), each having a cathode on the second power line side and a cathode facing the first power line side;
Each of the first to (N-1) charging diodes is provided between the cathode and the capacitor provided adjacent to the cathode, and between the first power supply line, and the anode is the (N-1) second discharge diodes (D42, D45) arranged with the cathode facing the first power supply line side on the second power supply line side,
2 (N-1) switches (S41 to S44) directly connected to the (N-1) first discharge diodes and the (N-1) second discharge diodes, respectively. 5. The method for controlling a single-phase / three-phase direct conversion device according to claim 1, comprising: The nonlinear capacitor circuit (4)
First to (N-1) th charging provided between the N capacitors with the anode facing the first power supply line (LH) and the cathode facing the second power supply line (LL), respectively. Diode (D41),
Each of the first to (N-1) charging diodes is provided between the anode and the capacitor provided adjacent to the anode, and between the second power supply line, (N-1) first discharging diodes (D43) arranged with the cathode facing the second power line side and facing the first power line side,
Each of the second to Nth charging diodes is provided between the cathode and the capacitor provided adjacent to the cathode and between the first power supply lines, and an anode is provided between the second power supply lines. (N-1) second discharge diodes (D42), each having a cathode on the side facing the first power supply line,
Between the anode of the (N-1) first discharge diodes and the second power supply line or the cathode of the (N-1) second discharge diodes and the first power supply line A switch element (S47) provided between
5. An Nth charging diode (D47) connected in parallel with the switch element with an anode facing the first power line and a cathode facing the second power line, respectively. The method for controlling a single-phase / three-phase direct conversion device according to claim 1.