JP2010219289A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a gate electrode from being dissolved to cause an abnormality in shape when forming a shared contact. <P>SOLUTION: The semiconductor device includes a transistor provided with the gate electrode 31 formed on a substrate 1 through a gate insulating film 2 and impurity regions 32 and 33 formed at both sides of the gate electrode 31 on the substrate 1, interlayer insulating films 11 and 12 formed on the substrate 1 so as to cover the transistor, and the shared contact 14 electrically connected to the impurity regions 32 and 33 and the gate electrode 31. A first sidewall 5 is formed so as to cover the side face lower part of the gate electrode 31, a second sidewall 6 is formed at the opposite side of the gate electrode 31 on the first sidewall 5, and a third sidewall 9b is formed so as to be held between the side face upper part of the gate electrode 31 and the second sidewall 6 on the first sidewall 5. The second and third sidewalls 6 and 9b are formed of materials different from that of the first sidewall 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a shared contact is formed on a gate electrode having a sidewall and a manufacturing method thereof.

  Along with the high integration and high performance of semiconductor devices, miniaturization of MISFETs (Metal Insulator Semiconductor Field Effect Transistors, hereinafter referred to as MIS transistors) is progressing. For this reason, the gate length of the gate electrode is made shorter (for example, about 30 nm), and the gate insulating film is made thinner (for example, about 2 nm).

  In addition, the gate electrode may be formed as a laminated structure of a polysilicon film and a metal material (for example, TiN film) for threshold control of the MIS transistor, reduction of gate electrode resistance, and the like.

  On the other hand, the MIS transistor has a problem of a short channel effect. As a technique for dealing with this problem, it is known to provide an LDD (Lightly Doped Drain). In this method, a shallow doping region is formed locally in the source / drain (near the channel) of the MIS transistor. The LDD doping concentration is lower than the original source / drain doping concentration. In order to form such an LDD, a sidewall is generally used.

  Thus, in order to suppress the short channel effect, LDDs have been formed in MIS transistors. However, when the channel length between the source / drain becomes smaller as the semiconductor device becomes finer, the source depletion layer and the drain depletion layer overlap. For this reason, the problem of the short channel effect becomes more serious.

  As a method corresponding to this, there is the following technique (for example, Patent Document 1).

  4A to 4C and FIGS. 5A to 5C are process cross-sectional views illustrating a method for manufacturing a semiconductor device as a technical background.

  First, the process shown in FIG. First, the gate oxide film 116 is formed by thermally oxidizing the surface of the semiconductor substrate 115. Next, a TiN film 117 and a polysilicon film 118 are sequentially formed on the gate oxide film 116 by a CVD (Chemical Vapor Deposition) method or a PVD (Physical Vapor Deposition) method.

  Subsequently, a resist (not shown) having a desired gate pattern is formed. After the gate pattern is transferred to the polysilicon film 118 and the TiN film 117 using a dry etching technique, the resist is removed by ashing and washing. As a result, a gate electrode 131 composed of the polysilicon film 118 and the TiN film 117 is formed on the gate oxide film 116.

  Next, impurity ions are implanted into the semiconductor substrate using the gate electrode 131 as a mask, thereby forming a shallow first doping region 132 as an LDD in the semiconductor substrate 115 on both sides of the gate electrode and the gate oxide film 116.

  Next, a silicon nitride film is formed on the entire surface of the semiconductor substrate 115 including the gate electrode by a CVD method. The entire surface of the silicon nitride film is dry-etched using a dry etching technique to form a first sidewall 119 made of a silicon nitride film on the side wall of the gate electrode.

  Next, as shown in FIG. 4B, a silicon oxide film 120a is formed on the entire surface of the semiconductor substrate 115 including the gate electrode and the first sidewall 119 by the CVD method.

  Next, as shown in FIG. 4C, the silicon oxide film 120a is subjected to dry etching on the entire surface by using a dry etching technique, whereby the second sidewall made of the silicon oxide film is formed on the side wall of the first sidewall 119. Side wall 120b is formed. Thereafter, impurity ions are implanted into the semiconductor substrate 115 using the gate electrode 131, the first sidewall 119, and the second sidewall 120b as a mask. Thus, the second doping region 133 having a higher impurity concentration than the LDD (first doping region 132) is formed as the source / drain region in the semiconductor substrate 115 on both sides of the second sidewall 120b.

  Next, as shown in FIG. 5A, the second sidewall 120b made of a silicon oxide film is selectively removed by wet etching using hydrofluoric acid.

  Next, as shown in FIG. 5B, a silicon nitride film 121 and a silicon oxide film 122 are sequentially formed on the entire surface of the semiconductor substrate 115 including the gate electrode 131, the first sidewall 119, and the source / drain regions. . For this, a CVD method may be used. Thereafter, the silicon oxide film 122 is planarized using a CMP (Chemical Mechanical Polishing) method.

  Next, as shown in FIG. 5C, a contact hole (shared contact hole) 123 exposing both of the gate electrode and the surface of the source / drain region 133 formed on the semiconductor substrate 115 is formed. Form.

  For this purpose, first, a resist (not shown) having a desired contact hole pattern is formed on the silicon oxide film 122. Next, using a dry etching technique, the silicon oxide film 122 is selectively etched using the resist as a mask. Thereafter, the resist is removed by ashing and washing. Thereby, a contact hole reaching the surface of the silicon nitride film 121 (upper part of the shared contact hole 123) is formed.

Next, using a dry etching technique, the silicon nitride film 121 is etched using the silicon oxide film 122 as a mask. Thereafter, the resist is removed by ashing and cleaning, and a lower portion of the shared contact hole 123 is formed.
JP 2002-368007 A

  However, according to the conventional configuration, the following problems occur.

That is, in the step of forming the shared contact hole 123 reaching the conductive region (source region or drain region) and the gate electrode 131 of the semiconductor substrate, the first sidewall is removed when the silicon nitride film 121 as the stopper film is removed. 119 is also etched (in FIG. 5C, the removed portion 119a of the first sidewall is indicated by a dotted line). For this reason, the TiN film 117 constituting the gate electrode 131 is dissolved in the APM (ammonia perwater: mixed solution of NH ₄ OH, H ₂ O ₂ and H ₂ O) cleaning in the next step (in FIG. 5C). The portion 117a from which the TiN film is removed is indicated by a dotted line). As a result, the gate electrode 131 becomes abnormal in shape, causing a problem that, for example, the contact resistance increases and the transistor characteristics cannot be evaluated. Therefore, the solution is an issue.

  In view of the above, an object of the present invention is to provide a semiconductor device having a structure for preventing a gate electrode from becoming abnormal in shape when a shared contact is formed, and a manufacturing method thereof.

  In order to achieve the above object, a semiconductor device according to the present invention includes a transistor having a gate electrode formed on a substrate via a gate insulating film, and impurity regions formed on both sides of the gate electrode in the substrate. An interlayer insulating film formed on the substrate so as to cover the transistor, and a shared contact that penetrates the interlayer insulating film and is electrically connected to the impurity region and the gate electrode, and covers at least a lower part of the side surface of the gate electrode As described above, the first sidewall is formed, the second sidewall is formed so as to cover the side surface of the first sidewall opposite to the gate electrode, and the gate electrode is formed on the first sidewall. A third sidewall is formed so as to be sandwiched between the upper part of the side surface and the second sidewall, and the second sidewall and the third sidewall are formed. Are both are constructed from a material different from that of the first sidewall.

  According to the semiconductor device of the present invention, the first sidewall provided at the lower portion of the side surface of the gate electrode has the second sidewall and the third sidewall whose upper surface and upper surface are made of a material different from that of the first sidewall. Covered by side walls. For this reason, when forming an impurity region as a source / drain region (referred to collectively as a source region and a drain region) and a shared contact electrically connected to the gate electrode, the gate electrode has an abnormal shape. Can be prevented.

  That is, in order to provide a shared contact, a contact hole is formed by etching the interlayer insulating film or the like. Here, it is possible to prevent the first sidewall from being removed by using the second sidewall and the third sidewall as an etch stopper. As a result, the side surface of the gate electrode is not exposed, and etching is prevented from becoming abnormal in shape.

  The interlayer insulating film has a structure in which a first interlayer insulating film as a lower layer and a second interlayer insulating film as an upper layer are stacked, and the first interlayer insulating film includes a second sidewall and It is preferable that the third sidewall is made of a different material.

  In this way, formation of the shared contact and avoidance of the abnormal shape of the gate electrode at that time can be more reliably performed.

  The material of the first sidewall may be a silicon nitride film, a silicon carbide film, or a silicon carbonitride film. The material of the second sidewall and the material of the third sidewall are a silicon oxide film, a PSG (Phospho Silicate Glass) film, a BSG (Boron Silicate Glass) film, or a BPSG (Boron Phospho Silicate Glass) film, respectively. Also good.

  The gate electrode preferably contains a metal material. In such a case, the effect of preventing the gate electrode from being melted and becoming abnormal in shape is remarkably exhibited.

  The impurity region preferably includes a first impurity region and a second impurity region formed deeper than the first impurity region.

  As a result, a MIS transistor structure having an LDD region is obtained.

  Next, in order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes forming a gate electrode containing a metal material on a substrate via a gate insulating film, and forming both sides of the gate electrode on the substrate. (A) forming an impurity region in the substrate, (b) forming a first sidewall made of the first insulating film on the side surface of the gate electrode, and forming a second insulating film on the entire surface of the substrate. After the formation, the step (c) of forming the second sidewall made of the second insulating film on the side surface of the first sidewall by etch back using the dry etching method, and using the dry etching method, A step (d) of forming a recess by removing the upper portion of the first sidewall, and forming a third insulating film filling the recess, and then using a dry etching method, a third insulating film other than the inside of the recess Remove After the step (e) and the step (e) of forming the third sidewall made of the third insulating film in the recess, the step (f) of forming an interlayer insulating film on the entire surface of the semiconductor substrate, and the interlayer insulation A step (g) of forming a contact hole in the film so as to open over the impurity region and the gate electrode, and a step (h) of filling the contact hole with a conductive material to form a shared contact. The one sidewall is made of a material different from both the second sidewall and the third sidewall.

  According to the method for manufacturing a semiconductor device of the present invention, the first sidewall is formed in the lower portion of the side surface of the gate electrode, and the second sidewall and the third sidewall covering the side surface and the upper surface of the first sidewall. Form. The first sidewall is formed using a material different from that of the second sidewall and the third sidewall. As a result, when the interlayer insulating film is etched to form the shared contact hole, the first sidewall can be prevented from being etched, and further, the gate electrode can be prevented from being etched to cause an abnormal shape. be able to.

  In the step (c), a fourth insulating film is further formed on the second insulating film, and a second sidewall composed of the second insulating film and the fourth insulating film is formed. ) And step (f), it is preferable to further include a step of removing the fourth insulating film on the second sidewall.

  Generally, an etching stopper made of, for example, a silicon nitride film is used for forming the contact hole. Here, the etching stopper film fills the space between the gate electrodes at a location where the interval between the adjacent gate electrodes is narrow. On the other hand, the etching stopper film is deposited in a desired film thickness at a location where the interval between adjacent gate electrodes is wide. As described above, the difference in the thickness of the etching stopper film depending on the formation location may make it difficult to remove the etching stopper film. Therefore, in order to cope with the miniaturization of the semiconductor device, it is advantageous to provide the fourth insulating film as described above and remove it.

  In step (f), an interlayer insulating film composed of a lower first interlayer insulating film and an upper second interlayer insulating film is formed. In step (g), the first interlayer insulating film is formed. After etching the second interlayer insulating film as an etch stopper, the first interlayer insulating film is etched, and the first interlayer insulating film is made of a material different from both the second sidewall and the third sidewall. It is preferable that

  In this case, the first interlayer insulating film can be used as an etching stopper when the second interlayer insulating film is etched, and the second sidewall is etched when the first interlayer insulating film is etched. And etching of the third sidewall can be avoided.

  The material of the first sidewall may be a silicon nitride film, a silicon carbide film, or a silicon carbonitride film. The material of the second sidewall and the third sidewall may be a silicon oxide film, a PSG film, a BSG film, or a BPSG film, respectively. These can be mentioned as examples of specific materials.

  Further, an impurity is introduced into the substrate between the step (e) and the step (f) using the first sidewall, the second sidewall, the third sidewall, and the gate electrode as a mask, so that the impurity region is more It is preferable to further include a step of forming another deep impurity region.

  In this way, a MIS transistor structure having an LDD can be obtained.

  According to the semiconductor device and the manufacturing method thereof of the present invention, the first sidewall can be prevented from being etched when removing the contact stopper film for forming the shared contact. In this case, it is possible to prevent the metal material of the gate electrode from being melted and to prevent an abnormal shape of the gate electrode.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIGS. 1A to 1C, FIGS. 2A to 2C, and FIGS. 3A to 3C are schematic cross-sectional views illustrating the manufacturing process of the semiconductor device of this embodiment. . Here, the case where the conductivity type of the MIS transistor formed on the semiconductor substrate is N-type will be taken as an example and will be specifically described.

First, the MIS transistor structure shown in FIG. For this purpose, first, an element isolation region (not shown) is selectively formed on the semiconductor substrate 1 made of, for example, P-type silicon. Thereafter, for example, a P-type well region (not shown) is formed by ion implantation of a P-type impurity such as boron (B) under the condition of an implantation dose amount of 1 × 10 ¹³ / cm ² .

  Next, a gate insulating film 2 including a base insulating film and a high dielectric constant insulating film laminated thereon is formed on the semiconductor substrate 1.

  For this purpose, a single layer film of a silicon oxide film, a single layer film of a silicon nitride film, or a laminated film of a silicon oxide film and a silicon nitride film is formed on the semiconductor substrate 1 as a base insulating film. As a first method for forming the base insulating film, for example, an in-situ steam generation (ISSG) method, a rapid thermal oxidation (RTO) method, or an oxidation furnace is used to oxidize the upper portion of the semiconductor substrate 1 to form a silicon oxide film. As a base insulating film is formed. As a second method, for example, a silicon oxide film is formed on the semiconductor substrate 1 using an ISSG method, an RTA method, or an oxidation furnace, and then the upper portion of the silicon oxide film is nitrided by a DPN (Decoupled Plasma Nitridation) method. Then, a base insulating film is formed as a laminated film of a silicon oxide film and a silicon nitride film. Furthermore, as a third method, for example, an ISSG method, an RTA method or an oxidation furnace is used to form a silicon oxide film on the semiconductor substrate 1, and then all the silicon oxide film is nitrided by the DPN method. As a base insulating film is formed.

Next, a high dielectric constant insulating film is formed on the base insulating film. As a material for the high dielectric constant insulating film, silicon nitride film (SiN), hafnium silicon oxide film (HaSiO), hafnium silicon nitride film (HaSiN), hafnium silicon oxynitride film (HaSiON), hafnium oxide film (HfO ₂ ), Examples thereof include a hafnium aluminum oxide film (HfAlO), a lanthanum aluminum oxide film (LaAlO), a ruthenium oxide film (Ru ₂ O ₃ ), a zircon oxide film (ZrO ₂ ), and a tantalum oxide film (Ta ₂ O ₅ ). Examples of a method for forming a high dielectric constant insulating film include an ALD (Atomic Layer Deposition) method and a MOCVD (Metal Organic Chemical Vapor Deposition) method.

Next, a gate electrode 31 made of the first conductive film 3 and the second conductive film 4 laminated thereon is formed on the gate insulating film 2 made of the base insulating film and the high dielectric constant insulating film. For this purpose, first, a first conductive film 3 made of a metal film such as titanium nitride (TiN) is formed on the semiconductor substrate 1. Thereafter, a polysilicon film is formed on the first conductive film 3 and, for example, phosphorus (P) or arsenic (As) is formed on the polysilicon film under the condition of an implantation dose of 1 × 10 ¹⁵ / cm ^2. N-type impurities are ion-implanted to form a second conductive film 4 made of an N-type silicon film.

  Next, a resist (not shown) having a desired gate pattern is formed on the second conductive film 4, and the second conductive film 4 and the first conductive film are etched using an etching technique using the resist as a mask. The gate pattern is transferred to the film 3 and the gate insulating film 2. Thereafter, by removing the resist by ashing and washing, as shown in FIG. 1A, the second conductive film is provided on the semiconductor substrate 1 with the gate insulating film 2 interposed therebetween and on the first conductive film 3. A gate electrode 31 having a structure in which the film 4 is laminated is obtained.

  Next, a first insulating film made of a silicon nitride film is formed on the semiconductor substrate 1 so as to cover the gate electrode 31. The first sidewall 5 is formed by performing dry etching on the entire surface, leaving the portions formed on the side surfaces of the gate electrode 31 and the gate insulating film 2 and removing the remaining portions of the first insulating film. To do.

Thereafter, for example, N-type impurities such as arsenic (As) are ion-implanted into the semiconductor substrate 1 using the gate electrode 31 and the first sidewall 5 as a mask under the condition that the implantation dose is 1 × 10 ¹⁵ / cm ^2. To do. As a result, a shallow first doping region 32 is formed below the first sidewall 5 in the semiconductor substrate 1.

  Subsequently, as shown in FIG. 1B, a silicon oxide film 6 and a silicon nitride film 7 stacked thereon are sequentially formed on the semiconductor substrate 1 so as to cover the gate electrode 31 and the first sidewall 5. .

  Subsequently, the process shown in FIG. Here, the silicon oxide film 6 and the silicon nitride film 7 are etched back by dry etching on the entire surface, and the second sidewall 21 is formed on the side surface of the gate electrode via the first sidewall 5. The second sidewall 21 includes a silicon oxide film 6 having an L-shaped cross-section by a portion along the first sidewall 5 and a portion along the semiconductor substrate 1, and a gate electrode 31 with respect to the silicon oxide film 6. And a silicon nitride film 7 located on the opposite side.

Here, the dry etching conditions for the silicon nitride film 7 are, for example, a source power of 800 W, a bias power of 100 W, a gas flow rate of CH ₂ F ₂ / O ₂ / Ar = 10/10/100 ml / min, and a pressure of O . 4 Pa and substrate temperature are 0 degreeC.

The dry etching conditions for the silicon oxide film 6 include, for example, a source power of 1000 W, a bias power of 100 W, a gas flow rate of CHF ₃ / O ₂ / Ar = 50/20/200 ml / min, a pressure of 0.4 Pa, and The substrate temperature is 0 ° C.

  Further, after the second sidewall 21 is formed, etching is performed under conditions for etching the silicon nitride film, and a part of the upper portion of the first sidewall 5 is removed to form the recess portion 8. At this time, the recess amount can be adjusted by adjusting dry etching conditions (for example, etching time).

  Subsequently, as shown in FIG. 2A, the second sidewall 21 and the gate electrode 31 are covered on the entire surface of the semiconductor substrate 1, and the recessed portion 8 provided on the first sidewall 5 is embedded. Thus, a silicon oxide film 9a is formed.

  Next, as shown in FIG. 2B, the entire surface of the silicon oxide film 9a is dry-etched. As a result, the silicon oxide film 9a other than the portion where the recessed portion 8 is buried on the first sidewall 5 is removed, and the silicon oxide film left in the recessed portion 8 is used as the third sidewall 9b.

Etching conditions at this time are, for example, a source power of 1000 W, a bias power of 100 W, a gas flow rate of CHF ₃ / O ₂ / Ar = 50/20/200 ml / min, a pressure of 0.4 Pa, and a substrate temperature of 0 ° C. is there.

After forming the third side wall 9b, the gate electrode 31, the first side wall 5, the second side wall 21, and the third side wall are formed under the condition of an implantation dose amount of 1 × 10 ¹⁵ / cm ² , for example. N-type impurities such as arsenic (As) are ion-implanted into the semiconductor substrate 1 using 9b as a mask. As a result, a second doping region 33 that is deeper than the first doping region 32 is formed below the second sidewall 21 in the semiconductor substrate 1. Further, the implanted N-type impurities are activated by heat treatment to form N-type source / drain regions.

  Next, the process shown in FIG. First, the silicon nitride film 7 which is a part of the second side wall 21 is removed, the silicon oxide film 6 which is the remaining part of the second side wall 21, and the silicon oxide film provided in the recess portion 8. The third side wall 9b made of is left.

  For this purpose, an etching method having etching selectivity with respect to the silicon oxide film and the silicon nitride film, for example, wet etching using hot phosphoric acid may be used.

  When hot phosphoric acid is used, the selectivity of the silicon nitride film to the silicon oxide film (the value obtained by dividing the etching rate of the silicon nitride film by the etching rate of the silicon oxide film) is approximately 100. Therefore, the first sidewall 5 made of the silicon nitride film is removed if it is etched with hot phosphoric acid. However, the first side wall 5 includes a third side wall 9b made of a silicon oxide film for embedding the recessed portion 8 thereon, and a silicon oxide film 6 (a part of the second side wall 21) covering the side surface. The whole surface is covered with. For this reason, even when the silicon nitride film 7 (the other part of the second sidewall 21) is removed using hot phosphoric acid, the first sidewall 5 is not removed.

  Next, a silicide forming metal film (not shown) made of, for example, nickel (Ni) is formed on the entire surface of the semiconductor substrate 1 by sputtering. Thereafter, the second conductive film 4 of the gate electrode 31 and the silicon of the second doping region 33 are reacted with nickel of the metal film for silicide formation by heat treatment. Thereby, a metal silicide layer (a metal silicide layer 10a in the doping region and a metal silicide layer 10b on the gate electrode) made of nickel silicide is formed on the second conductive film 4 and the second doping region 33 of the gate electrode 31. Form. Thereafter, the unreacted silicide forming metal film remaining on the third sidewall 9b, the second sidewall 21 (silicon oxide film 6), and the like is removed by etching.

  Next, as shown in FIG. 3A, a stopper film 11 made of, for example, a silicon nitride film is formed on the semiconductor substrate 1. Further, a silicon oxide film, for example, is formed on the stopper film 11 and planarized by the CMP (Chemical Mechanical Polishing) method to form the interlayer insulating film 12.

  Next, as shown in FIG. 3B, a contact hole 13 (shared contact hole) is formed that opens one of the second doping regions 33 (source region or drain region) and a region extending over the gate electrode 31. To do.

  For this purpose, a resist (not shown) having a contact hole pattern corresponding to the contact hole 13 is first formed on the interlayer insulating film 12. Next, the interlayer insulating film 12 is selectively etched by dry etching using the resist as a mask, and the resist is removed by ashing and cleaning, thereby forming a contact hole reaching the surface of the stopper film 11. Thereafter, using the dry etching technique again, the stopper film 11 is selectively etched using the interlayer insulating film 12 in which the contact holes are formed as a mask. As a result, the contact hole 13 reaches both the second doping region 33 and the gate electrode 31 formed in the semiconductor substrate 1 (more precisely, connected to the metal silicide layers 10a and 10b formed on the respective upper portions). Form.

  Next, as shown in FIG. 3C, a barrier metal film (not shown) made of, for example, titanium nitride (TiN) is formed on the bottom and side walls of the contact hole 13. Thereafter, a conductive film made of, for example, tungsten (W) is embedded in the contact hole 13 via a barrier metal film. Further, the conductive film and the barrier metal film are removed until the upper surface of the interlayer insulating film 12 is exposed to obtain a contact plug 14. For removal of the conductive film and the barrier metal film, whole surface dry etching using a dry etching technique, polishing by a CMP method, or the like can be used.

  As described above, a transistor structure having a shared contact can be obtained.

  According to the manufacturing method of the present embodiment, the first side wall 5 made of a silicon nitride film is provided below the side wall of the gate electrode 31, and the third side wall 9b made of silicon oxide is provided above the side wall of the gate electrode 31. Furthermore, a silicon oxide film 6 (remaining portion of the second sidewall 21) is provided on the side wall of the first sidewall 5. Thus, since the first sidewall 5 is covered with the third sidewall 9b and the silicon oxide film 6, these serve as a protective layer, and when the stopper film 11 in the process of forming the contact hole 13 is removed. It is not etched. Therefore, even in the cleaning process, which is the next process, the metal material of the gate electrode 31 is not dissolved, and an abnormal shape of the gate electrode can be suppressed.

  In this embodiment, the case where the conductivity type of the MIS transistor formed on the semiconductor substrate is N type has been described as an example. However, the present invention is not limited to this, and the same effect can be obtained even when the type is P type. it can.

  Moreover, although the case where a TiN film is used as the first conductive film 3 has been described, a metal film (metal-containing film) such as a TaN film, a TaC film, a TaCNO film, or a W film may be used.

  A silicon nitride film was used as the first insulating film for forming the first sidewall 5. However, other than this, a SiC film, a SiCN film, or the like may be used.

  Further, the silicon oxide film 6 constituting the second sidewall 21 can obtain the same effect even if it is replaced with another insulating film mainly composed of a silicon oxide film such as a PSG film, a BSG film, or a BPSG film. it can.

  Although the case where the third sidewall 9b is formed of a silicon oxide film has been described, other insulating films mainly composed of a silicon oxide film such as a PSG film, a BSG film, and a BPSG film may be used. Alternatively, a coating type silicon oxide film such as polyimide may be used.

  Further, although the case where the silicide layer is formed in at least one of the gate electrode 31 and the second doping region 33 (source / drain region) has been described, this is not essential. Even when the silicide layer is not formed, the effect of preventing the shape abnormality of the gate electrode can be obtained.

Further, the case where Ni is used for the metal film for silicide formation and a metal silicide film made of NiSi _{2 is} described. However, in addition to this, silicidation may be performed using a metal film such as Co or NiPt to form a metal silicide film such as CoSi ₂ or NiPtSi.

  The reason why the silicon nitride film 7 which is a part of the second sidewall 21 is removed in the step of FIG. 2C is to facilitate the removal of the stopper film 11 in the step of FIG. . That is, the stopper film 11 may fill the space left between the gate electrodes 31 at a place where the distance between the adjacent gate electrodes 31 is narrow, while the stopper film 11 is formed at a place where the distance between the gate electrodes 31 is wide. A desired film thickness is formed. When such a difference in film thickness occurs, it may be difficult to remove the stopper film 11. Therefore, by removing the silicon nitride film 7 after forming the second doping region 33, the space left between the gate electrodes 31 is widened to avoid being embedded by the stopper film 11. Thereby, the stopper film 11 can be easily removed.

  The semiconductor device and the manufacturing method thereof according to the present invention can prevent an abnormal shape of the gate electrode in the MIS transistor structure having the sidewall, and in particular, the shared contact is formed on the gate electrode having the sidewall. It is also useful for semiconductor devices and manufacturing methods thereof.

1A to 1C are process cross-sectional views illustrating a method for manufacturing an exemplary semiconductor device according to an embodiment of the present invention. 2A to 2C are process cross-sectional views illustrating the manufacturing method of the exemplary semiconductor device according to the embodiment of the present invention following FIG. 1C. 3A to 3C are process cross-sectional views illustrating the method for manufacturing the exemplary semiconductor device according to the embodiment of the present invention following FIG. 2C. 4A to 4C are process cross-sectional views illustrating a conventional method for manufacturing a semiconductor device. 5A to 5C are process cross-sectional views illustrating a conventional method for manufacturing a semiconductor device following FIG. 4C.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate insulating film 3 1st electrically conductive film 4 2nd electrically conductive film 5 1st side wall 6 Silicon oxide film 7 Silicon nitride film 8 Recessed part 9a Silicon oxide film 9b 3rd side wall 10 Metal silicide layer 11 Stopper film 12 Interlayer insulating film 13 Contact hole 14 Contact plug 21 Second sidewall 31 Gate electrode 32 First doping region 33 Second doping region

Claims (12)

A transistor having a gate electrode formed on a substrate via a gate insulating film, and an impurity region formed on both sides of the gate electrode in the substrate;
An interlayer insulating film formed on the substrate so as to cover the transistor;
A shared contact that penetrates the interlayer insulating film and is electrically connected to the impurity region and the gate electrode;
A first sidewall is formed so as to cover at least a lower portion of the side surface of the gate electrode;
A second sidewall is formed so as to cover a side surface of the first sidewall opposite to the gate electrode;
A third sidewall is formed on the first sidewall so as to be sandwiched between the upper side surface of the gate electrode and the second sidewall,
The second side wall and the third side wall are both made of a material different from that of the first side wall. In claim 1,
The interlayer insulating film has a structure in which a first interlayer insulating film as a lower layer and a second interlayer insulating film as an upper layer are laminated,
The semiconductor device according to claim 1, wherein the first interlayer insulating film is made of a material different from both the second sidewall and the third sidewall. In claim 1 or 2,
2. The semiconductor device according to claim 1, wherein the material of the second sidewall and the material of the third sidewall are a silicon oxide film, a PSG film, a BSG film, or a BPSG film, respectively. In any one of Claims 1-3,
The semiconductor device is characterized in that the material of the first sidewall is a silicon nitride film, a silicon carbide film, or a silicon carbonitride film. In any one of Claims 1-4,
The semiconductor device, wherein the gate electrode contains a metal material. In any one of Claims 1-5,
The semiconductor device, wherein the impurity region includes a first impurity region and a second impurity region formed deeper than the first impurity region. Forming a gate electrode including a metal material on a substrate via a gate insulating film, and forming an impurity region on both sides of the gate electrode in the substrate;
Forming a first sidewall made of a first insulating film on the side surface of the gate electrode;
After forming a second insulating film on the entire surface of the substrate, a second sidewall made of the second insulating film is formed on a side surface of the first sidewall by etching back using a dry etching method. Step (c) to perform,
(D) forming a recess by removing an upper portion of the first sidewall using a dry etching method;
After forming the third insulating film embedded in the recess, the third insulating film other than the recess is removed by using a dry etching method, and a third insulating film made of the third insulating film is formed in the recess. A step (e) of forming a sidewall of step (f), and a step (f) of forming an interlayer insulating film on the entire surface of the semiconductor substrate after the step (e),
A step (g) of forming a contact hole that opens over the impurity region and the gate electrode in the interlayer insulating film;
And (h) forming a shared contact by filling the contact hole with a conductive material,
The method of manufacturing a semiconductor device, wherein the first sidewall is made of a material different from any of the second sidewall and the third sidewall. In claim 7,
In the step (c), a fourth insulating film is further formed on the second insulating film, and a second sidewall made of the second insulating film and the fourth insulating film is formed.
A method of manufacturing a semiconductor device, further comprising a step of removing the fourth insulating film on the second sidewall between the step (e) and the step (f). In claim 7 or 8,
In the step (f), the interlayer insulating film composed of a first interlayer insulating film as a lower layer and a second interlayer insulating film as an upper layer is formed,
In the step (g), after the second interlayer insulating film is etched using the first interlayer insulating film as an etch stopper, the first interlayer insulating film is etched,
The method of manufacturing a semiconductor device, wherein the first interlayer insulating film is made of a material different from both the second sidewall and the third sidewall. In any one of Claims 7-9,
The method of manufacturing a semiconductor device, wherein the second sidewall and the third sidewall are respectively a silicon oxide film, a PSG film, a BSG film, or a BPSG film. In any one of Claims 7-10,
A method of manufacturing a semiconductor device, wherein the material of the first sidewall is a silicon nitride film, a silicon carbide film, or a silicon carbonitride film. In any one of Claims 7-11,
Between the step (e) and the step (f),
Introducing an impurity into the substrate using the first sidewall, the second sidewall, the third sidewall, and the gate electrode as a mask to form another impurity region deeper than the impurity region; A method for manufacturing a semiconductor device, further comprising:

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