JP2010212299A - Method of manufacturing laminated semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a laminated semiconductor device in which a relative position can be adjusted. <P>SOLUTION: An SOI (silicon-on-insulator) substrate, which has an insulating layer and an SOI layer formed in contact with the insulating layer, has: a through hole which penetrates between a top surface and a reverse surface of an SOI substrate; and a through connection portion which is formed in the through hole, and which electrically connects the top surface and reverse surface together. The method of manufacturing the laminated semiconductor device includes: the step of preparing the SOI substrate, to either surface of the top surface or reverse surface of which a support substrate is laminated; the step of adjusting the relative position between the support substrate and the other substrate so that the through connection portion of a surface, to which the support substrate of the SOI substrate is not laminated, is electrically connected to the prescribed position of the other substrate; and the step of pressing and contacting the SOI substrate and the other substrate, by making the gap between the SOI substrate and the other substrate narrow while maintaining the adjusted relative position. In the step of adjusting the relative position, the relative position is adjusted based on an index formed in a region, which is a side part of the support substrate and to which the SOI substrate is not laminated, and a position index of the other substrate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a stacked semiconductor device in which a plurality of semiconductor substrates are stacked and bonded.

  2. Description of the Related Art A stacked semiconductor device in which a plurality of semiconductor chips are stacked and bonded for the purpose of improving the performance of the semiconductor device without increasing the area is known. In a manufacturing process of a laminated semiconductor device, wafers on which a plurality of semiconductor elements are formed may be aligned and then bonded. In the three-dimensional LSI stacking apparatus disclosed in Patent Document 1, the wafers are aligned after confirming the alignment marks provided on the wafer with an infrared microscope, and then bonded.

Japanese Patent No. 2984441

  In some cases, a semiconductor element is formed on an SOI substrate having an SOI (silicon-on-insulator) layer for the purpose of improving the operation speed of the semiconductor device. A side portion of the SOI substrate may not be suitable for forming a semiconductor element, and the side portion can be effectively used by forming the alignment mark on the side portion. However, in the manufacturing process of the laminated semiconductor device, when the side portion is cut off, the positioning mark is also cut off.

  In order to solve the above-mentioned problem, in the first aspect of the present invention, an SOI substrate having an SOI layer formed in contact with the insulating layer and the insulating layer, and penetrates between the front surface and the back surface of the SOI substrate. An SOI having a through-hole and a through-coupling portion formed in the through-hole for electrically coupling the front surface and the back surface, and a support substrate attached to either the front surface or the back surface of the SOI substrate Prepare the substrate and adjust the relative position of the support substrate and the other substrate so that the through-bonding part of the surface of the SOI substrate where the support substrate is not affixed is electrically coupled to the predetermined position of the other substrate And maintaining the adjusted relative position while narrowing the gap between the SOI substrate and the other substrate and pressing the SOI substrate with the other substrate, and adjusting the relative position is supported. SOI substrate on the side of the substrate And index formed on Affixed non regions, based on the position indication of the other substrate, a manufacturing method of a stacked semiconductor device for adjusting the relative position is provided.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

An example of the section of substrate pasting device 200 is shown roughly. An example of the top view of SOI substrate 120 bonded together by substrate bonding apparatus 200 is shown roughly. An example of the section of SOI substrate 120 bonded together by substrate bonding apparatus 200 is shown roughly. An example of the section of SOI substrate 150 bonded together by substrate bonding apparatus 200 is shown roughly. An example of the cross section of the laminated semiconductor substrate 110 obtained by bonding the SOI substrate 120 and the SOI substrate 150 is shown schematically. An example of the manufacturing method of the laminated semiconductor device 100 is shown roughly.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 schematically shows an example of a cross section of the substrate bonding apparatus 200. The substrate bonding apparatus 200 manufactures a three-dimensional stacked semiconductor substrate by, for example, bonding the SOI substrate 120 and the SOI substrate 150 by applying pressure and heating. The substrate bonding apparatus 200 includes a frame body 210, a pressing unit 220 disposed inside the frame body 210, a pressure stage 230, a pressure receiving stage 240, and a pressure detection unit 250.

  The frame body 210 includes a top plate 212 and a bottom plate 216 that are parallel and horizontal to each other, and a plurality of columns 214 that couple the top plate 212 and the bottom plate 216. The top plate 212, the support column 214, and the bottom plate 216 have such a rigidity that deformation does not occur when a reaction force against pressure is applied to the SOI substrate 120 or the SOI substrate 150.

  The pressing part 220 is disposed on the bottom plate 216 inside the frame body 210. The pressing unit 220 includes a cylinder 222 that is fixed to the upper surface of the bottom plate 216 and a piston 224 that is disposed inside the cylinder 222. The piston 224 is driven by a fluid circuit (not shown), a cam, a train wheel, and the like, and moves up and down in a direction perpendicular to the bottom plate 216 indicated by an arrow Z in the drawing.

  The pressure stage 230 is mounted on the upper end of the piston 224. The pressure stage 230 includes a horizontal plate-like support portion 232 coupled to the upper end of the piston 224 and a plate-like first substrate holding portion 234 parallel to the support portion 232.

  The first substrate holding unit 234 is supported by the support unit 232 via a plurality of actuators 235. In addition to the pair of actuators 235 shown in the figure, the actuator 235 is also arranged forward and backward with respect to the paper surface. Each of these actuators 235 can be operated independently of each other. With such a structure, the inclination of the first substrate holding part 234 can be arbitrarily changed by appropriately operating the actuator 235. The first substrate holding unit 234 includes a heater 236 and is heated by the heater 236.

  The first substrate holding unit 234 attracts the support substrate 350 to the upper surface thereof by electrostatic adsorption, vacuum adsorption, or the like. The first substrate holding unit 234 sucks the surface of the support substrate 350 where the SOI substrate 150 is not attached. As a result, the support substrate 350 and the SOI substrate 150 swing together with the first substrate holding unit 234, while the support substrate 350 and the SOI substrate 150 are prevented from moving or dropping from the first substrate holding unit 234.

  The pressure receiving stage 240 includes a second substrate holding part 242 and a plurality of suspension parts 244. The suspension portion 244 is suspended from the lower surface of the top plate 212. The second substrate holding unit 242 is supported from below in the vicinity of the lower end of the suspension unit 244 and is disposed to face the pressure stage 230. The second substrate holding unit 242 includes a heater 246 and is heated by the heater 246.

  The second substrate holding part 242 is supported by the suspension part 244 from below, but the upward movement is not restricted. However, a plurality of load cells 252, 254 and 256 are sandwiched between the top plate 212 and the second substrate holding part 242. The plurality of load cells 252, 254, 256 form a part of the pressure detection unit 250, regulate upward movement of the second substrate holding unit 242, and are applied upward to the second substrate holding unit 242. Detect pressure.

  The second substrate holding unit 242 attracts the support substrate 320 to the lower surface thereof by electrostatic adsorption, vacuum adsorption, or the like. The second substrate holding unit 242 sucks the surface of the support substrate 320 on which the SOI substrate 120 is not attached. As a result, the support substrate 320 and the SOI substrate 120 swing together with the second substrate holding unit 242, while the support substrate 320 and the SOI substrate 120 are prevented from moving or dropping from the second substrate holding unit 242.

  In the state shown in FIG. 1, the support column 214 of the pressing unit 220 is drawn into the cylinder 222, and the pressure stage 230 is lowered. Therefore, there is a wide gap between the pressure stage 230 and the pressure receiving stage 240.

  Of the pair of SOI substrates 120 and SOI substrates 150 to be bonded, one SOI substrate 150 is inserted into the gap from the side and placed on the pressure stage 230. Similarly, the other SOI substrate 120 is inserted from the side into the gap, and held on the pressure receiving stage 240 so as to face the SOI substrate 150. The SOI substrate 120 may be inserted into the substrate bonding apparatus 200 with the support substrate 320 attached, or may be inserted into the substrate bonding apparatus 200 without the support substrate 320 attached. May be.

  As shown in FIG. 1, a support substrate 320 may be attached to one surface of the SOI substrate 120. Similarly, a support substrate 350 may be attached to one surface of the SOI substrate 150. In the present embodiment, the surface of the SOI substrate 120 on which the support substrate 320 is not attached is bonded to the surface of the SOI substrate 150 on which the support substrate 350 is not attached. Further, as shown in FIG. 1, in this embodiment, the diameters of the SOI substrate 120 and the SOI substrate 150 are smaller than the diameters of the support substrate 320 and the support substrate 350.

  The SOI substrate 120 and the SOI substrate 150 are aligned with each other in a plane orthogonal to the Z direction. The alignment between the SOI substrate 120 and the SOI substrate 150 may be performed by the substrate bonding apparatus 200, or the SOI substrate 120 and the SOI substrate 150 aligned by another alignment apparatus are the substrate bonding apparatus. 200 may be conveyed.

  When aligning the SOI substrate 120 and the SOI substrate 150 by the substrate bonding apparatus 200, for example, the pressing unit 220 moves in the Z direction and the Z direction between the first substrate holding unit 234 and the second substrate holding unit 242. The relative position in the direction perpendicular to the direction of rotation may be adjusted. Here, the rotation direction indicates an inclination with respect to a plane orthogonal to the Z direction.

  In this case, the pressing part 220 is driven by, for example, an elastic deformation body, a piezoelectric element or the like (not shown), and the relative position between the first substrate holding part 234 and the second substrate holding part 242 is set to submicron, nanometer. You may adjust precisely in units. The pressing unit 220 is driven by, for example, a servo motor (not shown), a feed screw, or the like, and roughly adjusts the relative position between the first substrate holding unit 234 and the second substrate holding unit 242 with a large stroke and low resolution. It's okay. The pressing unit 220 may execute the fine adjustment after the coarse adjustment.

  After the SOI substrate 120, the support substrate 320, the SOI substrate 150, and the support substrate 350 are disposed at predetermined positions of the substrate bonding apparatus 200, the pressure stage 230 is raised toward the pressure receiving stage 240, and the SOI substrate 120. And the SOI substrate 150 are pressed. Further, the heaters 246 and 236 heat the pressure stage 230 and the pressure receiving stage 240 during pressing. Thereby, the SOI substrate 120 and the SOI substrate 150 are joined.

  In the present embodiment, the case where the SOI substrate 120 is bonded to the SOI substrate 150 has been described. However, the present invention is not limited to this. For example, the SOI substrate 120 may be bonded to another substrate such as a Si substrate.

  FIG. 2 schematically shows an example of a cross section of the SOI substrate 120. As illustrated in FIG. 2, the SOI substrate 120 includes a substrate body 132, an insulating layer 134, and an SOI layer 136 in this order. The SOI layer 136 may be formed in contact with the insulating layer 134. The substrate body 132 may be a silicon substrate, for example. The insulating layer 134 suppresses current leakage from the SOI layer 136 to the substrate body 132. In the present embodiment, the substrate body 132 is disposed on the back surface 129 side of the SOI substrate 120, and the SOI layer 136 is disposed on the front surface 121 side of the SOI substrate 120.

  The SOI substrate 120 has a through hole 123 penetrating between the front surface 121 and the back surface 129 of the SOI substrate 120. The through hole 123 may be an example of a through hole. The through hole can be formed by, for example, etching or laser processing.

  The SOI substrate 120 has an alignment mark 124 on the surface 121. The alignment mark 124 may be an example of a representative index. In the present embodiment, the alignment mark 124 is formed outside the region of the SOI substrate 120 where the semiconductor chip 122 is formed in the SOI substrate 120. For example, the alignment mark 124 can be formed by patterning a metal thin film such as Al by etching or the like.

  The planar shape of the alignment mark 124 viewed from the Z direction may be a stripe shape, a lattice shape, or a cross shape. As another aspect of the alignment mark 124, a specific bump 128 may be used. Note that a plurality of alignment marks 124 may be included in one SOI substrate 120. A part of the semiconductor chip 122 may be used as the alignment mark 124. Further, the alignment mark 124 may be formed on the back surface 129 of the SOI substrate 120.

  The SOI substrate 120 has a plurality of semiconductor chips 122. The individual semiconductor chips 122 are cut out from the SOI substrate 120 by, for example, a dicing process after bonding. The semiconductor chip 122 includes a semiconductor element 127 formed in the SOI layer 136, a bump 128 that electrically couples the semiconductor element 127 and another semiconductor element, and an embedded that electrically couples the semiconductor element 127 and the bump 128. An electrode 126 is included.

  The embedded electrode 126 may be an example of a through coupling part. The embedded electrode 126 is formed in the through hole 123 and electrically couples the front surface 121 and the back surface 129. The embedded electrode 126 can be formed by embedding a conductive material such as Cu in the through hole 123 by a plating method or the like.

  The bump 128 is formed on the back surface 129 of the SOI substrate 120, for example. The bump 128 is formed to be more convex than the back surface 129. The bump 128 is electrically coupled to the embedded electrode 126. The embedded electrode 126 is also electrically coupled to the semiconductor element 127. Thereby, even when the semiconductor element 127 is formed on the surface 121 of the SOI substrate 120, the semiconductor element 127 and the bump 128 are electrically coupled via the embedded electrode 126. For the bump 128, for example, a conductive material such as solder or Au is used.

  A support substrate 320 may be attached to the surface 121 of the SOI substrate 120. The SOI substrate 120 and the support substrate 320 may be attached concentrically. The support substrate 320 may be a silicon substrate. In this embodiment, the SOI substrate 120 is processed so that the outer peripheral portion is cut away and the diameter is reduced before the support substrate 320 is attached. Thus, a region 324 where the SOI substrate 120 is not attached is formed on the side portion 322 of the support substrate 320.

  In the region 324, an index 326 may be formed. The index 326 may be a fiducial mark for substrate alignment. The index 326 can be formed by a laser using, for example, a laser irradiation method. The index 326 can be formed in any shape at any position in the region 324 regardless of the position, size, or the like of the alignment mark 124 or the semiconductor element 127 formed on the SOI substrate 120. Thereby, by using the index 326 as an index for alignment, alignment can be performed easily and accurately. Further, in the manufacturing process of the laminated semiconductor device, the alignment can be performed even when the alignment mark 124 is removed.

  In this embodiment, the case where the support substrate 320 is attached to the front surface 121 of the SOI substrate 120 and the bumps 128 are formed on the back surface 129 of the SOI substrate 120 has been described, but the present invention is not limited to this. For example, the support substrate 320 may be attached to the back surface 129 of the SOI substrate 120 and the bumps 128 may be formed on the front surface 121 of the SOI substrate 120.

  FIG. 3 schematically shows an example of a plan view of the SOI substrate 120. As shown in FIG. 3, a large number of semiconductor chips 122 are formed vertically and horizontally on the SOI substrate 120. An alignment mark 124 representative of the position of the embedded electrode 126 of the SOI substrate 120 may be formed on the SOI substrate 120. An index 326 may be formed in a region 324 of the support substrate 320 where the SOI substrate 120 is not attached. The support substrate 320 may have a notch 328. The notch may be an example of an orientation mark.

  FIG. 4 schematically shows an example of a cross section of the SOI substrate 150. The SOI substrate 150 may be an example of another substrate. The SOI substrate 150 may have a configuration similar to that of the SOI substrate 120. The SOI substrate 150 includes a substrate body 162, an insulating layer 164, and an SOI layer 166 in this order. The substrate body 162, the insulating layer 164, and the SOI layer 166 have the same configuration as the substrate body 132, the insulating layer 134, and the SOI layer 136, respectively, and thus description thereof is omitted. In the present embodiment, the substrate main body 162 is disposed on the back surface 159 side of the SOI substrate 150, and the SOI layer 166 is disposed on the front surface 151 side of the SOI substrate 150.

  A support substrate 350 may be attached to the surface 151 of the SOI substrate 150. A region 354 where the SOI substrate 150 is not attached may be formed on the side portion 352 of the support substrate 350. The support substrate 350, the side portion 352, and the region 354 have the same configuration as the support substrate 320, the side portion 322, and the region 324, respectively, and thus description thereof is omitted. In the region 354, an index 356 may be formed. The index 356 may be an example of a position index of another substrate. The indicator 356 may have a configuration similar to that of the indicator 326.

  The SOI substrate 150 has a through hole 153 that penetrates between the front surface 151 and the back surface 159 of the SOI substrate 150. The through hole 153 may be an example of a through hole. The through hole 153 can be formed by, for example, etching or laser processing.

  The SOI substrate 150 has a plurality of semiconductor chips 152. The semiconductor chip 152 may have a configuration similar to that of the semiconductor chip 122. In the present embodiment, the semiconductor chip 152 includes a buried electrode 156, a semiconductor element 157, and a bump 158. Since the embedded electrode 156, the semiconductor element 157, and the bump 158 have the same configuration as the embedded electrode 126, the semiconductor element 127, and the bump 128, respectively, description thereof is omitted.

  The SOI substrate 150 may have an alignment mark 154 similar to the alignment mark 124 of the SOI substrate 120. The alignment mark 154 may be an example of a position index of another substrate.

  FIG. 5 schematically shows an example of a cross section of the laminated semiconductor substrate 110. In the present embodiment, the laminated semiconductor substrate 110 is obtained by laminating an SOI substrate 120 and an SOI substrate 150. As shown in FIG. 5, the SOI substrate 120 and the SOI substrate 150 are bonded via bumps 128 formed on the back surface 129 of the SOI substrate 120 and bumps 158 formed on the back surface 159 of the SOI substrate 150. Thereby, the semiconductor chip 122 formed on the SOI substrate 120 and the semiconductor chip 152 formed on the SOI substrate 150 are stacked, and the stacked semiconductor device 100 is obtained.

  For example, the laminated semiconductor substrate 110 is formed by adjusting the relative positions of the SOI substrate 120 and the SOI substrate 150 so that the bumps 128 and the bumps 158 are bonded using the substrate bonding apparatus 200. It is obtained by being bonded to the SOI substrate 150. A plurality of stacked semiconductor devices 100 may be formed on the stacked semiconductor substrate 110. Each laminated semiconductor device 100 is obtained by cutting the laminated semiconductor substrate 110 by dicing or the like.

  In this embodiment, the case where the SOI substrate 120 and the SOI substrate 150 are bonded so that the back surface 129 of the SOI substrate 120 and the back surface 159 of the SOI substrate 150 face each other has been described. The method for attaching the substrate 150 is not limited to this. For example, the back surface 129 of the SOI substrate 120 and the front surface 151 of the SOI substrate 150 may be bonded to each other, and the front surface 121 of the SOI substrate 120 and the back surface 159 of the SOI substrate 150 may be bonded to each other. May be. Alternatively, the surface 121 of the SOI substrate 120 and the surface 151 of the SOI substrate 150 may be bonded to face each other.

  FIG. 6 shows an example of a method for manufacturing the stacked semiconductor device 100. As described with reference to FIG. 5, the stacked semiconductor device 100 is obtained by cutting the stacked semiconductor substrate 110. The laminated semiconductor substrate 110 can be manufactured using, for example, the substrate bonding apparatus 200. Hereinafter, a method for manufacturing a stacked semiconductor device will be described using the stacked semiconductor device 100 obtained by stacking the semiconductor chip 122 and the semiconductor chip 152 as an example.

  In this embodiment, the SOI substrate 120 and the SOI substrate 150 are prepared in S602. The SOI substrate 120 can be prepared by the following procedure, for example. First, an SOI substrate having the substrate body 132, the insulating layer 134, and the SOI layer 136 in this order is prepared. The SOI substrate may be a commercially available SOI substrate.

  The alignment mark 124 and the semiconductor element 127 are formed on the SOI layer 136 using a semiconductor manufacturing process. After the through hole 123 is formed in the SOI substrate by laser processing, a buried electrode 126 is formed in the through hole 123 by a plating method, and the SOI substrate 120 is obtained. In addition, the outer periphery of the SOI substrate 120 may be trimmed. Thereby, the diameter of the SOI substrate 120 becomes smaller than the diameter of the commercially available SOI substrate.

  Next, a support substrate 320 is attached to the surface 121 of the SOI substrate 120. An index 326 may be formed in a region 324 of the support substrate 320 where the SOI substrate 120 is not attached. The indicator 326 may be formed before the support substrate 320 is attached to the SOI substrate 120, or may be formed after the support substrate 320 is attached to the SOI substrate 120. As described above, the SOI substrate 120 can be prepared. The SOI substrate 150 can also be prepared by the same procedure as that for the SOI substrate 120.

  In this embodiment, before adjusting the relative position between the SOI substrate 120 and the SOI substrate 150, the relative positional relationship between the alignment mark 124 of the SOI substrate 120 and the index 326 of the support substrate 320 is measured in advance in S604. . The relative positional relationship can be measured, for example, by observation with an infrared microscope or the like. Similarly, the relative positional relationship between the alignment mark 154 of the SOI substrate 150 and the index 356 of the support substrate 350 may be measured in advance.

  In this embodiment, before the relative position between the SOI substrate 120 and the SOI substrate 150 is adjusted, the relative position between the SOI substrate 120 and the SOI substrate 150 is roughly adjusted in S606. The rough adjustment of the relative position may be performed using the notch 328 of the support substrate 320. For example, when viewed from the Z direction, the horizontal direction of the first substrate holding unit 234 and the second substrate holding unit 242 of the substrate bonding apparatus 200 so that the notch 328 of the support substrate 320 matches the notch of the support substrate 350, The rough adjustment is performed by adjusting the relative positions in the rotation direction and the vertical direction.

  In S608, the relative position between the SOI substrate 120 and the SOI substrate 150 is adjusted. The relative positions of the SOI substrate 120 and the SOI substrate 150 are such that one or both of the substrates are moved so that the alignment mark 124 of the SOI substrate 120 and the alignment mark 154 of the SOI substrate 150 coincide with each other when viewed from the Z direction. You may adjust with.

  As another aspect of the adjustment of the relative position, in the adjustment of the relative position, the embedded electrode 126 on the back surface 129 to which the support substrate 320 of the SOI substrate 120 is not attached is electrically coupled to a predetermined position of the SOI substrate 150. Thus, the relative position between the support substrate 320 and the SOI substrate 150 may be adjusted. This facilitates the adjustment of the relative position. In this embodiment, the relative relationship between the support substrate 320 and the SOI substrate 150 is such that the embedded electrode 126 of the SOI substrate 120 is electrically coupled to the embedded electrode 156 of the SOI substrate 150 via the bump 128 and the bump 158. The position is adjusted.

  The relative position may be adjusted based on the index 326 on the support substrate 320 and the alignment mark 154 on the SOI substrate 150. For example, using the index 356 of the support substrate 350 as the position index of the SOI substrate 150, the relative position is adjusted so that the index 326 of the support substrate 320 and the index 356 of the support substrate 350 coincide with each other when viewed from the Z direction. You can do it.

  As another aspect of the adjustment of the relative position, the relative position between the SOI substrate 120 and the SOI substrate 150 is calculated based on the index 326 of the support substrate 320, the position index of the SOI substrate 150, and the relative positional relationship measured in S604. You may adjust. For example, as many bumps 128 and bumps 158 as possible can be joined using the relative positional relationship between the alignment mark 124 and the index 326 and the relative positional relationship between the alignment mark 154 and the index 356 measured in S604. The relative position between the SOI substrate 120 and the SOI substrate 150 can be calculated. Using the index 326 of the support substrate 320, the position index of the SOI substrate 150, and the calculation result, for example, the relative positions of the SOI substrate 120 and the SOI substrate 150 can be adjusted by the following procedure.

  First, using the index 356 of the support substrate 350 as the position index of the SOI substrate 150, the relative position is adjusted so that the index 326 of the support substrate 320 and the index 356 of the support substrate 350 coincide with each other when viewed from the Z direction. . Next, as many bumps 128 and bumps 158 as possible can be joined using the relative positional relationship between the alignment mark 124 and the index 326 and the relative positional relationship between the alignment mark 154 and the index 356 measured in S604. The relative position between the SOI substrate 120 and the SOI substrate 150 is calculated. Then, the relative position between the SOI substrate 120 and the SOI substrate 150 can be adjusted by moving the SOI substrate 150 from the position where the index 326 and the index 356 coincide with each other to the position obtained by the above calculation.

  As another aspect of adjusting the relative position between the SOI substrate 120 and the SOI substrate 150 based on the relative positional relationship measured in S604, for example, a case where a plurality of indices 326 and indices 356 are formed can be exemplified. In this case, a combination of a specific index 326 and a specific index 356 is selected so that as many bumps 128 and bumps 158 as possible can be joined based on the relative positional relationship measured in S604. Then, the relative position is adjusted so that the selected index 326 and the selected index 356 match when viewed from the Z direction. In this example, the index 356 is used as a position index of the SOI substrate 150.

  In S610, the SOI substrate 120 and the SOI substrate 150 are brought into press contact. In the pressing contact, the SOI substrate 120 and the SOI substrate 150 are pressed into contact with each other by narrowing the interval between the SOI substrate 120 and the SOI substrate 150 while maintaining the adjusted relative position. For example, when solder bumps are used as the bumps 128 and 158, the bumps 128 and the bumps 158 are heated and pressed by the substrate bonding apparatus 200 so that the bumps 128 and the bumps 158 are thermocompression bonded. Be joined.

  When bumps formed of nickel, gold, or the like are used as the bumps 128 and 158, an underfill is filled between the semiconductor chip 122 and the semiconductor chip 152 to mechanically bond the bump 128 and the bump 158. Strength may be reinforced. Thereby, the laminated semiconductor substrate 110 is obtained. Since the laminated semiconductor substrate 110 includes a plurality of laminated semiconductor devices 100, the laminated semiconductor device 100 can be obtained by dicing the laminated semiconductor substrate 110.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

100 laminated semiconductor device, 110 laminated semiconductor substrate, 120 SOI substrate, 121 surface, 122 semiconductor chip, 123 through hole, 124 alignment mark, 126 embedded electrode, 127 semiconductor element, 128 bump, 129 back surface, 132 substrate body, 134 insulating layer 136 SOI layer, 150 SOI substrate, 151 surface, 152 semiconductor chip, 153 through hole, 154 alignment mark, 156 buried electrode, 157 semiconductor element, 158 bump, 159 back surface, 162 substrate body, 164 insulating layer, 166 SOI layer, 200 substrate bonding apparatus, 210 frame, 212 top plate, 214 support, 216 bottom plate, 220 pressing unit, 222 cylinder, 224 piston, 230 pressure stage, 232 support unit, 234 1 substrate holding portion, 235 actuator, 236 heater, 240 pressure receiving stage, 242 second substrate holding portion, 244 suspension portion, 246 heater, 250 pressure detection portion, 252 load cell, 254 load cell, 256 load cell, 320 support substrate, 322 side 324 region, 326 index, 328 notch, 350 support substrate, 352 side, 354 region, 356 index

Claims (4)

An SOI substrate having an insulating layer and an SOI layer formed in contact with the insulating layer, the through-hole penetrating between the front surface and the back surface of the SOI substrate, the surface formed on the through-hole, and the surface Providing an SOI substrate having a through-coupling portion that electrically couples back surfaces, and having a support substrate attached to either the front surface or the back surface of the SOI substrate;
Adjusting the relative position of the support substrate and the other substrate so that the through-coupling portion of the surface of the SOI substrate where the support substrate is not attached is electrically coupled to a predetermined position of the other substrate; When,
Maintaining the adjusted relative position while narrowing the interval between the SOI substrate and the other substrate, and pressing the SOI substrate and the other substrate;
With
The step of adjusting the relative position is performed by adjusting the relative position based on an index formed in a region of the support substrate that is not attached to the SOI substrate and a position index of the other substrate. To
A method of manufacturing a laminated semiconductor device. Measuring the relative positional relationship between the representative index representing the position of the through-coupling portion of the SOI substrate and the index of the support substrate in advance; and
The step of adjusting the relative position adjusts the relative position based on the index, the position index, and the relative positional relationship.
The manufacturing method according to claim 1. The support substrate is a silicon support substrate having orientation marks;
Before the step of adjusting the relative position, coarse adjustment step of coarsely adjusting the relative position of the SOI substrate and the other substrate using the orientation mark;
The manufacturing method of Claim 1 or Claim 2 further provided. The indicator of the support substrate is a fiducial mark formed by a laser.
The manufacturing method as described in any one of Claims 1-3.

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