JP2010205002A - Image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the memory access efficiency by making more multibank accesses generated. <P>SOLUTION: A memory controller 133 has an accessing means for receiving a request for access to an SDRAM 140 from masters (1 to M) and accessing a bank, corresponding to a bank address indicated by a bit, in a preset bit position among the bits constituting an address included in the access request. The memory controller has also a setting means for resetting the bit position. Furthermore, the memory controller has a statistical means for recording an access frequency for each bank accessed by the accessing means, in each changed bit position, after the bit position is changed by the setting means. Here, the setting means selects one changed bit position based on the access frequency for each bank and resets it as a bit position. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, and more particularly to an access control technique for a memory such as an SDRAM.

  Some memories such as an SDRAM mounted on an electronic apparatus such as an image processing apparatus have a plurality of memory banks. Some banks have a (multi-bank access) structure in which each bank can be accessed in parallel (independently) in order to increase processing speed. Patent Document 1 discloses a technique for realizing efficient multi-bank access.

JP 2002-268842 A

  However, even when multi-bank access is possible, access to the same bank from a plurality of masters (predetermined processing units for accessing the memory) may occur continuously. When the occurrence of access conflicts with respect to the same bank increases, the access efficiency to the memory of each master decreases due to an increase in waiting time, and the processing efficiency decreases.

  Therefore, an object of the present invention is to provide a technique for generating more multi-bank accesses and improving memory access efficiency.

  One aspect of the present invention for solving the above-described problems is an image processing apparatus including an SDRAM and a memory control circuit that controls the SDRAM, wherein the memory control circuit requests access to the SDRAM from a master. Access means for accessing the bank corresponding to the bank address indicated by the bit at the preset bit position among the bits constituting the address included in the access request, and setting means for resetting the bit position; Statistical means for changing the bit position by the setting means, and recording the access frequency accessed by the access means for each bank at each changed bit position after the change, the setting means, Select one modified bit position based on the access frequency for each bank, Resetting the bit position, characterized in that.

  Here, in the image processing apparatus, the memory control circuit includes a mode setting unit that sets either a setting mode for changing the setting of the bit position or a normal mode other than the setting mode. The statistical means records the access frequency for each bank when the setting mode is set, and the setting means records the access to each bank when the setting mode is set. One changed bit position may be selected based on the frequency and reset as the bit position in the normal mode.

  Further, in the above image processing apparatus, the access means uses predetermined test data for generating an access request to the SDRAM from the master when the setting mode is set, The access request may be accepted.

  In any of the image processing apparatuses described above, the setting unit may select a change bit position at which the access frequency with respect to each bank varies most evenly.

1 is a block diagram illustrating an example of a hardware configuration of an image processing apparatus 100 to which an embodiment of the present invention is applied. The figure which shows an example of the hardware constitutions of the memory control ASIC130. The figure which shows an example of the timing chart of multibank access. The figure explaining the relationship between a memory address and a bank address allocation position. The figure which shows an example of the statistics table 400. FIG. The flowchart which shows the process in bank address allocation setting mode.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a hardware configuration of an image processing apparatus 100 to which an embodiment of the present invention is applied. The image processing apparatus 100 is an apparatus such as a printer, a copier, a multifunction peripheral, or a scanner. The image processing apparatus 100 is connected to the information processing apparatus 200.

  The information processing apparatus 200 includes a general CPU (not shown), a RAM, a ROM, an auxiliary storage device such as a hard disk, a display, an input device such as a keyboard and a mouse, a communication interface, and the like. Realized by computer. In the information processing apparatus 200, an application program and a driver program (for example, a printer driver program) are executed.

  The image processing apparatus 100 includes a controller 110 as an electronic device control apparatus that controls various processes in the image processing apparatus 100, an engine unit 160 that executes printing on a print medium and reading of a document, and an input / output interface with a user. An operation panel 170 is provided.

  The controller 110 includes a CPU 120, a memory control ASIC 130, an SDRAM 140, and an I / O (Input / Output) control ASIC 150. The controller 110 controls various mechanisms such as the engine unit 160 and the operation panel 170, and realizes a printing function including various image processing, a facsimile function, a scanner function, a copy function, and the like. However, the controller 110 is not limited to this configuration. For example, the CPU 120 may be built in the memory control ASIC 130.

  The CPU 120 accesses the SDRAM 140 via the memory control ASIC 130, and executes various processes by reading and writing various data. The CPU 120 issues an access request for accessing the SDRAM 140 to the memory control ASIC 130.

  The memory control ASIC 130 controls access to the SDRAM 140 from the CPU 120, I / O control ASIC 150, and engine unit 160. The memory control ASIC 130 may control direct memory access to the SDRAM 140 without using the CPU 120.

  The SDRAM 140 is a memory that is controlled by the memory control ASIC 130. The SDRAM 140 has a plurality (N) of banks and is capable of multi-bank access. Each bank includes a plurality of pages (storage areas) specified by the same row address (Row Address). Access to the SDRAM 140 is performed in units of pages.

  The I / O control ASIC 150 controls transmission / reception of data to / from external devices (such as the operation panel 170 and the information processing apparatus 200).

  The engine unit 160 includes a paper supply / discharge mechanism, a printing mechanism, a scanning mechanism, and the like for realizing a printing function, a facsimile function, a scanner function, a copying function, and the like.

  The operation panel 170 is a unit for receiving user operations. The operation panel 170 includes, for example, a display such as an LCD and a touch panel provided on the display surface side of the display. The operation panel 170 may have various hard switches such as button keys.

  The hardware configuration of the image processing apparatus 100 has been described above. Of course, this configuration is not limited to the above-described configuration because the main configuration has been described in describing the features of the present invention. Further, other configurations included in the general image processing apparatus 100 are not excluded.

  FIG. 2 is a diagram illustrating an example of a hardware configuration of the memory control ASIC 130. As illustrated, the memory control ASIC 130 includes an interface unit 131, an arbitration circuit 132, and a memory controller 133.

  The interface unit 131 receives access requests from the CPU 120, the I / O control ASIC 150, and the engine unit 160, and notifies the arbitration circuit 132.

  The arbitration circuit 132 receives the notified access request and notifies the memory controller 133 of it. Here, the arbitration circuit 132 performs control to select one access request and notify the memory controller 133 when a plurality of access requests are received at the same timing.

  When the memory controller 133 accepts an access request from the arbitration circuit 132, the memory controller 133 issues a predetermined command to the SDRAM 140 to perform access control based on the access request.

  Specifically, each time the memory controller 133 accepts an access request, the memory controller 133 determines whether the access request is an access request to the same page (a page that is open at that time).

  If the memory controller 133 determines that it is not an access request to the same page, the memory controller 133 issues an active command for opening the page for which the access request has been made to the SDRAM 140 for command processing (issue of a read / write command). I do. On the other hand, if it is determined that the access request is for the same page, command processing is performed without issuing an active command.

  Then, regardless of whether or not the access request is for the same page, the memory controller 133 selects an open page after a predetermined period (hereinafter referred to as “open period”) has elapsed since the access request was received. A precharge command for closing is issued to the SDRAM 140.

  Accordingly, if there is an access request to the same page before the open period elapses, the memory controller 133 does not issue a precharge command and an active command, and continuously reads / writes (read / write) to / from the SDRAM 140. Issue command). When the open period has elapsed, the memory controller 133 issues a precharge command to close the page. When an access request for the same page is subsequently received, an active command is issued again. There is a need to.

  The above access control of the memory controller 133 can be executed in parallel independently for each bank. That is, pages belonging to different banks can be opened without waiting for the page to close. For example, as shown in FIG. 3, an active command for the bank address 001 of the master Y is issued between the read command for the bank address 000 of the master X and the precharge command, and the read command and the precharge for the bank address 001 of the master Y are issued. An active command for the bank address 010 of the master Z can be issued between the charge command. Note that it is necessary to close pages for different pages belonging to the same bank.

  Therefore, when access requests from different masters are continuous, access efficiency is improved when access is made to different banks as much as possible (so that access to the same bank is not continuous). On the other hand, when access requests to the same bank from different masters continue, it is necessary to wait for the page to be closed every time, so that the access efficiency decreases.

  By the way, normally, the bank address is assigned to a bit at a predetermined position in a memory address (request address) included in an access request from the master. For example, when the memory address is 32 bits ([31: 0]) and the number of banks is 4, the bank address assignment can be 2 bits [8: 7].

  Here, in the present invention, the allocation position of the bank address is also used as a bit such as a row address or a column address included in the memory address. That is, some bits such as a row address and a column address are used as a bank address. In this way, the bank address also changes in accordance with the change in the requested memory address, and at least a situation in which the banks actually used are extremely biased can be avoided.

  However, in the bank address assignment method described above, when access requests from different masters continue, it is not always possible to increase the possibility of access to different banks. On the other hand, access to the same bank may continue frequently.

  Therefore, in the present invention, the memory controller 133 has a configuration for increasing the possibility of multi-bank access even when access requests from different masters are continuous.

Specifically, the memory controller 133 has a register for setting a bank address allocation position. The memory controller 133 determines the bank to which the command is issued by referring to the bit at the allocation position set in this register among the bits of the request address. For example, as shown in FIG. 4, when the memory address is 32 bits ([31: 0]) and the number of banks is 8 (numbers 0 to 7), any 3 bits are set as the bank address allocation position. Can do. The number of bits L that need to be allocated when the number of banks is N is the minimum L that satisfies L ≧ log ₂ N.

  The memory controller 133 also has a register for setting a mode (bank address allocation setting mode) for setting a more appropriate bank address allocation position. It also has a register for setting whether the bank address allocation position is automatically set (automatic setting mode) or manually set (manual setting mode) based on the statistics recorded in this mode. . Note that a mode in which normal access control is performed with respect to the bank address allocation setting mode is hereinafter referred to as a normal mode.

  These register values may be set by the CPU 120 receiving a user instruction via the operation panel 170 or the information processing apparatus 200, for example.

  In the bank address assignment setting mode, the memory controller 133 performs the following processing. Moreover, it has the structure for it. In the bank address assignment setting mode, the CPU 120 reads a predetermined program (bank address assignment setting mode program) from a memory (not shown) such as a ROM and executes it, and requests access from a plurality of masters to the memory controller 133. Notify repeatedly. This predetermined program realizes all the masters constituting the functions (for example, printing function, scanner function, etc.) normally executed by the image processing apparatus 100, and performs predetermined processing executed by the controller 110, for example, immediately before execution of printing. This is a program for realizing the normal image processing up to.

The memory controller 133 sequentially sets an allocation position pattern of a predetermined number of bank addresses in the register. Then, for each pattern, a predetermined number of access requests are received by a plurality of masters, and the SDRAM 140 is accessed. Further, the following statistical processing (1) to (5) is performed for each pattern.
(1) Record the number of accesses to each bank for each master.
(2) For each master, select and record the most frequently accessed bank (the most frequent bank).
(3) Based on the most frequent bank of all masters, the number of times (the number of selections) selected by the master as the most frequent bank is recorded for each bank.
(4) Calculate and record the degree of variation in the number of selections for each bank. The degree of variation can be, for example, a sample variance value represented by the following formula 1.

  In order to record various data by performing the above processing, the memory controller 133 has a statistical table 400 as shown in FIG. 5, for example. The statistical table 400 includes a list in which the bank address assignment pattern 410 and the access variation degree 420 are associated with each other. Each bank address assignment pattern 410 includes a list in which the bank number 430 and the master number (number of selections) 440 are associated with each other. Each bank address allocation pattern 410 includes a list in which the master number 450 and the most frequent bank number 460 are associated with each other. In addition, for each master number 450, a list in which the bank number 470 and the access count 480 are associated is included. Of course, the method of recording data is not limited to the table method.

  When the automatic setting mode is set, the memory controller 133 selects one pattern having the most appropriate variation degree (accesses to each bank are most evenly distributed) among the bank address assignment patterns. For example, when the above sample variance value is used as the degree of variation, a pattern with the sample variance value closest to 0 is selected. This pattern is set in a register for setting the bank address allocation position.

  When the manual setting mode is set, the memory controller 133 causes the CPU 120 to display various recorded data (for example, data recorded in the statistical table 400) on the operation panel 170. Then, the CPU 120 accepts the bank address assignment pattern selection via the operation panel 170, and sets the pattern designated by the user in the register for setting the bank address assignment position.

  As described above, the memory controller 133 can set bank address assignment that can increase the possibility of multi-bank access even when access requests from different masters are continuous.

  The method for determining the bank address allocation position is not limited to the above. For example, the number of accesses to each bank is recorded for each bank address allocation position pattern, and the degree of variation in the number of accesses to each bank is calculated. Then, one pattern having the most appropriate variation degree (accesses to each bank are most evenly distributed) is selected.

  The configuration of the controller 110, the memory control ASIC 130, and the like has been described above. Of course, this configuration is not limited to the above-described configuration because the main configuration has been described in describing the features of the present invention. In addition, other configurations included in the general controller 110, the memory control ASIC 130, and the like are not excluded.

  Next, a characteristic operation of the memory controller 133 will be described.

  FIG. 6 is a flowchart showing processing in the bank address assignment setting mode. This flow is performed, for example, during the startup processing (initialization processing) of the controller 110 after the image processing apparatus 100 is powered on. In order to start the image processing apparatus 100 in the bank address assignment setting mode, for example, while the image processing apparatus 100 is operating in the normal mode, the bank address assignment setting mode is set in the register and the image processing apparatus 100 is restarted. do it. Of course, the image processing apparatus 100 may be activated in the bank address assignment setting mode every time.

  In S100, the CPU 120 determines whether or not the bank address allocation setting mode is set. Specifically, the CPU 120 refers to the register of the memory controller 133 and determines whether or not the bank address allocation setting mode is set. If the bank address assignment setting mode is set (S100: YES), the process proceeds to S110. If the bank address assignment setting mode is not set (S100: NO), the process proceeds to S190.

  In S110, memory access is started. Specifically, first, the memory controller 133 sets one bank address allocation pattern to be set in the register according to a predetermined setting order of bank address allocation patterns.

  Then, the CPU 120 reads out and executes a predetermined program (the bank address allocation setting mode program) from a memory (not shown) such as a ROM, and starts notifying the memory controller 133 of access requests from a plurality of masters. The plurality of masters are, for example, various image processes for predetermined image data. The memory controller 133 accesses the SDRAM 140 when receiving an access request from each master.

  In S120, the memory controller 133 records the number of accesses to each bank for each master. Specifically, the memory controller 133 specifies the bank number indicated by the bit of the allocation position of the bank address set in S110 among the number of the master that made the access request and each bit of the request address. Then, the access count 480 corresponding to the specified master number and bank number in the statistical table 400 is counted up.

  In S130, the memory controller 133 determines whether a predetermined number of accesses have been completed. Specifically, the memory controller 133 determines whether or not a predetermined number of bank address allocation patterns have been set. When the predetermined number of accesses are completed (S130: YES), the process proceeds to S140. In this case, the CPU 120 stops access requests from a plurality of masters. When the predetermined number of accesses are not completed (S130: NO), the memory controller 133 returns the process to S110.

  In S140, the memory controller 133 determines whether or not the automatic setting mode is set. If the automatic setting mode is set (S140: YES), the process proceeds to S150. If the manual setting mode is set (S140: NO), the process proceeds to S170.

  In S150, the memory controller 133 selects a bank address allocation pattern. Specifically, the memory controller 133 performs the processes (2) to (4) described above for each bank address assignment pattern set in S110. Then, one of the bank address allocation patterns having the most appropriate variation degree is selected. Then, the process proceeds to S160.

  In S160, the memory controller 133 sets the bank address allocation pattern selected in S150 in a register for setting the bank address allocation position. Then, the process proceeds to S190.

  In S170, the memory controller 133 accepts selection of a bank address assignment pattern. Specifically, the memory controller 133 performs the processes (2) to (4) described above for each bank address assignment pattern set in S110. Then, the CPU 120 displays part or all of the data recorded in the statistical table 400 on the operation panel 170. For example, a list of the bank address assignment pattern 410 and the access variation degree 420 is displayed. A list of master numbers 450 and most frequent bank numbers 460 may be displayed for each bank address assignment pattern 410. That is, it is preferable that statistical information necessary for the user to select a bank address allocation pattern is acquired from the memory controller 133 and displayed.

  In S <b> 170, the CPU 120 accepts the user's selection of the bank address assignment pattern via the operation panel 170 and sends the bank address assignment pattern to the memory controller 133. Then, the process proceeds to S180.

  In S180, the memory controller 133 sets the bank address allocation pattern sent from the CPU 120 in S170 to a register for setting the allocation position of the bank address. Then, the process proceeds to S190.

  In S190, the memory controller 133 shifts to the normal mode. Specifically, the setting of the register bank address allocation setting mode is canceled. Then, the memory controller 133 ends this flow. In the normal mode, an access request to the SDRAM 140 is processed by the memory controller 133 while maintaining the bank address assignment pattern set in S160 or S180.

  The embodiment of the present invention has been described above. According to the present embodiment, it is possible to generate more multi-bank accesses and improve memory access efficiency.

  That is, in the present embodiment, the bank address allocation setting mode can be set in the memory controller. When the bank address allocation setting mode is set, an access request to the SDRAM is made by each master realized by a predetermined program during the startup process and the initialization process, and a plurality of bank addresses are set by the memory controller. The number of accesses to each bank of each master is recorded for each allocation pattern. Then, based on the recorded number of accesses, the memory controller sets a bank address allocation position at which multi-bank access is more likely to occur.

  The above-described embodiments of the present invention are intended to illustrate the gist and scope of the present invention and are not intended to be limiting. Many alternatives, modifications, and variations will be apparent to those skilled in the art.

  For example, in the above embodiment, in the bank address assignment setting mode, the CPU 120 issues an access request for each master, but the memory controller 133 may issue an access request to itself. In this case, test data including continuous access requests from a plurality of masters in advance in a memory such as a ROM (for example, access requests from each master generated in normal image processing performed immediately before execution of printing executed by the controller 110). The memory controller 133 reads this test data and issues an access request to itself.

  The memory controller 133 may store a history of access requests of each master during the normal mode, and use the access request history as the test data in the bank address assignment setting mode. The bank address assignment setting mode program stores a history of access requests of each master during the normal mode, and generates an access request based on the access request history in the bank address assignment setting mode. It may be.

100: Image processing device, 110: Controller, 120: CPU, 130: Memory control ASIC, 131: Interface unit, 132: Arbitration circuit, 133: Memory controller, 140: SDRAM, 150: I / O control ASIC, 160: Engine , 170: Operation panel, 200: Information processing device, 400: Statistical table, 410: Bank address allocation pattern, 420: Access variation degree, 430: Master number, 440: Most frequent bank number, 450: Bank number, 460: number of access

Claims (4)

An image processing apparatus comprising an SDRAM and a memory control circuit for controlling the SDRAM,
The memory control circuit
An access means for receiving an access request to the SDRAM from a master and accessing a bank corresponding to a bank address indicated by a bit at a preset bit position among bits constituting an address included in the access request;
Setting means for resetting the bit position;
Statistical means for changing the bit position by the setting means, and recording the access frequency accessed by the access means for each bank at each changed bit position after the change,
The setting means includes
Selecting one modified bit position based on the access frequency for each bank and resetting as the bit position;
An image processing apparatus. The image processing apparatus according to claim 1,
The memory control circuit
A mode setting means for setting one of a normal mode and a setting mode for changing the setting of the bit position;
The statistical means is
When the setting mode is set, the access frequency for each bank is recorded,
The setting means includes
When the setting mode is set, select one change bit position based on the access frequency for each bank, and reset as the bit position in the normal mode;
An image processing apparatus. The image processing apparatus according to claim 2,
The access means is:
Accepting the access request using predetermined test data for generating an access request to the SDRAM from the master when the setting mode is set;
An image processing apparatus. The image processing apparatus according to any one of claims 1 to 3,
The setting means includes
Selecting a change bit position at which the access frequency for each bank varies most evenly;
An image processing apparatus.

Images