JP2010267845A - Component built-in wiring board and method of manufacturing the component built-in wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a component built-in wiring board manufactured at low cost while maintaining the reliability in connection with a semiconductor substrate and the function as the wiring board; and to provide a method of manufacturing the same. <P>SOLUTION: The wiring board includes a first insulating layer, a second insulating layer laminated on it, a semiconductor element embedded in the second insulating layer and having a terminal pad, a first wiring pattern which is interposed between the first and second insulating layers in contact with them, includes a surface-gilded connection land and is not surface-gilded except the connection land, a connection member making the terminal pad of the semiconductor element and the connection land electrically conductive, a resin applied to seal the connection member within it, and a second wiring pattern provided on a surface of the first insulating layer opposite to the surface on which the first wiring pattern is provided. An interlayer connection makes each first wiring pattern connected with the connection land and the second wiring pattern electrically conductive. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a component built-in wiring board in which components are embedded in an insulating plate and a manufacturing method thereof, and more particularly to a component built-in wiring board in which electronic components such as semiconductor elements are embedded and a manufacturing method thereof.

  As an example of a component built-in wiring board in which a semiconductor chip is embedded, there is one described in JP-A-2003-197849. To embed a semiconductor chip (bare chip), flip connection can be used as described in this disclosure.

  In the flip connection, for example, an Au bump is further formed on a terminal pad formed on a semiconductor chip, and this is press-contacted to a wiring pattern formed on a wiring board via an adhesive (underfill resin). Can be made. The consideration here is the low resistance connection between the Au bump and the wiring pattern and the securing of the connection reliability. For this reason, a high degree of cleaning is required on the surface of the wiring pattern, and as a common method, an Au plating layer (relatively thin) is also formed on the surface layer of the wiring pattern.

  Alternatively, in the flip connection, a semiconductor chip having terminal pads formed with Au bumps is brought into contact with a wiring pattern in which an Au plating layer (thicker than the above) is formed on the surface layer, and further, heat and ultrasonic waves are applied. There is also a method in which Au-Au metal bonding sites are formed by adding A mechanically robust connection is possible by forming a metal bonding site.

  In either case, generally, when flip-connecting a semiconductor chip on the main surface of a wiring board, a protective layer such as a solder resist is formed in advance, leaving only the portion of the wiring pattern to be connected, and then The Au plating layer is formed at the site for connection. As a result, Au plating, which is not inexpensive, can be applied with a minimum area.

  In the case of embedding a semiconductor chip in a wiring board and flip-connecting it, there are some differences from the flip-connection of the semiconductor chip on the main surface as described above. First, there is an influence of the solder resist becoming a part of the inner insulating layer. Generally, the adhesion between the solder resist and the insulating plate material used in the wiring board is not so strong between the insulating plate materials. Therefore, if a configuration in which the solder resist as the inner layer is omitted is adopted, Au plating is performed over a wide area, which affects the manufacturing cost. It cannot be said that the adhesion between the Au plating layer and the insulating plate material is strong, and a problem remains in this respect.

JP 2003-197849 A

  The present invention has been made in consideration of the above-described circumstances. In a component-embedded wiring board in which a semiconductor element is embedded in an insulating plate and a manufacturing method thereof, the reliability of semiconductor element connection and functionality as a wiring board are achieved. An object of the present invention is to provide a component built-in wiring board that can be manufactured at a low cost while maintaining it, and a manufacturing method thereof.

  In order to solve the above-described problem, a component built-in wiring board according to an aspect of the present invention includes a first insulating layer, a second insulating layer positioned in a stacked manner with respect to the first insulating layer, A semiconductor element having a terminal pad embedded in a second insulating layer, and a surface gold-plated connection land sandwiched between and in contact with the first insulating layer and the second insulating layer; A connection member that electrically connects the first wiring pattern in which the surface layer gold plating is not formed except on the connection land, and the terminal pad of the semiconductor element and the connection land of the first wiring pattern. And a resin provided so as to seal the connecting member therein and a surface of the first insulating layer opposite to the surface on which the first wiring pattern is provided The second wiring pattern formed and the first insulating layer penetrating the first wiring layer. An interlayer connection that electrically connects the first wiring pattern and the second wiring pattern, and the interlayer connection includes at least each of the first wiring pattern connected to the connection land and the first wiring pattern. The second wiring pattern is electrically connected to the wiring pattern.

  That is, in order to reliably connect the semiconductor element to the connection land of the wiring board through the terminal pad and the connection member, surface gold plating is applied on the connection land, and the connection member is sealed with resin. Yes. The surface gold plating is not formed except on the connection land. Therefore, it is not necessary to apply gold plating over a large area, and the cost is low. In addition, since a solder resist that forms the inner layer is not provided, adhesion to the insulating layer does not become a problem. Therefore, it is possible to provide a component built-in wiring board that can be manufactured at low cost while maintaining the reliability of semiconductor element connection and the functionality as a wiring board. The interlayer connection body electrically connects at least each of the first wiring pattern connected to the connection land and the second wiring pattern when the surface layer gold plating is performed on the connection land. This is because the interlayer connection is used as a feeding path for electrolytic plating.

  Moreover, the manufacturing method of the component built-in wiring board which is another aspect of this invention is the 1st insulating board which has a 1st surface and a 2nd surface, and the 1st laminated | stacked on the said 1st surface. The metal foil, the second metal foil laminated on the second surface, and the first metal foil and the second metal foil electrically passing through the first insulating plate A step of forming a laminated body having an interlayer connection to be conducted; patterning the second metal foil of the laminated body; and connecting a first wiring pattern including a connection land for a component to the connection land. A step of forming each of the first wiring patterns so as not to lose a contact portion with the interlayer connection body, and the connection land on the surface of the stacked body on which the first wiring pattern is provided. Forming the missing mask pattern, and using the mask pattern, the first gold Using the foil and the interlayer connector as a power supply path, the step of performing electrolytic gold plating on the connection land, the step of removing the mask pattern, and the connection land subjected to the electrolytic gold plating, Patterning a third metal foil laminated on a second insulating plate different from the first insulating plate, and electrically connecting a semiconductor element on the second surface of the first laminate. A step of forming a second wiring pattern and a third insulating plate different from the first and second insulating plates on the surface of the second insulating plate on the side where the second wiring pattern is present And stacking the electronic component in a fourth insulating plate different from the first to third insulating plates, and stacking the fourth, third, and second layers on the first insulating plate. And a step of integrating the two insulating plates in the order of the stacking positions. That.

  This manufacturing method is one method for manufacturing the component built-in wiring board. In this method, in order to reliably connect the semiconductor element to the connection land of the wiring board via the terminal pad and the connection member, surface gold plating is applied in advance on the connection land. Surface gold plating is not formed except on the connection lands by the mask pattern. Therefore, it is not necessary to apply gold plating over a large area, and the cost is low. In addition, since a solder resist that forms the inner layer is not provided, adhesion to the insulating layer does not become a problem. Therefore, it is possible to provide a component built-in wiring board that can be manufactured at low cost while maintaining the reliability of semiconductor element connection and the functionality as a wiring board. The above surface gold plating is formed by electrolytic plating using the first metal foil and the interlayer connector penetrating the first insulating plate as a power feeding path, so even a relatively thick plating layer can be efficiently formed. it can.

  According to the present invention, in a wiring board with a built-in component in which a semiconductor element is embedded in an insulating plate and a manufacturing method thereof, the reliability of the connection of the semiconductor element and the functionality as a wiring board can be maintained, and the manufacturing can be performed at low cost. A possible component built-in wiring board and a method of manufacturing the same can be provided.

Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on one Embodiment of this invention. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. FIG. 3 is a continuation diagram of FIG. 2, and is a process diagram schematically showing a part of a manufacturing process of the component built-in wiring board shown in FIG. 1. Process drawing which shows another part of manufacturing process of the component built-in wiring board shown in FIG. FIG. 9 is a process diagram schematically showing still another part of the manufacturing process of the component built-in wiring board shown in FIG. 1. Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention. Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention. Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention.

  As an embodiment of the present invention, the semiconductor element is flip-connected on the connection land of the first wiring pattern, and the connection member includes the terminal pad of the semiconductor element and the first wiring pattern. Conductive bumps sandwiched between the connection lands and electrically and mechanically connecting the terminal pads and the connection lands, wherein the resin includes the semiconductor element and the first insulating layer, The underfill resin may be provided between the wiring pattern and the wiring pattern. This aspect is a configuration example of a component built-in wiring board in which a semiconductor element is embedded and mounted by flip connection.

  Further, as an embodiment, the semiconductor element is provided on the first insulating layer such that a side having the terminal pad is directed to a side opposite to the first insulating layer, and the connection member Is a bonding wire provided so as to electrically connect the terminal pad of the semiconductor element and the connection land of the first wiring pattern, and the resin connects the semiconductor element and the bonding wire. It can be said that it is sealing. This aspect is a configuration example of a wiring board in which a semiconductor element is built with electrical connection by a bonding wire. Compared with the flip connection, the connection by the bonding wire can be inexpensively manufactured in terms of equipment.

  Here, in both of the above embodiments, the surface of the first wiring pattern on the second insulating layer side may be roughened except at least on the connection land. By such surface roughening, the adhesiveness and adhesiveness between the first wiring pattern and the second insulating layer are further increased, and the structural reliability can be improved.

  Here, it can be assumed that the first wiring pattern is roughened on the surface in contact with the resin. Such roughening of the surface of the first wiring pattern is preferable because it improves the adhesion to the resin. Alternatively, the first wiring pattern may be not roughened on the surface in contact with the resin. This is an aspect obtained when the surface of the first wiring pattern is roughened after the semiconductor element and the resin are provided during the manufacturing process. In this case, since the roughening treatment can be performed immediately before the first wiring pattern and the second insulating layer are stacked, it is preferable that the roughened state is easily maintained during the stacking.

  Further, as an embodiment, the interlayer connection body may be a conductive composition as a material thereof. Such an interlayer connection body of a conductive composition can be provided in a small region, and is suitable for increasing the density of a pattern as a wiring board.

  Here, the interlayer connection body may have a shape having an axis that coincides with the stacking direction and a diameter that changes in the direction of the axis. This interlayer connection body is a conductor derived from a conductive bump made of a conductive composition, and screen printing can be used for the formation thereof, which contributes to improvement in productivity.

  Further, as an embodiment of the manufacturing method, the fourth, third and second insulating plates are laminated on the first insulating plate after the step of applying the electrolytic gold plating on the connection land. The step of roughening the surface of the first wiring pattern may be further included before the step of integrating the layers in the order of the stacking positions. By such surface roughening, the adhesion and adhesion between the first wiring pattern and the fourth insulating plate are further increased, and the structural reliability can be improved.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to an embodiment of the present invention. As shown in FIG. 1, this component built-in wiring board includes an insulating layer 11 (first insulating layer), 12, 12, 13, 14, and 15 (12, 13, 14, 15 second insulating layer). ), Wiring layer 21 (second wiring pattern), 22 (first wiring pattern), 23, 24, 25 (another second wiring pattern), 26 (= 6 layers in total) , Interlayer connector 31, 32, 34, 35, through-hole conductor 33, semiconductor element 41, conductive bump 42 (connecting member), and underfill resin 51 (resin).

  The semiconductor element 41 is electrically and mechanically connected to the inner wiring layer 22 through conductive bumps 42 by flip connection. For this connection, conductive bumps 42 are formed in advance on terminal pads (not shown) of the semiconductor element 41, and the connection lands are patterned on the wiring layer 22 so as to be aligned with the conductive bumps 42. Yes. The conductive bump 42 is made of, for example, gold (Au) as a material, and is previously formed in a stud shape on the terminal pad. An underfill resin 51 is filled between the semiconductor element 41 and the wiring layer 22 and the insulating layer 11 for mechanical and chemical protection of the flip connection portion.

  The connection land of the wiring layer 22 is gold-plated on the surface layer. The plating layer 22b for that purpose can be, for example, a plating layer of Ni (lower layer) / Au (upper layer). The plating layer 22b is not formed except on the connection land. Therefore, the gold plating is not performed on a large area, so that the cost is low. The conductive bumps 42 formed on the terminal pads of the semiconductor element 41 and the plating layer 22b on the wiring layer 22 are Au—Au connections, have low resistance and improved connection reliability. The connection between the conductive bump 42 and the plating layer 22b can be a connection in which a metal bonding portion is formed in order to increase reliability.

  The surface of the wiring layer 22 that is in contact with the insulating layer 12 is a roughened surface 22a that has been treated so that the surface roughness is appropriately increased. This is a configuration for improving the adhesion between the wiring layer 22 and the insulating layer 12. The roughened surface 22a further contributes to improving the reliability of the electrical connection between the wiring layer 22 and the interlayer connector 32.

  Describing another structure as a component built-in wiring board, the wiring layers 21 and 26 are wiring layers on both main surfaces as a wiring board, and various components (not shown) can be mounted thereon. Solder resist 61 is provided on both main surfaces except for the land portions of the wiring layers 21 and 26 on which solder (not shown) is to be mounted in mounting, so that the solder melted at the time of solder connection is held on the land portions and thereafter functions as a protective layer. , 62 (thickness is about 20 μm, for example). An Ni / Au plating layer (not shown) with high corrosion resistance may be formed on the surface layer of the land portion.

  The wiring layers 22, 23, 24, and 25 are inner wiring layers, and the insulating layer 11 is insulated between the wiring layer 21 and the wiring layer 22, and the wiring layer 22 and the wiring layer 23 are insulated in this order. The insulating layer 13 is provided between the wiring layer 23 and the wiring layer 24, the insulating layer 14 is provided between the wiring layer 24 and the wiring layer 25, and the insulating layer 15 is provided between the wiring layer 25 and the wiring layer 26. However, the wiring layers 21 to 26 are separated from each other. Each of the wiring layers 21 to 26 is made of, for example, a metal (copper) foil having a thickness of 18 μm.

  Each of the insulating layers 11 to 15 is a rigid material made of, for example, a glass epoxy resin, for example, having a thickness of 100 μm, and the insulating layer 13 only having a thickness of, for example, 300 μm. In particular, the insulating layer 13 has an opening at a position corresponding to the built-in semiconductor element 41, and provides a space for incorporating the semiconductor element 41. The insulating layers 12 and 14 are deformed so as to fill the opening of the insulating layer 13 for the built-in semiconductor element 41 and the space inside the through-hole conductor 33 of the insulating layer 13 and become voids inside. There is no space.

  The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted by a through-hole conductor 33 provided through the insulating layer 13. The wiring layer 24 and the wiring layer 25 can be conducted by an interlayer insulator 34 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted by an interlayer connector 35 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15.

  The interlayer connectors 31, 32, 34, and 35 are derived from conductive bumps formed by screen printing of a conductive composition, respectively, and depend on the manufacturing process in the axial direction (shown in FIG. 1). The diameter changes in the upper and lower stacking directions). The diameter is, for example, 200 μm on the thick side. The interlayer connector 31 is always provided at least between each of the wiring patterns 22 connected to the connection land and the wiring pattern 21. This is because when the surface gold plating (plating layer 22b) is applied on the connection lands of the wiring pattern 22, these interlayer connection bodies 31 are used as a feeding path for electrolytic plating (described later in FIG. 2A).

  In the component built-in wiring board according to this embodiment, the semiconductor element 41 is connected to the connection land of the wiring layer 22 with high reliability through the terminal pad and the conductive bump 42. Therefore, the plating layer 22b is formed on the connection land. The formed conductive bumps 42 are sealed with an underfill resin 51. The plating layer 22b is not formed except on the connection land. Therefore, the gold plating is not performed on a large area, so that the cost is low. In addition, since no solder resist is provided as an inner layer, adhesion and adhesion to the insulating layer 12 do not become a problem. Therefore, it is possible to manufacture at low cost while maintaining the reliability of connection of the semiconductor element 41 and the functionality as a wiring board.

  Next, a manufacturing process of the component built-in wiring board shown in FIG. 1 will be described with reference to FIGS. 2A to 4. 2A to 4 are process diagrams schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. In these figures, the same or equivalent components as those shown in FIG.

  It demonstrates from FIG. 2A and FIG. 2B. 2A and 2B show a manufacturing process of a portion centering on the insulating layer 11 in each configuration shown in FIG. First, as shown in FIG. 2A (a), a paste-like conductive composition to be an interlayer connection 31 is formed on a metal foil (electrolytic copper foil) 22A having a thickness of, for example, 18 μm by, for example, screen printing. It is formed in a bump shape (bottom diameter, for example, 200 μm, height, for example, 160 μm).

  By forming the conductive bumps of the conductive composition by screen printing, the conductive bumps that fit in a very small region can be efficiently formed with high productivity. Conductive bumps that fit in such a small area are suitable for increasing the density of patterns as wiring boards. The conductive composition here is obtained by dispersing fine metal particles such as silver, gold, and copper or fine carbon particles in a paste-like resin. For convenience of explanation, printing is performed on the lower surface of the metal foil 22A, but it may be printed on the upper surface (the following drawings are also the same). After the interlayer connector 31 is printed, it is dried and cured.

  Next, as shown in FIG. 2A (b), an FR-4 prepreg 11A having a thickness of, for example, 100 μm is laminated on the metal foil 22A to penetrate the interlayer connector 31 so that the head is exposed. To do. At the time of exposure or afterwards, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connection body 31 is a shape having an axis coinciding with the stacking direction and the diameter changing in the axial direction). Subsequently, as shown in FIG. 2A (c), a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 11A, and the whole is integrated by pressing and heating. At this time, the metal foil 21A is in electrical continuity with the interlayer connector 31, and the prepreg 11A is completely cured to become the insulating layer 11.

  Next, as shown in FIG. 2A (d), patterning by, for example, well-known photolithography is performed on the metal foil 22A on one side, and this is processed into a wiring layer 22 including connection lands. In this processing, each wiring pattern 22 connected to the connection land is performed so as not to lose the contact portion with the interlayer connection body 31. In other words, the formation position of the interlayer connection body 31 is set in advance in the process shown in FIG. 2A (a).

  Next, a plating layer forming mask pattern 100 is formed on the insulating layer 11 including the patterned wiring layer 22. The plating layer forming mask pattern 100 is a pattern in which a region on the wiring layer 22 where the plating layer 22b is to be formed is omitted. Such a mask pattern can also be formed by processing using well-known photolithography.

  After the plating layer forming mask pattern 100 is formed, a plating layer 22b is formed on the wiring layer 22 in the region where the mask pattern 100 is removed, as shown in FIG. 2A (e). As described above, the plating layer 22b is formed, for example, by forming a nickel layer as a lower layer and a gold layer thereon. As a plating method, an electrolytic plating method can be employed in order to efficiently form a relatively thick gold plating layer (for example, 0.5 μm thick).

  In this electrolytic plating method, the metal foil 21A and the interlayer connection body 31 in contact with each of the wiring patterns 22 connected to the connection land can be used as a feed line. This is because, as already described, each of the wiring patterns 22 connected to the connection land is formed so as not to lose the contact portion with the interlayer connection body 31. After the formation of the plating layer 22b, the plating layer forming mask pattern 100 is removed (FIG. 2A (f)).

  Next, as shown in FIG. 2B (g), the semiconductor element 41 is flip-connected through the conductive bumps 42 on the wiring layer 22 on which the plating layer 22b is formed. More specifically, for example, first, the semiconductor element 41 with the conductive bump 42 is aligned with the connection land (plating layer 22b) of the wiring layer 22, and the conductive bump 42 and the plating layer 22b are brought into contact with each other. In this state, heat and ultrasonic waves are applied to form an Au—Au metal bonding site at the contact site. A mechanically robust connection can be achieved by forming a metal bonding site. Subsequently, a liquid resin to be the underfill resin 51 is injected between the semiconductor element 41 and the insulating layer 11 using, for example, a dispenser, and then heated to cure the liquid resin to form the underfill resin 51.

  After the semiconductor element 41 is flip-connected on the wiring layer 22, next, as shown in FIG. 2B (h), the surface of the wiring layer 22 exposed at this time is roughened to obtain a roughened surface 22a. . Specifically, for example, a blackening reduction process or a microetching process can be employed. Examples of the micro-etching process include CZ processing (MEC product name) and bond film processing (Atotech product name). This roughening treatment is performed to improve the adhesion and adhesion between the wiring layer 22 and the insulating layer 12 (see FIG. 1) laminated thereon.

  As described above, the semiconductor element 41 is connected to the connection land (plating layer 22 b) of the wiring layer 22 through the conductive bump 42, and the underfill resin 51 is interposed between the semiconductor element 41 and the wiring layer 22 and the insulating layer 11. The wiring board material 1 in a state in which is satisfied is obtained. The entire lamination process using this wiring board material 1 will be described later with reference to FIG. The wiring board material 1 can be used for the entire lamination process immediately after the roughening treatment of the wiring layer 22. Therefore, it is preferable in terms of maintaining the roughened state in the entire lamination process.

  In addition, the thing of the following structures can also be employ | adopted for the wiring board raw material 1 as a modification. In the following configuration, the form of the interlayer connector 31 is different from that described above. That is, for example, as the interlayer connection body 31, a metal bump formed by etching a metal plate, a connection body filled with a conductive composition, or a conductor bump formed by plating (for example, grown in a hole formed in the insulating layer 11. It is also possible to use a plated body or a plated body formed by forming a hole pattern mask on the metal foil 22A and growing in the hole). A wiring board material having such an interlayer connection and its manufacturing process itself are known. In any case, at the time of processing the metal foil 22A, the wiring pattern 22 connected to the connection land is formed in a pattern so as not to lose the contact portion with the interlayer connector 31.

  Next, a description will be given with reference to FIG. FIG. 3 shows a manufacturing process of a part centering on the insulating layer 13 and the same 12 in each configuration shown in FIG. First, as shown in FIG. 3A, for example, an FR-4 insulating layer 13 having a thickness of, for example, 300 μm in which metal foils (electrolytic copper foils) 23A and 24A having a thickness of 18 μm are laminated on both surfaces is prepared. A through-hole 72 for forming a through-hole conductor is formed at a predetermined position, and an opening 71 is formed in a portion corresponding to the built-in semiconductor element 41.

  Next, electroless plating and electrolytic plating are performed to form a through-hole conductor 33 on the inner wall of the through-hole 72 as shown in FIG. At this time, a conductor is also formed on the inner wall of the opening 71. Further, as shown in FIG. 3C, the metal foils 23A and 24A are patterned in a predetermined manner using well-known photolithography to form wiring layers 23 and 24. By patterning the wiring layers 23 and 24, the conductor formed on the inner wall of the opening 71 is also removed.

  Next, as shown in FIG. 3D, conductive bumps (bottom diameter, for example, 200 μm, height, for example, 160 μm) to be the interlayer connector 32 are formed at predetermined positions on the wiring layer 23 with the paste-like conductive composition. It is formed by screen printing. Subsequently, as shown in FIG. 3E, an FR-4 prepreg 12A (nominal thickness, for example, 100 μm) to be the insulating layer 12 is laminated on the wiring layer 23 side using a press. In the prepreg 12A, an opening corresponding to the built-in semiconductor element 41, similar to the insulating layer 13, is provided in advance.

  In this lamination process, the head of the interlayer connector 32 is passed through the prepreg 12A. In addition, the broken line of the head part of the interlayer connection body 32 in FIG. 3 (e) indicates that there are both cases where the head part is plastically deformed and crushed at this stage and when it is not plastically deformed. By this step, the wiring layer 23 is located by sinking to the prepreg 12A side. The wiring board material obtained as described above is referred to as a wiring board material 2.

  Note that the process shown in FIG. 3 can be performed as follows. In the stage of FIG. 3A, only the through hole 72 is formed, and the subsequent steps from FIG. 3B to FIG. 3D are performed without forming the opening 71 for the built-in component. Next, as a process corresponding to FIG. 3E, prepreg 12A (without opening) is stacked. And it is the process of forming simultaneously the opening part for components incorporation in the insulating layer 13 and the prepreg 12A.

  Next, a description will be given with reference to FIG. FIG. 4 is a diagram showing an arrangement relationship in which the wiring board materials 1 and 2 obtained as described above are stacked.

  In FIG. 4, the upper wiring board material 3 shown in FIG. 4 applies the same process as the lower wiring board material 1, and thereafter, the interlayer connection 34 and the prepreg 14A are connected to the interlayer connection body in the intermediate wiring board material 2 shown in FIG. 32 and the prepreg 12A. However, there is no component (semiconductor element 41) and no part (connection land) for connecting it, and the prepreg 14A is not provided with an opening for the semiconductor element 41. Other than that, the metal foil (electrolytic copper foil) 26A, the insulating layer 15, the interlayer connection body 35, the wiring layer 25, the prepreg 14A, and the interlayer connection body 34 are the metal foil 21A of the wiring board material 1, the insulating layer 11, and the interlayer connection, respectively. The same as the body 31, the wiring layer 22, the prepreg 12 </ b> A of the wiring board material 2, and the interlayer connection body 32.

  The wiring board materials 1, 2, and 3 are stacked and arranged in the arrangement as shown in FIG. Thereby, the prepregs 12A and 14A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12 </ b> A and 14 </ b> A obtained by heating, the prepregs 12 </ b> A and 14 </ b> A are deformed into the space around the semiconductor element 41 and the space inside the through-hole conductor 33, and no gap is generated. The wiring layers 22 and 24 are electrically connected to the interlayer connectors 32 and 34, respectively. In this laminating step, the roughened surface 22a is provided on the surface of the wiring layer 22, thereby improving the adhesion and adhesion between the insulating layer 12 and the wiring layer 22, and the interlayer connector 32 and the wiring layer 22 The reliability of electrical connection is improved.

  After the lamination step shown in FIG. 4, the metal foils 26A and 21A on the upper and lower surfaces are patterned in a predetermined manner by using well-known photolithography, and further layers of solder resists 61 and 62 are formed, as shown in FIG. Such a component built-in wiring board can be obtained. 4, the insulating layer 11 is a first insulating plate, the prepreg 12A and the insulating layer 13 are a fourth insulating plate, the prepreg 14A is a third insulating plate, and the insulating layer 15 is a second insulating plate. It corresponds to an insulating plate, respectively.

  In the patterning of the metal foil 21A after the entire lamination, all the interlayer connection bodies 31 may be intended to be a part of a circuit as a wiring board, but a part of the interlayer connection bodies 31 is used. The pattern formation may not be used in an actual circuit. That is, there may be a mode in which a part of the interlayer connection body 31 that contacts the wiring pattern 22 connected to the connection land is used only as a power supply path for the plating process.

  As a modification, the through-hole conductor 33 provided in the intermediate insulating layer 13 may naturally have a configuration similar to the interlayer connector 31 or 32. Further, the outer wiring layer 26 may be formed at the stage of the wiring board material 3 (for example, at a stage corresponding to FIG. 2A (d)), in addition to being obtained by patterning after the last lamination step. .

  Next, another embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to another embodiment. In FIG. 5, the same reference numerals are given to the same or equivalent components as those appearing in the already described drawings. The explanation is omitted unless there is a matter to be explained.

  In this embodiment, the roughened surface 22 a formed on the wiring layer 22 is formed including the part buried in contact with the underfill resin 51. Such roughening of the surface of the wiring pattern 22 is preferable because it improves the adhesion and adhesion between the wiring pattern 22 and the underfill resin 51. Other configurations are the same as those of the component built-in wiring board shown in FIG.

  In order to manufacture the component built-in wiring board of this embodiment, the following may be performed. That is, when the state of FIG. 2A (f) is obtained, the wiring layer 22 is subsequently roughened to form a roughened surface 22a. In this roughening treatment, the surface on which the plating layer 22b has already been formed is not roughened. After that, the semiconductor element 41 is flip-connected on the connection pad (plating layer 22 b) of the wiring layer 22 via the conductive bump 42. Other steps may be performed as described in FIGS. 2A to 4.

  Next, still another embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to still another embodiment. In FIG. 6, the same reference numerals are given to the same or equivalent components as those appearing in the already described drawings. The explanation is omitted unless there is a matter to be explained.

  In this embodiment, the built-in semiconductor element 41 is not flip-connected to the wiring layer 22 but electrically connected to the plating layer 22b formed on the wiring layer 22 via the bonding wire 43 as a connecting member. Is connected to. The entire semiconductor element 41 including the bonding wire 43 is sealed with a resin 52 different from the insulating material of the wiring board. Compared with the flip connection, the connection by the bonding wire 43 can be manufactured inexpensively in terms of equipment. Other configurations are the same as those of the component built-in wiring board shown in FIG.

  In order to manufacture the component built-in wiring board of this embodiment, the following may be performed. That is, the procedure is the same until the state shown in FIG. 2A (f) is obtained. However, a pattern and a region corresponding to the bonding wire 43 being connected are used for the pattern formed by the wiring layer 22 and the formation region of the plating layer 22b.

  Then, instead of the process shown in FIG. 2B (g), the semiconductor element 41 is placed and fixed on the insulating layer 11 so that the functional surface thereof is facing upward, A bonding wire 43 is used for bonding connection to the connection land (plating layer 22b) of the wiring layer 22. After that, a resin 52 is formed so as to seal the bonding wire 43 and the entire semiconductor element 41. The resin 52 can be, for example, a known potting resin or transfer mold resin. The process of FIG. 2B (h) and other processes may be performed as described in FIGS. 2A to 4.

  Next, still another embodiment of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to still another embodiment. In FIG. 7, the same reference numerals are given to the same or equivalent components as those appearing in the already described drawings. The explanation is omitted unless there is a matter to be explained.

  In this embodiment, unlike the embodiment shown in FIG. 6, the roughened surface 22 a formed on the wiring layer 22 is formed including the portion buried in contact with the resin 52. Such roughening of the surface of the wiring pattern 22 is preferable because it improves the adhesion and adhesion between the wiring pattern 22 and the resin 52. Other configurations are the same as those of the component built-in wiring board shown in FIG.

  In order to manufacture the component built-in wiring board of this embodiment, the manufacturing process using the component built-in wiring board shown in FIG. 6 may be modified as follows. That is, prior to a series of steps of placing the semiconductor element 41 on the insulating layer 11, fixing, connecting with the bonding wire 43, and forming the resin 52, first, the wiring layer 22 is subjected to a roughening process to be roughened surface 22 a. Form. Alternatively, the roughening process is performed after the semiconductor element 41 is placed and fixed on the insulating layer 11 or after the bonding wire 43 is further connected. In the roughening treatment in these cases, the surface on which the plating layer 22b has already been formed is not roughened. In short, by forming the resin 52 after the roughening treatment, the roughened surface 22 a is formed including the part buried in contact with the resin 52. Other steps may be performed as described in FIGS. 2A to 4.

  DESCRIPTION OF SYMBOLS 1 ... Wiring board material, 2 ... Wiring board material, 3 ... Wiring board material, 11 ... Insulating layer, 11A ... Prepreg, 12 ... Insulating layer, 12A ... Prepreg, 13 ... Insulating layer, 14 ... Insulating layer, 14A ... Prepreg, DESCRIPTION OF SYMBOLS 15 ... Insulating layer, 21 ... Wiring layer (2nd wiring pattern), 21A ... Metal foil (copper foil), 22 ... Wiring layer (1st wiring pattern), 22a ... Roughened surface, 22b ... Plating layer, 22A ... metal foil (copper foil), 23 ... wiring layer (wiring pattern), 23A ... metal foil (copper foil), 24 ... wiring layer (wiring pattern), 24A ... metal foil (copper foil), 25 ... wiring layer (already One second wiring pattern), 26 ... wiring layer (wiring pattern), 26A ... metal foil (copper foil), 31, 32, 34, 35 ... interlayer connection (conductive bumps printed by conductive composition), 33 through-hole conductor, 41 semiconductor element, 42 Conductive bumps (Au stud bumps; connection members), 43 ... bonding wires (connection members), 51 ... underfill resin, 52 ... potting resin or transfer mold resin, 61, 62 ... solder resist, 71 ... openings for parts, 72 ... Through hole, 100 ... Plating layer forming mask pattern.

Claims (13)

A first insulating layer;
A second insulating layer positioned in a stack with respect to the first insulating layer;
A semiconductor element having a terminal pad embedded in the second insulating layer;
The first insulating layer includes a surface gold-plated connection land sandwiched between and in contact with the first insulating layer and the second insulating layer, and has no surface gold plating except on the connection land. Wiring pattern of
A connection member for electrically connecting the terminal pad of the semiconductor element and the connection land of the first wiring pattern;
A resin provided to seal the connecting member therein;
A second wiring pattern provided on the surface of the first insulating layer opposite to the surface on which the first wiring pattern is provided;
An interlayer connector that penetrates through the first insulating layer and electrically connects the first wiring pattern and the second wiring pattern;
The component built-in wiring board, wherein the interlayer connection body electrically connects at least each of the first wiring patterns connected to the connection land and the second wiring pattern. . The semiconductor element is flip-connected on the connection land of the first wiring pattern;
The connection member is interposed between the terminal pad of the semiconductor element and the connection land of the first wiring pattern, and electrically connects the terminal pad and the connection land electrically and mechanically. Is a sex bump,
The component built-in wiring board according to claim 1, wherein the resin is an underfill resin provided between the semiconductor element, the first insulating layer, and the wiring pattern. The semiconductor element is provided on the first insulating layer such that a side having the terminal pad is directed to a side opposite to the first insulating layer;
The connection member is a bonding wire provided to electrically connect the terminal pad of the semiconductor element and the connection land of the first wiring pattern;
The component built-in wiring board according to claim 1, wherein the resin seals the semiconductor element and the bonding wire.   3. The component built-in wiring board according to claim 2, wherein a surface of the first wiring pattern is roughened except at least on the connection land.   4. The component built-in wiring board according to claim 3, wherein the first wiring pattern has a roughened surface on the second insulating layer side except at least on the connection land.   The component built-in wiring board according to claim 4, wherein the first wiring pattern is roughened on a surface in contact with the resin.   The component built-in wiring board according to claim 5, wherein the first wiring pattern is roughened on a surface in contact with the resin.   The component built-in wiring board according to claim 4, wherein the first wiring pattern is not roughened on a surface in contact with the resin.   The component built-in wiring board according to claim 5, wherein the first wiring pattern is not roughened on a surface in contact with the resin.   2. The component built-in wiring board according to claim 1, wherein the interlayer connection body is made of a conductive composition.   11. The component built-in wiring board according to claim 10, wherein the interlayer connection body has a shape having an axis coinciding with the stacking direction and a diameter changing in the direction of the axis. A first insulating plate having a first surface and a second surface, a first metal foil laminated on the first surface, and a second metal laminated on the second surface Forming a laminated body having a foil and an interlayer connection body that passes through the first insulating plate and electrically connects the first metal foil and the second metal foil;
The second metal foil of the laminate is patterned to form a first wiring pattern including a connection land for parts, and each of the first wiring patterns connected to the connection land is in contact with the interlayer connection body. The process of forming so as not to lose
Forming a mask pattern on the connection land on the surface of the laminate on which the first wiring pattern is provided;
Using the mask pattern, using the first metal foil and the interlayer connection as a power feed path, and applying electrolytic gold plating on the connection land;
Removing the mask pattern;
Electrically connecting a semiconductor element onto the second surface of the first laminate using the connection land subjected to the electrolytic gold plating;
Patterning a third metal foil laminated on a second insulating plate different from the first insulating plate to form a second wiring pattern;
Laminating a third insulating plate different from the first and second insulating plates on a surface of the second insulating plate on the side having the second wiring pattern;
The fourth, third, and second insulating plates are stacked on the first insulating plate so as to embed the electronic component in a fourth insulating plate different from the first to third insulating plates. And a step of integrating the layers in the order of the lamination positions.   After the step of applying the electrolytic gold plating on the connection lands, the fourth, third, and second insulating plates are integrated on the first insulating plate in the order of the stacking positions. 13. The method of manufacturing a component built-in wiring board according to claim 12, further comprising a step of roughening the surface of the first wiring pattern before the step.

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