JP2010258091A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a split-gate type nonvolatile memory which can reduce leakage current, by relaxing the strength of an electric field generated between a control gate electrode and a memory gate electrode, wherein the control gate electrode and the memory gate electrode are arranged mutually close. <P>SOLUTION: A gate insulating film GOX is formed on a semiconductor substrate 1S, and the control gate electrode CG is formed on the gate insulating film GOX. On the right sidewall of the control gate electrode CG, the memory gate electrode MG is formed, with a multilayer insulating film interposed therebetween. A bird's beak BV is formed at the upper end of the control gate electrode CG. As a result, since the upper end of the control gate electrode CG and the upper end of the memory gate electrode MG are separated by the length of the bird's beak BV, electric field strength is relaxed, and thereby the leakage current flowing between the control gate electrode CG and the memory gate electrode MG is reduced. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to the manufacture of a split gate type memory in which a memory gate electrode and a control gate electrode are formed adjacent to each other.

  Japanese Unexamined Patent Publication No. 2007-258497 (Patent Document 1) discloses a short circuit failure between a control gate electrode and a memory gate electrode in a semiconductor device having a MONOS (Metal Oxide Nitride Oxide Semiconductor) type nonvolatile memory cell having a split gate structure. Techniques that can be reduced are described.

  Specifically, a control gate electrode made of a polysilicon film is formed on a first region of a semiconductor substrate via a gate insulating film, and a first insulating film and a charge storage film are formed on a second region adjacent to the first region. Then, a memory gate electrode made of a polysilicon film is formed via the second insulating film. After that, by performing an oxidation process, the first insulating film formed between the upper portion of the control gate electrode and the charge storage film is formed into a bird's beak shape, and is formed between the memory gate electrode and the charge storage film. The second insulating film has a bird's beak shape.

JP 2007-258497 A

  As an electrically rewritable nonvolatile memory, a floating gate nonvolatile memory using polycrystalline silicon as a floating electrode is mainly used. However, as miniaturization of non-volatile memory cells progresses, an increase in capacity between adjacent non-volatile memory cells and a hindrance in operation due to a decrease in capacity between the control gate electrode and the floating electrode become significant. For this reason, the floating gate type nonvolatile memory is considered to reach the limit of scaling in the near future.

  MRAM (Magnetroresistive Random Access Memory) and PRAM (Phase change Random Access Memory) have been studied as alternative technologies for floating gate type non-volatile memory. New materials and new processes are required to develop these memories. Therefore, development is not easy.

  Therefore, in recent years, a MONOS type nonvolatile memory has been used as an alternative technology to the floating gate type nonvolatile memory. In the MONOS type nonvolatile memory, an insulating film having a trap level such as a silicon nitride film is used as the charge storage film instead of the polysilicon film used as the charge storage film of the floating gate type nonvolatile memory. Such a MONOS type nonvolatile memory can use a conventional technique represented by a similar floating gate type nonvolatile memory, does not require development of a new process, is easy to be miniaturized, It has advantages such as high reliability.

  The MONOS type nonvolatile memory includes a memory cell having a single transistor structure and a memory cell having a two-transistor structure provided with a control gate electrode (selection transistor) and a memory gate electrode (memory transistor). For example, a memory cell having a two-transistor structure has a gate insulating film formed on a semiconductor substrate and a control gate electrode formed on the gate insulating film, and has a sidewall shape on one side wall of the control gate electrode. Memory gate electrodes are formed. A first insulating film (first potential barrier film), a charge storage film (silicon nitride film), and a second insulation are provided between the control gate electrode and the memory gate electrode and between the memory gate electrode and the semiconductor substrate. A laminated insulating film made of a film (second potential barrier film) is formed. Further, a source region and a drain region are formed in a region in the semiconductor substrate that sandwiches the control gate electrode and the memory gate electrode.

  The two-transistor memory configured as described above is called a split gate nonvolatile memory. This split gate type non-volatile memory is characterized by the fact that it does not cause a depletion failure and can operate at high speed. However, the split gate nonvolatile memory has a structure in which the control gate electrode and the memory gate electrode are close to each other. Therefore, for example, when data is written to the split gate nonvolatile memory, a high potential difference is generated between the control gate electrode and the memory gate electrode. At this time, the control gate electrode and the memory gate electrode are insulated from each other via the stacked insulating film (first potential barrier film, charge storage film, second potential barrier film) described above. Thus, when a high potential difference occurs between the control gate electrode and the memory gate electrode, since only a thin laminated insulating film is interposed, the electric field density is increased, and a large leakage current is generated between the control gate electrode and the memory gate electrode. The problem that occurs occurs. When the leakage current occurs, power consumption increases and it may be difficult to realize a normal write operation.

  An object of the present invention is to reduce leakage of electric field intensity generated between a control gate electrode and a memory gate electrode, particularly in a split gate type nonvolatile memory in which the control gate electrode and the memory gate electrode are close to each other. The object is to provide a technique capable of reducing current.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a representative embodiment has a plurality of memory cells formed on a semiconductor substrate. Each of the plurality of memory cells includes (a) a gate insulating film formed on the semiconductor substrate, (b) a control gate electrode formed on the gate insulating film, and (c) a control gate electrode. And a memory gate electrode formed on the side wall. (D) a stacked insulating film formed between the control gate electrode and the memory gate electrode and between the memory gate electrode and the semiconductor substrate; and (e) a source formed in the semiconductor substrate. A region and a drain region. The stacked insulating film includes (d1) a first potential barrier film, (d2) a charge storage film formed on the first potential barrier film, and (d3) a second potential formed on the charge storage film. And a barrier film. At this time, a bird's beak is formed at the upper end of the control gate electrode. Here, the film thickness of the first potential barrier film formed at a position in contact with the middle end portion of the control gate electrode is a, and is formed in the gate length direction of the control gate electrode from the upper end portion of the control gate electrode. When the length of the bird's beak is b, the relationship of b> a is satisfied and the relationship of 2 nm ≦ a ≦ 5 nm is satisfied.

  A method of manufacturing a semiconductor device according to a representative embodiment relates to a method of manufacturing a semiconductor device having a memory cell formation region on a semiconductor substrate, and (a) a step of forming a gate insulating film on the semiconductor substrate; (B) forming a first conductor film on the gate insulating film; and (c) forming a mask film on the first conductor film. Next, (d) a step of patterning the mask film, and (e) a silicon oxide film is formed on the surface of the first conductor film exposed from the patterned mask film, and is covered with the mask film Forming a bird's beak so as to bite into the first conductor film. (F) forming a control gate electrode by processing the first conductor film using the patterned mask film as a mask; and (g) on the semiconductor substrate on which the control gate electrode is formed. Forming a laminated insulating film. (H) forming a second conductor film on the laminated insulating film; and (i) forming a memory gate electrode on the side wall of the control gate electrode by anisotropically etching the second conductor film. And a step of performing. And (j) forming the stacked insulating film between the control gate electrode and the memory gate electrode and between the memory gate electrode and the semiconductor substrate by etching the stacked insulating film; ) After the step (j), a step of forming a source region and a drain region in the semiconductor substrate is provided.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Among the nonvolatile memories, in particular, in a split gate nonvolatile memory in which the control gate electrode and the memory gate electrode are close to each other, the electric field strength generated between the control gate electrode and the memory gate electrode can be relaxed to reduce the leakage current.

3 is a diagram showing a layout configuration of a semiconductor chip in the first embodiment. FIG. It is sectional drawing which shows the structure of the semiconductor device in Embodiment 1 of this invention. FIG. 3 is an enlarged cross-sectional view of the memory cell shown in FIG. 2. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 4; FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; 6 is a cross-sectional view showing a modification of the first embodiment. FIG. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; FIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor device in a third embodiment. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in Embodiment 3. FIG. FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 26; FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 27; FIG. 10 is a cross-sectional view illustrating a configuration of a semiconductor device in a fourth embodiment. FIG. 30 is an enlarged cross-sectional view showing the memory cell shown in FIG. 29. FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device in the fourth embodiment. FIG. 32 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 31; FIG. 33 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 32; FIG. 34 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 33; FIG. 35 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 34; FIG. 36 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 35; FIG. 37 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 36; FIG. 38 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 37;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
The nonvolatile memory in the first embodiment will be described with reference to the drawings. First, a layout configuration of a semiconductor chip on which a system including nonvolatile memory cells is formed will be described. FIG. 1 is a diagram showing a layout configuration of the semiconductor chip CHP in the first embodiment. In FIG. 1, a semiconductor chip CHP includes a CPU (Central Processing Unit) 1, a RAM (Random Access Memory) 2, an analog circuit 3, an EEPROM (Electrically Erasable Programmable Read Only Memory) 4, a flash memory 5 and an I / O (Input / Input). Output) circuit 6 is provided.

  The CPU (circuit) 1 is also called a central processing unit and is the heart of a computer or the like. The CPU 1 reads and decodes instructions from the storage device, and performs a variety of calculations and controls based on the instructions.

  The RAM (circuit) 2 is a memory that can read stored information at random, that is, read stored information at any time, or write new stored information, and is also called a memory that can be written and read at any time. There are two types of RAM as an IC memory: DRAM (Dynamic RAM) using a dynamic circuit and SRAM (Static RAM) using a static circuit. DRAM is an occasional writing / reading memory that requires a memory holding operation, and SRAM is an occasional writing / reading memory that does not require a memory holding operation.

  The analog circuit 3 is a circuit that handles a voltage or current signal that changes continuously in time, that is, an analog signal, and includes, for example, an amplifier circuit, a conversion circuit, a modulation circuit, an oscillation circuit, and a power supply circuit.

  The EEPROM 4 and the flash memory 5 are a kind of non-volatile memory that can be electrically rewritten for both writing and erasing operations, and are also called electrically erasable programmable read-only memories. The memory cells of the EEPROM 4 and the flash memory 5 are composed of, for example, MONOS (Metal Oxide Nitride Oxide Semiconductor) type transistors or MNOS (Metal Nitride Oxide Semiconductor) type transistors for storage (memory). For example, the Fowler-Nordheim tunneling phenomenon is used for the writing operation and the erasing operation of the EEPROM 4 and the flash memory 5. Note that a write operation or an erase operation can be performed using hot electrons or hot holes. The difference between the EEPROM 4 and the flash memory 5 is that the EEPROM 4 is a non-volatile memory that can be erased in byte units, for example, whereas the flash memory 5 is a non-volatile memory that can be erased in word word units, for example. is there. In general, the flash memory 5 stores a program for the CPU 1 to execute various processes. On the other hand, the EEPROM 4 stores various data with high rewrite frequency.

  The I / O circuit 6 is an input / output circuit, and outputs data from the semiconductor chip CHP to a device connected to the outside of the semiconductor chip CHP, or from a device connected to the outside of the semiconductor chip CHP to the semiconductor chip. This is a circuit for inputting the data.

  Next, the configuration of the nonvolatile memory in the first embodiment will be described. The nonvolatile memory according to the first embodiment is a memory constituting the EEPROM 4 and the flash memory 5 shown in FIG. FIG. 2 is a diagram showing a cross section of the nonvolatile memory according to the first embodiment. In FIG. 2, a memory cell formation region MCR and a peripheral circuit formation region PER are illustrated, and one memory cell is illustrated in the memory cell formation region MCR. On the other hand, in the peripheral circuit formation region PER, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) constituting the peripheral circuit is illustrated.

  As shown in FIG. 2, in the memory cell formation region MCR, a well isolation layer NISO is formed on a semiconductor substrate 1S, and a p-type well PWL1 is formed on the well isolation layer NISO. On the other hand, in the peripheral circuit formation region PER, the element isolation region STI is formed in the semiconductor substrate 1S, and the p-type well PWL2 and the n-type well NWL1 are formed in the active region (active region) partitioned by the element isolation region STI. Is formed. The element isolation region STI is formed by embedding an insulating film such as a silicon oxide film in a groove formed in the semiconductor substrate 1S.

  First, the configuration of the MISFET formed in the peripheral circuit formation region PER divided by the element isolation region STI will be described. The peripheral circuit formation region PER indicates a region where a peripheral circuit is formed. Specifically, the nonvolatile memory (nonvolatile semiconductor memory device) includes a memory cell formation region MCR in which memory cells are formed in an array (matrix), and a memory cell formed in the memory cell formation region MCR. The peripheral circuit forming region PER is formed with a peripheral circuit for controlling the control. The peripheral circuit formed in the peripheral circuit formation region PER includes a word driver that controls the voltage applied to the control gate electrode of the memory cell, a sense amplifier that amplifies the output from the memory cell, a word driver, It consists of a control circuit that controls the sense amplifier. Therefore, in the peripheral circuit formation region PER shown in FIG. 2, for example, a MISFET constituting a word driver, a sense amplifier or a control circuit is illustrated. The n-channel MISFET constituting this peripheral circuit will be described below.

  As shown in FIG. 2, in the peripheral circuit formation region PER, a p-type well PWL2 is formed on the semiconductor substrate 1S. The p-type well PWL2 is formed from a p-type semiconductor region in which a p-type impurity such as boron (B) is introduced into the semiconductor substrate 1S.

  Next, a gate insulating film GOX is formed on the p-type well PWL2 (semiconductor substrate 1S), and a gate electrode G1 is formed on the gate insulating film GOX. The gate insulating film GOX is made of, for example, a silicon oxide film, and the gate electrode G1 is made of, for example, a polysilicon film PF1 and a cobalt silicide film CS formed on the surface of the polysilicon film PF1. For example, an n-type impurity such as phosphorus is introduced into the polysilicon film PF1 constituting the gate electrode G1 in order to suppress depletion of the gate electrode G1. The cobalt silicide film CS constituting a part of the gate electrode G1 is formed for reducing the resistance of the gate electrode G1.

  Side walls SW made of, for example, a silicon oxide film are formed on the side walls on both sides of the gate electrode G1, and a shallow low-concentration impurity diffusion region is formed in the semiconductor substrate 1S (p-type well PWL2) immediately below the sidewall SW. EX2 is formed. This shallow low-concentration impurity diffusion region EX2 is an n-type semiconductor region and is formed in alignment with the gate electrode G1. A deep high concentration impurity diffusion region NR2 is formed outside the shallow low concentration impurity diffusion region EX2. This deep high-concentration impurity diffusion region NR2 is also an n-type semiconductor region and is formed in alignment with the sidewall SW. A cobalt silicide film CS for reducing the resistance is formed on the surface of the deep high-concentration impurity diffusion region NR2. A source region is formed by the shallow low concentration impurity diffusion region EX2 and the deep high concentration impurity diffusion region NR2, and a drain region is formed by the shallow low concentration impurity diffusion region EX2 and the deep high concentration impurity diffusion region NR2. In this way, an n-channel MISFET is formed in the peripheral circuit formation region PER.

  Next, a p-channel type MISFET constituting the peripheral circuit will be described. As shown in FIG. 2, in the peripheral circuit formation region PER, an n-type well NWL1 is formed on the semiconductor substrate 1S. The n-type well NWL1 is formed from an n-type semiconductor region in which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S.

  Next, a gate insulating film GOX is formed on the n-type well NWL1 (semiconductor substrate 1S), and a gate electrode G2 is formed on the gate insulating film GOX. The gate insulating film GOX is formed of, for example, a silicon oxide film, and the gate electrode G2 is formed of, for example, a polysilicon film PF1 and a cobalt silicide film CS formed on the surface of the polysilicon film PF1. A p-type impurity such as boron (boron) is introduced into the polysilicon film PF1 constituting the gate electrode G2 in order to suppress depletion of the gate electrode G2. The cobalt silicide film CS constituting a part of the gate electrode G2 is formed for reducing the resistance of the gate electrode G2.

  Side walls SW made of, for example, a silicon oxide film are formed on the side walls on both sides of the gate electrode G2, and a shallow low-concentration impurity diffusion region is formed in the semiconductor substrate 1S (n-type well NWL1) immediately below the sidewall SW. EX3 is formed. This shallow low-concentration impurity diffusion region EX3 is a p-type semiconductor region and is formed in alignment with the gate electrode G2. A deep high-concentration impurity diffusion region PR1 is formed outside the shallow low-concentration impurity diffusion region EX3. This deep high-concentration impurity diffusion region PR1 is also a p-type semiconductor region and is formed in alignment with the sidewall SW. A cobalt silicide film CS for reducing the resistance is formed on the surface of the deep high-concentration impurity diffusion region PR1. A source region is formed by the shallow low concentration impurity diffusion region EX3 and the deep high concentration impurity diffusion region PR1, and a drain region is formed by the shallow low concentration impurity diffusion region EX3 and the deep high concentration impurity diffusion region PR1. In this way, the p-channel type MISFET is formed in the peripheral circuit formation region PER.

  Subsequently, a wiring structure connected to the MISFET formed in the peripheral circuit formation region PER will be described. On the MISFET, an interlayer insulating film IL1 made of a silicon oxide film is formed so as to cover the MISFET. The interlayer insulating film IL1 is formed of, for example, a stacked film of a silicon nitride film and a silicon oxide film. In the interlayer insulating film IL1, a contact hole CNT that penetrates the interlayer insulating film IL1 and reaches the cobalt silicide film CS constituting the source region and the drain region is formed. A titanium / titanium nitride film as a barrier conductor film is formed inside the contact hole CNT, and a tungsten film is formed so as to fill the contact hole. Thus, the conductive plug PLG1 is formed by embedding the titanium / titanium nitride film and the tungsten film in the contact hole CNT. An interlayer insulating film IL2 made of, for example, a silicon oxide film is formed on the interlayer insulating film IL1, and a wiring trench is formed in the interlayer insulating film IL2. A wiring L1 is formed so as to fill the wiring groove. The wiring L1 is formed of, for example, a laminated film of a tantalum / tantalum nitride film and a copper film, and is electrically connected to the plug PLG1 formed in the interlayer insulating film IL1.

  Next, the configuration of the memory cell formed in the memory cell formation region MCR will be described. As shown in FIG. 2, in the memory cell formation region MCR, a well isolation layer NISO made of an n-type semiconductor region is formed on a semiconductor substrate 1S, and a p-type well PWL1 is formed on the well isolation layer NISO. Yes. A memory cell is formed on the p-type well PWL1. The memory cell includes a selection unit that selects a memory cell and a storage unit that stores information.

  First, the configuration of the selection unit that selects a memory cell will be described. The memory cell has a gate insulating film GOX formed on the semiconductor substrate 1S (p-type well PWL1), and a control gate electrode (control electrode) CG is formed on the gate insulating film GOX. The gate insulating film GOX is made of, for example, a silicon oxide film, and the control gate electrode CG is made of, for example, the polysilicon film PF1 and the cobalt silicide film CS formed on the polysilicon film PF1. The cobalt silicide film CS is formed to reduce the resistance of the control gate electrode CG. The control gate electrode CG has a function of selecting a memory cell. That is, a specific memory cell is selected by the control gate electrode CG, and a write operation, an erase operation, or a read operation is performed on the selected memory cell.

  Next, the configuration of the storage unit of the memory cell will be described. A memory gate electrode MG is formed on a side wall on one side of the control gate electrode CG via a laminated insulating film made of an insulating film. The memory gate electrode MG has a sidewall shape formed on one side wall of the control gate electrode CG, and is formed of a polysilicon film PF2 and a cobalt silicide film CS formed on the polysilicon film PF2. ing. The cobalt silicide film CS is formed to reduce the resistance of the memory gate electrode MG.

  A laminated insulating film is formed between the control gate electrode CG and the memory gate electrode MG and between the memory gate electrode MG and the semiconductor substrate 1S. The stacked insulating film includes a potential barrier film EB1 formed on the semiconductor substrate 1S, a charge storage film EC formed on the potential barrier film EB1, and a potential barrier film formed on the charge storage film EC. It is composed of EB2. The potential barrier film EB1 is made of, for example, a silicon oxide film, and functions as a gate insulating film formed between the memory gate electrode MG and the semiconductor substrate 1S. This potential barrier film made of a silicon oxide film also has a function as a tunnel insulating film. For example, the memory unit of the memory cell stores and erases information by injecting electrons from the semiconductor substrate 1S into the charge storage film EC via the potential barrier film EB1 or injecting holes into the charge storage film EC. Therefore, the potential barrier film EB1 functions as a tunnel insulating film.

  The charge storage film EC formed on the potential barrier film EB1 has a function of storing charges. Specifically, in the first embodiment, the charge storage film EC is formed from a silicon nitride film. The storage unit of the memory cell according to the first embodiment stores information by controlling the current flowing in the semiconductor substrate 1S under the memory gate electrode MG according to the presence or absence of charges stored in the charge storage film EC. It has become. That is, information is stored by utilizing the fact that the threshold voltage of the current flowing in the semiconductor substrate 1S under the memory gate electrode MG changes depending on the presence or absence of charges accumulated in the charge storage film EC.

  In the first embodiment, an insulating film having a trap level is used as the charge storage film EC. An example of the insulating film having this trap level is a silicon nitride film. However, the insulating film is not limited to a silicon nitride film, and is higher than a silicon nitride film such as an aluminum oxide film (alumina), a hafnium oxide film, or a tantalum oxide film. A high dielectric constant film having a dielectric constant may be used. When an insulating film having a trap level is used as the charge storage film EC, charges are trapped in the trap level formed in the insulating film. Thus, charges are accumulated in the insulating film by trapping the charges at the trap level.

  Conventionally, a polysilicon film has been mainly used as the charge storage film EC. However, when a polysilicon film is used as the charge storage film EC, somewhere in the potential barrier film EB1 or the potential barrier film EB2 surrounding the charge storage film EC. If there is a defect in part, since the charge storage film EC is a conductor film, all charges accumulated in the charge storage film EC may be lost due to abnormal leakage.

  Therefore, a silicon nitride film that is an insulator has been used as the charge storage film EC. In this case, electric charges contributing to data storage are accumulated in discrete trap levels (capture levels) existing in the silicon nitride film. Therefore, even if a defect occurs in a part of the potential barrier film EB1 or the potential barrier film EB2 surrounding the charge storage film EC, all charges are stored in the discrete trap levels of the charge storage film EC. Charges do not escape from the charge storage film EC. For this reason, the reliability of data retention can be improved.

  For this reason, the reliability of data retention can be improved by using a film that includes not only a silicon nitride film but also a discrete trap level as the charge storage film EC. Further, in the first embodiment, a silicon nitride film having excellent data retention characteristics is used as the charge storage film EC. Therefore, the thicknesses of the potential barrier film EB1 and the potential barrier film EB2 provided to prevent the outflow of charges from the charge storage film EC can be reduced. Thus, there is an advantage that the voltage for driving the memory cell can be lowered.

  Next, the memory gate electrode MG is formed on one side of the sidewalls of the control gate electrode CG, while the sidewall SW made of a silicon oxide film is formed on the other side. Similarly, a control gate electrode CG is formed on one side of the sidewalls of the memory gate electrode MG, and a sidewall SW made of a silicon oxide film is formed on the other side.

  A pair of shallow low-concentration impurity diffusion regions EX1 that are n-type semiconductor regions are formed in the semiconductor substrate 1S immediately below the sidewall SW, and an outer region in contact with the pair of shallow low-concentration impurity diffusion regions EX1. A pair of deep high-concentration impurity diffusion regions NR1 is formed. This deep high-concentration impurity diffusion region NR1 is also an n-type semiconductor region, and a cobalt silicide film CS is formed on the surface of the deep high-concentration impurity diffusion region NR1. A pair of shallow low-concentration impurity diffusion regions EX1 and a pair of deep high-concentration impurity diffusion regions NR1 form a source region or a drain region of the memory cell. By forming the source region and the drain region with the shallow low-concentration impurity diffusion region EX1 and the deep high-concentration impurity diffusion region NR1, the source region and the drain region can have an LDD (Lightly Doped Drain) structure. Here, the transistor including the gate insulating film GOX, the control gate electrode CG formed on the gate insulating film GOX, and the above-described source region and drain region is referred to as a selection transistor. On the other hand, a stacked insulating film composed of the potential barrier film EB1, the charge storage film EC, and the potential barrier film EB2, a memory gate electrode MG formed on the stacked insulating film, and a transistor constituted by the source region and the drain region described above. It will be called a memory transistor. Thereby, it can be said that the selection part of a memory cell is comprised from the selection transistor, and the memory | storage part of the memory cell is comprised from the memory transistor. In this way, a memory cell is configured.

  Next, a wiring structure connected to the memory cell will be described. Over the memory cell, an interlayer insulating film IL1 made of a silicon nitride film and a silicon oxide film is formed so as to cover the memory cell. In the interlayer insulating film IL1, a contact hole CNT that penetrates the interlayer insulating film IL1 and reaches the cobalt silicide film CS constituting the source region and the drain region is formed. A titanium / titanium nitride film, which is a barrier conductor film, is formed inside the contact hole CNT, and a tungsten film is formed so as to fill the contact hole CNT. Thus, the conductive plug PLG1 is formed by embedding the titanium / titanium nitride film and the tungsten film in the contact hole CNT. An interlayer insulating film IL2 made of, for example, a silicon oxide film is formed on the interlayer insulating film IL1, and a wiring trench is formed in the interlayer insulating film IL2. A wiring L1 is formed so as to fill the wiring groove. The wiring L1 is formed of, for example, a laminated film of a tantalum / tantalum nitride film and a copper film, and is electrically connected to the plug PLG1 formed in the interlayer insulating film IL1. As described above, the memory cell and the MISFET constituting the peripheral circuit are formed on the semiconductor substrate 1S.

  Next, the operation of the nonvolatile memory cell in the first embodiment will be described. Here, the voltage applied to the control gate electrode CG is Vcg, and the voltage applied to the memory gate electrode MG is Vmg. Further, voltages applied to the source region and the drain region are Vs and Vd, respectively, and a voltage applied to the semiconductor substrate (p-type well) is Vsub. The injection of electrons into the silicon nitride film as the charge storage film EC is defined as “writing”, and the injection of holes into the silicon nitride film is defined as “erasing”.

  First, the write operation will be described. The writing operation is performed by hot electron writing called a so-called source side injection method (source side injection method). As the write voltage, for example, the voltage Vs applied to the source region is 5V, the voltage Vmg applied to the memory gate electrode is 10V, and the voltage Vcg applied to the control gate electrode is 1V. The voltage Vd applied to the drain region is controlled so that the channel current at the time of writing becomes a certain set value. The voltage Vd at this time is determined by the set value of the channel current and the threshold voltage of the selection transistor having the control gate electrode, and is, for example, about 0.5V. The voltage Vsub applied to the p-type well PWL1 (semiconductor substrate) is 0V. In this specification, a semiconductor region to which a high voltage is applied during a write operation is referred to as a source region, and a semiconductor region to which a low voltage is applied during a write operation is referred to as a drain region. For example, referring to FIG. 2, a semiconductor region composed of a deep high concentration impurity diffusion region NR1 and a shallow low concentration impurity diffusion region EX1 on the memory gate electrode MG side is a source region, and a deep high concentration impurity diffusion on the control gate electrode CG side. A semiconductor region composed of the region NR1 and the shallow low-concentration impurity diffusion region EX1 serves as a drain region.

  The movement of charges when performing such a write operation by applying such a voltage is shown. As described above, by applying a potential difference between the voltage Vs applied to the source region and the voltage Vd applied to the drain region, electrons (electrons) flow through the channel region formed between the source region and the drain region. . Electrons flowing through the channel region are accelerated into hot electrons in the channel region (between the source region and the drain region) near the boundary between the control gate electrode CG and the memory gate electrode MG. Then, hot electrons are injected into the silicon nitride film (charge storage film EC) under the memory gate electrode MG by a vertical electric field by a positive voltage (Vmg = 10 V) applied to the memory gate electrode MG. The injected hot electrons are trapped in the trap level in the silicon nitride film, and as a result, electrons are accumulated in the silicon nitride film and the threshold voltage of the memory transistor rises. In this way, the write operation is performed.

  Next, the erase operation will be described. The erasing operation is performed by, for example, BTBT (Band to Band Tunneling) erasing using the band-to-band tunneling phenomenon. In BTBT erase, for example, the voltage Vmg applied to the memory gate electrode MG is -6V, the voltage Vs applied to the source region is 6V, the voltage Vcg applied to the control gate electrode CG is 0V, and the drain region is open. As a result, the holes generated by the band-to-band tunneling phenomenon at the end of the source region due to the voltage applied between the source region and the memory gate electrode MG are accelerated by the high voltage applied to the source region and Become. A part of the hot hole is attracted to the negative voltage applied to the memory gate electrode MG, and is injected into the silicon nitride film. The injected hot holes are captured by trap levels in the silicon nitride film, and the threshold voltage of the memory transistor is lowered. In this way, the erase operation is performed.

  Next, the reading operation will be described. In reading, the voltage Vd applied to the drain region is Vdd (1 V), the voltage Vs applied to the source region is 0 V, the voltage Vcg applied to the control gate electrode CG is Vdd (1.5 V), and is applied to the memory gate electrode MG. The voltage Vmg is set to 0 V, and current is supplied in the direction opposite to that at the time of writing. The voltage Vd applied to the drain region and the voltage Vs applied to the source region may be interchanged to set the voltages to 0 V and 1 V, respectively, so that reading with the same current direction as that during writing may be performed. At this time, when the memory cell is in a write state and the threshold voltage is high, no current flows through the memory cell. On the other hand, when the memory cell is in the erased state and the threshold voltage is low, a current flows through the memory cell.

  In this manner, whether the memory cell is in a written state or an erased state can be determined by detecting the presence or absence of a current flowing through the memory cell. Specifically, the presence or absence of current flowing through the memory cell is detected by a sense amplifier. For example, a reference current (reference current) is used to detect the presence or absence of a current flowing through the memory cell. That is, when the memory cell is in the erased state, a read current flows during reading, and the read current is compared with the reference current. The reference current is set lower than the read current in the erased state. If the read current is larger than the reference current as a result of comparing the read current and the reference current, it can be determined that the memory cell is in the erased state. On the other hand, when the memory cell is in a write state, no read current flows. That is, as a result of comparing the read current with the reference current, if the read current is smaller than the reference current, it can be determined that the memory cell is in the write state. In this way, a read operation can be performed.

  The memory cell in the first embodiment is composed of a split gate type nonvolatile memory cell in which a selection transistor and a memory transistor are arranged adjacent to each other. The advantages of this split gate nonvolatile memory cell will be described. For example, in the MONOS type nonvolatile memory cell, there is a single-structure nonvolatile memory cell in addition to the split gate type nonvolatile memory cell as in the first embodiment. This non-volatile memory cell having a single structure includes a first potential barrier film, a charge storage film, and a second potential barrier film on a semiconductor substrate between a source region and a drain region formed in a semiconductor substrate. It has a laminated insulating film. A memory gate electrode is provided on the laminated insulating film. A single-structure nonvolatile memory cell has a structure having only a memory transistor without a selection transistor unlike a split-gate nonvolatile memory cell. In this non-volatile memory cell having a single structure, the memory cell is selected / unselected by controlling the voltage applied to the memory gate electrode of the memory transistor.

  For example, in a single-structure nonvolatile memory cell, it is assumed that charges (electrons) are accumulated in the charge accumulation film and the threshold voltage is 5 V or higher when in a write state. On the other hand, in the erased state, it is assumed that the charge (electrons) stored in the charge storage film is extracted and the threshold value is 5 V or less. When reading such a single structure nonvolatile memory cell, a voltage of 5 V is applied to the memory gate electrode. As a result, when a single-structure nonvolatile memory cell is in a write state, the threshold voltage is 5 V or higher, so that no read current flows between the source region and the drain region. On the other hand, when the nonvolatile memory cell having a single structure is in the erased state, the threshold voltage is 5 V or less, so that a read current flows between the source region and the drain region. As described above, information stored in the nonvolatile memory cell having a single structure can be read based on the magnitude of the read current in the writing state and the erasing state.

  From the above, in the selected nonvolatile memory cell, the information stored in the nonvolatile memory cell can be read by applying 5 V to the memory gate electrode. At this time, for example, 0 V is applied to the memory gate electrode of the non-selected nonvolatile memory cell that is not selected. This voltage is lower than the threshold voltage of the nonvolatile memory cell in the erased state. That is, a voltage lower than the threshold voltage of the erased nonvolatile memory cell is applied to the non-selected nonvolatile memory cell. As a result, the read current does not flow when the non-selected nonvolatile memory cell is in the write state or the erase state. In this manner, in a single-structure nonvolatile memory cell, selection / non-selection is controlled by the voltage applied to the memory gate electrode. Therefore, the read current does not flow in the non-selected nonvolatile memory cell.

  However, in general, when erasing information in a nonvolatile memory cell, the erasing speed may differ between individual nonvolatile memory cells. In other words, the erasing speed varies depending on the individual difference of each nonvolatile memory cell. In this case, the erase time of the nonvolatile memory cell is set so that even a nonvolatile memory cell with a slow erase speed can be sufficiently erased. Therefore, there is a case where a non-volatile memory cell having a high erase speed is in an over-erased state. In other words, the electrons stored in the charge storage film are extracted more than necessary. This causes the threshold voltage in the erased state of the nonvolatile memory cell to be further lowered. As a result, in some nonvolatile memory cells having a high erase speed, the threshold voltage is lower than the voltage applied to the memory gate electrode of the non-selected nonvolatile memory cell. Specifically, when the voltage applied to the memory gate electrode of the non-selected nonvolatile memory cell is 0V, in some nonvolatile memory cells having a high erase speed, the threshold is lower than 0V, for example, −1V. There may be a value voltage.

  In this case, when the nonvolatile memory cell having a reduced erase voltage and a fast erase speed becomes a non-selected nonvolatile memory cell, when a voltage of 0 V is applied to the memory gate electrode, the threshold voltage ( Since a voltage higher than −1V) is applied, a current flows. That is, during the read operation, current flows also to the non-selected non-volatile memory cell. As a result, the current that is flowing is the current caused by the selected non-volatile memory cell or the non-erased non- It is impossible to distinguish whether the current is caused by the selected nonvolatile memory cell. This means that the read operation cannot be performed normally, and this phenomenon is called a depletion failure. Therefore, in a single-structure nonvolatile memory cell, a depletion failure is likely to occur.

  On the other hand, in the split gate nonvolatile memory cell having the selection transistor and the memory transistor, it is possible to prevent the deficiency defect. This is because even if the threshold voltage of the memory transistor of the split gate type nonvolatile memory cell is lowered due to over-erasing, the current can be forcibly cut off by the selection transistor. That is, in the split gate type nonvolatile memory cell, since the selection / non-selection of the memory cell is performed by the selection transistor, there is an advantage that a depletion failure can be prevented.

  Furthermore, the split gate type nonvolatile memory cell has an advantage that it can operate at a higher speed than the nonvolatile memory cell having a single structure. This is because a single layer nonvolatile memory cell has a thick laminated insulating film (first potential barrier film, charge storage film, second potential barrier film) between the memory gate electrode and the semiconductor substrate (channel formation region). Therefore, the operation speed of selection / non-selection becomes slow. On the other hand, in the split gate type nonvolatile memory cell, the selection / non-selection operation is performed by a selection transistor different from the memory transistor. A thin gate insulating film exists between the control gate electrode of the selection transistor and the semiconductor substrate (channel formation region). That is, unlike the stacked insulating film, the gate insulating film of the selection transistor can be thinned, so that the operation speed of the selection transistor can be increased.

  Here, for example, taking a write operation as an example, a voltage of 1 V is applied to the control gate electrode CG of the split gate nonvolatile memory cell, and a voltage of 10 V is applied to the memory gate electrode CG. That is, the potential difference between the control gate electrode CG and the memory gate electrode MG is increased. At this time, in the split gate nonvolatile memory cell, the memory gate electrode MG is formed on the side wall of the control gate electrode CG, and the control gate electrode CG and the memory gate electrode MG are close to each other. Therefore, the electric field strength generated between the control gate electrode CG and the memory gate electrode MG is increased. As a result, the electric field strength applied to the laminated insulating film (first potential barrier film EB1, charge storage film EC, second potential barrier film EB2) formed between the control gate electrode CG and the memory gate electrode MG is large. As a result, the leakage current flowing between the control gate electrode CG and the memory gate electrode MG through the laminated insulating film increases. When the leakage current increases, the power consumption of the entire nonvolatile memory increases and there is a possibility that normal operation cannot be ensured. That is, in the split gate type nonvolatile memory cell, miniaturization can be promoted by forming the memory gate electrode MG on the side wall of the control gate electrode CG. On the other hand, the control gate electrode CG and the memory gate electrode MG are close to each other. Will do. For this reason, when a large potential difference occurs between the control gate electrode CG and the memory gate electrode MG as in writing, the electric field strength applied to the stacked insulating film increases, and the control gate electrode CG and the memory are interposed via the stacked insulating film. The leakage current generated between the gate electrodes MG increases.

  Therefore, in the split gate nonvolatile memory cell according to the first embodiment, the electric field strength between the control gate electrode CG and the memory gate electrode MG is relaxed, and the leakage current flowing between the control gate electrode CG and the memory gate electrode MG is reduced. The technical idea to reduce is demonstrated below.

  FIG. 3 is an enlarged view of the memory cells formed in the memory cell formation region MCR of FIG. In FIG. 3, the feature of the first embodiment is that a bird's beak BV is formed at the upper end of the control gate electrode CG. Thereby, the substantial distance between the control gate electrode CG and the memory gate electrode MG can be increased. That is, by forming a bird's beak BV at the upper end of the control gate electrode CG, a stacked insulating film (first potential barrier film EB1) is formed between the memory gate electrode MG and the control gate electrode CG at the upper end of the control gate electrode CG. , The charge storage film EC, the second potential barrier film EB2) and the bird's beak BV exist. For example, the distance between the control gate electrode CG and the memory gate electrode MG by the amount of the bird's beak BV made of a silicon oxide film. Can be released. As a result, even if a large potential difference occurs between the control gate electrode CG and the memory gate electrode MG, the electric field strength applied to the laminated insulating film formed therebetween is relaxed. That is, the electric field strength decreases as the distance between the control gate electrode CG and the memory gate electrode MG increases, so that by forming the bird's beak BV, the electric field strength is between the control gate electrode CG and the memory gate electrode MG. The generated electric field strength can be reduced. As a result, the leakage current flowing between the control gate electrode CG and the memory gate electrode MG via the stacked insulating film can be reduced.

  In the first embodiment, a bird's beak BV is formed at the upper end of the control gate electrode CG. This also means that the control gate electrode CG has a convex shape. Here, as shown in FIG. 3, in the first embodiment, the bird's beak BV is formed only at the upper end of the control gate electrode CG. In other words, since the bird's beak BV is not formed in a region other than the upper end portion of the control gate electrode CG (for example, the middle end portion or the lower end portion of the control gate electrode CG), the control gate electrode CG and the memory gate electrode MG The distance between is only the film thickness of the laminated insulating film. Therefore, even if the distance from the memory gate electrode MG is increased only at the upper end portion of the control gate electrode CG, the distance from the memory gate electrode MG changes at the middle end portion and the lower end portion of the control gate electrode CG. There will be no. Therefore, since the electric field strength is not relaxed in the region other than the upper end portion of the control gate electrode CG, it is considered that the leakage current flowing in the region other than the upper end portion of the control gate electrode CG cannot be reduced. However, the increase in leakage current becomes a problem in the laminated insulating film in the region formed at the upper end portion of the laminated insulating film formed between the control gate electrode CG and the memory gate electrode MG. The reason for this will be described.

  In the split gate nonvolatile memory cell according to the first embodiment, after forming the control gate electrode CG and the memory gate electrode MG, the source region and the drain region are formed in the semiconductor substrate 1S. The source region and the drain region are formed by a shallow low concentration impurity diffusion region EX1 and a deep high concentration impurity diffusion region NR1. The shallow low-concentration impurity diffusion region EX1 and the deep high-concentration impurity diffusion region NR1 are semiconductor regions, and are formed by introducing n-type impurities such as phosphorus and arsenic into the semiconductor substrate 1S (p-type well PWL1). That is, the source region and the drain region are formed by introducing the n-type impurity into the semiconductor substrate 1S (p-type well PWL1) by ion implantation after forming the control gate electrode CG and the memory gate electrode MG. Therefore, n-type impurities are introduced into the semiconductor substrate 1S (p-type well PWL1) in order to form the source region and the drain region, and are also formed on the surfaces of the control gate electrode CG and the memory gate electrode MG that are already formed. N-type impurities are also introduced. In particular, since a laminated insulating film is formed between the control gate electrode CG and the memory gate electrode MG, an n-type impurity is also introduced into the surface of the laminated insulating film. At this time, the laminated insulating film is an insulating film, but it is known that the insulation resistance deteriorates when an n-type impurity such as phosphorus or arsenic is introduced into the laminated insulating film. In other words, since n-type impurities are introduced into the surface of the laminated insulating film, the surface of the laminated insulating film into which the n-type impurities are introduced is more than the other regions of the laminated insulating film (regions into which n-type impurities are not introduced). The insulation resistance deteriorates. Therefore, even if the film thickness of the laminated insulating film is uniform, the electric field strength becomes a problem because the insulation resistance deteriorates in the vicinity of the surface of the laminated insulating film. That is, since the insulation resistance is deteriorated at the upper end portion of the laminated insulating film, it is easily affected by the electric field strength. For this reason, it is necessary to relax the electric field strength at the upper end of the laminated insulating film. In other words, in the regions other than the upper end portion (the middle end portion and the lower end portion) of the laminated insulating film, since the insulation resistance is not deteriorated, it can be said that the influence of the electric field strength is less affected. In other words, the film thickness of the stacked insulating film formed between the control gate electrode CG and the memory gate electrode MG is formed with a film thickness sufficient to reduce the leakage current. In this case, n-type impurities such as phosphorus and arsenic are introduced to deteriorate insulation resistance (leakage current increases). Therefore, it is necessary to relax the electric field strength and reduce the leakage current.

  As described above, by forming the bird's beak BV at the upper end portion of the control gate electrode CG, the distance between the control gate electrode CG and the memory gate electrode MG at the upper end portion between the control gate electrode CG and the memory gate electrode MG. Can be released. For this reason, since the electric field strength at the upper end portion of the multilayer insulating film can be relaxed, it is possible to reduce the leakage current at the upper end portion of the multilayer insulating film, which easily deteriorates the insulation resistance.

  Hereinafter, specifically, conditions for sufficiently achieving electric field relaxation between the control gate electrode CG and the memory gate electrode MG will be described. That is, a condition that is satisfied by the bird's beak BV formed at the upper end of the control gate electrode CG is considered. First, as shown in FIG. 3, the film thickness of the first potential barrier film EB1 formed at a position in contact with the middle end portion (or the lower end portion) of the control gate electrode CG is a, and the upper end of the control gate electrode CG is When the length of the bird's beak formed in the gate length direction of the control gate electrode CG from the part is b, the bird's beak BV is formed so that the relationship b> a is established. Thereby, the length of the bird's beak BV becomes sufficiently long, and the combined length of the laminated insulating film and the bird's beak BV becomes longer. As a result, the distance between the upper end of the control gate electrode CG and the upper end of the memory gate electrode MG becomes longer, the electric field strength between the control gate electrode CG and the memory gate electrode MG is relaxed, and the leakage current is reduced. In other words, under the condition that the length b of the bird's beak BV is smaller than the film thickness a of the first potential barrier film EB1, it cannot be said that the length of the bird's beak BV is sufficiently long, and the control gate electrode CG It can be said that the electric field relaxation between the memory gate electrode MG and the memory gate electrode MG cannot be sufficiently achieved. It should be noted that the film thickness a at the middle end portion (or lower end portion) of the first potential barrier film EB1 constituting a part of the laminated insulating film is formed to satisfy the relationship of 2 nm ≦ a ≦ 5 nm, for example. . Here, the film thickness a at the middle end (or lower end) of the first potential barrier film EB1 is the first potential at a position closer to the bottom surface of the control gate electrode CG than the surface of the control gate electrode CG. It refers to the thickness of the barrier film EB1.

  Further, the length b of the bird's beak BV is such that b ≧ d / 2, where d is the thickness of the laminated insulating film formed at a position in contact with the middle end (or lower end) of the control gate electrode CG. The relationship is also satisfied. As a result, the distance between the upper end portion of the control gate electrode CG and the upper end portion of the memory gate electrode MG is 3/2 times or more the film thickness d of the stacked insulating film. For this reason, the electric field strength generated between the upper end portion of the control gate electrode CG and the upper end portion of the memory gate electrode MG is 2/3 or less compared to the case where the bird's beak BV is not formed. Therefore, the electric field strength between the control gate electrode CG and the memory gate electrode MG is sufficiently relaxed, and the leakage current can be reduced.

  From the above, it can be said that the length b of the bird's beak BV is 5 nm or more. From the viewpoint of increasing the influence of electric field relaxation, it is desirable to increase the length b of the bird's beak BV. However, the length b of the bird's beak BV is b <L / 2 when the gate length of the control gate electrode CG is L. Considering that the bird's beak BV is formed at the upper ends on both sides of the control gate electrode CG, when the length b of the bird's beak BV exceeds L / 2, the bird's beak BV is formed on the entire surface of the control gate electrode CG. Because it will be. That is, when the length b of the bird's beak BV exceeds L / 2, the cobalt silicide film CS is not formed on the surface of the control gate electrode CG, and the resistance of the control gate electrode CG cannot be reduced. It is. Therefore, from the viewpoint of reducing the electric field strength between the upper end of the control gate electrode CG and the upper end of the memory gate electrode MG and reducing the resistance of the control gate electrode CG, the length of the bird's beak BV b needs to satisfy the relationship of 5 nm ≦ b <L / 2.

  Further, it is more desirable that the length b of the bird's beak BV is as long as possible in the lateral direction. That is, it is more desirable that the length b of the bird's beak BV is larger than the thickness of the bird's beak BV.

  The split gate nonvolatile memory cell according to the first embodiment is characterized in that a bird's beak BV made of an insulating film is formed at the upper end of the control gate electrode. With this feature, in the first embodiment, the distance between the upper end portion of the control gate electrode CG and the upper end portion of the memory gate electrode MG can be substantially separated, and the upper end portion of the control gate electrode CG and the memory gate electrode MG are separated. The electric field strength at the upper end portion of the laminated insulating film interposed between the upper end portions of the memory cell can be reduced, and the leakage current between the control gate electrode CG and the memory gate electrode MG can be reduced.

  Further, in the first embodiment, by providing the bird's beak BV at the upper end portion of the control gate electrode CG, there is an effect different from the relaxation of the electric field strength. This another effect will be described. In the split gate type nonvolatile memory cell, miniaturization can be realized by forming the sidewall-shaped memory gate electrode MG on the side wall of the control gate electrode CG. However, with miniaturization, the distance between the control gate electrode CG and the memory gate electrode MG becomes closer. The control gate electrode CG and the memory gate electrode MG are formed of a polysilicon film, and in order to reduce resistance, a cobalt silicide film is formed on the surface of the control gate electrode CG and the surface of the memory gate electrode MG. CS is formed. In this case, since the surface of the control gate electrode CG and the surface of the memory gate electrode MG are separated from each other only by the stacked insulating film, the surface is formed on the cobalt silicide film CS formed on the control gate electrode CG and the memory gate electrode MG. The cobalt silicide film CS to be contacted may cause a short circuit between the control gate electrode CG and the memory gate electrode MG.

  As in the first embodiment, by forming a bird's beak BV on the upper end of the control gate electrode CG, the cobalt silicide film CS formed on the surface of the control gate electrode CG and the surface of the memory gate electrode MG are formed. The distance from the cobalt silicide film CS can be increased. For this reason, a short circuit failure between the control gate electrode CG and the memory gate electrode MG can be prevented. As described above, in the first embodiment, the bird's beak BV is formed at the upper end portion of the control gate electrode CG, thereby increasing the distance between the upper end portion of the control gate electrode CG and the upper end portion of the memory gate electrode MG. be able to. As a result, the first effect of reducing the electric field strength of the laminated insulating film interposed between the upper end portion of the control gate electrode CG and the upper end portion of the memory gate electrode MG, and the surface of the control gate electrode CG are formed. It is possible to obtain a second effect that can prevent a short circuit failure caused by contact between the cobalt silicide film CS and the cobalt silicide film CS formed on the surface of the memory gate electrode MG.

  The semiconductor device according to the first embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings. 4 to 15 are cross-sectional views illustrating the manufacturing process of the semiconductor device according to the first embodiment. In FIGS. 4 to 15, the memory cell formation region MCR is shown in the left region, and the peripheral region is in the right region. A circuit formation region PER is shown.

  First, as shown in FIG. 4, a semiconductor substrate 1S made of a silicon single crystal into which a p-type impurity such as boron (boron) is introduced is prepared. At this time, the semiconductor substrate 1S is in a state of a substantially wafer-shaped semiconductor wafer. Then, an element isolation region STI is formed in the peripheral circuit formation region PER of the semiconductor substrate 1S. The element isolation region STI is provided to prevent the elements from interfering with each other. The element isolation region STI can be formed using, for example, a LOCOS (local Oxidation of silicon) method or an STI (shallow trench isolation) method. For example, in the STI method, the element isolation region STI is formed as follows. That is, the element isolation trench is formed in the semiconductor substrate 1S by using the photolithography technique and the etching technique. Then, a silicon oxide film is formed on the semiconductor substrate 1S so as to fill the element isolation trench, and then unnecessary silicon oxide formed on the semiconductor substrate 1S by chemical mechanical polishing (CMP). Remove the membrane. As a result, the element isolation region STI in which the silicon oxide film is embedded only in the element isolation trench can be formed.

  Subsequently, impurities are introduced into the semiconductor substrate 1S in the memory cell formation region MCR to form a well isolation layer NISO. The well isolation layer NISO is formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 1S. Then, by introducing impurities into the semiconductor substrate 1S, the p-type well PWL1 is formed in the memory cell formation region MCR, and the p-type well PWL2 and the n-type well NWL1 are formed in the peripheral circuit formation region PER. The p-type wells PWL1 and PWL2 are formed, for example, by introducing a p-type impurity such as boron (boron) into the semiconductor substrate 1S by an ion implantation method. On the other hand, the n-type well NWL1 is formed, for example, by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 1S by an ion implantation method.

Next, as shown in FIG. 5, a gate insulating film GOX is formed on the semiconductor substrate 1S. The gate insulating film GOX is formed of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. However, the gate insulating film GOX is not limited to the silicon oxide film and can be variously changed. For example, the gate insulating film GOX may be a silicon oxynitride film (SiON). That is, a structure in which nitrogen is segregated at the interface between the gate insulating film GOX and the semiconductor substrate 1S may be employed. The silicon oxynitride film has a higher effect of suppressing generation of interface states in the film and reducing electron traps than the silicon oxide film. Therefore, the hot carrier resistance of the gate insulating film GOX can be improved, and the insulation resistance can be improved. In addition, the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film. For this reason, by using a silicon oxynitride film as the gate insulating film GOX, it is possible to suppress a variation in threshold voltage due to diffusion of impurities in the gate electrode toward the semiconductor substrate 1S. For example, the silicon oxynitride film may be formed by heat-treating the semiconductor substrate 1S in an atmosphere containing nitrogen such as NO, NO _2, or NH ₃ . Further, after forming a gate insulating film GOX made of a silicon oxide film on the surface of the semiconductor substrate 1S, the semiconductor substrate 1S is heat-treated in an atmosphere containing nitrogen, and nitrogen is segregated at the interface between the gate insulating film GOX and the semiconductor substrate 1S. The same effect can be obtained also by making it.

  Further, the gate insulating film GOX may be formed of a high dielectric constant film having a dielectric constant higher than that of a silicon oxide film, for example. Conventionally, a silicon oxide film has been used as the gate insulating film GOX from the viewpoint of high insulation resistance and excellent electrical and physical stability at the silicon-silicon oxide interface. However, with the miniaturization of elements, the thickness of the gate insulating film GOX is required to be extremely thin. When such a thin silicon oxide film is used as the gate insulating film GOX, a so-called tunnel current is generated in which electrons flowing through the channel of the MISFET tunnel through the barrier formed by the silicon oxide film and flow to the gate electrode.

  Therefore, by using a material having a dielectric constant higher than that of the silicon oxide film, a high dielectric constant film capable of increasing the physical film thickness even when the capacitance is the same has been used. According to the high dielectric constant film, since the physical film thickness can be increased even if the capacitance is the same, the leakage current can be reduced. In particular, the silicon nitride film is also a film having a higher dielectric constant than the silicon oxide film, but in the first embodiment, it is desirable to use a high dielectric constant film having a higher dielectric constant than the silicon nitride film.

For example, a hafnium oxide film (HfO ₂ film), which is one of hafnium oxides, is used as a high dielectric constant film having a dielectric constant higher than that of a silicon nitride film, but instead of the hafnium oxide film, an HfAlO film (hafnium film) is used. Other hafnium-based insulating films such as aluminate film), HfON film (hafnium oxynitride film), HfSiO film (hafnium silicate film), and HfSiON film (hafnium silicon oxynitride film) can also be used. Further, a hafnium-based insulating film in which an oxide such as tantalum oxide, niobium oxide, titanium oxide, zirconium oxide, lanthanum oxide, or yttrium oxide is introduced into these hafnium-based insulating films can also be used. Since the hafnium-based insulating film has a dielectric constant higher than that of the silicon oxide film or the silicon oxynitride film, like the hafnium oxide film, the same effect as that obtained when the hafnium oxide film is used can be obtained.

  Next, a polysilicon film PF1 is formed on the gate insulating film GOX. The polysilicon film PF1 can be formed using, for example, a CVD method. Thereafter, n-type impurities such as phosphorus and arsenic are introduced into the polysilicon film PF1 in the memory cell formation region by using a photolithography technique and an ion implantation method.

  Subsequently, as shown in FIG. 6, a silicon nitride film SIN is formed on the polysilicon film PF1, and a silicon oxide film OX1 is formed on the silicon nitride film SIN. The silicon nitride film SIN and the silicon oxide film OX1 can be formed by using, for example, a CVD (Chemical Vapor Deposition) method.

  Then, as shown in FIG. 7, the silicon oxide film OX1 and the silicon nitride film SIN are patterned by using a photolithography technique and an etching technique. In the patterning of the silicon oxide film OX1 and the silicon nitride film SIN, the silicon oxide film OX1 and the silicon nitride film SIN remain on the control gate electrode formation region in the memory cell formation region, and the silicon oxide film OX1 and the silicon nitride film in other regions. SIN is performed to be removed. On the other hand, in the peripheral circuit formation region PER, the silicon oxide film OX1 and the silicon nitride film SIN are left on the entire surface.

  Next, as shown in FIG. 8, the surface of the polysilicon film PF1 formed on the semiconductor substrate 1S is oxidized. Specifically, in the memory cell formation region MCR, the silicon oxide film OX2 is formed on the surface of the polysilicon film PF1 exposed from the silicon oxide film OX1 and the silicon nitride film SIN. At this time, by performing sufficient thermal oxidation treatment, the bird's beak BV is formed so as to bite into the polysilicon film PF1 formed under the silicon nitride film SIN covering the control gate electrode formation region. In the first embodiment, since sufficient thermal oxidation treatment can be performed without considering the amount of heat treatment, a bird's beak BV that sufficiently penetrates into the lower layer of the silicon nitride film can be formed. That is, in the first embodiment, since the bird's beak BV is formed before the semiconductor element (memory cell or MISFET) is formed, sufficient heat treatment is applied without considering the influence on the semiconductor element. Can do. As a result, a sufficiently large bird's beak BV can be formed.

  On the other hand, for example, in the technique described in the background art (Patent Document 1), after forming a semiconductor element (memory cell), heat treatment is performed to form a bird's beak. That is, the heat treatment is performed after the source region and the drain region of the memory cell are formed. The source region and the drain region are semiconductor regions into which impurities are introduced. When heat treatment is performed after the source region or drain region is formed, the profile of the impurities introduced into the semiconductor region changes, and the electrical characteristics of the semiconductor element Fluctuations and deterioration occur. For this reason, in the heat treatment performed after the semiconductor element is formed, the heat load is limited, and it is difficult to form a sufficient bird's beak.

  On the other hand, in the first embodiment, the heat treatment is performed before the formation of the source region and the drain region of the semiconductor element, and further before the formation of the control gate electrode and the memory gate electrode. Therefore, it is possible to perform a heat treatment with a sufficient heat load without taking into consideration fluctuations and deteriorations in the electrical characteristics of the semiconductor element (memory cell). From this, in this Embodiment 1, since the amount of heat treatment can be adjusted freely, an effective bird's beak BV having a sufficient size can be formed. That is, the feature of the manufacturing technique of the semiconductor device according to the first embodiment is that the bird's beak BV is formed by a heat treatment performed at a stage before forming a semiconductor element.

  Subsequently, as shown in FIG. 9, after the silicon oxide film OX2 formed on the surface of the polysilicon film PF1 is removed by, for example, anisotropic etching, the patterned silicon oxide film OX1 and silicon nitride film SIN are masked. As a result, the polysilicon film PF1 is processed. Thereby, the control gate electrode CG made of the polysilicon film PF1 can be formed in the memory cell formation region MCR. A bird's beak BV is formed at the upper end of the control gate electrode CG.

  Next, as shown in FIG. 10, the patterned silicon oxide film OX1 is removed. Then, as shown in FIG. 11, a silicon oxide film OX3 is formed on the entire surface of the semiconductor substrate 1S as an insulating film to be a potential barrier film EB1 described later, and an insulating film to be a charge storage film EC described later is formed on the silicon oxide film OX3. A silicon nitride film SIN2 is formed as a film. Thereafter, a silicon oxide film OX4 is formed on the silicon nitride film SIN2 as an insulating film to be a potential barrier film EB2 to be described later, and a polysilicon film PF2 is formed on the silicon oxide film OX4. For example, the silicon oxide film OX3 can be formed using a thermal oxidation method or an ISSG oxidation method, and the silicon nitride film SIN2 can be formed using a CVD method. Further, the silicon oxide film OX4 can be formed using an ISSG oxidation method or a CVD method. Further, the polysilicon film PF2 can be formed by using, for example, a CVD method.

  Here, since the silicon oxide film OX3 is formed with the silicon nitride film SIN formed on the control gate electrode CG, the shape of the bird's beak BV formed on the upper end of the control gate electrode CG is deteriorated. The silicon oxide film OX3 can be formed. That is, the silicon nitride film SIN formed on the control gate electrode CG has a function of protecting the shape of the bird's beak BV formed in the lower layer. For example, when the silicon oxide film OX3 is formed without forming the silicon nitride film SIN on the control gate electrode CG, the upper end portion (corner portion) of the control gate electrode CG is easily oxidized, so that the oxidation process proceeds and the control is performed. The upper end portion of the gate electrode CG becomes round. The fact that the upper end portion of the control gate electrode CG has a round shape means that the shape of the bird's beak BV formed on the upper end portion is deteriorated, and the usefulness of forming the bird's beak BV is lowered. Therefore, in the first embodiment, the silicon oxide film OX3 is formed with the silicon nitride film SIN formed on the control gate electrode CG. From the above, the silicon nitride film SIN is used for the purpose of protecting the shape of the bird's beak BV formed in the lower layer.

  In the first embodiment, as shown in FIG. 6, a laminated film of a silicon nitride film SIN and a silicon oxide film OX1 is used to process the polysilicon film PF1. Among these, as described above, the silicon nitride film SIN is formed for the purpose of protecting the shape of the bird's beak BV formed in the polysilicon film PF1 from the subsequent oxidation process. Therefore, it is considered that only the silicon nitride film SIN needs to be used without using the laminated film of the silicon nitride film SIN and the silicon oxide film OX1 as a hard mask for processing the polysilicon film PF1. However, in the first embodiment, a laminated film of the silicon nitride film SIN and the silicon oxide film OX1 is used as a hard mask for processing the polysilicon film PF1. This is due to the following reason.

  That is, it is difficult to use only the silicon nitride film SIN as a hard mask for processing the polysilicon film PF1. This is because the polysilicon film PF1 and the silicon nitride film SIN cannot have an etching selectivity, and the silicon nitride film SIN cannot be used as a hard mask for processing the polysilicon film PF1. For this reason, the silicon oxide film OX1 is formed on the silicon nitride film SIN. That is, since the silicon oxide film OX1 has a high etching selectivity with respect to the polysilicon film PF1, it can be sufficiently used as a hard mask. From the above, the silicon nitride film SIN and the silicon oxide film OX1 formed on the polysilicon film PF1 have different functions. Specifically, after forming the bird's beak BV, the silicon nitride film SIN has a function of protecting the shape of the bird's beak BV in the subsequent oxidation step (step of forming the silicon oxide film OX3), while the silicon oxide film OX1 Therefore, it has a function as a hard mask when the polysilicon film PF1 is processed into the control gate electrode CG.

  Subsequently, the polysilicon film PF2 formed on the semiconductor substrate 1S is processed by using anisotropic etching. As a result, the sidewall-shaped polysilicon film PF2 remains on the sidewalls on both sides of the control gate electrode CG.

  Thereafter, as shown in FIG. 12, the sidewall-shaped polysilicon film PF2 formed on one side of the control gate electrode CG is removed in the memory cell formation region MCR by using a photolithography technique and an etching technique. . As a result, the sidewall-shaped polysilicon film PF2 remains only on one side wall of the control gate electrode CG. Further, the silicon nitride film SIN formed to protect the shape of the bird's beak BV by etching the laminated insulating film (silicon oxide film OX3, silicon nitride film SIN2, silicon oxide film OX4) and silicon nitride film SIN. Then, the memory gate electrode MG having a side wall shape can be formed on the side wall on one side of the control gate electrode CG via a laminated insulating film. At this time, the laminated insulating film includes the silicon oxide film OX3, the silicon nitride film SIN2, and the silicon oxide film OX4. For example, the silicon oxide film OX3 serves as the potential barrier film EB1, and the silicon nitride film SIN2 serves as the charge storage film EC. . Further, the silicon oxide film OX4 becomes the potential barrier film EB2.

  Thereafter, an n-type impurity such as phosphorus or arsenic and a p-type impurity such as boron (boron) are introduced into the polysilicon film PF1 in the peripheral circuit formation region PER by using a photolithography technique and an ion implantation method.

  Next, as shown in FIG. 13, the polysilicon film PF1 formed in the peripheral circuit formation region PER is processed by using a photolithography technique and an etching technique. Thereby, the gate electrode G1 and the gate electrode G2 made of the polysilicon film PF1 can be formed in the peripheral circuit formation region PER.

  Subsequently, as shown in FIG. 14, by using a photolithography technique and an ion implantation method, in the memory cell formation region MCR, a shallow low-concentration impurity diffusion region EX1 aligned with the control gate electrode CG and the memory gate electrode MG is formed. Form. The shallow low-concentration impurity diffusion region EX1 is an n-type semiconductor region into which an n-type impurity such as phosphorus or arsenic is introduced. On the other hand, in the peripheral circuit formation region PER, a shallow low concentration impurity diffusion region EX2 aligned with the gate electrode G1 is formed. This shallow low-concentration impurity diffusion region EX2 is also an n-type semiconductor region into which an n-type impurity is introduced. Similarly, in the peripheral circuit formation region PER, a shallow low-concentration impurity diffusion region EX3 aligned with the gate electrode G2 is also formed. This shallow low-concentration impurity diffusion region EX3 is a p-type semiconductor region into which p-type impurities are introduced.

  Thereafter, as shown in FIG. 15, a silicon oxide film is formed on the semiconductor substrate 1S. The silicon oxide film can be formed using, for example, a CVD method. Then, the sidewall SW is formed by anisotropically etching the silicon oxide film. In memory cell formation region MCR, sidewalls SW are formed on the sidewalls of control gate electrode CG and memory gate electrode MG. Similarly, in the peripheral circuit formation region PER, sidewalls SW are formed on the sidewalls on both sides of the gate electrode G1 and the gate electrode G2. These sidewalls SW are formed from a single layer film of a silicon oxide film. However, the present invention is not limited to this, and for example, a sidewall SW composed of a laminated film of a silicon nitride film and a silicon oxide film may be formed. .

  Subsequently, a deep high-concentration impurity diffusion region NR1 aligned with the sidewall SW is formed in the memory cell formation region MCR by using a photolithography technique and an ion implantation method. The deep high-concentration impurity diffusion region NR1 is an n-type semiconductor region into which an n-type impurity such as phosphorus or arsenic is introduced. The deep high concentration impurity diffusion region NR1 and the shallow low concentration impurity diffusion region EX1 form a source region or a drain region of the memory cell. By forming the source region and the drain region with the shallow low-concentration impurity diffusion region EX1 and the deep high-concentration impurity diffusion region NR1 in this way, the source region and the drain region can have an LDD (Lightly Doped Drain) structure.

  On the other hand, a deep high-concentration impurity diffusion region NR2 aligned with the sidewall SW is formed in the peripheral circuit formation region PER. The deep high-concentration impurity diffusion region NR2 is an n-type semiconductor region into which an n-type impurity such as phosphorus or arsenic is introduced. The deep high-concentration impurity diffusion region NR2 and the shallow low-concentration impurity diffusion region EX2 form the source region or drain region of the n-channel MISFET. By forming the source region and the drain region with the shallow low-concentration impurity diffusion region EX2 and the deep high-concentration impurity diffusion region NR2, the source region and the drain region can have an LDD (Lightly Doped Drain) structure.

  Similarly, in the peripheral circuit formation region PER, a deep high concentration impurity diffusion region PR1 is formed in alignment with the sidewall SW formed on the sidewall of the gate electrode G2. The deep high-concentration impurity diffusion region PR1 is a p-type semiconductor region into which a p-type impurity such as boron (boron) is introduced. The deep high-concentration impurity diffusion region PR1 and the shallow low-concentration impurity diffusion region EX3 form the source region or drain region of the p-channel type MISFET. By forming the source region and the drain region with the shallow low-concentration impurity diffusion region EX3 and the deep high-concentration impurity diffusion region PR1, the source region and the drain region can have an LDD (Lightly Doped Drain) structure. Further, the deep high-concentration impurity diffusion region NR2 in the peripheral circuit formation region PER can be formed simultaneously with the deep high-concentration impurity diffusion region NR1 in the memory cell formation region MCR.

  Here, in the memory cell formation region MCR, a shallow low-concentration impurity diffusion region EX1 and a deep high-concentration impurity diffusion region NR1 are formed by introducing n-type impurities such as phosphorus and arsenic into the semiconductor substrate 1S. At this time, n-type impurities such as phosphorus and arsenic are also introduced into the upper end portion of the control gate electrode CG, the upper end portion of the memory gate electrode MG, and the upper end portion of the stacked insulating film. In particular, when an n-type impurity is introduced into the upper end portion of the laminated insulating film composed of the insulating film, a phenomenon that the insulation resistance of the laminated insulating film is deteriorated occurs. Then, the leakage current flowing between the upper end portion of the control gate electrode CG insulated by the laminated insulating film and the upper end portion of the memory gate electrode MG increases. However, since the bird's beak BV is formed at the upper end of the control gate electrode CG in the first embodiment, the substantial distance between the upper end of the control gate electrode CG and the upper end of the memory gate electrode MG is increased. Can do. This means that the electric field strength can be relaxed in the laminated insulating film existing between the control gate electrode CG and the memory gate electrode MG. Therefore, even if an n-type impurity is introduced into the upper end portion of the laminated insulating film and the insulation resistance of the laminated insulating film is deteriorated, the electric field strength generated in the laminated insulating film can be reduced by forming the bird's beak BV. As a result, the leakage current flowing between the control gate electrode CG and the memory gate electrode MG can be reduced.

  Thus, after forming the deep high-concentration impurity diffusion regions NR1, NR2, and PR1, heat treatment at about 1000 ° C. is performed. Thereby, the introduced impurities are activated.

  Next, after forming a cobalt film on the semiconductor substrate 1S, heat treatment is performed to thereby form the control gate electrode CG, the polysilicon films PF1 and PF2 constituting the memory gate electrode MG, and the cobalt film in the memory cell formation region MCR. To form a cobalt silicide film CS. Thereby, the control gate electrode CG and the memory gate electrode MG have a laminated structure of the polysilicon films PF1 and PF2 and the cobalt silicide film CS, respectively. Similarly, on the surface of the high-concentration impurity diffusion region NR1, silicon and the cobalt film react to form a cobalt silicide film CS.

  On the other hand, also in the peripheral circuit formation region PER, the cobalt silicide film CS is formed on the surface of the polysilicon film PF1 constituting the gate electrodes G1 and G2. Thus, the gate electrodes G1 and G2 are composed of the polysilicon film PF1 and the cobalt silicide film CS. Similarly, the silicon silicide film reacts with the surface of the deep high-concentration impurity diffusion regions NR2 and PR1 to form the cobalt silicide film CS. In the first embodiment, the cobalt silicide film CS is formed. For example, instead of the cobalt silicide film CS, a nickel silicide film, a titanium silicide film, or a platinum silicide film is formed. Also good.

  At this time, in the first embodiment, since the bird's beak BV is formed at the upper end portion of the control gate electrode CG, the upper end portion of the control gate electrode CG sandwiching the laminated insulating film and the upper end portion of the memory gate electrode MG are arranged. The distance between can be separated. This means that the distance between the cobalt silicide film CS formed on the surface of the control gate electrode CG and the cobalt silicide film CS formed on the surface of the memory gate electrode MG can be increased. Therefore, even when the memory cell is miniaturized, the cobalt silicide film CS formed on the surface of the control gate electrode CG contacts the cobalt silicide film CS formed on the surface of the memory gate electrode MG. It is possible to suppress short circuit defects.

  As described above, a plurality of memory cells can be formed in the memory cell formation region MCR of the semiconductor substrate 1S, and a plurality of n-channel MISFETs and p-channel MISFETs can be formed in the peripheral circuit formation region PER.

  Next, the wiring process will be described with reference to FIG. As shown in FIG. 2, an interlayer insulating film IL1 is formed on the main surface of the semiconductor substrate 1S. This interlayer insulating film IL1 is formed of, for example, a silicon nitride film and a silicon oxide film. Thereafter, the surface of the interlayer insulating film IL1 is planarized using, for example, a CMP (Chemical Mechanical Polishing) method.

  Subsequently, contact holes CNT are formed in the interlayer insulating film IL1 using a photolithography technique and an etching technique. For example, contact holes CNT are formed in the memory cell formation region MCR and the peripheral circuit formation region PER.

  Thereafter, a titanium / titanium nitride film is formed on the interlayer insulating film including the bottom surface and inner wall of the contact hole CNT. The titanium / titanium nitride film is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. This titanium / titanium nitride film has a so-called barrier property that prevents, for example, tungsten, which is a material of a film to be embedded in a later process, from diffusing into silicon.

  Then, a tungsten film is formed on the entire main surface of the semiconductor substrate 1S so as to fill the contact holes CNT. This tungsten film can be formed using, for example, a CVD method. Then, the plug PLG1 can be formed by removing the unnecessary titanium / titanium nitride film and tungsten film formed on the interlayer insulating film IL1 by, for example, the CMP method.

  Next, as shown in FIG. 2, an interlayer insulating film IL2 is formed on the interlayer insulating film IL1 on which the plug PLG1 is formed. Then, a trench is formed in the interlayer insulating film IL2 by using a photolithography technique and an etching technique. Thereafter, a tantalum / tantalum nitride film is formed on the interlayer insulating film IL2 including the inside of the trench. This tantalum / tantalum nitride film can be formed by sputtering, for example. Subsequently, after a seed film made of a thin copper film is formed on the tantalum / tantalum nitride film by, for example, a sputtering method, an electrolytic plating method using this seed film as an electrode is formed on the interlayer insulating film IL2 in which the groove is formed. A copper film is formed. Thereafter, the copper film exposed on the interlayer insulating film IL2 other than the inside of the trench is removed by polishing, for example, by CMP, thereby leaving the copper film only in the trench formed in the interlayer insulating film IL2. . Thereby, the wiring L1 can be formed. Furthermore, although wiring is formed in the upper layer of wiring L1, description here is abbreviate | omitted. In this manner, the semiconductor device according to the first embodiment can be finally formed.

  In the first embodiment, the example of forming the wiring L1 made of a copper film has been described. However, for example, the wiring L1 made of an aluminum film may be formed. In this case, a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film are sequentially formed on the interlayer insulating film IL1 and the plug PLG1. These films can be formed by using, for example, a sputtering method. Subsequently, these films are patterned by using a photolithography technique and an etching technique to form the wiring L1. Thereby, the wiring L1 made of an aluminum film can be formed.

  In the first embodiment, as shown in FIG. 2, the nonvolatile memory cell in which the memory gate electrode MG is formed on the side wall on one side of the control gate electrode CG has been described. For example, as shown in FIG. The technical idea of the present invention can also be applied to a nonvolatile memory cell in which the memory gate electrode MG is formed on the side walls on both sides of the electrode CG.

  Specifically, FIG. 16 is a cross-sectional view showing the structure of a nonvolatile memory cell in a modification of the first embodiment. In FIG. 16, the structure of the non-volatile memory cell in the modification is almost the same as that of the non-volatile memory cell in the first embodiment shown in FIGS. The difference is that in the modification, memory gate electrodes MG1 and MG2 are formed on the side walls on both sides of the control gate electrode CG. For example, a sidewall-shaped memory gate electrode MG1 is formed on the right side wall of the control gate electrode CG, and a stacked insulating film is formed between the control gate electrode CG and the memory gate electrode MG1. This laminated insulating film is composed of a first potential barrier film EB1 (A), a charge storage film EC (A), and a second potential barrier film EB2 (A). At this time, since the bird's beak BV is formed at the upper right end of the control gate electrode CG, the distance between the control gate electrode CG and the memory gate electrode MG1 can be increased. As a result, the leakage current generated between the control gate electrode CG and the memory gate electrode MG1 can be reduced, and the cobalt silicide film CS formed on the surface of the control gate electrode CG and the surface of the memory gate electrode MG1 It is possible to suppress short-circuit defects with the cobalt silicide film CS formed on the substrate.

  Similarly, a sidewall-shaped memory gate electrode MG2 is formed on the left side wall of the control gate electrode CG, and a stacked insulating film is formed between the control gate electrode CG and the memory gate electrode MG2. This laminated insulating film is composed of a first potential barrier film EB1 (B), a charge storage film EC (B), and a second potential barrier film EB2 (B). At this time, since the bird's beak BV is also formed at the upper left end of the control gate electrode CG, the distance between the control gate electrode CG and the memory gate electrode MG2 can be increased. As a result, leakage current generated between the control gate electrode CG and the memory gate electrode MG2 can be reduced, and the cobalt silicide film CS formed on the surface of the control gate electrode CG and the surface of the memory gate electrode MG2 It is possible to suppress short-circuit defects with the cobalt silicide film CS formed on the substrate.

(Embodiment 2)
In the second embodiment, a method for manufacturing a semiconductor device capable of forming a bird's beak larger than that in the first embodiment will be described with reference to the drawings.

  In the manufacturing method of the semiconductor device in the second embodiment, the steps shown in FIGS. 4 to 6 are the same as those in the first embodiment. Subsequently, as shown in FIG. 17, the silicon oxide film OX1 formed on the semiconductor substrate 1S is patterned. That is, the silicon oxide film OX1 is processed by using a photolithography technique and an etching technique. Specifically, in the memory cell formation region MCR, the silicon oxide film OX1 is left so as to cover the control gate electrode formation region, and the silicon oxide film OX1 formed in other regions is removed. On the other hand, in the peripheral circuit formation region PER, the silicon oxide film OX1 is left on the entire surface.

  Next, as shown in FIG. 18, the silicon nitride film SIN formed in the lower layer is processed using the patterned silicon oxide film OX1 as a mask. Specifically, the silicon nitride film SIN is processed by wet etching with hot phosphoric acid. Since the wet etching with hot phosphoric acid is an isotropic etching, not only the exposed silicon nitride film SIN is removed, but also formed in the lower layer of the silicon oxide film OX1 as shown in FIG. The silicon nitride film SIN is also etched so as to go around. That is, the silicon nitride film SIN is removed so as to bite into the lower layer of the silicon oxide film OX1 formed in the control gate electrode formation region. As a result, the size of the silicon nitride film SIN formed below the silicon oxide film OX1 is smaller than the size of the silicon oxide film OX1.

  Subsequently, as shown in FIG. 19, the exposed surface of the polysilicon film PF1 is oxidized. Specifically, a silicon oxide film OX2 is formed on the exposed surface of the polysilicon film PF1 by performing a thermal oxidation process on the semiconductor substrate 1S. At this time, the bird's beak BV is formed so as to bite into the polysilicon film PF1 formed under the silicon oxide film OX1 serving as a mask. In particular, in the second embodiment, since the size of the silicon nitride film SIN is smaller than the size of the silicon oxide film OX1, the bird's beak BV is sufficiently formed. That is, the width of the bird's beak BV formed in the second embodiment is larger than the width of the bird's beak BV formed in the first embodiment. In the second embodiment, since the silicon nitride film SIN is etched by isotropic etching, the size of the silicon nitride film SIN is smaller than the size of the silicon oxide film OX1, so that the silicon nitride film SIN is formed below the silicon oxide film OX1. The exposed region of the polysilicon film PF1 becomes larger. As a result, the width of the bird's beak BV formed so as to wrap around the lower layer of the silicon oxide film OX1 (in the gate length direction of the control gate electrode) is increased.

  Then, as shown in FIG. 20, the control gate electrode CG is formed in the memory cell formation region MCR by processing the polysilicon film PF1 using the silicon oxide film OX1 as a hard mask. A bird's beak BV having a width larger than that of the first embodiment is formed at the upper end of the control gate electrode CG.

  Subsequent steps are the same as those in the first embodiment. In this way, the semiconductor device according to the second embodiment can be manufactured. In the second embodiment, as described above, the width (size) of the bird's beak BV formed at the upper end of the control gate electrode CG can be made sufficiently large, so that the control gate electrode CG and the memory gate electrode MG Can be separated from each other. As a result, the leakage current generated between the upper end portion of the control gate electrode CG and the upper end portion of the memory gate electrode MG across the stacked insulating film can be reduced, and the leakage current generated on the surface of the control gate electrode CG is formed. Short-circuit defects between the cobalt silicide film CS and the cobalt silicide film CS formed on the surface of the memory gate electrode MG can be suppressed.

(Embodiment 3)
In the first embodiment, the example in which the bird's beak BV is formed on the upper end portions on both sides of the control gate electrode CG has been described. In the third embodiment, the bird's beak BV is formed only on the upper end portion on one side of the control gate electrode CG. An example will be described.

  FIG. 21 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment. The configuration of the semiconductor device illustrated in FIG. 21 is substantially the same as the configuration of the semiconductor device illustrated in FIG. Below, it explains including a different point. In FIG. 21, a feature of the nonvolatile memory cell formed in the memory cell formation region MCR is that a bird's beak BV is formed only at the upper end portion on one side of the control gate electrode CG1. Specifically, although two adjacent nonvolatile memory cells are illustrated in the memory cell formation region MCR of FIG. 21, a description will be given by taking the nonvolatile memory cell on the right as an example. First, the memory gate electrode MG1 is formed on the right side wall of the control gate electrode CG1, and a laminated insulating film is formed between the control gate electrode CG1 and the memory gate electrode MG1. This laminated insulating film is composed of a first potential barrier film EB1 (A), a charge storage film EC (A), and a second potential barrier film EB2 (A). At this time, the bird's beak BV is formed at the upper right end portion where the memory gate electrode MG1 is formed among the upper end portions on both sides of the control gate electrode CG1. As a result, the distance between the upper end portion of the control gate electrode CG1 and the upper end portion of the memory gate electrode MG1 across the stacked insulating film can be increased. As a result, the leakage current generated between the control gate electrode CG1 and the memory gate electrode MG1 can be reduced, and the cobalt silicide film CS formed on the surface of the control gate electrode CG1 and the surface of the memory gate electrode MG1. It is possible to suppress short-circuit defects with the cobalt silicide film CS formed on the substrate.

  On the other hand, in the third embodiment, the bird's beak BV is not formed at the left upper end portion where the memory gate electrode MG1 is not formed among the upper end portions on both sides of the control gate electrode CG1. This is because the memory gate electrode MG1 is not formed on the left side wall of the control gate electrode CG1, and therefore it is not necessary to form the bird's beak BV in order to increase the distance between the control gate electrode CG1 and the memory gate electrode MG1. . That is, in the third embodiment, the bird's beak BV is formed only in the minimum necessary area. The reason is shown below.

  For example, in FIG. 21, when the bird's beak BV is formed at the upper ends on both sides of the control gate electrode CG1, the region where the cobalt silicide film CS is formed on the surface of the control gate electrode CG1 is reduced. As a result, the resistance of the control gate electrode CG1 cannot be reduced. That is, the formation of the bird's beak BV at the upper end of the control gate electrode CG1 means that the area where the cobalt silicide film CS is formed is reduced. Therefore, from the viewpoint of reducing the resistance of the control gate electrode CG1 by forming a sufficient cobalt silicide film CS on the surface of the control gate electrode CG1, it is desirable to reduce the region where the bird's beak BV is formed as much as possible. Therefore, in the third embodiment, the bird's beak BV is formed only in the minimum necessary region, and the cobalt silicide film CS is formed in the other region, thereby providing a gap between the control gate electrode CG1 and the memory gate electrode MG1. Therefore, the resistance of the control gate electrode CG1 is reduced while the electric field intensity of the control gate electrode CG1 is relaxed.

  The above has described the nonvolatile memory cell formed on the right side of the two nonvolatile memory cells shown in FIG. 21, but the same applies to the nonvolatile memory cell formed on the left side.

  The semiconductor device according to the third embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  4 to 6 are the same as those in the first embodiment. Subsequently, as shown in FIG. 22, the silicon oxide film OX1 and the silicon nitride film SIN are patterned by using a photolithography technique and an etching technique. Specifically, in the peripheral circuit formation region PER, the entire surface of the silicon oxide film OX1 and the silicon nitride film SIN is covered. On the other hand, in the memory cell formation region MCR, the silicon oxide film OX1 and the silicon nitride film SIN remain in the region covering the two adjacent control gate electrode formation regions, and the silicon oxide film OX1 and the silicon nitride film SIN in the other regions. It is patterned so as to remove. That is, the feature of the third embodiment is that the region covered with the silicon oxide film OX1 and the silicon nitride film SIN is not one control gate electrode formation region but two adjacent control gate electrode formation regions wider than this. In the point.

  Next, as shown in FIG. 23, a silicon oxide film OX2 is formed on the surface of the exposed polysilicon film PF1. Specifically, by performing a thermal oxidation process on the surface of the semiconductor substrate 1S, a silicon oxide film OX2 is formed on the exposed surface of the polysilicon film PF1, and the silicon oxide film OX1 and the silicon nitride film SIN are formed. A bird's beak BV is formed so as to bite into the polysilicon film PF1 covered with. This bird's beak BV is formed in the vicinity of the end portions of the patterned silicon oxide film OX1 and silicon nitride film SIN.

  Subsequently, as shown in FIG. 24, the silicon oxide film OX1 and the silicon nitride film SIN functioning as a hard mask are further patterned by using a photolithography technique and an etching technique. This patterning is performed so that the silicon oxide film OX1 and the silicon nitride film SIN cover only one control gate electrode formation region. That is, in the third embodiment, in the first patterning, the silicon oxide film OX1 and the silicon nitride film SIN are patterned so as to cover the two control gate electrode formation regions, and the first patterned silicon oxide film OX1 and the nitridation are performed. The surface of the polysilicon film PF1 exposed from the silicon film SIN is oxidized and a bird's beak BV is formed. Thereafter, by performing second patterning, the silicon oxide film OX1 and the silicon nitride film SIN are patterned so as to cover one control gate electrode formation region. Thus, the bird's beak BV is formed only at one end of the silicon oxide film OX1 and the silicon nitride film SIN covering one control gate electrode formation region, and the bird's beak BV is not formed at the other end. it can. Specifically, in FIG. 24, by performing the second patterning, a hard mask composed of the silicon oxide film OX1 (A) and the silicon nitride film SIN (A), the silicon oxide film OX1 (B), and the silicon nitride film SIN. A hard mask made of (B) can be formed.

  Thereafter, as shown in FIG. 25, the second patterned silicon oxide film OX1 (A) and silicon nitride film SIN (A), silicon oxide film OX1 (B) and silicon nitride film SIN (B) are used as hard masks. By processing the polysilicon film PF1, control gate electrodes CG1 and CG2 are formed. In the control gate electrode CG1, the bird's beak BV is formed only at the right upper end of the upper ends on both sides, and in the control gate electrode CG2, the bird's beak BV is formed only on the left upper end of the both ends.

  Next, as shown in FIG. 26, the patterned silicon oxide film OX1 (A) and silicon oxide film OX1 (B) are removed. As shown in FIG. 27, a silicon oxide film OX3 is formed on the entire surface of the semiconductor substrate 1S as an insulating film to be a potential barrier film EB1, which will be described later. A silicon nitride film SIN2 is formed as a film. Thereafter, for example, a silicon oxide film OX4 is formed on the silicon nitride film SIN2 as an insulating film to be a potential barrier film EB2, which will be described later, and a polysilicon film PF2 is formed on the silicon oxide film OX4. For example, the silicon oxide film OX3 can be formed using a thermal oxidation method or an ISSG oxidation method, and the silicon nitride film SIN2 can be formed using a CVD method. Further, the silicon oxide film OX4 can be formed using an ISSG oxidation method or a CVD method. Further, the polysilicon film PF2 can be formed by using, for example, a CVD method.

  Subsequently, the polysilicon film PF2 formed on the semiconductor substrate 1S is processed by using anisotropic etching. As a result, the sidewall-shaped polysilicon film PF2 remains on the sidewalls on both sides of the control gate electrode CG.

  Thereafter, as shown in FIG. 28, by using a photolithography technique and an etching technique, the sidewall-shaped polysilicon film PF2 formed on one side of the control gate electrodes CG1 and CG2 is formed in the memory cell formation region MCR. Remove. Thereby, the sidewall-shaped polysilicon film PF2 remains only on one side wall of the control gate electrodes CG1 and CG2. Further, the silicon nitride film formed to protect the shape of the bird's beak BV by etching the laminated insulating film (silicon oxide film OX3, silicon nitride film SIN2, silicon oxide film OX4) and silicon nitride film SIN. By removing the SIN, side wall-shaped memory gate electrodes MG1 and MG2 can be formed on one side wall of the control gate electrodes CG1 and CG2 via a laminated insulating film. At this time, the laminated insulating film includes the silicon oxide film OX3, the silicon nitride film SIN2, and the silicon oxide film OX4. For example, the silicon oxide film OX3 becomes the potential barrier films EB1 (A) and EB1 (B), and the silicon nitride film SIN2 becomes the charge storage films EC (A) and EC (B). Further, the silicon oxide film OX4 becomes the potential barrier films EB2 (A) and EB2 (B).

  Thereby, in the control gate electrodes CG1 and CG2, the bird's beak BV can be formed only at the upper end of the memory gate electrodes MG1 and MG2. The subsequent steps are the same as those in the first embodiment. As described above, the semiconductor device according to the third embodiment can be manufactured. In the third embodiment, the bird's beak BV is formed only in the minimum necessary region, and the cobalt silicide film CS is formed in the other regions, so that the electric field between the control gate electrode CG1 and the memory gate electrode MG1 is formed. The resistance of the control gate electrode CG1 can be reduced while the strength is relaxed.

(Embodiment 4)
In the first embodiment, the split gate nonvolatile memory in which the memory gate electrode MG is formed on the side wall of the control gate electrode CG has been described. However, in the fourth embodiment, the control gate electrode CG is formed on the side wall of the memory gate electrode MG. A split gate nonvolatile memory in which is formed will be described.

  FIG. 29 is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment. The configuration of the nonvolatile memory cell formed in the memory cell formation region MCR shown in FIG. 29 will be described below using the enlarged view shown in FIG. In FIG. 30, a laminated insulating film is formed on the semiconductor substrate 1S (p-type well PWL1). Specifically, the stacked insulating film includes a first potential barrier film EB1, a charge storage film EC formed on the first potential barrier film EB1, and a second potential barrier film formed on the charge storage film EC. It is composed of EB2. A memory gate electrode MG is formed on the stacked insulating film. The memory gate electrode MG is formed of a polysilicon film PF1 and a cobalt silicide film CS.

  A control gate electrode CG is formed on the side wall on one side of the memory gate electrode MG via a gate insulating film GOX2. The control gate electrode CG is formed of a laminated film of a polysilicon film PF2 and a cobalt silicide film CS.

  Next, the control gate electrode CG is formed on one side of the sidewalls of the memory gate electrode MG, while the sidewall SW made of a silicon oxide film is formed on the other side. Similarly, a memory gate electrode MG is formed on one side of the side walls of the control gate electrode CG, and a side wall SW made of a silicon oxide film is formed on the other side.

  A pair of shallow low-concentration impurity diffusion regions EX1 that are n-type semiconductor regions are formed in the semiconductor substrate 1S immediately below the sidewall SW, and an outer region in contact with the pair of shallow low-concentration impurity diffusion regions EX1. A pair of deep high-concentration impurity diffusion regions NR1 is formed. This deep high-concentration impurity diffusion region NR1 is also an n-type semiconductor region, and a cobalt silicide film CS is formed on the surface of the deep high-concentration impurity diffusion region NR1. A pair of shallow low-concentration impurity diffusion regions EX1 and a pair of deep high-concentration impurity diffusion regions NR1 form a source region or a drain region of the memory cell. By forming the source region and the drain region with the shallow low-concentration impurity diffusion region EX1 and the deep high-concentration impurity diffusion region NR1, the source region and the drain region can have an LDD (Lightly Doped Drain) structure.

  A feature of the fourth embodiment is that a gate insulating film GOX2 is also formed at the upper end portion of the memory gate electrode MG. Hereinafter, this portion is referred to as a gate insulating film GOX3. As a result, the substantial distance between the memory gate electrode MG and the control gate electrode CG can be increased. That is, by forming the gate insulating film GOX3 at the upper end of the memory gate electrode MG, the gate insulating film GOX2 and the gate insulating film are formed between the memory gate electrode MG and the control gate electrode CG at the upper end of the memory gate electrode MG. GOX3 exists, and for example, the distance between the control gate electrode CG and the memory gate electrode MG can be separated by the gate insulating film GOX3 made of a silicon oxide film. As a result, even if a large potential difference occurs between the control gate electrode CG and the memory gate electrode MG, the electric field strength applied to the gate insulating film GOX2 formed therebetween is relaxed. That is, the electric field strength decreases as the distance between the control gate electrode CG and the memory gate electrode MG increases, and therefore, by forming the gate insulating film GOX3, the electric field strength between the control gate electrode CG and the memory gate electrode MG is reduced. The electric field strength generated between them can be relaxed. As a result, the leakage current flowing between the control gate electrode CG and the memory gate electrode MG via the gate insulating film GOX2 can be reduced.

  Further, as in the fourth embodiment, by forming the gate insulating film GOX3 on the upper end portion of the memory gate electrode MG, the cobalt silicide film CS formed on the surface of the memory gate electrode MG, and the control gate electrode CG The distance from the cobalt silicide film CS formed on the surface can be increased. For this reason, a short circuit failure between the control gate electrode CG and the memory gate electrode MG can be prevented. As described above, in the fourth embodiment, the gate insulating film GOX3 is formed on the upper end portion of the memory gate electrode MG, whereby the distance between the upper end portion of the memory gate electrode MG and the upper end portion of the control gate electrode CG. Can be released. As a result, the first effect that the electric field strength of the gate insulating film GOX2 interposed between the upper end portion of the memory gate electrode MG and the upper end portion of the control gate electrode CG can be relaxed, and the surface of the memory gate electrode MG is formed. It is possible to obtain a second effect that can prevent a short circuit failure due to contact between the cobalt silicide film CS and the cobalt silicide film CS formed on the surface of the control gate electrode CG.

  Hereinafter, specifically, conditions for sufficiently achieving electric field relaxation between the memory gate electrode MG and the control gate electrode CG will be described. That is, a condition that is satisfied by the gate insulating film GOX3 formed on the upper end portion of the memory gate electrode MG is considered. First, as shown in FIG. 30, the thickness of the gate insulating film GOX2 formed at a position in contact with the middle end portion (or the lower end portion) of the memory gate electrode MG may be d, and from the upper end portion of the memory gate electrode MG. When the length of the gate insulating film GOX3 formed in the gate length direction of the memory gate electrode MG is b, the gate insulating film GOX3 is formed so that the relationship of b> d / 2 is satisfied. Thereby, the length of the gate insulating film GOX3 becomes sufficiently long, and the combined length of the gate insulating film GOX2 and the gate insulating film GOX3 formed on the upper end portion of the memory gate electrode MG becomes long. As a result, the distance between the upper end of the memory gate electrode MG and the upper end of the control gate electrode CG becomes longer, the electric field strength between the memory gate electrode MG and the control gate electrode CG is relaxed, and the leakage current is reduced. In other words, under the condition that the length b of the gate insulating film GOX3 is smaller than half the film thickness d of the gate insulating film GOX2, it cannot be said that the length of the gate insulating film GOX3 is sufficiently long. It can be said that the electric field relaxation between the gate electrode MG and the control gate electrode CG cannot be sufficiently achieved. The film thickness d at the middle end of the gate insulating film GOX2 is formed to satisfy the relationship of 10 nm ≦ d ≦ 20 nm, for example. Similarly, the thickness of the gate insulating film GOX2 formed between the semiconductor substrate 1S and the control gate electrode CG is also about 10 nm to 20 nm.

  In this case, the distance between the upper end portion of the memory gate electrode MG and the upper end portion of the control gate electrode CG is 3/2 times or more the film thickness d of the gate insulating film GOX2. For this reason, the electric field strength generated between the upper end portion of the memory gate electrode MG and the upper end portion of the control gate electrode CG is 2/3 times or less compared to the case where the gate insulating film GOX3 is not formed. Therefore, the electric field strength between the memory gate electrode MG and the control gate electrode CG is sufficiently relaxed, and the leakage current can be reduced.

  From the above, it can be said that the length b of the gate insulating film GOX3 is 5 nm or more. From the viewpoint of increasing the influence of electric field relaxation, it is desirable to increase the length b of the gate insulating film GOX3. However, the length b of the gate insulating film GOX3 is b <L / 2 when the gate length of the memory gate electrode MG is L. The gate insulating film GOX3 is formed at the upper end of the memory gate electrode MG on the control gate electrode side, and the sidewall SW is formed at the upper end of the other side of the memory gate electrode MG (this is referred to as the sidewall SW2 and In view of the above, since the length of the gate insulating film GOX3 and the side wall SW2 is approximately the same, when each length b exceeds L / 2, the entire surface of the memory gate electrode MG is formed. This is because the gate insulating film GOX3 and the sidewall SW2 are formed. That is, when the length b of the gate insulating film GOX3 and the sidewall SW2 exceeds L / 2, the cobalt silicide film CS is not formed on the surface of the memory gate electrode MG, and the resistance of the memory gate electrode MG is reduced. It is because it becomes impossible to do. Therefore, from the viewpoint of reducing the electric field strength between the upper end portion of the memory gate electrode MG and the upper end portion of the control gate electrode CG and reducing the resistance of the memory gate electrode MG at the same time, the gate insulating film GOX3 The length b of the sidewall SW2 needs to satisfy the relationship of 5 nm ≦ b <L / 2.

  The semiconductor device according to the fourth embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings. First, the processes up to the step shown in FIG. 4 are the same as those in the first embodiment. Subsequently, as shown in FIG. 31, a silicon oxide film OX3 is formed on the entire surface of the semiconductor substrate 1S as an insulating film to be a potential barrier film EB1 described later, and a charge storage film EC described later is formed on the silicon oxide film OX3. A silicon nitride film SIN2 is formed as an insulating film. Then, a silicon oxide film OX4 is formed on the silicon nitride film SIN2 as an insulating film to be a potential barrier film EB2 described later, and a polysilicon film PF1 is formed on the silicon oxide film OX4. Thereafter, a silicon oxide film OX1 is formed on the polysilicon film PF1. For example, the silicon oxide film OX3 can be formed using a thermal oxidation method or an ISSG oxidation method, and the silicon nitride film SIN2 can be formed using a CVD method. Further, the silicon oxide film OX4 can be formed using an ISSG oxidation method or a CVD method. The polysilicon film PF2 can be formed by using, for example, a CVD method, and the silicon oxide film OX1 can also be formed by using a CVD method.

  Next, as shown in FIG. 32, the silicon oxide film OX1 is patterned by using a photolithography technique and an etching technique. The patterning of the silicon oxide film OX1 is performed so that the silicon oxide film OX1 is formed only in the memory gate electrode formation region and the silicon oxide film OX1 does not remain in other regions. That is, in the memory cell formation region MCR, the silicon oxide film OX1 remains only in the memory gate electrode formation region, and in other regions, the silicon oxide film OX1 is removed and the surface of the polysilicon film PF1 is exposed. On the other hand, in the peripheral circuit formation region PER, all the silicon oxide film OX1 is removed.

  Subsequently, as shown in FIG. 33, the surface of the polysilicon film PF1 formed on the semiconductor substrate 1S is oxidized. Specifically, the silicon oxide film OX2 is formed on the surface of the polysilicon film PF1 exposed from the silicon oxide film OX1 in the memory cell formation region MCR. At this time, by performing sufficient thermal oxidation treatment, the bird's beak BV is formed so as to bite into the polysilicon film PF1 formed under the silicon oxide film OX1 covering the memory gate electrode formation region. Also in the fourth embodiment, since sufficient thermal oxidation treatment can be performed without considering the amount of heat treatment, a bird's beak BV that sufficiently penetrates into the lower layer of the silicon oxide film can be formed. That is, in the fourth embodiment, since the bird's beak BV is formed before the semiconductor element (memory cell or MISFET) is formed, sufficient heat treatment is applied without considering the influence on the semiconductor element. Can do. As a result, a sufficiently large bird's beak BV can be formed.

  Next, as shown in FIG. 34, after the silicon oxide film OX2 formed on the surface of the polysilicon film PF1 is removed by, for example, anisotropic etching, the patterned silicon oxide film OX1 is used as a mask to form the polysilicon film PF1. Is processed. Thereby, the memory gate electrode MG made of the polysilicon film PF1 can be formed in the memory cell formation region MCR. A bird's beak BV is formed at the upper end of the memory gate electrode MG. Further, by processing the silicon oxide film OX4, the silicon nitride film SIN2, and the silicon oxide film OX3 formed in the lower layer of the polysilicon film PF1, the second potential made of the silicon oxide film OX4 is formed in the lower layer of the memory gate electrode MG. The barrier film EB2, the charge storage film EC made of the silicon nitride film SIN2, and the first potential barrier film EB1 made of the silicon oxide film OX3 can be formed. Thereafter, the silicon oxide film OX1 formed over the memory gate electrode MG is removed. At this time, the bird's beak formed by the process shown in FIG. 33 is also removed at the same time. In the peripheral circuit formation region PER, the silicon oxide film OX2, the polysilicon film PF1, the silicon oxide film OX4, the silicon nitride film SIN2, and the silicon oxide film OX3 are all removed.

  Subsequently, as shown in FIG. 35, a gate insulating film GOX2 made of, for example, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1S, and then a polysilicon film PF2 is formed on the gate insulating film GOX2. The gate insulating film GOX2 can be formed by, for example, a thermal oxidation method or a CVD method, and the polysilicon film PF2 can be formed by, for example, a CVD method. When the gate insulating film GOX2 is formed, as described above, the portion where the bird's beak BV is removed, that is, the upper end portion (corner portion) of the memory gate electrode MG is easily oxidized. The upper end of the MG becomes round. Thereafter, n-type impurities such as phosphorus and arsenic are introduced into the polysilicon film PF1 in the memory cell formation region by using a photolithography technique and an ion implantation method, and n-type impurities such as phosphorus and arsenic in the peripheral circuit formation region. And p-type impurities such as boron (boron) are introduced.

  Thereafter, as shown in FIG. 36, the polysilicon film PF2 and the gate insulating film GOX2 are processed by using a photolithography technique and an etching technique. Thereby, in the memory cell formation region MCR, the sidewall-shaped control gate electrode CG can be formed on the sidewall of the memory gate electrode MG via the gate insulating film GOX2. Further, a gate insulating film GOX3 that is the same layer as the gate insulating film GOX2 is formed in the portion where the bird's beak BV is removed. On the other hand, in the peripheral circuit formation region PER, the gate electrode G1 of the n-channel type MISFET and the gate electrode G2 of the p-channel type MISFET can be formed.

  Subsequently, as shown in FIG. 37, by using a photolithography technique and an ion implantation method, a shallow low-concentration impurity diffusion region EX1 aligned with the control gate electrode CG and the memory gate electrode MG is formed in the memory cell formation region MCR. Form. The shallow low-concentration impurity diffusion region EX1 is an n-type semiconductor region into which an n-type impurity such as phosphorus or arsenic is introduced. On the other hand, in the peripheral circuit formation region PER, a shallow low concentration impurity diffusion region EX2 aligned with the gate electrode G1 is formed. This shallow low-concentration impurity diffusion region EX2 is also an n-type semiconductor region into which an n-type impurity is introduced. Similarly, in the peripheral circuit formation region PER, a shallow low-concentration impurity diffusion region EX3 aligned with the gate electrode G2 is also formed. This shallow low-concentration impurity diffusion region EX3 is a p-type semiconductor region into which p-type impurities are introduced.

  Thereafter, as shown in FIG. 38, a silicon oxide film is formed on the semiconductor substrate 1S. The silicon oxide film can be formed using, for example, a CVD method. Then, the sidewall SW is formed by anisotropically etching the silicon oxide film. In memory cell formation region MCR, sidewalls SW are formed on the sidewalls of control gate electrode CG and memory gate electrode MG. Further, a sidewall SW2, which is a film in the same layer as the sidewall SW, is formed in the portion where the bird's beak BV is removed. Similarly, in the peripheral circuit formation region PER, sidewalls SW are formed on the sidewalls on both sides of the gate electrode G1 and the gate electrode G2. These sidewalls SW are formed from a single layer film of a silicon oxide film. However, the present invention is not limited to this, and for example, a sidewall SW composed of a laminated film of a silicon nitride film and a silicon oxide film may be formed. .

  Subsequently, a deep high-concentration impurity diffusion region NR1 aligned with the sidewall SW is formed in the memory cell formation region MCR by using a photolithography technique and an ion implantation method. The deep high-concentration impurity diffusion region NR1 is an n-type semiconductor region into which an n-type impurity such as phosphorus or arsenic is introduced. The deep high concentration impurity diffusion region NR1 and the shallow low concentration impurity diffusion region EX1 form a source region or a drain region of the memory cell. By forming the source region and the drain region with the shallow low-concentration impurity diffusion region EX1 and the deep high-concentration impurity diffusion region NR1 in this way, the source region and the drain region can have an LDD (Lightly Doped Drain) structure.

  On the other hand, a deep high-concentration impurity diffusion region NR2 aligned with the sidewall SW is formed in the peripheral circuit formation region PER. The deep high-concentration impurity diffusion region NR2 is an n-type semiconductor region into which an n-type impurity such as phosphorus or arsenic is introduced. The deep high-concentration impurity diffusion region NR2 and the shallow low-concentration impurity diffusion region EX2 form the source region or drain region of the n-channel MISFET. By forming the source region and the drain region with the shallow low-concentration impurity diffusion region EX2 and the deep high-concentration impurity diffusion region NR2, the source region and the drain region can have an LDD (Lightly Doped Drain) structure.

  Similarly, in the peripheral circuit formation region PER, a deep high concentration impurity diffusion region PR1 is formed in alignment with the sidewall SW formed on the sidewall of the gate electrode G2. The deep high-concentration impurity diffusion region PR1 is a p-type semiconductor region into which a p-type impurity such as boron (boron) is introduced. The deep high-concentration impurity diffusion region PR1 and the shallow low-concentration impurity diffusion region EX3 form the source region or drain region of the p-channel type MISFET. By forming the source region and the drain region with the shallow low-concentration impurity diffusion region EX3 and the deep high-concentration impurity diffusion region PR1, the source region and the drain region can have an LDD (Lightly Doped Drain) structure.

  Here, in the memory cell formation region MCR, a shallow low-concentration impurity diffusion region EX1 and a deep high-concentration impurity diffusion region NR1 are formed by introducing n-type impurities such as phosphorus and arsenic into the semiconductor substrate 1S. At this time, n-type impurities such as phosphorus and arsenic are also introduced into the upper end portion of the control gate electrode CG, the upper end portion of the memory gate electrode MG, and the upper end portion of the gate insulating film GOX2. In particular, when an n-type impurity is introduced into the upper end portion of the gate insulating film GOX2 made of an insulating film, a phenomenon that the insulation resistance of the gate insulating film GOX2 deteriorates occurs. Then, the leakage current flowing between the upper end portion of the memory gate electrode MG insulated by the gate insulating film GOX2 and the upper end portion of the control gate electrode CG increases. However, in the fourth embodiment, since the gate insulating film GOX3 is formed on the upper end portion of the memory gate electrode MG, the substantial distance between the upper end portion of the memory gate electrode MG and the upper end portion of the control gate electrode CG is set. Can be released. This means that the electric field strength can be relaxed in the gate insulating film GOX2 existing between the memory gate electrode MG and the control gate electrode CG. Therefore, even if an n-type impurity is introduced into the upper end portion of the gate insulating film GOX2 and the insulation resistance of the gate insulating film GOX2 is deteriorated, the electric field strength generated in the gate insulating film GOX2 by forming the gate insulating film GOX3. Therefore, the leakage current flowing between the memory gate electrode MG and the control gate electrode CG can be reduced.

  Thus, after forming the deep high-concentration impurity diffusion regions NR1, NR2, and PR1, heat treatment at about 1000 ° C. is performed. Thereby, the introduced impurities are activated.

  Next, after forming a cobalt film on the semiconductor substrate 1S, heat treatment is performed to thereby form the polysilicon films PF1, PF2 and the cobalt film constituting the memory gate electrode MG and the control gate electrode CG in the memory cell formation region MCR. To form a cobalt silicide film CS. Thereby, the memory gate electrode MG and the control gate electrode CG have a laminated structure of the polysilicon films PF1 and PF2 and the cobalt silicide film CS, respectively. Similarly, on the surface of the high-concentration impurity diffusion region NR1, silicon and the cobalt film react to form a cobalt silicide film CS.

  On the other hand, also in the peripheral circuit formation region PER, the cobalt silicide film CS is formed on the surface of the polysilicon film PF1 constituting the gate electrodes G1 and G2. As a result, the gate electrodes G1 and G2 are composed of the polysilicon film PF2 and the cobalt silicide film CS. Similarly, the silicon silicide film reacts with the surface of the deep high-concentration impurity diffusion regions NR2 and PR1 to form the cobalt silicide film CS. In the fourth embodiment, the cobalt silicide film CS is formed. However, for example, a nickel silicide film or a titanium silicide film may be formed instead of the cobalt silicide film CS.

  At this time, in the fourth embodiment, since the gate insulating film GOX3 is formed at the upper end of the memory gate electrode MG, the distance between the memory gate electrode MG and the control gate electrode CG can be increased. This means that the distance between the cobalt silicide film CS formed on the surface of the memory gate electrode MG and the cobalt silicide film CS formed on the surface of the control gate electrode CG can be increased. Therefore, even when the memory cell is miniaturized, the cobalt silicide film CS formed on the surface of the memory gate electrode MG and the cobalt silicide film CS formed on the surface of the control gate electrode CG are in contact with each other. It is possible to suppress short circuit defects.

  As described above, a plurality of memory cells can be formed in the memory cell formation region MCR of the semiconductor substrate 1S, and a plurality of n-channel MISFETs and p-channel MISFETs can be formed in the peripheral circuit formation region PER. The subsequent wiring process is the same as in the first embodiment.

  In the fourth embodiment, unlike the first embodiment (see FIG. 7), as shown in FIG. 32, only the silicon oxide film OX1 is formed on the polysilicon film PF1. This is because, when a silicon nitride film and a silicon oxide film OX1 are used as a hard mask on the polysilicon film PF1, in the fourth embodiment, the step of removing the silicon nitride film is formed in the peripheral circuit formation region PER. This is because the gate electrodes G1 and G2 and the gate insulating film GOX2 that are present must be exposed. That is, in the state of FIG. 36, if a silicon nitride film is formed on the memory gate electrode MG, the gate electrodes G1 and G2 are already processed in the peripheral circuit formation region PER when the silicon nitride film is removed. This is because the exposed gate electrodes G1 and G2 are damaged in the step of removing the silicon nitride film. For this reason, in the fourth embodiment, only the silicon oxide film OX1 is used as a hard mask for processing the polysilicon film PF1, not the laminated film of the silicon nitride film and the silicon oxide film OX1. ing. Therefore, in the fourth embodiment, since the silicon nitride film that protects the shape of the bird's beak BV is not formed, the bird's beak BV is also removed at the same time in the step of removing the silicon oxide film OX1 shown in FIG. The However, also in the fourth embodiment, when the damage given to the gate electrodes G1 and G2 formed in the peripheral circuit formation region PER is not so much a problem, a silicon nitride film and a hard mask for processing the polysilicon film PF1 are used. A stacked film of the silicon oxide film OX1 can be used. In this case, since the shape of the bird's beak BV is protected by the silicon nitride film, the effect of relaxing the electric field by the bird's beak BV and the effect of preventing the short-circuit between the silicide films can be increased.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

1 CPU
1S semiconductor substrate 2 RAM
3 Analog circuit 4 EEPROM
5 Flash memory 6 I / O circuit BV Bird's beak CG Control gate electrode CG1 Control gate electrode CG2 Control gate electrode CHP Semiconductor chip CNT Contact hole CS Cobalt silicide film EB1 First potential barrier film EB2 Second potential barrier film EC Charge storage film EB1 ( A) First potential barrier film EB2 (A) Second potential barrier film EC (A) Charge storage film EB1 (B) First potential barrier film EB2 (B) Second potential barrier film EC (B) Charge storage film EX1 Shallow Low concentration impurity diffusion region EX2 Shallow low concentration impurity diffusion region EX3 Shallow low concentration impurity diffusion region G1 Gate electrode G2 Gate electrode GOX Gate insulation film GOX2 Gate insulation film GOX3 Gate insulation film IL1 Interlayer insulation film IL2 Interlayer insulation film L1 Wiring MCR Memory cell Formation Area MG Memory gate electrode MG1 Memory gate electrode MG2 Memory gate electrode NISO Well isolation layer NR1 Deep high-concentration impurity diffusion region NR2 Deep high-concentration impurity diffusion region NWL1 N-type well OX1 Silicon oxide film OX1 (A) Silicon oxide film OX1 (B) Silicon oxide film OX2 Silicon oxide film OX3 Silicon oxide film OX4 Silicon oxide film PER Peripheral circuit formation region PF1 Polysilicon film PF2 Polysilicon film PLG1 Plug PR1 Deep high-concentration impurity diffusion region PWL1 p-type well PWL2 p-type well SIN silicon nitride film SIN (A) Silicon nitride film SIN (B) Silicon nitride film SIN2 Silicon nitride film STI Element isolation region SW sidewall SW2 sidewall

Claims (26)

Having a plurality of memory cells formed on a semiconductor substrate;
Each of the plurality of memory cells includes
(A) a gate insulating film formed on the semiconductor substrate;
(B) a control gate electrode formed on the gate insulating film;
(C) a memory gate electrode formed on a side wall of the control gate electrode;
(D) a laminated insulating film formed between the control gate electrode and the memory gate electrode and between the memory gate electrode and the semiconductor substrate;
(E) a source region and a drain region formed in the semiconductor substrate;
The laminated insulating film is
(D1) a first potential barrier film;
(D2) a charge storage film formed on the first potential barrier film;
(D3) a second potential barrier film formed on the charge storage film,
A semiconductor device in which a bird's beak is formed at the upper end of the control gate electrode,
The film thickness of the first potential barrier film formed at a position in contact with the middle end portion of the control gate electrode is a, and is formed in the gate length direction of the control gate electrode from the upper end portion of the control gate electrode. A semiconductor device characterized in that when the length of the bird's beak is b, a relationship of b> a is established and a relationship of 2 nm ≦ a ≦ 5 nm is satisfied. The semiconductor device according to claim 1,
A semiconductor device characterized in that a relation of b ≧ d / 2 is satisfied, where d is a film thickness of the laminated insulating film formed at a position in contact with the middle end portion of the control gate electrode. The semiconductor device according to claim 1,
When the length of the control gate electrode in the gate length direction is L, the semiconductor device satisfies the relationship of 5 nm ≦ b <L / 2. The semiconductor device according to claim 1,
The bird's beak is formed only at the upper end on the side where the memory gate electrode is formed among the upper ends on both sides of the control gate electrode. The semiconductor device according to claim 1,
The semiconductor device, wherein the charge storage film is formed of a silicon nitride film. The semiconductor device according to claim 1,
The control gate electrode and the memory gate electrode are both formed of a polysilicon film and a silicide film formed on the polysilicon film. Having a plurality of memory cells formed on a semiconductor substrate;
Each of the plurality of memory cells includes
(A) a laminated insulating film formed on the semiconductor substrate;
(B) a memory gate electrode formed on the stacked insulating film;
(C) a control gate electrode formed on a side wall of the memory gate electrode;
(D) a gate insulating film formed between the memory gate electrode and the control gate electrode and between the control gate electrode and the semiconductor substrate;
(E) a first sidewall formed on the sidewall of the memory gate electrode, and a second sidewall made of a film in the same layer as the first sidewall formed on the sidewall of the control gate electrode;
(F) a source region and a drain region formed in the semiconductor substrate;
A first insulating film made of the same layer as the gate insulating film is formed on the control gate electrode side of the upper end portion of the memory gate electrode, and the first sidewall side of the upper end portion of the memory gate electrode is on the first sidewall side. A semiconductor device in which a second insulating film made of the same layer as one sidewall is formed,
The film thickness of the gate insulating film formed at a position in contact with the middle end portion of the memory gate electrode is d, and the first thickness formed from the upper end portion of the memory gate electrode in the gate length direction of the memory gate electrode. When the length of one insulating film is b and the length of the second insulating film formed in the gate length direction of the memory gate electrode from the upper end of the memory gate electrode is c, b ≧ d / 2 and A semiconductor device characterized in that a relationship of c ≧ d / 2 is established. The semiconductor device according to claim 7,
2. A semiconductor device characterized by satisfying a relationship of 5 nm ≦ b <L / 2 and 5 nm ≦ c <L / 2 when the length of the memory gate electrode in the gate length direction is L. The semiconductor device according to claim 7,
The semiconductor device, wherein the second insulating film is not formed and the first insulating film is formed. The semiconductor device according to claim 7,
The laminated insulating film is
(A1) a first potential barrier film formed on the semiconductor substrate;
(A2) a charge storage film formed on the first potential barrier film;
(A3) A semiconductor device having a second potential barrier film formed on the charge storage film. The semiconductor device according to claim 10,
The semiconductor device, wherein the charge storage film is formed of a silicon nitride film. The semiconductor device according to claim 7,
The control gate electrode and the memory gate electrode are both formed of a polysilicon film and a silicide film formed on the polysilicon film. A method of manufacturing a semiconductor device having a memory cell formation region on a semiconductor substrate,
(A) forming a gate insulating film on the semiconductor substrate;
(B) forming a first conductor film on the gate insulating film;
(C) forming a mask film on the first conductor film;
(D) patterning the mask film;
(E) forming a silicon oxide film on the surface of the first conductor film exposed from the patterned mask film and forming a bird's beak so as to bite into the first conductor film covered with the mask film; When,
(F) forming a control gate electrode by processing the first conductor film using the patterned mask film as a mask;
(G) forming a laminated insulating film on the semiconductor substrate on which the control gate electrode is formed;
(H) forming a second conductor film on the laminated insulating film;
(I) forming a memory gate electrode on a sidewall of the control gate electrode by anisotropically etching the second conductive film;
(J) forming the laminated insulating film between the control gate electrode and the memory gate electrode and between the memory gate electrode and the semiconductor substrate by etching the laminated insulating film;
(K) A step of forming a source region and a drain region in the semiconductor substrate after the step (j). A method for manufacturing a semiconductor device according to claim 13, comprising:
The first conductor film and the second conductor film are polysilicon films;
(L) A method of manufacturing a semiconductor device, comprising forming a silicide film on the surface of the control gate electrode and the surface of the memory gate electrode. A method for manufacturing a semiconductor device according to claim 13, comprising:
The step (c)
(C1) forming a silicon nitride film on the first conductor film;
(C2) forming a silicon oxide film on the silicon nitride film, and
Between the step (f) and the step (g),
(M) removing the silicon oxide film;
Between the step (j) and the step (k),
(N) A method of manufacturing a semiconductor device, comprising a step of removing the silicon nitride film. A method for manufacturing a semiconductor device according to claim 15, comprising:
The step (d)
(D1) patterning the silicon oxide film;
(D2) after the step (d1), patterning the silicon nitride film using the patterned silicon oxide film as a mask,
In the step (d2), the silicon nitride film is patterned by isotropic etching with hot phosphoric acid. A method for manufacturing a semiconductor device according to claim 13, comprising:
In the step (d), the mask film is first patterned so as to cover a pair of adjacent control gate electrode formation regions,
The step (f)
(F1) a step of second patterning the mask film so as to cover only the control gate electrode formation region;
(F2) forming the respective control gate electrodes by processing the first conductive film using the second patterned mask film as a mask, and a method of manufacturing a semiconductor device . A method for manufacturing a semiconductor device according to claim 13, comprising:
The semiconductor substrate further includes a peripheral circuit formation region for forming a peripheral circuit,
After the step (j) and before the step (k), a step of forming the gate electrode of the MISFET constituting the peripheral circuit by processing the second conductor film formed in the peripheral circuit formation region. A method for manufacturing a semiconductor device, comprising: A method for manufacturing a semiconductor device according to claim 13, comprising:
The step (g)
(G1) forming a first potential barrier film on the semiconductor substrate on which the control gate electrode is formed;
(G2) forming a charge storage film on the first potential barrier film;
And (g3) forming a second potential barrier film on the charge storage film. A method of manufacturing a semiconductor device according to claim 19,
The method of manufacturing a semiconductor device, wherein the charge storage film is formed of a silicon nitride film. A method of manufacturing a semiconductor device having a memory cell formation region on a semiconductor substrate,
(A) forming a laminated insulating film on the semiconductor substrate;
(B) forming a first conductor film on the laminated insulating film;
(C) forming a mask film on the first conductor film;
(D) patterning the mask film;
(E) The first conductor film is oxidized to form a silicon oxide film on the surface of the first conductor film exposed from the patterned mask film, and the first conductor film is covered with the mask film. Forming a bird's beak so as to bite into the conductor film;
(F) forming a memory gate electrode by processing the first conductor film using the patterned mask film as a mask;
(G) removing the mask film and the bird's beak;
(H) forming a gate insulating film on the semiconductor substrate on which the memory gate electrode is formed;
(I) forming a second conductor film on the gate insulating film;
(J) forming a control gate electrode on a side wall of the memory gate electrode by anisotropically etching the second conductor film;
(K) forming the gate insulating film between the memory gate electrode and the control gate electrode and between the control gate electrode and the semiconductor substrate by etching the gate insulating film; and Forming a first insulating film on an upper end of the control gate electrode side of
(L) After the step (k), forming a first semiconductor region in the semiconductor substrate;
(M) forming a third insulating film on the semiconductor substrate on which the memory gate electrode and the control gate electrode are formed;
(N) etching the third insulating film to form a first sidewall on a side wall of the memory gate electrode, and a second insulating film on an upper end portion of the memory gate electrode on the first sidewall side; And forming a second sidewall on the side wall of the control gate electrode;
(O) After the step (n), a method of forming a second semiconductor region electrically connected to the first semiconductor region in the semiconductor substrate is provided. A method of manufacturing a semiconductor device according to claim 21,
The first conductor film and the second conductor film are polysilicon films,
(P) forming a silicide film on the surface of the memory gate electrode and the surface of the control gate electrode. A method of manufacturing a semiconductor device according to claim 21,
The step (a)
(A1) forming a first potential barrier film on the semiconductor substrate;
(A2) forming a charge storage film on the first potential barrier film;
(A3) forming a second potential barrier film on the charge storage film; and a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 21,
The method of manufacturing a semiconductor device, wherein the mask film is a silicon oxide film. A method of manufacturing a semiconductor device according to claim 23, wherein
The method of manufacturing a semiconductor device, wherein the charge storage film is formed of a silicon nitride film. The semiconductor device according to claim 1,
The length b of the bird's beak is larger than the thickness of the bird's beak.

Images