JP2010256819A - Active matrix type organic light emitting display device and method for driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type organic light emitting display device excellent in gradation reproducibility, and to provide a method for driving an active matrix type organic light emitting display device. <P>SOLUTION: The active matrix type organic light emitting display device includes a plurality of video signal lines VL and a plurality of pixels PX. Each pixel PX has: a cathode, an anode, and an organic light emitting diode OLED including an organic layer; an N channel type drive transistor DR; an output switch SWa; a first capacitor section Cs; and a second capacitor section Cx. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an active matrix organic light emitting display device and a driving method of the active matrix organic light emitting display device.

  In recent years, an active matrix organic electroluminescence (EL) display device has been developed as an active matrix display device. In an active matrix organic electroluminescence (EL) display device, the gradation of an image displayed on each pixel is controlled by the magnitude of a video signal. An active matrix organic EL display device using a voltage signal as a video signal is disclosed (for example, see Patent Document 1).

  In general, the threshold voltage and mobility of a driving transistor vary between pixels. For this reason, even if the same video signal is supplied to the pixel, the current flowing through the organic light emitting diode differs from pixel to pixel, resulting in uneven brightness.

  Here, Patent Document 1 discloses a technique for suppressing variation in threshold voltage. As a result, variations in drive current due to variations in threshold voltage can be suppressed, and excellent gradation reproducibility can be obtained.

  In addition, a technique is disclosed in which variation in threshold voltage is suppressed by providing a cancel (offset cancel) operation twice, and variation in mobility of a driving transistor is absorbed by a gate potential distribution (for example, Patent Document 2). reference). In this case, both the influence of the threshold voltage variation and the mobility variation can be suppressed.

JP 2007-10993 A JP 2006-215213 A

  By the way, the mobility compensation by the cancel operation is performed while lowering the voltage between the gate electrode and the source electrode of the drive transistor. In this case, since the gate electrode is lowered, the gradation reproducibility may vary.

Further, the mobility compensation by the cancel operation needs to be performed in a span of 1 μsec or less, and the gradation reproducibility may vary from pixel to pixel due to the CR product of the wiring or the operation delay of the driver.
The present invention has been made in view of the above points, and an object of the present invention is to provide an active matrix organic light emitting display device excellent in gradation reproducibility and a driving method of the active matrix organic light emitting display device.

In order to solve the above-described problem, an active matrix organic light emitting display device according to an aspect of the present invention includes:
Multiple video signal lines;
A plurality of pixels connected to each of the video signal lines,
Each pixel is
An organic light emitting diode including a cathode connected to a low-potential power line, an anode disposed opposite to the cathode, and an organic material layer sandwiched between the cathode and the anode;
An N-channel driving transistor including a drain electrode connected to a high-potential power wiring, a source electrode connected to the anode of the organic light emitting diode, and a gate electrode;
An output switch connected between the high-potential power line and the drain electrode of the driving transistor;
A first capacitor including a first electrode connected to a gate electrode of the driving transistor and a second electrode connected to an anode of the organic light emitting diode;
A second capacitor portion including an electrode connected to the gate electrode of the driving transistor.

In addition, a driving method of an active matrix organic light emitting display device according to another aspect of the present invention includes:
A plurality of video signal lines; and a plurality of pixels connected to the video signal lines, each pixel including a cathode connected to a low-potential power line, an anode disposed opposite to the cathode, and the cathode And an organic light emitting diode including an organic material layer sandwiched between anodes, a drain electrode connected to a high-potential power wiring, a source electrode connected to the anode of the organic light emitting diode, and an N channel type including a gate electrode A drive transistor; an output switch connected between the high-potential power line and the drain electrode of the drive transistor; a first electrode connected to the gate electrode of the drive transistor; and a second electrode connected to the anode of the organic light emitting diode. An active capacitor having a first capacitor portion including an electrode and a second capacitor portion including an electrode connected to the gate electrode of the driving transistor. In the driving method of Rikusu organic light emitting display device,
During the light emission period, a drive signal is output from the drive transistor to the organic light emitting diode,
A change in the potential of the anode when the driving signal starts to flow through the organic light emitting diode is propagated to the gate electrode of the driving transistor through the first capacitor, and at this time, the gate electrode is driven by the second capacitor. The propagation of the change in the potential of the anode to is suppressed.

  According to the present invention, it is possible to provide an active matrix organic light emitting display device excellent in gradation reproducibility and a driving method of the active matrix organic light emitting display device.

1 is a plan view schematically showing an organic light emitting display device according to an embodiment of the present invention. It is sectional drawing which shows the drive transistor and organic light emitting diode of the said organic light emitting display. It is a top view which shows the equivalent circuit of the pixel in the said organic light emitting display device. It is a schematic plan view which shows the said pixel. FIG. 5 is a developed cross-sectional view taken along line A1-A2 of FIG. 3 is a timing chart showing on / off timings of a control signal in the driving method of the organic light emitting display device, and also shows a gate potential of the driving transistor, an initialization voltage, a source potential of the driving transistor, and a reset voltage. FIG. It is a figure which shows the equivalent circuit of the pixel in the reset operation | movement of the said organic light emitting display device. It is a figure which shows the equivalent circuit of the pixel in the cancellation operation | movement of the said organic light emitting display device. It is a figure which shows the equivalent circuit of the pixel in the write-in operation | movement of the said organic light emitting display device. It is a figure which shows the equivalent circuit of the pixel in the light emission operation | movement of the said organic light emitting display. It is a top view which shows the equivalent circuit of the modification of the pixel of the said organic light emitting display device. It is a schematic plan view of the pixel shown in FIG. It is a top view which shows the equivalent circuit of the other modification of the pixel of the said organic light emitting display device. FIG. 14 is a schematic plan view of the pixel shown in FIG. 13.

  Hereinafter, an active matrix organic light emitting display device and an active matrix organic light emitting display device driving method according to embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a plan view schematically showing a display device according to an embodiment of the present invention. FIG. 2 is a partial cross-sectional view schematically showing an example of a structure that can be employed in the display device of FIG. FIG. 3 is an equivalent circuit diagram of a pixel included in the display device of FIG. FIG. 4 is a plan view schematically showing the pixel. FIG. 5 is a cross-sectional view schematically showing a part of the pixel. In FIG. 2, the display device is depicted such that its display surface, that is, the front surface or the light emitting surface faces upward, and the back surface faces downward. This display device is a top emission type organic light emitting display device adopting an active matrix driving method. In this embodiment, the top emission organic light emitting display device is used. However, the present embodiment can be easily applied to a bottom emission organic light emitting display device.

  As shown in FIGS. 1 to 5, the organic light emitting display device includes a display panel DP, a video signal line driver XDR, and a scanning signal line driver YDR. The video signal line driver XDR and the scanning signal line driver YDR form a drive unit 10.

The display panel DP includes, for example, an insulating substrate SUB such as a glass substrate. An undercoat layer UC is formed on the insulating substrate SUB. For example, the undercoat layer UC is formed by laminating a SiN _X layer and a SiO _X layer in this order on the insulating substrate SUB.

  A semiconductor layer SC is formed on the undercoat layer UC. Each semiconductor layer SC is, for example, a polysilicon layer including a p-type region and an n-type region. A second electrode Cs2 is further formed on the undercoat layer UC. Here, the semiconductor layer SC and the second electrode Cs2 are integrally formed.

  The semiconductor layer SC and the second electrode Cs2 are covered with the gate insulating film GI. The gate insulating film GI can be formed using, for example, TEOS (tetraethyl orthosilicate).

  On the gate insulating film GI, scanning signal lines SL1, SL2, SL3, and SL4 are formed. Each of the scanning signal lines SL1, SL2, SL3, and SL4 extends in the row direction X of the pixel PX, which will be described later, and is aligned in the column direction Y of the pixel PX. The scanning signal lines SL1, SL2, SL3, SL4 are made of, for example, MoW.

  On the gate insulating film GI, a reset line RSL and a first electrode C1 are further formed. The reset line RSL and the first electrode C1 are made of, for example, MoW. The reset line RSL and the first electrode C1 can be formed in the same process as the scanning signal lines SL1, SL2, SL3, SL4.

  Each of the scanning signal lines SL1, SL2, SL3, and SL4 intersects the semiconductor layer SC, and these intersecting portions constitute a thin film transistor. The first electrode C1 intersects with the semiconductor layer SC, and these intersecting portions also constitute a thin film transistor.

  Specifically, the thin film transistor formed by the intersection of the scanning signal line SL1 and the semiconductor layer SC is the output switch SWa. A thin film transistor formed by the intersection of the scanning signal line SL2 and the semiconductor layer SC is an initialization switch SWc. The thin film transistor formed by the intersection of the scanning signal line SL3 and the semiconductor layer SC is the write switch SWd. A thin film transistor formed by the intersection of the scanning signal line SL4 and the semiconductor layer SC is a reset switch SWb.

The thin film transistor formed by the intersection of the first electrode C1 and the semiconductor layer SC is the drive transistor DR.
In this example, the switch SWa is a top gate type P-channel thin film transistor. The drive transistor DR and the switches SWb to SWd are top-gate N-channel thin film transistors. In FIG. 2, the portion indicated by reference numeral G is a gate electrode of the drive transistor DR formed by extending a part of the first electrode C1.

  The first electrode C1 faces the second electrode Cs2. The first electrode C1, the second electrode Cs2, and the gate insulating film GI interposed therebetween form a first capacitor portion Cs. Here, the first capacitor Cs is a capacitor.

The gate insulating film GI, the scanning signal lines SL1, SL2, SL3, SL4, the reset line RSL, and the first electrode C1 are covered with an interlayer insulating film II. The interlayer insulating film II is made of, for example, SiO _X formed by a plasma CVD method or the like.

  On the interlayer insulating film II, a video signal line VL, an initialization signal line BL, and a high potential power supply line PSL are formed. On the interlayer insulating film II, the source electrode SE and the drain electrode DE shown in FIG. 2 are further formed.

  Each video signal line VL extends in the column direction Y and is arranged in the row direction X. The video signal line VL is connected to the source electrode of the write switch SWd. In this example, the initialization signal lines BL extend in the column direction Y and are aligned in the row direction X. The initialization signal line BL is connected to the source electrode of the initialization switch SWc. In this example, the high-potential power lines PSL extend in the column direction Y and are aligned in the row direction X. The high potential power line PSL is connected to the source electrode of the output switch SWa and the second capacitor Cx. The reset line RSL is connected to the source electrode of the reset switch SWb.

  The source electrode SE and the drain electrode DE are connected to the source region and the drain region of the semiconductor layer SC through contact holes formed in the interlayer insulating film II and the gate insulating film GI, respectively. The source electrode SE and the drain electrode DE are used for connection between elements included in the pixel PX.

  A second electrode Cx2 is further formed on the interlayer insulating film II. In this embodiment, the second electrode Cx2 is formed by extending a part of the high potential power supply line PSL. The second electrode Cx2 is opposed to the first electrode C1. The first electrode C1, the second electrode Cx2, and the interlayer insulating film II interposed between them form a second capacitor portion Cx. Here, the second capacitor Cx is a capacitor.

  The video signal line VL, the initialization signal line BL, the high potential power supply line PSL, the second electrode Cx2, the source electrode SE, and the drain electrode DE have, for example, a three-layer structure of Mo / Al / Mo. These can be formed in the same process.

The video signal line VL, the initialization signal line BL, the high potential power supply line PSL, the second electrode Cx2, the source electrode SE, and the drain electrode DE are covered with the passivation film PS. The passivation film PS is made of, for example, SiN _X.

  The pixel electrodes PE are arranged on the passivation film PS. Each pixel electrode PE is connected to the source electrode SE of the drive transistor DR through a contact hole provided in the passivation film PS.

  In this example, the pixel electrode PE is a back electrode having light reflectivity. Further, the pixel electrode PE is an anode in this example. As the pixel electrode PE, for example, a structure in which a transparent conductive material such as ITO (Indium Tin Oxide) and a metal material with high light reflectance such as Ag are stacked on the back side of the transparent conductive material can be used. . Further, the pixel electrode PE and the gate electrode of the driving transistor DR are connected via the first capacitor portion Cs.

  A partition insulating layer PI is further formed on the passivation film PS. In the partition insulating layer PI, a through hole is provided at a position corresponding to the pixel electrode PE, or a slit is provided at a position corresponding to a column or row formed by the pixel electrode PE. Here, as an example, the partition insulating layer PI has a through hole at a position corresponding to the pixel electrode PE. The partition insulating layer PI is, for example, an organic insulating layer. The partition insulating layer PI is formed using, for example, a photolithography technique.

  On the pixel electrode PE, an organic layer ORG including a light emitting layer is formed as an active layer. The light emitting layer is, for example, a thin film containing a luminescent organic compound whose emission color is red, green, or blue. The organic layer ORG can further include a hole injection layer, a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like in addition to the light emitting layer.

  The partition insulating layer PI and the organic layer ORG are covered with the counter electrode CE. In this example, the counter electrode CE is an electrode connected to each other between the pixels PX, that is, a common electrode. In this example, the counter electrode CE is a cathode and a light-transmitting front electrode. The counter electrode CE is electrically connected to an electrode wiring (not shown) formed on the same layer as the video signal line VL through, for example, a contact hole provided in the passivation film PS and the partition insulating layer PI. It is connected. Each organic light emitting diode OLED includes a pixel electrode PE, an organic material layer ORG, and a counter electrode CE.

  In this embodiment, the pixel electrode PE and the counter electrode CE are connected via the third capacitor Ck, but the case where the capacitor Coled of the organic light emitting diode OLED itself is used is shown. A first electrode Ck1 that is electrically equivalent to the pixel electrode PE and a second electrode Ck2 that is electrically equivalent to the counter electrode CE are shown as electrodes of the third capacitor Ck.

  Each pixel PX includes a drive transistor DR, switches SWa to SWd, an organic light emitting diode OLED, a first capacitor Cs, a second capacitor Cx, and a third capacitor Ck. As described above, in this example, the drive transistor DR and the switches SWb to SWd are N-channel thin film transistors. The switch SWa is a P-channel thin film transistor.

  The output switch SWa, the drive transistor DR, and the organic light emitting diode OLED are connected in series in this order between the high potential power supply terminal ND1 of the high potential power supply wiring PSL and the low potential power supply terminal ND2 of the low potential power supply wiring. .

  Specifically, the source electrode of the output switch SWa is connected to the high potential power supply terminal ND1, and the counter electrode CE of the organic light emitting diode OLED is connected to the low potential power supply terminal ND2.

The gate electrode of the output switch SWa is connected to the scanning signal line SL1. The output switch SWa is turned on (conductive state) and turned off (non-conductive state) in response to the control signal BG supplied from the scanning signal line SL1. The source electrode SE of the drive transistor DR is connected to the pixel electrode PE, and the drain electrode DE of the drive transistor DR is the drain electrode of the output switch SWa.

The first capacitor unit Cs is connected between the gate electrode and the source electrode of the drive transistor DR. More specifically, the first electrode C1 of the first capacitor unit Cs is connected to the gate electrode of the driving transistor DR. The second electrode Cs2 of the first capacitor unit Cs is connected to the source electrode of the drive transistor DR. The first capacitor unit Cs holds a potential difference between the gate electrode and the source electrode of the driving transistor DR.
In addition, the first capacitor unit Cs propagates the change in the potential of the pixel electrode PE when the drive signal starts to flow to the organic light emitting diode OLED to the gate electrode of the drive transistor DR.

The second capacitor unit Cx is connected to the gate electrode of the drive transistor DR. In this embodiment, the first electrode C1 of the second capacitor unit Cx is connected to the gate electrode of the drive transistor DR. The second electrode Cx2 of the second capacitor unit Cx is connected to the high potential power supply line PSL.
Note that the second electrode Cx2 may be connected to other than the high-potential power supply wiring PSL. In this case, the second electrode Cx2 only needs to be connected to a constant-potential wiring.

  In addition, the second capacitor Cx has a change in the potential of the pixel electrode PE to the gate electrode of the drive transistor DR when the first capacitor Cs propagates the change in the potential of the pixel electrode PE to the gate electrode of the drive transistor DR. It suppresses propagation.

  The third capacitor unit Ck is connected between the pixel electrode PE and the counter electrode CE. More specifically, the first electrode Ck1 of the third capacitor Ck is connected to the pixel electrode PE, the source electrode of the driving transistor DR, and the second electrode Cs2. The second electrode Ck2 of the third capacitor unit Ck is connected to the counter electrode CE.

  The initialization switch SWc is connected between the initialization signal line BL and the gate electrode of the drive transistor DR. The gate electrode of the initialization switch SWc is connected to the scanning signal line SL2. The initialization switch SWc is turned on / off in response to the control signal IG supplied from the scanning signal line SL2. The initialization switch SWc switches whether to output the initialization voltage Vini transmitted via the initialization signal line BL.

  The write switch SWd is connected between the video signal line VL and the gate electrode of the drive transistor DR. The gate electrode of the writing switch SWd is connected to the scanning signal line SL3. The write switch SWd is turned on / off in response to the control signal SG supplied from the scanning signal line SL3. The write switch SWd switches whether to output the video signal voltage Vsig transmitted through the video signal line VL.

  The reset switch SWb is connected between the reset line RSL, the source electrode of the drive transistor DR, and the second electrode Cs2. The gate electrode of the reset switch SWb is connected to the scanning signal line SL4. The reset switch SWb is turned on / off in response to a control signal RG supplied from the scanning signal line SL4. The reset switch SWb switches whether to output a reset voltage RS transmitted via the reset line RSL. Here, the reset voltage RS is a constant voltage.

  In this example, the video signal line driver XDR and the scanning signal line driver YDR are mounted on the display panel DP by COG (chip on glass). The video signal line driver XDR and the scanning signal line driver YDR may be mounted by TCP (tape carrier package) instead of COG mounting.

  A video signal line VL is connected to the video signal line driver XDR. In this example, an initialization signal line BL and a high-potential power supply line PSL are further connected to the video signal line driver XDR. The video signal line driver XDR outputs a video signal voltage Vsig as a video signal to the video signal line VL. In addition, the video signal line driver XDR outputs an initialization voltage Vini (constant voltage) as an initialization signal to the initialization signal line BL, and supplies a power supply voltage to the high potential power supply wiring PSL.

  Scan signal lines SL1, SL2, SL3, and SL4 are connected to the scan signal line driver YDR. The scanning signal line driver YDR outputs voltage signals as scanning signals to the scanning signal lines SL1, SL2, SL3, and SL4, respectively.

Next, the operation of the pixel PX when the organic light emitting diode OLED emits light (displays an image) will be described.
In the organic light emitting display device configured as described above, the operation of the pixel PX is divided into a reset operation, a cancel operation, a write operation, and a light emission operation as a display operation. These series of operations are performed, for example, in one vertical scanning period.

  Here, FIG. 6 is a timing chart showing the ON / OFF timings of the control signals BG, IG, RG, and SG, the gate potential Vg of the drive transistor, the initialization voltage Vini, the source potential Vs of the drive transistor, and the reset voltage RS. is there.

First, the reset operation will be described.
The reset operation is performed during the reset period P1. The reset operation is performed following the previous light emission operation. The length of the reset period P1 is, for example, one horizontal scanning period (1H).

FIG. 7 shows the pixel PX in the reset period P1.
As shown in FIG. 1 to FIG. 6 and FIG. 7, in the reset operation, the scanning signal line driver YDR outputs a level (off potential) for turning off the write switch SWd, in this case, a low level control signal SG. Has been.

  In this state, a level (off potential) for turning off the output switch SWa, here, a high level control signal BG is output. At the same time, the scanning signal line driver YDR outputs a level (ON potential) for turning on the initialization switch SWc and the reset switch SWb, in this case, high level control signals IG and RG.

  For this reason, the output switch SWa is turned off, and the initialization switch SWc and the reset switch SWb are turned on. As a result, the gate potential Vg of the drive transistor DR is set to the initialization potential Vini (Vg = Vini), and the source potential Vs is set to the reset potential RS (Vs = RS). Note that the potential between Vini and RS is set so that the drive transistor DR is turned on, specifically, the value of Vini-RS is larger than the threshold voltage of the drive transistor DR.

Next, the cancel operation will be described.
The cancel operation is performed in a cancel period P2 following the reset period P1. The length of the cancellation period P2 is, for example, one horizontal scanning period.
FIG. 8 shows the pixel PX in the cancellation period P2.

  As shown in FIGS. 1 to 6 and 8, in the cancel operation, the output of the off-potential control signal SG is maintained from the scanning signal line driver YDR to the write switch SWd, and the on-potential control is performed to the initialization switch SWc. The output of the signal IG is maintained, an off-potential control signal RG is output to the reset switch SWb, and an on-potential control signal BG is output to the output switch SWa.

  For this reason, the reset switch SWb is turned off and the output switch SWa is turned on. At this time, since the driving transistor DR is in the ON state, a current flows from the high potential power supply line PSL that is higher than the reset potential RS to the source of the driving transistor DR, and the source potential of the driving transistor DR rises, and the gate of the driving transistor DR The voltage Vgs1 between the electrode and the source electrode gradually approaches the threshold voltage Vth. In order to prevent current from flowing through the organic light emitting diode OLED during the cancellation period, the potential of the low potential power supply line is set so that a reverse bias is applied to the organic light emitting diode OLED during this period.

As in this embodiment, in the cancel period P2, the voltage Vgs1 between the gate electrode and the source electrode of the drive transistor DR reaches the threshold voltage Vth, and the first capacitor Cs has a potential difference corresponding to the threshold voltage Vth. Retained (stored).
Here, the gate potential Vg, the source potential Vs, and the voltage Vgs1 between the gate electrode and the source electrode of the driving transistor DR are set as follows.

Vg = Vini
Vs = Vini−Vth
Vgs1 = Vth
Next, the write operation will be described.
The write operation is performed in the write period P3 following the cancel period P2. Here, the length of the writing period P3 is shorter than one horizontal scanning period.
Here, between the cancel period P2 and the write period P3, the off-potential control signals BG and IG are output to the output switch SWa and the initialization switch SWc, and the initialization switch SWc is switched off.

  FIG. 9 shows the pixel PX in the writing period P3.

  As shown in FIG. 1 to FIG. 6 and FIG. 9, in the write operation, output of the control signals BG, RG, and IG of the off potential from the scanning signal line driver YDR to the output switch SWa, the reset switch SWb, and the initialization switch SWc. Is maintained, and a control signal SG having an ON potential is output to the write switch SWd.

For this reason, the write switch SWd is turned on. As a result, the video signal voltage Vsig is supplied via the video signal line VL and the write switch SWd. Then, the gate potential Vg is displaced by ΔVsig. Further, the source potential Vs is displaced by ΔVsig × Cs / (Ck + Cs). The capacity of the first capacitor Cs is Cs, and the capacity of the third capacitor Ck is Ck.
Here, the gate potential Vg, the source potential Vs, and the voltage Vgs2 between the gate electrode and the source electrode of the driving transistor DR are set as follows.

Vg = Vini + ΔVsig
Vs = Vini−Vth + ΔVsig × Cs / (Ck + Cs)
Vgs2 = Vth + ΔVsig × Ck / (Ck + Cs)
Thereafter, an off-potential control signal SG is output to the write switch SWd. For this reason, the write switch SWd is turned off. Accordingly, the gate-source voltage of the driving transistor DR corresponding to the video signal is held in the first capacitor unit Cs with the threshold voltage Vth as a base point.

Next, the light emission operation will be described.
The light emission operation is performed in a light emission period P4 as a display period after the writing period P3 has elapsed. The length of the light emission period P4 is, for example, until one vertical scanning period ends (until the next reset operation is started).
FIG. 10 shows the pixel PX in the light emission period P4.

  As shown in FIGS. 1 to 6 and FIG. 10, in the light emission operation, the scanning signal line driver YDR outputs the control signals RG, IG, and SG having off potentials to the reset switch SWb, the initialization switch SWc, and the writing switch SWd. Is maintained, and the on-potential control signal BG is output to the output switch SWa.

  For this reason, the output switch SWa is turned on. Thereby, a drive signal is output from the drive transistor DR to the organic light emitting diode OLED. In other words, the organic light emitting diode OLED is given a drive current according to the gradation of the image.

Here, the operation at the timing T1 when the output switch SWa is turned on will be described.
The drive unit 10 turns on the output switch SWa to change the potential of the pixel electrode PE when the drive signal starts to flow through the organic light emitting diode OLED (timing T1) via the first capacitor unit Cs. Propagate to the gate electrode. The second capacitor Cx suppresses the propagation of the potential change of the pixel electrode PE to the gate electrode of the drive transistor DR.

  At timing T1, the potential of the pixel electrode PE of the organic light emitting diode OLED rises to a potential at which a light emission current corresponding to the gate potential of the driving transistor DR can flow. The potential ΔVa of the pixel electrode PE rising at this time is larger as the organic light emitting diode OLED connected to the driving transistor DR having higher mobility.

This is because when the gate potential of the drive transistor DR is changed by the same amount after the cancel operation, only the magnitude of the mobility leads to the magnitude of the light emission current. As the potential of the pixel electrode PE increases, the source potential Vs is displaced by ΔVa. Further, the gate potential Vg is displaced by ΔVa × Cs / (Cx + Cs), and this displacement is larger as the driving transistor DR has a higher mobility. Note that the capacity of the second capacitor Cx is Cx.
Here, the gate potential Vg, the source potential Vs, and the voltage Vgs3 between the gate electrode and the source electrode of the driving transistor DR are set as follows.

Vg = Vini + ΔVsig + ΔVa × Cs / (Cx + Cs)
Vs = Vini−Vth + ΔVsig × Cs / (Ck + Cs) + ΔVa
Vgs3 = Vth + ΔVsig × Ck / (Ck + Cs) −ΔVa × Cx / (Cx + Cs)
Therefore, the drive transistor DR having a high mobility (ΔVa) is closer to the off-direction than the drive transistor DR having a low mobility (ΔVa), and the compensation of the mobility variation is an automatic adjustment of the gate potential. Will be done in the form.

  That is, the plurality of drive transistors DR included in the organic light emitting display device are formed with variations in characteristics due to manufacturing. In order to obtain the gradation of an image based on the threshold voltage Vth by the operation in the cancel period and the write period. The gate potential of the driving transistor DR can be displaced by this potential, and the mobility variation can be compensated by the operation at the timing T1. In other words, the gate potential of the drive transistor DR is set to a state in which a desired light emission current can flow at a desired timing.

  According to the organic light emitting display device and the organic light emitting display device driving method configured as described above, the organic light emitting display device includes a plurality of video signal lines VL, a plurality of initialization signal lines BL, and a plurality of pixels PX. And a drive unit 10. Each pixel PX includes a drive transistor DR, switches SWa to SWb, an organic light emitting diode OLED, a first capacitor Cs, a second capacitor Cx, and a third capacitor Ck.

  The operations of the pixel PX performed by the drive unit 10 are a reset operation, a cancel operation, a write operation, and a light emission operation. By the cancel operation, the voltage between the gate electrode and the source electrode of the drive transistor DR can reach the threshold voltage, and thus the influence of the threshold voltage variation of the drive transistor DR can be suppressed.

  Further, at the timing T1, the change in the potential of the pixel electrode PE can be propagated to the gate electrode of the driving transistor DR via the first capacitor portion Cs. At this time, the second capacitor Cx can make the rise in the gate potential lower than the rise in the source potential. Specifically, the increase in gate potential can be suppressed to Cs / (Cx + Cs) times. Thereby, variation in mobility of the drive transistor DR can be compensated.

  As described above, both the influence of the threshold voltage variation and the mobility variation can be suppressed. In addition, it is possible to obtain an organic light emitting display device that is excellent in gradation reproducibility and capable of suppressing luminance unevenness and a driving method of the organic light emitting display device.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some components may be added to all the components shown in the embodiment.

  For example, as shown in an equivalent circuit diagram in FIG. 11 and a pixel plan view in FIG. 12, the organic light emitting display device may add a capacitor Cextra other than the capacitor Coled of the organic light emitting diode OLED itself as the third capacitor Ck. . The capacitor Cextra is formed by the potential power supply line SLa and the second electrode Cs2. In this case, it is possible to adjust the source potential displacement amount of the driving transistor DR at the time of writing the video signal by the value of the added capacitance Cextra, and it becomes easy to adjust the W / L ratio of the driving transistor DR.

  Further, since the electrode on the side not equivalent to the pixel electrode PE of the capacitor Cextra to be added may be set at a fixed potential, other than the counter electrode CE as shown in the equivalent circuit diagram in FIG. 13 and the pixel plan view in FIG. It may be connected to the high potential power supply line PSL.

Even if the driving method of the present invention is applied to the voltage signal type pixel PX having the same threshold cancel function as that of the above-described embodiment, it can be expected to obtain the same effect as that of the above-described embodiment.
The switch SWa may be composed of an N-channel transistor. The switches SWb to SWd may be composed of P-channel transistors.

  DESCRIPTION OF SYMBOLS 10 ... Drive part, DP ... Display panel, XDR ... Video signal line driver, YDR ... Scanning signal line driver, VL ... Video signal line, BL ... Initialization signal line, PSL ... High potential power supply wiring, SLa ... Low potential power supply wiring , SL1, SL2, SL3, SL4 ... scanning signal line, ND1 ... high potential power supply terminal, ND2 ... low potential power supply terminal, PX ... pixel, OLED ... organic light emitting diode, DR ... drive transistor, SWa ... output switch, SWb ... reset Switch, SWc ... Initialization switch, SWd ... Write switch, Cs ... First capacitor, C1 ... First electrode, Cs2 ... Second electrode, Cx ... Second capacitor, Cx2 ... Second electrode, Ck ... Third capacitor Part, Ck1 ... first electrode, Ck2 ... second electrode, Coled ... capacitance, PE ... pixel electrode, ORG ... organic layer, CE ... counter electrode, P1 ... reset period, P2 ... ki Nseru period, P3 ... write period, P4 ... light-emitting period, T1 ... timing, BG, IG, RG, SG ... control signal, Vsig ... video signal voltage.

Claims (5)

Multiple video signal lines;
A plurality of pixels connected to each of the video signal lines,
Each pixel is
An organic light emitting diode including a cathode connected to a low-potential power line, an anode disposed opposite to the cathode, and an organic material layer sandwiched between the cathode and the anode;
An N-channel driving transistor including a drain electrode connected to a high-potential power wiring, a source electrode connected to the anode of the organic light emitting diode, and a gate electrode;
An output switch connected between the high-potential power line and the drain electrode of the driving transistor;
A first capacitor including a first electrode connected to a gate electrode of the driving transistor and a second electrode connected to an anode of the organic light emitting diode;
An active matrix organic light emitting display device comprising: a second capacitor portion including an electrode connected to the gate electrode of the driving transistor.   The active matrix organic light emitting display device according to claim 1, further comprising a third capacitor connected between an anode and a cathode of the organic light emitting diode. A driving unit connected to the plurality of pixels and the plurality of video signal lines;
The drive unit is
During the cancellation period, the voltage between the gate electrode and the source electrode of the driving transistor is set to the threshold voltage of the driving transistor,
In the light emission period after the cancellation period, a drive signal is output from the drive transistor to the organic light emitting diode, and a change in the potential of the anode when the drive signal starts to flow through the organic light emitting diode is detected in the first capacitor unit. 2. The active matrix organic light-emitting display according to claim 1, wherein the second capacitor portion suppresses propagation of a change in potential of the anode to the gate electrode. apparatus. A plurality of video signal lines; and a plurality of pixels connected to the video signal lines, each pixel including a cathode connected to a low-potential power line, an anode disposed opposite to the cathode, and the cathode And an organic light emitting diode including an organic material layer sandwiched between anodes, a drain electrode connected to a high-potential power wiring, a source electrode connected to the anode of the organic light emitting diode, and an N channel type including a gate electrode A drive transistor; an output switch connected between the high-potential power line and the drain electrode of the drive transistor; a first electrode connected to the gate electrode of the drive transistor; and a second electrode connected to the anode of the organic light emitting diode. An active capacitor having a first capacitor portion including an electrode and a second capacitor portion including an electrode connected to the gate electrode of the driving transistor. In the driving method of Rikusu organic light emitting display device,
During the light emission period, a drive signal is output from the drive transistor to the organic light emitting diode,
A change in the potential of the anode when the driving signal starts to flow through the organic light emitting diode is propagated to the gate electrode of the driving transistor through the first capacitor, and at this time, the gate electrode is driven by the second capacitor. A method of driving an active matrix organic light emitting display device that suppresses propagation of a change in potential of the anode to the substrate.   5. The driving method of an active matrix organic light emitting display device according to claim 4, wherein a voltage between the gate electrode and the source electrode of the driving transistor is set to a threshold voltage of the driving transistor in a cancel period before the light emitting period.

Images