JP2010114369A - Nonvolatile semiconductor storage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable and inexpensive nonvolatile semiconductor storage. <P>SOLUTION: A memory string MS includes: a U-shaped semiconductor layer 35 including a pair of columnar sections 35a; a memory gate insulating layer 34 formed while surrounding the side of the columnar section 35a; and word line conductive layers 32a-32d formed while surrounding the memory gate insulating layer 34. A drain-side selection transistor SDTr includes: a drain-side columnar semiconductor layer 57a extended upward from upper surfaces of the columnar sections 35a; a drain-side gate insulating layer 56a formed while surrounding the side of the drain-side columnar semiconductor layer 57a; and a drain-side conductive layer 52a formed while surrounding the drain-side gate insulating layer 56a. A dummy transistor DTr includes a dummy word line conductive layer 41 formed while surrounding the boundary between the U-shaped semiconductor layer 35 and the drain-side columnar semiconductor layer 57a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device capable of electrically rewriting data.

  Conventionally, LSIs have been formed by integrating elements in a two-dimensional plane on a silicon substrate. In order to increase the storage capacity of a memory, it is common to reduce the size of one element (miniaturize), but in recent years, the miniaturization has become costly and technically difficult. For miniaturization, photolithography technology needs to be improved, but the cost required for the lithography process is steadily increasing. Even if miniaturization is achieved, it is expected that physical limits such as breakdown voltage between elements will be reached unless the drive voltage is scaled. That is, there is a high possibility that operation as a device is difficult.

  Therefore, in recent years, a semiconductor memory device in which memory cells are arranged three-dimensionally has been proposed in order to increase the degree of integration of the memory (see Patent Document 1).

  One conventional semiconductor memory device in which memory cells are arranged three-dimensionally is a semiconductor memory device using a transistor having a cylindrical structure (Patent Document 1). In a semiconductor memory device using a transistor having a cylindrical structure, a multi-layered conductive layer to be a gate electrode and a pillar-shaped columnar semiconductor are provided. The columnar semiconductor functions as a channel (body) portion of the transistor. A memory gate insulating layer is provided around the columnar semiconductor. A structure including these conductive layers, columnar semiconductors, and memory gate insulating layers is called a memory string.

  In general, a selection transistor is provided above or below the memory string. The selection transistor includes a columnar semiconductor and a gate insulating layer formed around the columnar semiconductor. The columnar semiconductor of the selection transistor is formed so as to be in contact with the upper surface or the lower surface of the columnar semiconductor of the memory string.

That is, a contact resistance is generated between the memory string and the select transistor due to the boundary between the columnar semiconductors. Thereby, the cell current at the time of reading cannot be made sufficiently high. On the other hand, it is also desired to maintain the cutoff characteristics of the selection transistor.
JP 2007-266143 A

  The present invention provides a highly reliable nonvolatile semiconductor memory device.

  A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series, select transistors connected to both ends of the memory string, and the memory A dummy transistor provided between a string and the selection transistor is provided, and the memory string is formed so as to surround a first semiconductor layer having a columnar portion extending in a direction perpendicular to a substrate and a side surface of the columnar portion. And a first conductive layer that is formed so as to surround the side surface of the columnar portion and the charge storage layer and functions as a control electrode of the memory cell, and the selection transistor includes the columnar portion of the columnar portion. A second semiconductor layer extending in the vertical direction from the upper surface or the lower surface, and a gate formed so as to surround a side surface of the second semiconductor layer. And a second conductive layer formed to surround the side surface of the second semiconductor layer and the gate insulating layer and function as a control electrode of the selection transistor, and the dummy transistor includes the first semiconductor A layer, the second semiconductor layer, the charge storage layer, the gate insulating layer, a boundary between the first semiconductor layer and the second semiconductor layer, and a boundary between the charge storage layer and the gate insulating layer. And a third conductive layer functioning as a control electrode of the dummy transistor.

  The present invention can provide a nonvolatile semiconductor memory device having high reliability.

  Hereinafter, an embodiment of a nonvolatile semiconductor memory device according to the present invention will be described with reference to the drawings.

[First Embodiment]
(Configuration of Nonvolatile Semiconductor Memory Device 100 according to First Embodiment)
FIG. 1 is a schematic view of a nonvolatile semiconductor memory device 100 according to the first embodiment of the present invention. As shown in FIG. 1, the nonvolatile semiconductor memory device 100 according to the first embodiment mainly includes a memory transistor region 12, a word line drive circuit 13, a source side select gate line (SGS) drive circuit 14, and a drain side select gate. A line (SGD) drive circuit 15, a sense amplifier 16, a source line drive circuit 17, a back gate transistor drive circuit 18, and a dummy word line drive circuit 19 are included. The memory transistor region 12 includes a memory transistor that stores data. The word line drive circuit 13 controls the voltage applied to the word line WL. The source side select gate line (SGS) drive circuit 14 controls the voltage applied to the source side select gate line SGS. The drain side select gate line (SGD) drive circuit 15 controls the voltage applied to the drain side select gate line (SGD). The sense amplifier 16 amplifies the potential read from the memory transistor. The source line driver circuit 17 controls the voltage applied to the source line SL. The back gate transistor drive circuit 18 controls the voltage applied to the back gate line BG. The dummy word line drive circuit 19 controls the voltage applied to the dummy word line DWL. In addition to the above, the nonvolatile semiconductor memory device 100 according to the first embodiment includes a bit line driving circuit that controls a voltage applied to the bit line BL. (Not shown).

  FIG. 2 is a schematic perspective view of a part of the memory transistor region 12 of the nonvolatile semiconductor memory device 100 according to the first embodiment. In the first embodiment, the memory transistor region 12 has m × n memory cells MS, source side select transistors SSTr, and drain side select transistors SDTr (m and n are natural numbers). FIG. 2 shows an example of m = 6 and n = 2.

  In the nonvolatile semiconductor memory device 100 according to the first embodiment, the memory transistor region 12 is provided with a plurality of memory strings MS. As will be described in detail later, the memory string MS has a configuration in which a plurality of electrically rewritable memory transistors MTr1 to MTr8 are connected in series. As shown in FIGS. 1 and 2, the memory transistors MTr1-MTr8 constituting the memory string MS are formed by stacking a plurality of semiconductor layers.

  Each memory string MS includes a U-shaped semiconductor SC, word lines WL1 to WL8, and a back gate line BG.

  The U-shaped semiconductor SC is formed in a U shape when viewed from the row direction. That is, the U-shaped semiconductor SC has a pair of columnar portions CL extending in a substantially vertical direction with respect to the semiconductor substrate Ba, and a connecting portion JP formed to connect the lower ends of the pair of columnar portions CL. Note that the columnar portion CL may be cylindrical or prismatic. Further, the columnar portion CL may be a columnar shape having a stepped shape. Here, the row direction is a direction orthogonal to the stacking direction, and a column direction to be described later is a direction orthogonal to the stacking direction and the row direction.

  The U-shaped semiconductor SC is arranged so that a straight line connecting the central axes of the pair of columnar portions CL is parallel to the column direction. Further, the U-shaped semiconductor SC is arranged in a matrix form in a plane constituted by the row direction and the column direction.

  The word lines WL1 to WL8 in each layer have a shape extending in parallel to the row direction. The word lines WL <b> 1 to WL <b> 8 in each layer are repeatedly formed in a line with a predetermined pitch in the column direction and insulated from each other. The word line WL1 is formed in the same layer as the word line WL8. Similarly, the word line WL2 is formed in the same layer as the word line WL7, the word line WL3 is formed in the same layer as the word line WL6, and the word line WL4 is formed in the same layer as the word line WL5.

  The gates of the memory transistors MTr1-MTr8 provided at the same position in the column direction and arranged in the row direction are connected to the same word lines WL1-WL8. The end portions in the row direction of the respective word lines WL1 to WL8 are formed in a step shape. Each of the word lines WL1 to WL8 is formed so as to surround a plurality of columnar portions CL arranged in the row direction.

  As shown in FIG. 3, an ONO (Oxide-Nitride-Oxide) layer NL is formed between the word lines WL1 to WL8 and the columnar part CL. The ONO layer NL includes a tunnel insulating layer TI in contact with the columnar portion CL, a charge storage layer EC in contact with the tunnel insulating layer TI, and a block insulating layer BI in contact with the charge storage layer EC. The charge storage layer EC has a function of storing charges. In other words, the charge storage layer EC is formed so as to surround the side surface of the columnar part CL. Each word line WL1 to WL8 is formed so as to surround the charge storage layer EC.

  The drain side select transistor SDTr has a columnar semiconductor SCa and a drain side select gate line SGD. The columnar semiconductor SCa is formed to extend upward from the upper surface of one columnar portion CL in a direction perpendicular to the substrate Ba. The drain side select gate line SGD is provided above the uppermost word line WL1. The drain side select gate line SGD has a shape extending in parallel to the row direction. The drain side select gate lines SGD are repeatedly formed in a line so as to alternately provide a predetermined pitch in the column direction and sandwich the source side select gate lines SGS described later. The drain side select gate line SGD is formed so as to surround a plurality of columnar semiconductors SCa arranged in the row direction. As shown in FIG. 3, a gate insulating layer DGI is formed between the drain side select gate line SGD and the columnar semiconductor SCa. In other words, each drain-side selection gate line SGD is formed so as to surround the gate insulating layer DGI.

  The source side select transistor SSTr has a columnar semiconductor SCb and a source side select gate line SGS. The columnar semiconductor SCb is formed to extend upward from the upper surface of the other columnar portion CL. The source side select gate line SGS is provided above the uppermost word line WL8. The source side select gate line SGS has a shape extending in parallel to the row direction. The source side selection gate lines SGS are provided in a predetermined pitch in the column direction, and are repeatedly formed in a line shape with the drain side selection gate lines SGD interposed therebetween. The source side select gate line SGS is formed so as to surround the columnar semiconductors SCb arranged in a plurality of rows in the row direction. As shown in FIG. 3, a gate insulating layer SGI is formed between the source side select gate line SGS and the columnar semiconductor SCb. In other words, each drain-side selection gate line SGS is formed so as to surround the gate insulating layer SGI.

  The dummy word line DWL1 is formed between the drain side select gate line SGD and the word line WL1. The dummy word line WL1 has a shape extending in parallel to the row direction. The dummy word line DWL1 is formed so as to surround the columnar semiconductors SCa and the columnar portions CL arranged in a plurality of rows in parallel in the row direction. As shown in FIG. 3, a gate insulating layer DGI is formed between the dummy word line DWL1 and the columnar semiconductor SCa. An ONO layer NL is formed between the dummy word line DWL1 and the columnar part CL.

  The dummy word line DWL2 is formed between the source side select gate line SGS and the word line WL8. Like the word line WL, the dummy word line WL2 has a shape extending in parallel to the row direction. The dummy word line DWL2 is formed so as to surround the columnar semiconductors SCb and the columnar portions CL arranged in a plurality of rows in parallel in the row direction. As shown in FIG. 3, a gate insulating layer SGI is formed between the dummy word line DWL2 and the columnar semiconductor SCb. Further, an ONO layer NL is formed between the dummy word line DWL2 and the columnar part CL.

  The back gate line BG is formed to extend two-dimensionally in the row direction and the column direction so as to cover the lower portions of the plurality of connecting portions JP. As shown in FIG. 3, the ONO layer NL described above is formed between the back gate line BG and the connecting portion JP.

  Returning to FIG. 2 again, the description will be continued. The columnar semiconductor SCb is formed adjacent to the column direction. A source line SL is connected to the upper ends of the pair of columnar semiconductors SCb. The source line SL is provided in common for the pair of columnar semiconductors SCb.

  A bit line BL is formed at the upper end of the columnar semiconductor SCa surrounded by the drain side select gate line SGD via the plug line PL. Each bit line BL is formed to be positioned above the source line SL. Each bit line BL is repeatedly formed in a line extending in the column direction with a predetermined interval in the row direction.

  Next, a circuit configuration including the memory string MS, the drain side selection transistor SDTr, and the source side selection transistor SSTr in the first embodiment will be described with reference to FIGS. FIG. 4 is a partial circuit diagram of the nonvolatile semiconductor memory device 100 according to the first embodiment.

  As shown in FIGS. 2 to 4, in the first embodiment, each memory string MS is formed by connecting eight electrically rewritable memory transistors MTr <b> 1 to MTr <b> 8 in series. The source side select transistor SSTr and the drain side select transistor SDTr are connected to both ends of the memory string MS. The back gate transistor BGTr is provided in the memory string MS (between the memory transistor MTr4 and the memory transistor MTr5).

  Each memory transistor MTr includes a columnar portion CL, an ONO layer NL (charge storage layer EC), and a word line WL. The word line WL functions as a control gate electrode of the memory transistor MTr.

  The drain side select transistor SDTr is configured by a columnar semiconductor SCa, a gate insulating layer DGI, and a drain side select gate line SGD. The drain side select gate line SGD functions as a control gate electrode of the drain side select transistor SDTr.

  The source side select transistor SSTr is configured by a columnar semiconductor SCb, a gate insulating layer SGI, and a source side select gate line SGS. The source side select gate line SGS functions as a control gate electrode of the source side select transistor SSTr.

  The dummy transistor DTr1 includes a columnar semiconductor SCa, a columnar portion CL, an ONO layer NL (charge storage layer EC), a gate insulating layer DGI, and a dummy word line DWL1. The dummy word line WL1 functions as a control gate electrode of the dummy transistor DTr1.

  The dummy transistor DTr2 includes a columnar semiconductor SCb, a columnar portion CL, an ONO layer NL (charge storage layer EC), a gate insulating layer SGI, and a dummy word line DWL2. The dummy word line WL2 functions as a control gate electrode of the dummy transistor DTr2.

  The back gate transistor BGTr is composed of a connecting portion JP, an ONO layer NL (charge storage layer EC), and a back gate line BG. The back gate line BG functions as a control gate electrode of the back gate transistor BGTr.

(Specific Configuration of Nonvolatile Semiconductor Memory Device 100 According to First Embodiment)
Next, a specific configuration of the nonvolatile semiconductor memory device 100 according to the first embodiment will be described with reference to FIG. FIG. 5 is a cross-sectional view of the memory transistor region 12 of the nonvolatile semiconductor memory device 100 according to the first embodiment.

  As shown in FIG. 5, the memory transistor region 12 includes a back gate transistor layer 20, a memory transistor layer 30, a dummy transistor layer 40, a selection transistor layer 50, and a wiring layer 60 sequentially from the semiconductor substrate Ba in the stacking direction. Have. The back gate transistor layer 20 functions as the above-described back gate transistor BGTr. The memory transistor layer 30 functions as the memory transistors MTr1 to MTr8 described above. The dummy transistor layer 40 functions as the above-described dummy transistors DTr1 and DTr2. The selection transistor layer 50 functions as the above-described source side selection transistor layer SSTr and drain side selection transistor SDTr.

  The back gate transistor layer 20 includes a back gate insulating layer 21 and a back gate conductive layer 22 that are sequentially stacked on the semiconductor substrate Ba. The back gate insulating layer 21 and the back gate conductive layer 22 are formed to extend in the row direction and the column direction up to the end of the memory transistor region 12.

  The back gate conductive layer 22 is formed to the same height as the upper surface of the connecting portion 35b so as to cover the lower surface and side surfaces of the connecting portion 35b of the U-shaped semiconductor layer 35 described later.

The back gate insulating layer 21 is composed of silicon oxide (SiO ₂ ). The back gate conductive layer 22 is composed of polysilicon (p-Si).

  The back gate transistor layer 20 has a back gate hole 23 formed so as to excavate the back gate conductive layer 22. The back gate hole 23 is configured by an opening that is short in the row direction and long in the column direction. The back gate holes 23 are formed at predetermined intervals in the row direction and the column direction. In other words, the back gate holes 23 are formed in a matrix in a plane including the row direction and the column direction.

  The memory transistor layer 30 includes first to fifth inter-word line insulating layers 31 a to 31 e and first to fourth word line conductive layers 32 a to 32 d that are alternately stacked on the back gate conductive layer 22.

  The first to fifth inter-wordline insulating layers 31a to 31e and the first to fourth wordline conductive layers 32a to 32d are repeatedly formed in a line shape so as to extend in the row direction and at a predetermined interval in the column direction. Yes. Although not shown in FIG. 5, the first to fifth inter-wordline insulating layers 31a to 31e and the first to fourth wordline conductive layers 32a to 32d are processed in a stepped manner at the end in the row direction. Yes.

The first to fifth inter-wordline insulating layers 31a to 31e are composed of silicon oxide (SiO ₂ ). The first to fourth word line conductive layers 32a to 32d are made of polysilicon (p-Si).

  The memory transistor layer 30 has a memory hole 33 formed so as to penetrate the first to fifth inter-wordline insulating layers 31a to 31e and the first to fourth wordline conductive layers 32a to 32d. The memory holes 33 are formed so as to be aligned with positions in the vicinity of both ends of each back gate hole 23 in the column direction.

  The dummy transistor layer 40 includes a dummy word line conductive layer 41 and a dummy inter-word line insulating layer 42 on the fifth inter-word line insulating layer 31e. The dummy word line conductive layer 41 and the dummy word line insulating layer 42 are repeatedly formed in a line shape so as to extend in the row direction and at a predetermined interval in the column direction. The dummy word line conductive layer 41 includes a boundary between a U-shaped semiconductor layer 35 and a drain side columnar semiconductor layer 57a (source side columnar semiconductor layer 57b) described later, and a memory gate insulating layer 34 (charge storage layer) and a drain side gate. It is formed so as to surround the boundary with the insulating layer 56a (source side gate insulating layer 56b).

The dummy word line conductive layer 41 is made of polysilicon (p-Si). The dummy word line insulating layer 42 is made of silicon oxide (SiO ₂ ).

  The dummy transistor layer 40 has a dummy hole 43 formed so as to penetrate the dummy word line conductive layer 41 and the dummy word line insulating layer 42. The dummy hole 43 is integrally formed continuously with the memory hole 33.

  The back gate transistor layer 20, the memory transistor layer 30, and the dummy transistor layer 40 have a memory gate insulating layer 34, a U-shaped semiconductor layer (memory semiconductor layer) 35, and a groove 73. The memory gate insulating layer 34 is formed on the sidewall of the dummy hole 43, the sidewall of the memory hole 33, and the sidewall of the back gate hole 23. As shown in FIG. 6, the memory gate insulating layer 34 is formed to a height between the lower surface and the upper surface of the dummy word line conductive layer 41. The memory gate insulating layer 34 has a thickness of 15 nm, for example.

  The U-shaped semiconductor layer 35 is formed in a U shape when viewed from the row direction. The U-shaped semiconductor layer 35 is formed so as to be in contact with the memory gate insulating layer 34 and to fill the back gate hole 23 and the memory hole 33. The U-shaped semiconductor layer 35 includes a pair of columnar portions 35a extending in a direction perpendicular to the semiconductor substrate Ba when viewed from the row direction, and a connecting portion 35b formed to connect the lower ends of the pair of columnar portions 35a. As shown in FIG. 6, the U-shaped semiconductor layer 35 is formed to a height between the lower surface and the upper surface of the dummy word line conductive layer 41.

Memory gate insulating layer 34, silicon oxide (SiO ₂₎ - silicon nitride (SiN) - are composed of silicon oxide (SiO _2). The U-shaped semiconductor layer 35 is configured by polysilicon (p-Si) (n-type semiconductor) doped with phosphorus (P). The U-shaped semiconductor layer 35 has an effective impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more. Here, the effective impurity concentration is a concentration obtained by subtracting the p-type impurity concentration from the n-type impurity concentration.

  The groove 73 penetrates the first to fifth inter-word line insulating layers 31a to 31e, the first to fourth word line conductive layers 32a to 32d, the dummy word line conductive layer 41, and the dummy inter-word line insulating layer 42. Is formed. The groove 73 is formed between the memory hole 33 and the dummy hole 43 arranged in the column direction. The groove 73 is formed to extend in the row direction.

  In the configuration of the back gate transistor layer 20 and the memory transistor layer 30, the back gate conductive layer 22 functions as a gate electrode of the back gate transistor BGTr. The back gate conductive layer 22 functions as a back gate line BG. The first to fourth word line conductive layers 32a to 32d function as gate electrodes of the memory transistors MTr1 to MTr8, and the first to fourth word line conductive layers 32a to 32d function as word lines WL1 to WL8.

  The select transistor layer 50 includes an interlayer insulating layer 51, a drain side conductive layer 52 a, a source side conductive layer 52 b, a select transistor insulating layer 53, and an interlayer insulating layer 54 deposited on the memory transistor layer 30. The interlayer insulating layer 51 is formed so as to be in contact with the side surface of the groove 73 and the upper surface of the dummy word line insulating layer 42. The drain-side conductive layer 52a, the source-side conductive layer 52b, and the select transistor insulating layer 53 are provided on the interlayer insulating layer 51, and are repeatedly formed in a line shape so as to extend in the row direction and at a predetermined interval in the column direction. ing.

  Similarly to the first to fourth word line conductive layers 32a to 32d, the drain side conductive layer 52a is formed to extend in the row direction with a predetermined pitch in the column direction. Similarly, the source-side conductive layers 52b are formed to extend in the row direction with a predetermined pitch in the column direction. The pair of drain side conductive layers 52a and the pair of source side conductive layers 52b are alternately formed in the column direction. The select transistor insulating layer 53 is formed between the drain side conductive layer 52a and the source side conductive layer 52b formed as described above. The interlayer insulating layer 54 is formed on the drain side conductive layer 52 a, the source side conductive layer 52 b, and the select transistor insulating layer 53.

The drain side conductive layer 52a and the source side conductive layer 52b are made of polysilicon (p-Si) (P + type semiconductor) doped with boron (B). The interlayer insulating layers 51 and 54 and the select transistor insulating layer 53 are composed of silicon oxide (SiO ₂ ).

  The select transistor layer 50 includes a drain side hole 55a, a source side hole 55b, and a source line wiring groove 55c.

  The drain side hole 55 a is formed so as to penetrate the interlayer insulating layer 54, the drain side conductive layer 52 a, and the interlayer insulating layer 51. The source side hole 55 b is formed so as to penetrate the interlayer insulating layer 54, the source side conductive layer 52 b, and the interlayer insulating layer 51. The drain side hole 55 a and the source side hole 55 b are formed at positions aligned with the memory hole 33 and the dummy hole 43. The source line wiring groove 55c is formed so as to dig the interlayer insulating layer 54 above the source side hole 55b adjacent in the column direction. The source line wiring groove 55c is formed so as to connect the upper portions of the source side holes 55b adjacent in the column direction and extend in the row direction.

  The selection transistor layer 50 and the dummy transistor layer 40 include a drain side gate insulating layer 56a, a source side gate insulating layer 56b, a drain side columnar semiconductor layer 57a, and a source side columnar semiconductor layer 57b.

  The drain side gate insulating layer 56 a is formed on the side wall of the drain side hole 55 a and the side wall of the dummy hole 43. The source side gate insulating layer 56 b is formed on the side wall of the source side hole 45 b and the side wall of the dummy hole 43. The drain side gate insulating layer 56 a and the source side gate insulating layer 56 b are formed in contact with the upper surface of the memory gate insulating layer 34. That is, the drain side gate insulating layer 56a and the source side gate insulating layer 56b are formed from the height between the lower surface and the upper surface of the dummy word line conductive layer 41 to the upper layer.

  As shown in FIG. 6, the drain side gate insulating layer 56a (source side gate insulating layer 56b) is formed so as to cover the side surface of the drain side columnar semiconductor layer 57a (source side columnar semiconductor layer 57b) and a part of the bottom surface thereof. Has been. The drain side gate insulating layer 56a (source side gate insulating layer 56b) is formed so as to cover a part of the side surface and a part of the upper surface of the columnar part 35a. The drain side gate insulating layer 56a is a region in contact with the side surface of the drain side columnar semiconductor layer 57a and has a thickness of 10 nm, for example. The drain side gate insulating layer 56a is a region in contact with the side surface of the U-shaped semiconductor layer 35 and has a thickness of 15 nm, for example. The source side gate insulating layer 56b has the same thickness as the drain side gate insulating layer 56b. That is, the drain side gate insulating layer 57a (source side columnar semiconductor layer 57b) in the vicinity of the dummy word line conductive layer 41 is the drain side gate insulating layer 57a (source in the vicinity of the drain side conductive layer 52a (source side conductive layer 52b). It is thicker than the side columnar semiconductor layer 57b).

  The drain side columnar semiconductor layer 57a is formed so as to be in contact with the drain side gate insulating layer 56a from the dummy hole 43 to the drain side hole 55a. The source side columnar semiconductor layer 57b is formed so as to be in contact with the source side gate insulating layer 56b from the dummy hole 43 to the source side hole 56b. The drain side columnar semiconductor layer 57 a and the source side columnar semiconductor layer 57 b are formed so as to contact the upper surface of the columnar portion 35 a of the U-shaped semiconductor layer 35. That is, the drain side columnar semiconductor layer 57a and the source side columnar semiconductor layer 57b are formed from the height between the lower surface and the upper surface of the dummy word line conductive layer 41 to the upper layer.

  Further, the select transistor layer 50 includes a plug conductive layer 58a and a source conductive layer 58b in the drain side hole 55a and the source wiring groove 55c.

  The plug conductive layer 58a is formed in contact with the upper surface of the drain side columnar semiconductor layer 57a. The plug conductive layer 58 a is formed so as to fill the drain side hole 55 a up to the upper surface of the select transistor layer 50. The source conductive layer 58b is formed in contact with the upper surface of the source side columnar semiconductor layer 57b. The source side columnar semiconductor layer 57b is formed so as to fill the source side hole 55b and the source line wiring trench 55c up to the upper surface of the select transistor layer 50.

The drain side gate insulating layer 56a and the source side gate insulating layer 56b are made of silicon oxide (SiO ₂ ). The drain side columnar semiconductor layer 57a and the source side columnar semiconductor layer 57b are formed of polysilicon (p-Si) (n-type semiconductor) doped with a minute amount of phosphorus (P), or polysilicon not doped with impurities (Si ) (I-type semiconductor). The drain side columnar semiconductor layer 57a and the source side columnar semiconductor layer 57b have an effective impurity concentration of 3 × 10 ¹⁷ cm ⁻³ or less. That is, the effective impurity concentration of the drain side columnar semiconductor layer 57 a and the source side columnar semiconductor layer 57 b is lower than the effective impurity concentration of the U-shaped semiconductor layer 35. The plug conductive layer 58a and the source conductive layer 58b are composed of titanium (Ti) -titanium nitride (TiN) -tungsten (W).

  In the configuration of the dummy transistor layer 40, the dummy word line conductive layer 41 functions as a gate electrode of the dummy transistor DTr. The dummy word line conductive layer 41 functions as a dummy word line DWL.

  In the configuration of the select transistor layer 50, the drain side conductive layer 52a functions as a gate electrode of the drain side select transistor layer SDTr. The drain side conductive layer 52a functions as the drain side selection line SGD. The source side conductive layer 52b functions as a gate electrode of the source side select transistor SSTr. The source side conductive layer 52b functions as the source side selection line SGS. The source conductive layer 58b functions as the source line SL.

  The wiring layer 60 includes an interlayer insulating layer 61, a hole 61 a, a plug layer 61 b, and a bit line layer 62. The interlayer insulating layer 61 is formed on the upper surface of the select transistor layer 50. The hole 61a is formed at a position passing through the interlayer insulating layer 61 and aligned with the drain side hole 55a. The plug layer 61b is formed up to the upper surface of the interlayer insulating layer 61 so as to fill the hole 61a. The bit line layer 62 is formed in a line extending in the column direction with a predetermined pitch in the row direction so as to be in contact with the upper surface of the plug layer 61b.

The interlayer insulating layer 61 is composed of silicon oxide (SiO ₂ ). The plug layer 61b and the bit line layer 62 are composed of titanium (Ti) -titanium nitride (TiN) -tungsten (W).

  In the configuration of the wiring layer 60, the bit line layer 62 functions as the bit line BL.

(Operation of Nonvolatile Semiconductor Memory Device 100 According to First Embodiment)
Next, operations (reading, writing, erasing) of the nonvolatile semiconductor memory device 100 according to the first embodiment will be described. In the nonvolatile semiconductor memory device 100 according to the first embodiment, the target memory string MS is selected by the source side select transistor SSTr and the drain side select transistor SDTr. The nonvolatile semiconductor memory device 100 performs the operation by controlling the voltage applied to the word lines WL1 to WL8, that is, controlling the charge accumulated in the charge accumulation layers of the memory transistors MTr1 to MTr8. In the case of the erase operation, the nonvolatile semiconductor memory device 100 sets the word lines WL1 to WL8 to the same 0V, and performs data erase in units of blocks including a plurality of memory strings MS.

  When performing each operation, the nonvolatile semiconductor memory device 100 applies a voltage to the back gate line BG to turn on the back gate transistor BGTr.

  The nonvolatile semiconductor memory device 100 controls the potentials of the dummy word lines DWL1 and DWL2 according to each operation of the memory transistor MTr. The nonvolatile semiconductor memory device 100 controls the potentials of the dummy word lines DWL1 and DWL2 so as to be the same potential as the word lines WL1 to WL8 connected to the non-selected memory transistors MTr. In the erase operation, the nonvolatile semiconductor memory device 100 controls the potential of the dummy word line DWL so as to have the same potential as all the word lines WL1 to WL8.

(Method for Manufacturing Nonvolatile Semiconductor Memory Device 100 According to First Embodiment)
A method for manufacturing the nonvolatile semiconductor memory device 100 according to the first embodiment is now described with reference to FIGS. 7 to 24 are cross-sectional views illustrating manufacturing steps of the nonvolatile semiconductor memory device 100 according to the first embodiment.

First, as shown in FIG. 7, silicon oxide (SiO ₂ ) and polysilicon (p-Si) are deposited on the semiconductor substrate Ba to form a back gate insulating layer 21 and a back gate conductive layer 22.

  Next, as shown in FIG. 8, the back gate conductive layer 22 is engraved using a lithography method or RIE (Reactive Ion Etching) method to form a back gate hole 23.

  Subsequently, as shown in FIG. 9, silicon nitride (SiN) is deposited so as to fill the back gate hole 23 to form a sacrificial layer 71.

Next, as shown in FIG. 10, silicon oxide (SiO ₂ ) and polysilicon (p-Si) are alternately deposited on the back gate conductive layer 22 and the sacrificial layer 71 to form the first to fifth word lines. The inter-layer insulating layers 31a to 31e, the first to fourth word line conductive layers 32a to 32d, the dummy word line conductive layer 41, and the dummy inter-word line insulating layer 42 are formed.

  Subsequently, as shown in FIG. 11, the first to fifth inter-word line insulating layers 31a to 31e, the first to fourth word line conductive layers 32a to 32d, the dummy word line conductive layer 41, and the dummy inter-word line insulation. A memory hole 33 and a dummy hole 43 are formed through the layer 42. The memory hole 33 and the dummy hole 43 are formed so as to reach the upper surfaces of both ends of the sacrifice layer 71 in the column direction. Note that the memory hole 33 and the dummy hole 43 are integrally and continuously formed.

  Next, as shown in FIG. 12, silicon nitride (SiN) is deposited so as to fill the memory hole 33 and the dummy hole 43 to form a sacrificial layer 72.

  Subsequently, as shown in FIG. 13, the first to fifth inter-word line insulating layers 31a to 31e, the first to fourth word line conductive layers 32a to 32d, the dummy word line conductive layer 41, and the dummy inter-word line insulation. A groove 73 is formed through the layer 42. The groove 73 is formed between the memory hole 33 and the dummy hole 43 arranged in the column direction. The groove 73 is formed so as to extend in the row direction.

Next, as shown in FIG. 14, silicon oxide (SiO ₂ ) is deposited so as to fill the groove 73, thereby forming an interlayer insulating layer 51.

Subsequently, as shown in FIG. 15, polysilicon (p-Si) and silicon oxide (SiO ₂ ) are deposited on the interlayer insulating layer 51, and the drain-side conductive layer 52 a, the source-side conductive layer 52 _b , and the select transistor insulation. A layer 53 and an interlayer insulating layer 54 are formed. Here, the drain side conductive layer 52a, the source side conductive layer 52b, and the select transistor insulating layer 53 are formed so as to extend in the row direction with a predetermined pitch in the column direction. The pair of drain side conductive layers 52a and the pair of source side conductive layers 52b are formed so as to be alternately arranged in the column direction.

  Next, as shown in FIG. 16, a drain side hole 55a is formed through the interlayer insulating layer 54, the drain side conductive layer 52a, and the interlayer insulating layer 51. Further, a source side hole 55b is formed through the interlayer insulating layer 54, the source side conductive layer 52b, and the interlayer insulating layer 51. The drain side hole 55 a and the source side hole 55 b are formed at positions aligned with the memory hole 33 and the dummy hole 43.

  Subsequently, as shown in FIG. 17, the sacrificial layers 71 and 72 are removed with a hot phosphoric acid solution.

Next, as shown in FIG. 18, silicon oxide (SiO ₂ ), silicon nitride (SiN), and silicon oxide (SiO ₂ ) are deposited to form an ONO layer 84. The ONO layer 84 is formed so as to cover the side surfaces of the back gate hole 23, the memory hole 33, the dummy hole 43, the drain side hole 55a, and the source side hole 55b.

Subsequently, as shown in FIG. 19, polysilicon (p-Si) is deposited in the memory hole 33 and the back gate hole 23, and phosphorus (P) is doped. By these steps, the U-shaped semiconductor layer 35 is formed. Here, the effective impurity concentration of the U-shaped semiconductor layer 35 is set to 1 × 10 ¹⁹ cm ⁻³ or more. The U-shaped semiconductor layer 35 is formed up to a height between the lower surface and the upper surface of the dummy word line conductive layer 41. The U-shaped semiconductor layer 35 is formed so that its upper surface is located between the upper surface and the lower surface of the dummy word line conductive layer 41.

  Next, as shown in FIG. 20, the ONO layer 84 formed in the drain side hole 55a, the source side hole 55b, and the dummy hole 43 is removed. Here, the ONO layer 84 is removed to a height between the lower surface and the upper surface of the dummy word line conductive layer 41. The ONO layer 84 is removed so that the upper surface thereof is located between the upper surface and the lower surface of the dummy word line conductive layer 41. The ONO layer 84 is removed so that the upper surface thereof is located below the upper surface of the U-shaped semiconductor layer 35. By this step, the ONO layer 84 remaining in the dummy hole 43, the memory hole 33, and the back gate hole 23 becomes the memory gate insulating layer 34.

Subsequently, as shown in FIG. 21, silicon oxide (SiO ₂ ) is deposited on the sidewalls of the drain-side hole 55a and the source-side hole 55b and the dummy hole 43, and the drain-side gate insulating layer 56a and the source-side hole are then deposited. A gate insulating layer 56b is formed. Here, the drain side gate insulating layer 56a (source side gate insulating layer 56b) is formed so as to cover a partial side surface and a partial top surface of the U-shaped semiconductor layer 35 (columnar portion 35a).

Next, as shown in FIG. 22, in the drain side hole 55a and the source side hole 55b,
Polysilicon (p-Si) is deposited to a height between the lower surface and the upper surface of the dummy word line conductive layer 41, and phosphorus (P) is doped. Through these steps, the drain side columnar semiconductor layer 57a and the source side columnar semiconductor layer 57b are formed. Here, the effective impurity concentration of the drain side columnar semiconductor layer 57a and the source side columnar semiconductor layer 57b is 3 × 10 ¹⁷ cm ⁻³ or less. That is, the effective impurity concentration of the drain side columnar semiconductor layer 57 a and the source side columnar semiconductor layer 57 b is set to be equal to or lower than the effective impurity concentration of the U-shaped semiconductor layer 35.

  Subsequently, as shown in FIG. 23, the interlayer insulating layer 54 is dug so as to connect the upper portions of the respective source side holes 55b adjacent in the column direction in the column direction, thereby forming the source line wiring grooves 55c. The source line wiring groove 55c is formed to have a rectangular opening that is short in the column direction and long in the row direction.

  Next, as shown in FIG. 24, titanium (Ti) -titanium nitride (TiN) -tungsten (W) is deposited so as to fill the drain side hole 52a, the source side hole 52b, and the source line wiring groove 55c, A plug layer 58a and a source line conductive layer 58b are formed.

  Subsequently, the wiring layer 60 is formed, and the nonvolatile semiconductor memory device 100 shown in FIG. 5 is formed.

(Effect of Nonvolatile Semiconductor Memory Device 100 According to First Embodiment)
Next, effects of the nonvolatile semiconductor memory device 100 according to the first embodiment will be described. The nonvolatile semiconductor memory device 100 according to the first embodiment can be highly integrated as shown in the stacked structure.

  Furthermore, the nonvolatile semiconductor memory device 100 according to the first embodiment includes a dummy word line conductive layer 41. As described above, the dummy word line conductive layer 41 is provided at the boundary between the U-shaped semiconductor layer 35 and the drain side columnar semiconductor layer 57a (source side columnar semiconductor layer 57b). That is, the dummy word line conductive layer 41 generates high concentration carriers in the vicinity of the boundary due to the electric field effect. Therefore, in the nonvolatile semiconductor memory device 100, the boundary between the U-shaped semiconductor layer 35 and the drain side columnar semiconductor layer 57a (source side columnar semiconductor layer 57b) can have a good contact resistance. The nonvolatile semiconductor memory device 100 can increase the read current while suppressing variations in transistor characteristics and maintaining good cut-off characteristics. In addition, the nonvolatile semiconductor memory device 100 according to the first embodiment includes the bit line conductive layer 62 (bit line BL) and the first to fourth word line conductive layers 32a to 32d (gates of the memory transistors MTr1 to MTr8). The capacitive coupling between them can be reduced.

  Further, in the nonvolatile semiconductor memory device 100 according to the first embodiment, the dummy word line conductive layer 41 (dummy word lines DWL1, DWL2) is set to a potential determined according to each operation as described above. The influence of the potential of the first to fourth word line conductive layers 32a to 32d (the gates of the memory transistors MTr1 to MTr8) can be shielded. As a result, the nonvolatile semiconductor memory device 100 can particularly stabilize the read operation and increase the reliability.

  Next, in order to explain the effect of the nonvolatile semiconductor memory device 100 according to the first embodiment, consider a comparative example. It is assumed that the nonvolatile semiconductor memory device according to the comparative example does not have the dummy word line conductive layer 41. In the nonvolatile semiconductor memory device according to the comparative example, the terminal portion of the memory gate insulating layer 34 is the fourth word line conductive layer 32d (uppermost word line conductive layer) and the drain side conductive layer 52a (source side conductive layer). 52b). In such a comparative example, the cell current at the time of reading increases and decreases depending on the charge trap state of the memory gate insulating layer in the vicinity of the terminal end. On the other hand, the nonvolatile semiconductor memory device 100 according to the first embodiment has a dummy word line conductive layer 41. Further, in the nonvolatile semiconductor memory device 100, the terminal portion of the memory gate insulating layer 34 is located directly beside the dummy word line conductive layer 41. Thus, unlike the comparative example, the nonvolatile semiconductor memory device 100 can maintain a good cell current even when charge is trapped at the terminal portion of the memory gate insulating layer 34. That is, the nonvolatile semiconductor memory device 100 can improve read accuracy. Further, the nonvolatile semiconductor memory device 100 can control the fourth word line conductive layer 32d in the same manner as the first to third word line conductive layers 32a to 32c.

  In the nonvolatile semiconductor memory device 100 according to the first embodiment, the drain-side gate insulating layer 56a (source-side gate insulating layer 56b) is a region in contact with the U-shaped semiconductor layer 35 and the memory gate insulating layer 34. It has the same thickness (see FIG. 6). That is, the drain side gate insulating layer 56a (source side gate insulating layer 56b) has a breakdown voltage similar to that of the memory gate insulating layer 34 in a predetermined region. Thereby, the nonvolatile semiconductor memory device 100 can raise the potential of the dummy word line conductive layer 41 (the gates of the dummy transistors DTr1 and DTr2) sufficiently high to a level that does not affect the cell current during reading. At the same time, the thickness of the drain-side gate insulating layer 56a (source-side gate insulating layer 56b) of the select transistor layer 50 can be reduced. In particular, during a read operation, it is desirable that the drain side select transistor SDTr (source side select transistor SSTr) reduce leakage current from the non-selected memory string MS as much as possible, and an on / off switch that is steep with respect to the gate voltage. It is desirable to show characteristics. Accordingly, it is desirable to use a relatively thin film thickness of about 10 nm as the gate insulating layer. That is, as in the first embodiment, by changing the thickness of the drain side gate insulating layer 56a (source side gate insulating layer 56b) and the thickness of the memory gate insulating layer 34, the drain side selection transistor SDTr (source side selection transistor) is changed. The cutoff characteristics of the transistor SSTr) and the gate breakdown voltage of the dummy transistors DTr1 and DTr2 can both be achieved.

  In the nonvolatile semiconductor memory device 100 according to the first embodiment, the effective impurity concentration of the drain side columnar semiconductor layer 57 a and the source side columnar semiconductor layer 57 b is smaller than the effective impurity concentration of the U-shaped semiconductor layer 35. . Therefore, the nonvolatile semiconductor memory device 100 can reduce the parasitic resistance between the gates of the memory transistors MTr1 to MTr8 (between the first to fourth word line conductive layers 32a to 32d) and increase the cell current at the time of reading. it can. In addition, the nonvolatile semiconductor memory device 100 can reduce the generated recombination current and can configure the drain side selection transistor SDTr and the source side selection transistor SSTr with good cut-off characteristics.

The effective impurity concentration of the drain side columnar semiconductor layer 57a and the source side columnar semiconductor layer 57b is 3 × 10 ¹⁷ cm ⁻³ or less, and the effective impurity concentration of the U-shaped semiconductor layer 35 is 1 × 10 ^19. cm ⁻³ or more. Here, it is generally known that the carrier density in the polysilicon layer changes rapidly with an effective impurity concentration of about 1 × 10 ¹⁸ cm ⁻³ as a boundary. That is, in the nonvolatile semiconductor memory device 100 according to the first embodiment, the effective impurity concentration of the drain side columnar semiconductor layer 57a and the source side columnar semiconductor layer 57b and the effective impurity concentration of the U-shaped semiconductor layer 35 are 1 It is configured to avoid an effective impurity concentration of × 10 ¹⁸ cm ⁻³ . Therefore, even if a slight variation occurs in the effective impurity concentration during the manufacture of the nonvolatile semiconductor memory device 100 according to the first embodiment, the carrier density does not change greatly. The nonvolatile semiconductor memory device 100 according to the first embodiment can improve the yield.

  The nonvolatile semiconductor memory device 100 includes a drain-side conductive layer 52a and a source-side conductive layer 52b that are made of polysilicon (p-Si) doped with boron (B) (P + type semiconductor). Therefore, the nonvolatile semiconductor memory device 100 according to the first embodiment can make the threshold voltages of the drain side select transistor SDTr and the source side select transistor SSTr positive. Thereby, the source side selection gate line drive circuit 14 and the drain side selection gate line drive circuit 15 can be simplified.

[Second Embodiment]
(Specific Configuration of Nonvolatile Semiconductor Memory Device According to Second Embodiment)
Next, a specific configuration of the nonvolatile semiconductor memory device according to the second embodiment will be described with reference to FIG. FIG. 25 is a cross-sectional view of the memory transistor region of the nonvolatile semiconductor memory device according to the second embodiment. Note that in the second embodiment, identical symbols are assigned to configurations similar to those in the first embodiment and descriptions thereof are omitted.

  As shown in FIG. 25, the nonvolatile semiconductor memory device according to the second embodiment has a dummy transistor layer 40A different from the first embodiment.

The dummy transistor layer 40A further includes an insulating layer 36 in addition to the configuration of the first embodiment. The insulating layer 36 is formed at the interface between the columnar portion 35a and the drain side columnar semiconductor layer 57a (source side columnar semiconductor layer 57b). The insulating layer 36 is formed at the boundary between the columnar portion 35a and the drain side columnar semiconductor layer 47a (source side columnar semiconductor layer 47b). The insulating layer 36 is composed of silicon oxide (SiO ₂ ) or silicon nitride (SiN). The insulating layer 36 has a thickness of 1 nm or less.

(Effects of Nonvolatile Semiconductor Memory Device According to Second Embodiment)
Next, effects of the nonvolatile semiconductor memory device according to the second embodiment will be described. The nonvolatile semiconductor memory device according to the second embodiment has substantially the same configuration as that of the first embodiment. Therefore, the nonvolatile semiconductor memory device according to the second embodiment has the same effect as that of the first embodiment.

  Furthermore, the nonvolatile semiconductor memory device according to the second embodiment has an insulating layer 36. Therefore, in the nonvolatile semiconductor memory device according to the second embodiment, the insulating layer 36 suppresses diffusion of impurities from the U-shaped semiconductor layer 35 to the drain side columnar semiconductor layer 57a (source side columnar semiconductor layer 57b). Can do.

[Third Embodiment]
(Configuration of Nonvolatile Semiconductor Memory Device According to Third Embodiment)
Next, the configuration of the nonvolatile semiconductor memory device according to the third embodiment will be described with reference to FIG. FIG. 26 is a partial schematic perspective view of the memory transistor region of the nonvolatile semiconductor memory device according to the third embodiment. Note that. In the third embodiment, the same components as those in the first and second embodiments are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 26, the non-volatile semiconductor memory device according to the third embodiment mainly includes an I-shaped columnar semiconductor CLa instead of the U-shaped semiconductor SC as in the first and second embodiments. Have. The memory transistor region includes, from the lower layer, a source-side selection transistor SSTRa, a first dummy transistor DTra1, a memory string MSa including memory transistors MTra1 to MTra4, a second dummy transistor DTra2, and a drain-side selection transistor SDTra. Further, they are arranged in m × n (m and n are natural numbers) in a plane in the row direction × column direction. FIG. 26 shows an example of m = 3 and n = 4.

  Each of the memory transistors MTra1 to MTra4 includes a columnar columnar semiconductor CLa, a charge storage layer formed so as to surround the columnar semiconductor CLa, and word lines WLa1 to WLa4 formed so as to surround the charge storage layer.

  The word lines WLa1 to WLa4 are formed so as to expand two-dimensionally in the horizontal direction and have a plate-like planar structure composed of the same layer. The word lines WLa1 to WLa4 are formed by the same conductive layer and are common to each other. That is, all the gates of the memory transistors MTra1 of each memory string MSa are connected to the word line WLa1. In addition, all the gates of the memory transistors MTra2 of each memory string MSa are connected to the word line WLa2. All the gates of the memory transistors MTra3 of each memory string MSa are connected to the word line WLa3. All the gates of the memory transistors MTra4 of each memory string MSa are connected to the word line WLa4. In the nonvolatile semiconductor memory device according to the third embodiment, as shown in FIG. 26, the word lines WLa1 to WLa4 are each formed in a plate shape that extends two-dimensionally in the horizontal direction parallel to the semiconductor substrate Ba. Has been. Further, the word lines WLa1 to WLa4 are arranged substantially perpendicular to the memory string MSa, respectively.

  Each columnar semiconductor CLa is formed in the vertical direction from the semiconductor substrate Ba, and is formed through the word lines WLa1 to WLa4. Each columnar semiconductor CLa is arranged in a matrix on the surface. That is, the memory strings MSa are arranged in a matrix in a plane perpendicular to the columnar semiconductor CLa. Note that the columnar semiconductor CLa may be cylindrical or prismatic. The columnar semiconductor CLa includes a columnar semiconductor having a stepped shape.

  As shown in FIG. 26, below the memory string MSa, a first dummy transistor DTra1 and a source side select transistor SSTRA are provided. The first dummy transistor DTra1 includes columnar semiconductors CLa and CLb1, a charge storage layer, an insulating film (not shown), and a first dummy word line DWLa1. The source side select transistor SSTra includes a columnar semiconductor CLb1, an insulating film (not shown), and a source side select gate line SGSa.

  Here, the first dummy word line DWLa1 and the source side selection gate line SGSa are formed so as to expand two-dimensionally in a horizontal direction parallel to the semiconductor substrate Ba. The first dummy word line DWLa1 is formed so as to surround the columnar semiconductors CLa and CLb1 aligned in the row and column directions. The source side select gate line SGSa is formed so as to surround the columnar semiconductors CLb1 arranged in the row and column directions. The columnar semiconductor CLb1 is formed to extend downward from the lower surface of the columnar semiconductor CLa. The lower surface of the columnar semiconductor CLb1 is formed in contact with the semiconductor substrate Ba. The insulating layer is formed on the side surface of the columnar semiconductor CLb1. Note that a region functioning as the source line SLa is formed on the semiconductor substrate Ba.

  As shown in FIG. 26, a second dummy transistor DTra2 and a drain side selection transistor SDTr are provided above the memory string MSa. The second dummy transistor DTra2 includes columnar semiconductors CLa and CLb2, a charge storage layer, an insulating film (not shown), and a second dummy word line DWLa2. The drain side select transistor SDTr includes a columnar semiconductor CLb2, an insulating film (not shown), and a source side select gate line SGDa.

  Here, the second dummy word line DWLa2 is formed to expand two-dimensionally in the horizontal direction parallel to the semiconductor substrate Ba. The drain side select gate lines SGDa are formed so as to extend in the row direction, and are arranged with a predetermined pitch in the column direction. The second dummy word line DWLa2 is formed so as to surround the columnar semiconductors CLa and CLb2 aligned in the row and column directions. The drain side select gate line SGDa is formed so as to surround the columnar semiconductors CLb2 arranged in the row direction. The columnar semiconductor CLb2 is formed to extend upward from the upper surface of the columnar semiconductor CLa. The upper surface of the columnar semiconductor CLb2 is formed in contact with the bit lines BLa1 to BLa3. The insulating layer is formed on the side surface of the columnar semiconductor CLb2. The bit lines BLa1 to BLa3 extend in the column direction and are arranged with a predetermined pitch in the row direction.

  Next, with reference to FIGS. 26 and 27, a circuit configuration constituted by the memory string MSa and its operation in the third embodiment will be described. FIG. 27 is a circuit diagram of a part of the nonvolatile semiconductor memory device according to the third embodiment.

  As shown in FIGS. 26 and 27, in the third embodiment, the memory string MSa includes four memory transistors MTra1 to MTra4. At both ends of the memory string MSa, a source-side selection transistor SSTra and a drain-side selection transistor SDTr are provided via first and second dummy transistors DTra1 and DTra2. The memory transistors MTra1 to MTra4, the first and second dummy transistors DTra1 and DTra2, the source side selection transistor SSTra, and the drain side selection transistor SDTRA are connected in series (see FIG. 27).

  A source line SLa is connected to the source of the source side select transistor SSTRA. A bit line BLa is connected to the drain of the drain side select transistor SDTr.

(Specific Configuration of Nonvolatile Semiconductor Memory Device According to Third Embodiment)
Next, a specific configuration of the nonvolatile semiconductor memory device according to the third embodiment will be described with reference to FIG. FIG. 28 is a cross-sectional view of the memory transistor region of the nonvolatile semiconductor memory device according to the third embodiment. Note that in the third embodiment, identical symbols are assigned to configurations similar to those in the first and second embodiments and descriptions thereof are omitted.

  As shown in FIG. 28, the nonvolatile semiconductor memory device according to the third embodiment has a stacked structure different from that of the first and second embodiments.

  In the nonvolatile semiconductor memory device, a source side selection transistor layer 20B, a first dummy transistor layer 20B, a memory transistor layer 40B, a second dummy transistor layer 50B, a drain side selection transistor layer 60B, and a wiring are sequentially formed on a semiconductor substrate Ba. It has a layer 70B. The source side select transistor layer 20B functions as the source side select transistor SSTra. The first dummy transistor layer 30B functions as the first dummy transistor layer DTra1. The memory transistor layer 40B functions as the memory transistors MTra1 to MTra4 (memory string MSa). The second dummy transistor layer 50B functions as the second dummy transistor DTra2. The drain side select transistor layer 60B functions as the drain side select transistor SDTr.

  As shown in FIG. 28, the nonvolatile semiconductor memory device has a P− type region (P-Well region) Ba1 on a semiconductor substrate Ba. Further, the semiconductor substrate Ba has an n + region (region that becomes the source line SLa) Ba2 on the P− type region Ba1.

  The source side select transistor layer 20B includes a source side first insulating layer 21B, a source side conductive layer 22B, and a source side second insulating layer 23B, which are sequentially stacked on the semiconductor substrate Ba.

  The source side first insulating layer 21B, the source side conductive layer 22B, and the source side second insulating layer 23B are formed so as to expand two-dimensionally in a horizontal direction parallel to the semiconductor substrate Ba. The source-side first insulating layer 21B, the source-side conductive layer 22B, and the source-side second insulating layer 23 are divided for each predetermined region (erase unit) in the memory transistor region.

The source side first insulating layer 21B and the source side second insulating layer 23B are made of silicon oxide (SiO ₂ ). The source side conductive layer 22B is made of polysilicon (p-Si) (p + type semiconductor) doped with boron (B).

  The source side select transistor layer 20B has a source side hole 24B. The source side hole 24B is formed so as to penetrate the source side second insulating layer 23B, the source side conductive layer 22B, and the source side first insulating layer 21B.

  The first dummy transistor layer 30B includes a first dummy word line conductive layer 31B and a first inter-dummy word line insulating layer 32B formed on the source side select transistor layer 20B. The first dummy word line conductive layer 31B and the first dummy word line insulating layer 32B are formed to expand two-dimensionally in the horizontal direction parallel to the semiconductor substrate Ba. The first dummy word line conductive layer 31B is formed so as to surround a boundary between a source side column semiconductor layer 26B and a memory columnar semiconductor layer 45B, which will be described later, and a boundary between the source side gate insulating layer 25B and the memory gate insulating layer 44B. ing.

The first dummy word line conductive layer 31B is made of polysilicon (p-Si). The first dummy word line insulating layer 32B is made of silicon oxide (SiO ₂ ).

  The first dummy transistor layer 30B has a first dummy hole 33B. The first dummy hole 33B is formed so as to penetrate the first dummy word line conductive layer 31B and the first inter-dummy word line insulating layer 32B. The first dummy hole 33B is formed continuously and integrally with the source side hole 24B.

  The source side select transistor layer 20B and the first dummy transistor layer 30B include a source side gate insulating layer 25B and a source side columnar semiconductor layer 26B. The source side gate insulating layer 25B is formed on the side wall of the first dummy hole 33B and the side wall of the source side hole 24B. The source side gate insulating layer 25B is formed to a height between the lower surface and the upper surface of the first dummy word line conductive layer 31B.

  The source-side columnar semiconductor layer 26B is formed in a columnar shape (I shape) when viewed from a direction parallel to the semiconductor substrate Ba. The source side columnar semiconductor layer 26B is formed so as to be in contact with the source side gate insulating layer 25B and to fill the source side hole 24B and the first dummy hole 33B. The source side columnar semiconductor layer 26B is formed to a height between the lower surface and the upper surface of the first dummy word line conductive layer 31B.

The source side gate insulating layer 25B is composed of silicon oxide (SiO ₂ ). The source side columnar semiconductor layer 26B is configured by polysilicon (p-Si) (n-type semiconductor) doped with phosphorus (P). The source side columnar semiconductor layer 26B has an effective impurity concentration of 3 × 10 ¹⁷ cm ⁻³ or less. Note that the effective impurity concentration of the source-side columnar semiconductor layer 26B is equal to or lower than the effective impurity concentration of the memory columnar semiconductor layer 45B described later.

  In the configuration of the source side select transistor layer 20B and the first dummy transistor layer 30B, the source side conductive layer 22B functions as a gate electrode of the source side select transistor SDTra. The source side conductive layer 22B functions as the source side gate line SGSa.

  The memory transistor layer 40B includes first to fifth inter-wordline insulating layers 41Ba to 41Be and first to fourth wordline conductive layers 42Ba to 42Bd formed on the first dummy transistor layer 30B. The first to fifth inter-wordline insulating layers 41Ba to 41Be and the first to fourth wordline conductive layers 42Ba to 42Bd are formed to expand two-dimensionally in the horizontal direction parallel to the semiconductor substrate Ba. Yes.

The first to fifth inter-wordline insulating layers 41Ba to 41Be are composed of silicon oxide (SiO ₂ ). The first to fourth word line conductive layers 42Ba to 42Bd are made of polysilicon (p-Si).

  The memory transistor layer 40B has a memory hole 43B. The memory hole 43B is formed so as to penetrate the first to fifth inter-word line insulating layers 41Ba to 41Be and the first to fourth word line conductive layers 42Ba to 42Bd. The memory hole 43B is formed at a position aligned with the source side hole 24B and the first dummy hole 33B.

  The second dummy transistor layer 50B includes a second dummy word line conductive layer 51B and a second dummy word line insulating layer 52B formed on the memory transistor layer 40B. The second dummy word line conductive layer 51B and the second dummy word line insulating layer 52B are formed to expand two-dimensionally in a horizontal direction parallel to the semiconductor substrate Ba. The second dummy word line conductive layer 51B is formed so as to surround a boundary between a memory columnar semiconductor layer 45B and a drain side columnar semiconductor layer 67B, which will be described later, and a boundary between the memory gate insulating layer 44B and the drain side gate insulating layer 66B. ing.

The second dummy word line conductive layer 51B is composed of polysilicon (p-Si). The second dummy word line insulating layer 52B is made of silicon oxide (SiO ₂ ).

  The second dummy transistor layer 50B has a second dummy hole 53B. The second dummy hole 53B is formed so as to penetrate the second dummy word line conductive layer 51B and the second dummy word line insulating layer 52B. The second dummy hole 53B is formed continuously and integrally with the memory hole 43B.

  The first dummy transistor layer 30B, the memory transistor layer 40B, and the second dummy transistor layer 50B include a memory gate insulating layer 44B and a memory columnar semiconductor layer 45B. The memory gate insulating layer 44B is formed on the sidewall of the second dummy hole 53B, the sidewall of the memory hole 43B, and the sidewall of the first dummy hole 33B. The memory gate insulating layer 44B is formed in contact with the upper surface of the source side gate insulating layer 25B. That is, the memory gate insulating layer 44B is formed from the height between the lower surface and the upper surface of the first dummy word line conductive layer 31B to the upper layer. The memory gate insulating layer 44B is formed to a height between the lower surface and the upper surface of the second dummy conductive layer 51B. The memory gate insulating layer 44B is formed so as to cover a partial side surface and a partial top surface of the source side columnar semiconductor layer 26B.

  The memory columnar semiconductor layer 45B is formed in a columnar shape (I shape) when viewed from a direction parallel to the semiconductor substrate Ba. The memory columnar semiconductor layer 45B is formed so as to be in contact with the source-side gate insulating layer 25B and to fill the first dummy hole 33B, the memory hole 43B, and the second dummy hole 53B. The memory columnar semiconductor layer 45B is formed in contact with the upper surface of the source side columnar semiconductor layer 26B. That is, the memory columnar semiconductor layer 45B is formed from the height between the lower surface and the upper surface of the first dummy word line conductive layer 31B to the upper layer. The memory columnar semiconductor layer 45B is formed to a height between the lower surface and the upper surface of the second dummy conductive layer 51B.

Memory gate insulating layer 44B is, silicon oxide (SiO ₂₎ - silicon nitride (SiN) - are composed of silicon oxide (SiO _2). The memory columnar semiconductor layer 45B is composed of polysilicon (p-Si) (n-type semiconductor) doped with phosphorus (P). The memory columnar semiconductor layer 45B has an effective impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more.

  In the configuration of the first dummy transistor layer 30B and the memory transistor layer 40B, the first dummy word line conductive layer 31B functions as the gate electrode of the first dummy transistor DTra1. The first dummy word line conductive layer 31B functions as the first dummy word line DWLa1. The first to fourth word line conductive layers 42Ba to 42Bd function as gate electrodes of the memory transistors MTra1 to MTra4. The first to fourth word line conductive layers 42Ba to 42Bd function as the word lines WLa1 to WLa4.

  The drain side select transistor layer 60B includes a first drain side insulating layer 61B, a drain side conductive layer 62B, an interlayer insulating layer 63B, and a second drain side insulating layer 64B. The drain-side conductive layers 62B extend in the row direction and are arranged with a predetermined pitch in the column direction.

The first and second drain side insulating layers 61B and 64B and the interlayer insulating layer 63B are made of silicon oxide (SiO ₂ ). The drain side conductive layer 62B is made of polysilicon (p-Si) (p + type semiconductor) doped with boron (B).

  The drain side select transistor layer 60B has a drain side hole 65B. The drain side hole 65B is formed so as to penetrate the first and second drain side insulating layers 61B and 64B and the drain side conductive layer 62B. The drain side hole 65B is formed at a position aligned with the second dummy hole 53B and the memory hole 43B.

  The drain side select transistor layer 60B and the second dummy transistor layer 50B include a drain side gate insulating layer 66B and a drain side columnar semiconductor layer 67B. The drain side gate insulating layer 66B is formed on the side wall of the drain side hole 65B and the side wall of the second dummy hole 53B. The drain side gate insulating layer 66B is in contact with the upper surface of the memory gate insulating layer 44B and is formed up to the upper surface of the second drain side insulating layer 64B. That is, the drain side gate insulating layer 66B is formed from the height between the lower surface and the upper surface of the second dummy conductive layer 51B to the upper layer. The drain side gate insulating layer 66B is formed so as to cover a partial side surface and a partial top surface of the memory columnar semiconductor layer 45B.

  The drain side columnar semiconductor layer 67B is formed in a columnar shape (I shape) when viewed from a direction parallel to the semiconductor substrate Ba. The drain side columnar semiconductor layer 67B is formed so as to be in contact with the drain side gate insulating layer 66B and to fill the drain side hole 65B and the second dummy hole 65B. That is, the drain side columnar semiconductor layer 67B is formed from the height between the lower surface and the upper surface of the second dummy conductive layer 51B to the upper layer.

The drain side gate insulating layer 66B is composed of silicon oxide (SiO ₂ ). The drain side columnar semiconductor layer 67B is made of polysilicon (p-Si) (n-type semiconductor) doped with phosphorus (P). The drain side columnar semiconductor layer 67B has an effective impurity concentration of 3 × 10 ¹⁷ cm ⁻³ or less.

  In the configuration of the second dummy transistor layer 50B and the drain side select transistor layer 60B, the second dummy word line conductive layer 51B functions as the gate electrode of the second dummy transistor DTra2. The second dummy word line conductive layer 51B functions as the second dummy word line DWLa2. The drain side conductive layer 62B functions as the gate electrode of the drain side select transistor SDTRA. The drain side conductive layer 62B functions as the drain side select gate line SGDa.

  The wiring layer 70B includes an interlayer insulating layer 71B, a bit line conductive layer 72B, a hole 73B, and a plug conductive layer 74B formed on the drain side select transistor layer 60B. The bit line conductive layers 72B extend in the column direction and are arranged with a predetermined pitch in the row direction. The hole 73B is formed so as to penetrate the interlayer insulating layer 71B. The hole 73B is formed at a position aligned with the drain side hole 65B and the bit line conductive layer 72B. Plug conductive layer 74B is formed to fill hole 73B.

The interlayer insulating layer 71B is composed of silicon oxide (SiO ₂ ). The bit line conductive layer 72B and the plug conductive layer 74B are composed of titanium (Ti) -titanium nitride (TiN) -tungsten (W).

(Effects of Nonvolatile Semiconductor Memory Device According to Third Embodiment)
Next, effects of the nonvolatile semiconductor memory device according to the third embodiment will be described. The nonvolatile semiconductor memory device according to the third embodiment includes first and second dummy word line conductive layers 31B and 51B. Therefore, the nonvolatile semiconductor memory device according to the third embodiment has the same effect as that of the first embodiment.

[Other embodiments]
Although one embodiment of the nonvolatile semiconductor memory device has been described above, the present invention is not limited to the above-described embodiment, and various modifications, additions, substitutions, and the like can be made without departing from the spirit of the invention. Is possible.

  For example, in the third embodiment, an insulating layer may be provided between the source side columnar semiconductor layer 26B and the memory columnar semiconductor layer 45B (boundary) as in the second embodiment. In the third embodiment, an insulating layer may be provided between the drain side columnar semiconductor layer 67B and the memory columnar semiconductor layer 45B (boundary) as in the second embodiment.

1 is a schematic configuration diagram of a nonvolatile semiconductor memory device 100 according to a first embodiment of the present invention. 2 is a partial schematic perspective view of a memory transistor region 12 according to the first embodiment. FIG. 3 is an enlarged view of one memory string MS according to the first embodiment. FIG. 1 is a circuit diagram of a part of a nonvolatile semiconductor memory device 100 according to a first embodiment. 1 is a cross-sectional view of a nonvolatile semiconductor memory device 100 according to a first embodiment. FIG. 6 is a partially enlarged view of FIG. 5. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device 100 concerning 1st Embodiment. It is sectional drawing of the non-volatile semiconductor memory device which concerns on 2nd Embodiment. It is a partial schematic perspective view of a memory transistor region according to a third embodiment of the present invention. FIG. 6 is a circuit diagram of a part of a nonvolatile semiconductor memory device according to a third embodiment. It is sectional drawing of the non-volatile semiconductor memory device which concerns on 3rd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Nonvolatile semiconductor memory device, 12 ... Memory transistor area | region, 13 ... Word line drive circuit, 14 ... Source side selection gate line drive circuit, 15 ... Drain side selection gate line drive circuit, 16 ... Sense amplifier, 17 ... Source line Drive circuit, 18 ... Back gate transistor drive circuit, 19 ... Dummy word line drive circuit, 20 ... Back gate transistor layer, 30, 40B ... Memory transistor layer, 40, 40A ... Dummy transistor layer, 50 ... Selection transistor layer, 60, 70B ... Wiring layer, 20B ... Source side selection transistor layer, 30B ... First dummy transistor layer, 50B ... Second dummy transistor layer, Ba ... Semiconductor substrate, SE ... U-shaped semiconductor, MTr1-MTr8, MTra1-MTra4 ... Memory Transistor, SST , SSTra ... source-side selection transistor, SDTr, SDTra ... drain-side selection transistor, DTr1, DTr2, DTra1, DTra2 ... dummy transistor, BGTr ... back gate transistor.

Claims (5)

A plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series, a selection transistor connected to both ends of the memory string, and a dummy transistor provided between the memory string and the selection transistor With
The memory string is
A first semiconductor layer having a columnar portion extending in a direction perpendicular to the substrate;
A charge storage layer formed so as to surround a side surface of the columnar part;
A first conductive layer that is formed so as to surround a side surface of the columnar part and the charge storage layer, and functions as a control electrode of the memory cell;
The selection transistor is:
A second semiconductor layer extending in the vertical direction from an upper surface or a lower surface of the columnar portion;
A gate insulating layer formed to surround a side surface of the second semiconductor layer;
A second conductive layer formed so as to surround a side surface of the second semiconductor layer and the gate insulating layer, and functioning as a control electrode of the selection transistor;
The dummy transistor is
The first semiconductor layer and the second semiconductor layer;
The charge storage layer and the gate insulating layer;
A third conductive layer formed so as to surround a boundary between the first semiconductor layer and the second semiconductor layer and a boundary between the charge storage layer and the gate insulating layer and function as a control electrode of the dummy transistor; A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1, wherein an effective impurity concentration of the second semiconductor layer is equal to or less than an effective impurity concentration of the first semiconductor layer. The nonvolatile semiconductor memory device according to claim 1, further comprising an insulating layer formed at an interface between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer is formed on an upper layer of the first semiconductor layer,
4. The nonvolatile semiconductor memory device according to claim 1, wherein the first semiconductor layer has a connection portion formed to connect lower ends of the pair of columnar portions. 5. . 5. The non-volatile device according to claim 1, wherein the gate insulating layer in the vicinity of the third conductive layer is thicker than the gate insulating layer in the vicinity of the second conductive layer. Semiconductor memory device.

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