JP2010103855A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect, in a short time, a defective pixel caused by RTS noise. <P>SOLUTION: The present invention relates to a solid-state imaging apparatus including: a pixel unit (1) having a photoelectric converter (2) for converting incident light into an electric charge, an amplifier (3) for outputting a signal based on a potential at its input part, a transfer section (4) for transferring the electric charge held in the photoelectric converter to the input part of the amplifier, and a reset section (5) for resetting the potential at the input part of the amplifier; a buffer (10) which performs buffering operation upon an output signal outputted from the pixel unit; and a memory (12) for storing the output signal, wherein the buffer includes a switching means for switching between a first mode during which the buffering operation is performed on the output signal, and a second mode during which a maximum value or a minimum value of the output signal within a fixed period of time is detected. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  In recent years, the market of digital video cameras and digital still cameras equipped with solid-state imaging devices has been expanded. In order to meet the demand for higher image quality from the market, multi-pixel miniaturization and higher S / N are being performed as solid-state imaging devices. In multi-pixel miniaturization of solid-state imaging devices, as shown in Non-Patent Document 1 below, a new noise called random telegraph signal noise is a problem. Hereinafter, random telegraph signal noise is referred to as RTS noise. It is known that RTS noise is generated in a MOS transistor that accumulates a photoelectric conversion signal in a gate electrode and performs signal amplification in a source follower circuit among transistors constituting a pixel (see Non-Patent Document 1). According to Non-Patent Document 1, RTS noise is caused by fluctuations in the signal output after amplification depending on whether charges are trapped or released in traps in the vicinity of the silicon-silicon oxide film interface of the MOS transistor. When the output of the same pixel is repeatedly read, the output fluctuates randomly. In particular, in a moving image, it is visually recognized that the pixel repeats blinking. It is also known that the RTS noise has a fluctuation cycle determined by the charge / discharge time constant of the trap, and a long one has a cycle of a second. Therefore, in order to detect defective pixels due to RTS noise with high probability, it is necessary to observe the output of the same pixel for a long time.

  Japanese Patent Application Laid-Open No. 2004-133561 performs defective pixel attributed to the RTS noise by characteristic inspection of the solid-state imaging device. According to Patent Document 1, the imaging output of a solid-state imaging device that has been subjected to output offset and sensitivity difference correction is monitored over a plurality of frames, and pixels whose output value fluctuation magnitude or frequency in the plurality of frames exceeds a determination criterion are detected. By detecting, a defective pixel is specified and detected.

JP 2003-298949 A X. Wang, P.R.Rao, A. Mierop, A.J.P.Theuwissen, “Random Telegraph Signal in CMOS Image Sensors Pixels”, IEEE Proceedings, IEDM 2006

  In the defective pixel detection method of Patent Document 1, imaging over several hundred frames is performed in order to detect a blinking defect with a long cycle. In the defective pixel detection, since a plurality of frames are imaged, the detection time increases as the number of frames increases. Also, one frame imaging time increases with the miniaturization of the solid-state imaging device.

  It is an object of the present invention to detect defective pixel detection caused by RTS noise in a shorter time.

  The solid-state imaging device of the present invention includes a photoelectric conversion unit that converts incident light into electric charge, an amplification unit that outputs a signal based on the potential of the input unit, and an electric charge held in the photoelectric conversion unit that is input to the amplification unit. A pixel unit including a transfer unit that transfers to the output unit, a reset unit that resets the potential of the input unit of the amplification unit, a buffer unit that performs a buffer operation on an output signal output from the pixel unit, and the output signal A solid-state imaging device having a memory unit for storing, wherein the buffer unit detects a first mode in which a buffer operation is performed on the output signal and a maximum value or a minimum value of the output signal in a certain period. And switching means for switching between the two modes.

  In the second mode, by detecting the maximum value or the minimum value, it is possible to detect defective pixels caused by RTS noise with a small number of frames or a short inspection time.

(First embodiment)
FIG. 1 is a configuration diagram of a solid-state imaging device according to the first embodiment of the present invention. For convenience of explanation, a circuit for one pixel among a plurality of pixels arranged in a two-dimensional array, a signal line for each column, and a readout circuit are shown.

  Reference numeral 1 denotes a pixel portion. Reference numeral 2 denotes a photodiode (photoelectric conversion unit) that converts incident light into electric charges. Hereinafter, the photodiode is referred to as PD. Reference numeral 3 denotes a pixel source follower (SF) transistor (amplifying unit) that outputs a signal based on the charge of the input unit (gate). A transfer MOS transistor (transfer unit) 4 transfers the charge of PD2 to the input unit of the pixel SF transistor 3. Reference numeral 5 denotes a reset MOS transistor (reset unit) that resets the input unit of the pixel SF transistor 3 to a predetermined potential. Reference numeral 6 denotes a selection MOS transistor (pixel selection unit) for selecting PD2.

  The pixel unit 1 includes a PD 2, a pixel SF transistor 3, a transfer MOS transistor 4, a reset MOS transistor 5, and a selection MOS transistor 6. However, since the present embodiment can be realized even in a configuration without the selection MOS transistor 6, it does not depend on whether or not the selection MOS transistor 6 is present. Reference numeral 7 denotes a signal line for transmitting an output signal of the pixel SF transistor 3. Here, in order to simplify the description, a state where one pixel portion 1 is connected to the signal line 7 is shown. However, when a plurality of pixel portions 1 are provided, a plurality of pixel portions 1 are provided. Is connected to the signal line 7. Reference numeral 8 denotes a clamp unit (differential operation unit) that performs a clamping operation. Reference numeral 9 denotes a MOS switch (PC0R) for performing a clamping operation. A signal processing circuit unit (buffer unit) 10 processes the output signal of the signal line 7. Reference numeral 11 denotes an operation switching control terminal for switching between the buffer operation and the maximum value holding operation. Reference numeral 12 denotes a line memory unit for accumulating output signals from the signal processing circuit unit 10. The line memory unit 12 includes a capacitor 14, a MOS switch 13, and a MOS switch 15.

  FIG. 2 is a diagram showing drive pulse timings in the first mode of the solid-state imaging device of FIG. The first mode is a normal imaging operation mode. The reference numerals in parentheses of the pulse names in FIG. 2 are the same as the reference numerals in FIG. The MOS switch 11 in FIG. 3 is on at time t1 to t13 with the gate voltage at a high level.

  After time t1, the selection MOS transistor 6 is turned on when the gate voltage of the selection MOS transistor 6 becomes high level. The selection MOS transistor 6 selects the pixel unit 1. As a result, the potential of the signal line 7 changes according to the gate potential of the pixel SFMOS transistor 3 included in the selected pixel unit 1. At time t2 to t3, the gate voltage of the reset MOS transistor 5 becomes high level, so that the reset MOS transistor 5 is turned on. The reset MOS transistor 5 resets the input portion of the pixel SF transistor 3 to a predetermined potential (for example, a power supply potential). During the period from time t4 to time t5, the gate voltage of the MOS switch 9 becomes high level, so that the MOS switch 9 is turned on and the clamp unit 8 performs the clamping operation of the noise signal. In the clamping operation, the noise signal N corresponding to the reset of the gate of the pixel SFMOS transistor 3 of the pixel unit 1 is clamped. Next, when the gate voltage of the transfer MOS transistor 4 becomes high level at time t6, the transfer MOS transistor 4 is turned on. The transfer MOS transistor 4 transfers the optical signal charge accumulated in the PD 2 to the input portion of the pixel SF transistor 3 during the period when the signal PTX is at the high level. As a result, the gate potential of the pixel SF transistor 3 fluctuates by an amount corresponding to the charge amount of the optical signal charge accumulated in the PD 2 with respect to the potential immediately after being reset by the reset MOS transistor 5. The pixel SF transistor 3 outputs a signal S based on the optical signal charge at the input unit, and the signal S is sent to the signal line 7. Note that a component corresponding to the noise signal N is superimposed on the signal S. As a result, the clamp unit 8 subtracts the clamped noise signal N from the signal S. In other words, the clamp unit (difference calculating unit) 8 outputs the noise signal N output from the pixel SF transistor 3 when reset by the reset MOS transistor 5 and the pixel SF transistor 3 when transferred by the transfer MOS transistor 4. The difference calculation with the optical signal to be performed is performed. The subtracted signal (S−N) passes through the signal processing circuit unit 10 and is output to the line memory unit 12. At this time, the signal processing circuit unit (buffer unit) 10 performs a buffer operation on the output signal of the clamp unit 8. When the gate voltage of the MOS switch 13 becomes high level at time t9, the MOS switch 13 is turned on, and the output of the signal line 7 is accumulated in the capacitor 14. When the gate voltage of the MOS switch 15 becomes high level at time t12, the MOS switch 15 is turned on, and the signal accumulated in the capacitor 14 is output to the outside.

  FIG. 3 is a circuit diagram of the signal processing circuit unit 10 of FIG. The signal processing circuit unit 10 includes a differential amplifier circuit 11a, a source follower circuit 11b that receives an output signal of the differential amplifier circuit 11a, and a MOS switch (switching means) 11 that switches between a buffer operation and a maximum value holding operation. Consists of. The MOS switch 11 is an NMOS transistor, and its control terminal (gate) is connected to the control terminal 11 of FIG. Node a is an output of the differential amplifier circuit 11a, and in and node b are input terminals of the differential amplifier circuit 11a. in is a non-inverting input terminal, and b is an inverting input terminal. An output terminal of the clamp unit 8 is connected to the input in. The output terminal out of the source follower circuit 11 b is connected to the inverting input terminal (node) b of the differential amplifier circuit 11 a and the drain terminal of the MOS switch 11. Further, by applying a predetermined voltage to the gate terminal of the MOS switch 11, the MOS switch 11 operates as a constant current source of the source follower circuit 11b. The signal processing circuit unit 10 performs a buffer operation by feeding back the output out to the voltage of the input in. The MOS switch 11 switches between conduction and interruption between the output terminal of the source follower circuit 11b and the reference potential node (ground potential node).

  Next, a defective pixel detection operation caused by random telegraph signal noise (RTS noise) will be described. FIG. 4 is a drive pulse timing chart in the second mode (defective pixel detection mode). The difference from the operation timing in the normal imaging operation mode of FIG. 2 is that the MOS switch 11 is turned off (cut off) during the time t8 to t11 which is the high level period of the gate voltage of the MOS switch 13. Turning off the MOS switch 11 eliminates the current supply of the source follower for lowering the voltage of the output out. Since the current supply of the source follower is lost, the voltage of the output out cannot be decreased, and the potential of the output out can only be increased. Therefore, the signal processing circuit unit 10 can hold the maximum value of the pixel SF transistor 3 in the period from time t8 to time t11. By setting the time period from t8 to t10 to be sufficiently long, the output fluctuation caused by the RTS noise during that time can be detected as the maximum value of the output.

  RTS noise alternates between a charge trapping state and a discharge state. Whether the RTS noise signal ΔN is superimposed on the signal output is determined by the capture state and the emission state. When the RTS noise ΔN is added to the noise signal N, the noise signal (N + ΔN) is clamped in the clamp unit 8. If the RTS noise ΔN is not added, the noise signal N is clamped as it is in the clamp unit 8. Similarly, when the optical output signal S is read, the RTS noise signal ΔN may or may not be superimposed. When the RTS noise ΔN signal is superimposed on the optical output signal S, the signal output becomes S + ΔN, and otherwise the signal output remains S. Since the RTS noise ΔN is randomly generated when the noise signal N is read and when the optical signal S is read, the signal (S−N) read via the clamp unit 8 takes the following three output values. The first is the case where the noise signal remains N and the optical signal is (S + ΔN), and the output after the clamping operation is (S + ΔN) −N = (S−N) + ΔN. The second is a case where the noise signal is (N + ΔN) and the optical signal remains S. In this case, the output after the clamping operation is S− (N + ΔN) = (S−N) −ΔN. The third is the case where the noise signal and the optical signal remain N and S, respectively, and the case where the noise signal and the optical signal are (N + ΔN) and (S + ΔN), respectively. In this case, the output after the clamping operation is ( SN).

  In the present embodiment, among the above three values, ΔN> 0 and (S−N) + ΔN is detected. Its feature is that it is used as a defective pixel detection circuit caused by RTS noise ΔN by switching the MOS switch 11 of the signal processing circuit section 10 on and off. When a defective pixel is detected, the signal processing circuit unit 10 can store the maximum value of the pixel SF transistor 3 in the period 14 from time t8 to t11 in the capacitor 14 of the line memory unit 12. A pixel having a large maximum output value can be determined as a blinking defective pixel. By setting the times t8 to t10 to be sufficiently long, defective pixels can be detected even with one detection operation.

  FIG. 5 shows another configuration example of the signal processing circuit unit 10 of FIG. This configuration is only the differential amplifier circuit 11a, and the MOS switch 11 is a MOS transistor in the differential amplifier circuit 11a. By applying a predetermined voltage to the gate terminal of the MOS switch 11, the MOS switch 11 operates as a constant current source of the differential amplifier circuit 11a. The inverting input terminal (node) b of the differential amplifier circuit 11a is short-circuited with the output terminal out (node a) of the differential amplifier circuit 11a. The signal processing circuit unit 10 performs a buffer operation by feeding back the output out to the voltage of the input (non-inverting input terminal) in. For detection of blinking defective pixels, the MOS switch 11 is turned off during the period from time t8 to t11, which is a high level period of the gate voltage of the MOS switch 13 in FIG. As a result, the signal processing circuit unit 10 continues to hold the maximum value of the pixel SF transistor 3 in the period from time t8 to t10, and therefore, it is possible to detect a defective pixel even with one imaging.

  As described above, the signal processing circuit 10 detects the maximum value of the output signal of the clamp unit 8 during the fixed period and the first mode in which the buffer operation is performed with respect to the output signal of the clamp unit 8. A MOS switch (switching means) 11 for switching between the two modes (FIG. 4) is provided. The first mode is used as a normal imaging operation. The second mode is used to detect defective pixels caused by RTS noise.

  According to the technique described in Patent Document 1, the imaging operation is repeated over a plurality of frames in order to detect a blinking defective pixel. Therefore, the time required for detection increases according to the number of repeated frames. In particular, the time required to extract a signal from the solid-state imaging device cannot be ignored. On the other hand, the present invention can detect a defective pixel by sufficiently lengthening the period for detecting the maximum value in the signal processing circuit unit, thereby reducing the time required for reading a signal from the solid-state imaging device. It becomes possible to do.

(Second Embodiment)
The equivalent circuit diagram of the solid-state imaging device according to the second embodiment of the present invention is the same as FIG. FIG. 6 is a circuit diagram of the signal processing circuit unit 10 according to the second embodiment of the present invention. The signal processing circuit unit 10 switches between a buffer operation and a minimum value holding operation. The signal processing circuit unit 10 includes a differential amplifier circuit 11a, a source follower circuit 11b, and a MOS switch 11 that switches between a buffer operation and a minimum value holding operation. Unlike the first embodiment, the MOS switch 11 is a PMOS transistor. Node a is an output of the differential amplifier circuit 11a, and in and node b are input terminals of the differential amplifier circuit 11a. In is a non-inverting input, and b is an inverting input terminal. An output terminal of the clamp unit 8 is connected to the input in. The output terminal out of the source follower circuit 11 b is connected to the inverting input terminal (node) b of the differential amplifier circuit 11 a and the drain terminal of the MOS switch 11. The MOS switch 11 switches between conduction and interruption between the output terminal of the source follower circuit 11b and the power supply potential node.

  The drive pulse timing chart at the normal time in this embodiment is exactly the same as FIG. 2 of the drive timing of the first embodiment except that the polarity of the signal for driving the MOS switch 11 is reversed. The MOS switch 11 is a PMOS transistor and is turned off when the gate voltage is at a high level. By turning on the MOS switch 11, it operates as a current source of the source follower. The signal processing circuit unit 10 performs a buffer operation by feeding back the output out to the voltage of the input in.

  The drive pulse timing diagram for detecting a pixel defect caused by RTS noise is exactly the same as that of FIG. 4 of the first embodiment except that the polarity of the signal for driving the MOS switch 11 is reversed. Hereinafter, the operation will be described with reference to FIG. During time t8 to t11, which is a high level period of the gate voltage of the MOS switch 13, the MOS switch 11 is turned off (cut off), thereby cutting off the current supply of the source follower for increasing the voltage of the output out. When the current supply of the source follower is lost, the voltage of the output out cannot be increased, and the voltage of the output out can only be decreased. Therefore, the signal processing circuit unit 10 can hold the minimum value of the pixel SF transistor 3 in the period from time t8 to time t11. By setting the time period from t8 to t11 to be sufficiently long, the output fluctuation caused by the RTS noise during that period can be detected as the minimum value of the output.

  As described in the first embodiment, the output after the clamping operation has three values (S−N), (S−N + ΔN), and (S−N−ΔN). In the present embodiment, pixel defects caused by RTS noise are detected by detecting (S−N−ΔN) (where ΔN> 0) among them using a minimum value circuit. Its feature is that it is used as a defective pixel detection circuit by switching the MOS switch 11 of the signal processing circuit unit 10 on and off. When a defective pixel is detected, the signal processing circuit unit 10 can store the minimum value of the pixel SF transistor 3 in the period 14 from time t8 to t10 in the capacitor 14 of the line memory unit 12. By setting the period from time t8 to t10 to be sufficiently long, defective pixels can be detected with the same detection probability in a short time compared to the conventional method. For example, a defective pixel due to RTS noise of a solid-state imaging device having 10 million pixels could be detected in 1.2 seconds.

  As described above, the signal processing circuit 10 performs the buffer operation for the output signal of the clamp unit 8 and the second mode for detecting the minimum value of the output signal of the clamp unit 8 during a certain period. A MOS switch (switching means) 11 for switching between.

  The effect of shortening the time is the same as in the case of using the maximum value detection circuit of the first embodiment, and there is no profit or loss other than the difference in circuit configuration.

(Third embodiment)
FIG. 7 is a configuration diagram of a solid-state imaging device according to the third embodiment of the present invention. As in FIG. 1, for convenience of explanation, a circuit for one pixel among a plurality of pixels arranged in an array, a signal line for each column, and a readout circuit are shown. In this embodiment, by adding a column amplifier unit to the readout circuit for each column, the signal is amplified at a stage where the circuit noise is small, and the S / N is improved.

  The configuration and role of the pixel unit 1, the photodiode 2, the pixel SF transistor 3, the transfer MOS transistor 4, and the reset MOS transistor 5 are exactly the same as those in FIG. Reference numeral 16 denotes a column amplifier that amplifies a signal output from the pixel SF transistor 3. The column amplifier unit 16 has a two-stage configuration, and is composed of a signal processing circuit unit 10 located in a column amplifier front stage 17 and a column amplifier rear stage. The column amplifier front stage 17 includes a capacitive feedback type differential amplifier and a clamp unit. Reference numeral 11 denotes a MOS switch control terminal for switching between a buffer operation and a maximum value holding operation. The line memory unit 12 includes a capacitor (CTN) 19, a MOS switch 18, a capacitor (CTS) 21, and a MOS switch 20. The capacitor 19 stores only the offset voltage of the column amplifier unit 16. The capacitor 21 stores an optical signal including the offset voltage of the column amplifier unit 16. Reference numeral 22 denotes an output stage that outputs an optical signal from which the offset voltage of the column amplifier unit 16 is removed.

  FIG. 8 is a timing chart for driving pulses in the first mode (normal imaging operation mode) of the solid-state imaging device of FIG. The MOS switch 11 has a gate voltage at a high level and is on. The reset MOS transistor 5 is turned on when the gate voltage of the reset MOS transistor 5 becomes high during the period from time t2 to t3. The reset MOS transistor 5 resets the input portion of the pixel SF transistor 3 to a predetermined potential. When the gate voltage of the MOS switch 9 becomes a high level at time t4, the MOS switch 9 is turned on, and the column amplifier front stage (clamp unit) 17 performs a clamping operation on the noise signal of the signal line 7. In the clamping operation, the noise signal N of the pixel unit 1 is clamped. When the gate voltage of the MOS switch 18 becomes high level at time t6, the MOS switch 18 is turned on, and the offset voltage of the column amplifier unit 16 is accumulated in the capacitor 19 of the line memory unit 12. Next, when the gate voltage of the transfer MOS transistor 4 becomes high level at time t8, the transfer MOS transistor 4 is turned on. The transfer MOS transistor 4 transfers the optical signal charge accumulated in the PD 2 to the input portion of the pixel SF transistor 3. The pixel SF transistor 3 outputs a signal S based on the optical signal charge at the input unit, and the signal S is transmitted to the signal line 7. The column amplifier front stage 17 subtracts the clamped noise signal N from the signal S. That is, the column amplifier front stage 17 includes a difference calculation unit. The difference calculation unit 17 generates a noise signal N output from the pixel SF transistor 3 when reset by the reset MOS transistor 5 and an optical signal S output from the pixel SF transistor 3 when transferred by the transfer MOS transistor 4. Perform a difference operation. The subtracted signal (S−N) is amplified by the column amplifier unit 16. The amplified signal is stored in the capacitor 21 of the line memory unit 12. At this time, the signal stored in the capacitor 21 is an optical signal including the offset voltage of the column amplifier unit 16. The output stage 22 subtracts the signal accumulated in the capacitor 19 from the signal accumulated in the capacitor 21, thereby removing the offset voltage of the column amplifier unit 16, and the optical signal (SN) from which noise has been subtracted. Output.

  The signal processing circuit unit 10 can be either the circuit of FIG. 2 or FIG. 3 applied in the first embodiment. The signal processing circuit unit 10 performs a buffer operation by feeding back the output out to the voltage of the input in.

  FIG. 9 is a drive pulse timing chart in the second mode (defective pixel detection mode). In the period from time t11 to t12 when the gate voltage of the MOS switch 20 becomes high level, the defective pixel detection operation is performed by turning off the MOS switch 11. Other than that is the same as FIG. By setting the period from the time t10 when the MOS switch 11 is turned off to the time t12 when the MOS switch 20 is turned off to be sufficiently long, pixel defects caused by RTS noise are detected from the maximum value. The principle of detecting RTS noise by maximum value detection is exactly the same as in the first embodiment. By using the minimum value circuit of the second embodiment instead of the reading unit 10 of the present embodiment, a defect inspection circuit that detects the minimum value can be configured. The effect of shortening the inspection time according to this embodiment is the same as that of the first embodiment and the second embodiment.

  In the present embodiment, a defect detection circuit using a column amplifier circuit is shown as means for improving the S / N ratio of the two-dimensional solid-state imaging device.

  As described above, the signal processing circuit 10 includes the first mode (FIG. 8) in which the buffer operation is performed on the output signal of the column amplifier front stage 17 and the maximum value or the minimum value of the output signal of the column amplifier front stage 17 during a certain period. A MOS switch 11 is provided for switching between the second mode (FIG. 9) for detecting a value.

  As described above, according to the first to third embodiments, by providing the maximum value detection circuit or the minimum value detection circuit in the column readout circuit of the solid-state imaging device, the RTS noise can be achieved with a small number of frames or a short inspection time. It becomes possible to detect defective pixels caused by the above. As a result, it becomes possible to detect defective pixels caused by short-time RTS noise.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

1 is a configuration diagram of a solid-state imaging device according to a first embodiment of the present invention. It is a drive pulse timing diagram of the solid-state imaging device of the first embodiment. It is a signal processing circuit diagram of the solid-state imaging device of the first embodiment. It is a drive pulse timing diagram of the defective pixel detection operation of the solid-state imaging device of the first embodiment. It is a circuit diagram which shows another example of the signal processing circuit of the solid-state imaging device of 1st Embodiment. It is a signal processing circuit diagram of the solid-state imaging device concerning a 2nd embodiment of the present invention. It is a block diagram of the solid-state imaging device which concerns on the 3rd Embodiment of this invention. It is a drive pulse timing diagram of the solid-state imaging device of a 3rd embodiment. It is a drive pulse timing diagram of the defective pixel detection operation of the solid-state imaging device of the third embodiment.

Explanation of symbols

1 Pixel part 2 Photodiode (PD)
3 Pixel source follower (SF) transistor 4 Transfer MOS transistor (PTX)
5 Reset MOS transistor (PRES)
6 Select MOS transistor (PSEL)
7 Signal line 8 Clamping part 9 MOS switch (PC0R)
10 signal processing circuit section 11 MOS switch (operation switching control terminal)
12 line memory unit 13 MOS switch (PTC1)
14 Capacity (CTC)
15 MOS switch (PTC2)
16 row amplifier 17 row amplifier front stage 18 MOS switch (PTN)
19 Capacity (CTN)
20 MOS switch (PTS)
21 Capacity (CTS)
22 Output stage

Claims (9)

A photoelectric conversion unit that converts incident light into electric charge; an amplification unit that outputs a signal based on the potential of the input unit; a transfer unit that transfers the charge held in the photoelectric conversion unit to the input unit of the amplification unit; A pixel unit having a reset unit for resetting the potential of the input unit of the amplification unit;
A buffer unit that performs a buffer operation on an output signal output from the pixel unit;
A solid-state imaging device having a memory unit for storing the output signal,
The buffer unit includes switching means for switching between a first mode for buffering the output signal and a second mode for detecting a maximum value or a minimum value of the output signal in a certain period. A solid-state imaging device. The amplifying unit based on the noise signal output from the amplifying unit based on the resetting of the input unit by the reset unit and the charge transferred from the photoelectric conversion unit to the input unit by the transfer unit Has a difference calculation unit that performs a difference calculation with the optical signal output from
The solid-state imaging device according to claim 1, wherein the difference calculation unit includes a clamp unit that clamps the noise signal.   The solid-state imaging device according to claim 2, wherein the difference calculation unit includes a capacitive feedback differential amplifier.   The buffer unit includes a differential amplifier circuit that receives the output signal at a non-inverting input terminal, and a source follower circuit that receives the output signal of the differential amplifier circuit, and the output terminal of the source follower circuit is the The solid-state imaging device according to claim 1, wherein the solid-state imaging device is connected to an inverting input terminal of the differential amplifier circuit.   The switching means conducts the output terminal of the source follower circuit and the reference potential node in the first mode, and disconnects the output terminal of the source follower circuit and the reference potential node in the second mode. The solid-state imaging device according to claim 4, wherein   The switching means conducts the output terminal of the source follower circuit and the power supply potential node in the first mode, and disconnects the output terminal of the source follower circuit and the power supply potential node in the second mode. The solid-state imaging device according to claim 4, wherein The buffer unit includes a differential amplifier circuit that receives the output signal at a non-inverting input terminal;
The differential amplifier circuit includes a constant current source,
The solid-state imaging device according to claim 1, wherein an inverting input terminal of the differential amplifier circuit is short-circuited with an output terminal of the differential amplifier circuit.   8. The solid-state imaging device according to claim 7, wherein the switching unit operates the constant current source in the first mode and shuts off the constant current source in the second mode. The first mode is used as a normal imaging operation,
The solid-state imaging device according to any one of claims 1 to 8, wherein the second mode is used for detection of defective pixels caused by random telegraph signal noise.

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