JP2010102387A - Parasitic element extracting device and parasitic element extracting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a parasitic element extracting device and a parasitic element extracting method for extracting a parasitic element around a well region by a simple circuit configuration. <P>SOLUTION: In the parasitic element extracting device 1, a parasitic capacitance extraction part 11 extracts a layout pattern of each of well regions as a parasitic capacitance respectively from layout data 100 of a semiconductor integrated circuit, a parasitic resistance extraction part 12 extracts a layout pattern of a subcontact included in the well region as a parasitic resistance from the layout data 100, and a parasitic element addition part 13 adds the parasitic capacitance extracted by the parasitic capacitance extraction part 11 and the parasitic resistance extracted by the parasitic resistance extraction part 12 to a netlist 300 extracted from the layout data 100 in common among back gate terminals of all MOSFETs included in the respective well regions to output a parasitic element-added netlist 400. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a parasitic element extraction apparatus and a parasitic element extraction method.

  In the design of semiconductor integrated circuits, in order to perform circuit evaluation close to actual measurement, after layout execution, wiring resistance and wiring capacitance contained in wiring, parasitic capacitance between transistors and wiring, etc. are extracted from the layout pattern. Back annotation is performed to add parasitic components to the original circuit.

  In recent years, the miniaturization of transistors has progressed, and in CMOS LSI and the like, the influence on the device characteristics due to the potential of the back gate of the MOSFET has become remarkable. Therefore, in the back annotation, it is necessary to extract a parasitic element around the well region that becomes the back gate of the MOSFET.

  Conventionally, as a method of extracting parasitic elements around the well region, the well region is divided into meshes, the parasitic resistance and the parasitic capacitance are extracted for each rectangular region divided into meshes, and these are combined in a mesh shape. Has been proposed (see, for example, Patent Document 1).

  If a network as described above is created, a highly accurate simulation can be executed. However, since the number of elements is much larger than that of the original circuit and the circuit configuration is complicated, it takes much time to execute the simulation. In particular, in the case of a large-scale circuit, there arises a problem that analysis cannot be performed in a realistic time.

In general, it is desired that the simulation result is obtained earlier than the simulation accuracy in the initial stage of circuit evaluation.
JP-A-10-50849 (5th page, FIG. 10)

  Therefore, an object of the present invention is to provide a parasitic element extraction apparatus and a parasitic element extraction method that can extract parasitic elements around a well region with a simple circuit configuration.

  According to one aspect of the present invention, there is provided a parasitic element extraction apparatus that extracts a parasitic element from layout data of a semiconductor integrated circuit and adds the parasitic element to a netlist extracted from the layout data, wherein each well region is extracted from the layout data. A parasitic capacitance extracting means for extracting each of the layout patterns as a parasitic capacitance; a parasitic resistance extracting means for extracting a layout pattern of a sub-contact included in the well region from the layout data as a parasitic resistance; and There is provided a parasitic element extraction device comprising: parasitic element addition means for adding the parasitic capacitance and the parasitic resistance in common to the back gate terminals of all MOSFETs included in the respective well regions. .

  According to another aspect of the present invention, there is provided a parasitic element extraction method for extracting a parasitic element from layout data of a semiconductor integrated circuit and adding the parasitic element to a net list extracted from the layout data, wherein the parasitic data is extracted from the layout data. A parasitic capacitance extracting step of extracting a layout pattern of each well region as a parasitic capacitance; a parasitic resistance extracting step of extracting a layout pattern of sub-contacts included in the well region as a parasitic resistance from the layout data; and the netlist. And a parasitic element adding step for adding the parasitic capacitance and the parasitic resistance in common to the back gate terminals of all MOSFETs included in the respective well regions. Is provided.

  According to the present invention, parasitic elements around the well region can be extracted with a simple circuit configuration.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  FIG. 1 is a block diagram illustrating an example of the configuration of a parasitic element extraction apparatus according to Embodiment 1 of the present invention.

  The parasitic element extraction apparatus 1 of this embodiment includes a parasitic capacitance extraction unit 11 that extracts the layout pattern of each well region as a parasitic capacitance from the layout data 100 of the semiconductor integrated circuit, and a sub-element included in the well region from the layout data 100. For the parasitic resistance extractor 12 that extracts the contact layout pattern as a parasitic resistance, and the netlist 300 extracted from the layout data 100, the common back gate terminals of all MOSFETs included in the respective well regions, A parasitic element adding unit 13 that adds the parasitic capacitance extracted by the parasitic capacitance extracting unit 11 and the parasitic resistance extracted by the parasitic resistance extracting unit 12 and outputs a parasitic element adding netlist 400.

  Here, in the netlist 300, the terminal names and signal names corresponding to the circuit diagram 200 are given by the circuit comparison unit 2000 to the elements extracted from the layout data 100 by the element extraction unit 1000 using the conventional technique. Has been generated.

  FIG. 2 is a flowchart showing an example of the flow of parasitic element extraction processing in the parasitic element extraction apparatus 1 of the present embodiment.

  When the parasitic element extraction starts, first, the parasitic capacitance extraction unit 11 reads the layout pattern of the well region from the layout data 100 (step S01), and calculates the parasitic capacitance value based on the pattern area. When the pattern area is calculated and the parasitic capacitance value is calculated based on the pattern peripheral length, the pattern peripheral length is calculated. Alternatively, when calculating the parasitic capacitance value based on the pattern area and the pattern peripheral length, both the pattern area and the pattern peripheral length of the layout pattern are calculated (step S02).

  Subsequently, the parasitic capacitance extraction unit 11 multiplies the calculated pattern area by a predetermined capacitance value per unit area, and multiplies the pattern peripheral length by a predetermined capacitance value per unit peripheral length. The parasitic capacitance value of the well region is calculated (step S03).

  Subsequently, the parasitic resistance extraction unit 12 reads the layout pattern of the sub-contact included in the well region from the layout data 100 (step S04), and calculates the parasitic resistance value of the sub-contact based on the contact resistance value calculated in advance. Calculate (step S05).

  Finally, the parasitic element adding unit 13 is extracted by the parasitic capacitance and parasitic resistance extracting unit 12 extracted by the parasitic capacitance extracting unit 11 in common to the back gate terminals of all MOSFETs included in each well region. A parasitic resistance is added (step S06), the parasitic element addition net list 400 is output (step S07), and the process is terminated.

  Next, an example of the parasitic element extraction operation in this embodiment will be described with reference to FIGS.

  FIG. 3 is an image diagram of a layout pattern to be subjected to parasitic element extraction processing. Here, as an example of the well region, an N well region in which the PMOSFET is disposed will be described as an example, but the same processing is performed in the P well region in which the NMOSFET is disposed. In this example, it is assumed that PMOSFETs P1 to P5 are extracted in the N well 21 region by the element extraction unit 1000.

  Four sub-contacts 22 are arranged in the N well 21, and each sub-contact 22 is connected to a power supply wiring pattern 23.

  For such a layout pattern, as shown in FIG. 4A, the parasitic capacitance extraction unit 11 reads the pattern of the N well 21, calculates the pattern area, and parasitic capacitance C derived from the N well 21. The capacity value of is calculated. Further, as shown in FIG. 4B, the parasitic resistance extraction unit 12 reads the pattern of the subcontact 22 included in the region of the N well 21, and extracts the parasitic resistances R1, R2, R3, and R4 derived from the subcontact. Calculate the resistance value.

  The parasitic element addition unit 13 adds the above-described parasitic capacitance C and parasitic resistances R1 to R4 to the back gate terminals of the PMOSFETs P1 to P5 included in the well region of the N well 21, and outputs a parasitic element addition netlist 400. To do.

  FIG. 5 shows the parasitic element added netlist 400 as a symbolic circuit diagram.

  Here, when a terminal in which the back gate terminals of the PMOSFETs P1 to P5 are connected in common is represented as a common back gate terminal BG, the parasitic capacitance C is added between the common back gate terminal BG and the ground terminal, and the parasitic resistances R1 to R1. R4 is added between the common back gate terminal BG and the power supply terminal VDD.

  According to the present embodiment, since the parasitic element around the well region is commonly added to the back gate terminal of the MOSFET included in the well region, the circuit configuration for adding the parasitic element to the back gate terminal of the MOSFET is provided. Can be simple. As a result, when simulating a circuit to which a parasitic element is added, the simulation execution time can be shortened, and the analysis time of the circuit operation considering the influence of the parasitic element around the well region can be shortened.

  With the recent progress in miniaturization and high integration of semiconductor integrated circuits, the influence of power supply wiring on the reduction in power supply voltage, so-called IR drop circuit operation, is increasing. Therefore, extraction of the wiring resistance of the power supply wiring is performed as one of the parasitic elements. However, if the resistance of the sub-contact connected to the well region is ignored at that time, the power supply wiring in the section where the sub-contact is connected is short-circuited through the well region. As a result, the wiring resistance of the power supply wiring in the section where the sub-contact is connected is not calculated, and accurate IR drop analysis cannot be performed.

  Therefore, in this embodiment, the parasitic resistance extraction unit 12 calculates the resistance of the subcontact and calculates the wiring resistance between the subcontacts of the power supply wiring to which the subcontact is connected.

  When calculating the wiring resistance between the sub-contacts, the parasitic resistance extraction unit 12 calculates the wiring length between the sub-contacts of the power supply wiring, and calculates the wiring resistance corresponding to each wiring length.

  FIG. 6 is an example of calculation of the wiring length between sub-contacts by the parasitic resistance extraction unit 12 for the layout pattern of FIG.

  In the example shown in FIG. 6, the wiring lengths L1, L2, and L3 between the four sub-contacts 22 connected to the power wiring pattern 23 are calculated.

  For the wiring lengths L1, L2, and L3, the parasitic resistance extraction unit 12 calculates a wiring resistance value based on the resistance value per unit wiring length of the power supply wiring pattern 23.

  In addition to the parasitic elements added to the back gate terminal of the MOSFET as shown in the first embodiment, the parasitic element adding unit 13 in this embodiment uses the wiring resistance of the power supply wiring pattern 23 as a parasitic element around the N well 21. Add as

  FIG. 7 shows, as a symbolic circuit diagram image, an example of a parasitic element addition netlist 400 output from the parasitic element addition unit 13 with wiring resistances R1, L12, and R13 corresponding to the wiring lengths L1, L2, and L3.

  As shown in FIG. 7, in this embodiment, the wiring resistors R11, R12, and R13 are connected to the common back gate terminal BG through the sub-contact parasitic resistors R1, R2, R3, and R4. Therefore, the power supply wiring in the section where the sub-contact is connected is not short-circuited, and a simulation can be performed in consideration of the resistance of the power supply wiring.

  According to the present embodiment, since the wiring resistance between the sub-contacts of the power supply wiring is also added as a parasitic element, the circuit operation analysis closer to the actual operation including the voltage drop due to the wiring resistance of the power supply wiring is included. Is possible.

The block diagram which shows the example of a structure of the parasitic element extraction apparatus which concerns on Example 1 of this invention. FIG. 3 is a flowchart illustrating an example of a flow of parasitic element extraction processing in the parasitic element extraction apparatus according to the first embodiment. The image figure of the layout pattern of a parasitic element extraction process target. FIG. 3 is a diagram illustrating an example of parasitic element extraction in the parasitic element extraction apparatus according to the first embodiment. The figure which shows the parasitic element addition net list | wrist output from the parasitic element extraction apparatus of Example 1 symbolically. The figure for demonstrating the wiring resistance extraction process by the parasitic resistance extraction part of Example 2 of this invention. FIG. 9 is a diagram symbolically showing a parasitic element addition net list output from a parasitic element extraction apparatus of Embodiment 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Parasitic element extraction apparatus 11 Parasitic capacitance calculation part 12 Parasitic resistance calculation part 13 Parasitic element addition part

Claims (5)

A parasitic element extraction device that extracts a parasitic element from layout data of a semiconductor integrated circuit and adds the parasitic element to a net list extracted from the layout data,
Parasitic capacitance extraction means for extracting the layout pattern of each well region as a parasitic capacitance from the layout data;
A parasitic resistance extracting means for extracting a layout pattern of a sub-contact included in the well region as a parasitic resistance from the layout data;
Parasitic element adding means for adding the parasitic capacitance and the parasitic resistance to the netlist in common to the back gate terminals of all MOSFETs included in the respective well regions Element extraction device. The parasitic capacitance extracting means includes
2. The parasitic element extraction device according to claim 1, wherein a capacitance value of the parasitic capacitance is calculated based on an area or a peripheral length of the layout pattern of the well region or an area and a peripheral length. The parasitic resistance extracting means includes
The parasitic element extraction device according to claim 1, wherein a resistance value of the parasitic resistance is calculated based on a contact resistance value of the sub-contact. The parasitic resistance extracting means is
The wiring resistance between the sub-contacts of the power wiring pattern is calculated according to the wiring length between the sub-contacts of the power wiring pattern to which a plurality of the sub-contacts are connected. Parasitic element extraction device. A parasitic element extraction method for extracting a parasitic element from layout data of a semiconductor integrated circuit and adding it to a netlist extracted from the layout data,
A parasitic capacitance extraction step of extracting the layout pattern of each well region as a parasitic capacitance from the layout data;
A parasitic resistance extraction step of extracting a layout pattern of a sub-contact included in the well region as a parasitic resistance from the layout data;
A parasitic element adding step for adding the parasitic capacitance and the parasitic resistance to the netlist in common to the back gate terminals of all MOSFETs included in the respective well regions. Element extraction method.

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