JP2010177692A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve packaging properties of a semiconductor device assembled by using a leadframe. <P>SOLUTION: The semiconductor device includes: a sealing section 3; a tab 1b which supports a semiconductor chip 2; a tab hanging lead which supports the tab 1b; a plurality of leads 1a which are arranged around the tab 1b; a cutting burr 1i which is formed at a cutting end of a lead 1a and the tub hanging lead when a leadframe 1 is cut, and which does not project but recedes from a connected surface 1d of the lead 1a and the tub hanging lead; and a wire which connects a pad of a semiconductor chip 2 and the lead 1a. A recess 1j as a thin part is formed in a cut-off area 1k of the leadframe 1. This makes the tip of the cutting burr 1i formed by lead-cutting with a blade 6 not project but recede from the connected surface 1d of the lead 1a and the tub hanging lead. Thereby, a flatness degree of the connected surface 1d of the lead 1a or the tab hanging lead is improved, and the packaging properties of the QFN (Quad Flat Non-leaded package) are improved. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique that is effective when applied to improve the mountability of a semiconductor device assembled using a lead frame.

  The technology described below has been studied by the present inventors in researching and completing the present invention, and the outline thereof is as follows.

  As a miniaturized semiconductor device, a small semiconductor package, which is slightly larger than a semiconductor chip called QFN (Quad Flat Non-leaded Package), has been developed. A plurality of leads serving as external terminals are arranged so as to be exposed, and the semiconductor package having such a structure is called a peripheral type.

  In the assembly of QFN, a plurality of semiconductor chips are collectively molded in one cavity of a mold, and after the molding, the packaged sealing part is cut and separated by a dicing blade together with a lead frame to separate the chips. A scheme has been devised.

  Note that the structure of the QFN assembled using the lead frame is described in Non-Patent Document 1, for example.

Press Journal Co., Ltd., issued July 27, 1998, “Monthly Semiconductor World special issue '99 Semiconductor assembly and inspection technology”, pages 53-57

  However, in the assembly of the QFN of the above-described technique, when the lead is cut after molding, a cutting burr protrudes from the connected surface of the lead (including the suspension lead). In particular, since the location where the blade movement direction intersects the X direction and the Y direction is cut twice, the cutting burr is greatly formed on the lead at the corner of the QFN and protrudes to the connected surface. .

  As a result, the flatness of the connected surface of the lead deteriorates, and there is a problem that the mountability of the completed QFN is lowered.

  An object of the present invention is to provide a method of manufacturing a semiconductor device that improves mountability.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the method for manufacturing a semiconductor device according to the present invention includes: (a) a chip mounting portion, a plurality of suspension leads that support the chip mounting portion, and a plurality of leads that are arranged around the chip mounting portion. A package region and a plurality of package regions, each of which is located between adjacent package regions and formed thinner than each of the plurality of leads, each of the plurality of suspension leads and each of the plurality of leads. And (b) preparing a plurality of semiconductor chips each having a main surface on which a plurality of pads are formed, and arranging the plurality of semiconductor chips in the plurality of package regions. (C) mounting the plurality of pads and the plurality of leads of the semiconductor chip with a plurality of wires; (D) a step of sealing the plurality of semiconductor chips, the plurality of wires, and the plurality of package regions with a resin so that a part of each of the plurality of leads is exposed. (E) preparing a blade having a width narrower than a width of the cutting portion, running the blade along the cutting portion so that an edge portion of the blade is located in the cutting portion, and Dividing the package region.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1). A concave portion corresponding to the dicing line is formed in the cut portion of the thin plate member capable of supporting the semiconductor chip, and the size of the cutting burr can be reduced by dividing the concave portion by a blade in the concave portion. Protrusion of the cutting burr to the connection surface can be prevented. As a result, the flatness of the connected surface of the external terminal can be improved, and the mountability of the semiconductor device can be improved.

  (2). By forming recesses in the cutting part in at least two rows at the same interval as the thickness of the blade, the edge part of the blade can be placed in the recess during cutting, and the size of the cutting burr is reliably reduced Can do. As a result, the flatness of the connected surface of the external terminal can be further improved, and the mountability of the semiconductor device can be improved.

  (3). Even if the cut part is cut twice at the orthogonal part by forming a concave part corresponding to the dicing line and another concave part or through hole deeper than the concave part corresponding to the orthogonal part of the dicing line. The size of the cutting burr formed at that time can be reduced. Accordingly, it is possible to reliably prevent the cutting burr from projecting to the connected surface at the external terminal at the corner of the semiconductor device.

(A), (b), (c) is a figure which shows the structure of QFN which is an example of the semiconductor device assembled by the manufacturing method of the semiconductor device of embodiment of this invention, (a) is a top view, ( b) is a side view, and (c) is a bottom view. It is an expanded sectional view which shows the structure of QFN shown in FIG. It is a process flow figure showing an example of an assembly procedure in manufacture of QFN shown in FIG. FIG. 2 is a partial plan view showing a structure of a lead frame used for assembling the QFN shown in FIG. 1. (A), (b) is a figure which shows an example of the state after a mold in the assembly procedure shown in FIG. 3, (a) is a top view, (b) is a side view. (A), (b), (c) is a figure which shows an example of the state at the time of the cutting | disconnection in the assembly procedure shown in FIG. 3, (a) is a fragmentary sectional view before cutting | disconnection, (b) is a figure of (a). The expanded partial sectional view of A part, (c) is the fragmentary sectional view after a cutting | disconnection. (A), (b) is a figure which shows the shape of the recessed part of the modification with respect to the recessed part of the lead frame shown in FIG. 6, (a) is a fragmentary sectional view before a cutting | disconnection, (b) is B part of (a). FIG. FIG. 7 is a partial plan view showing the shape of a lead frame according to a modification of the lead frame shown in FIG. 6. (A), (b) is an expanded partial sectional view which shows the shape of the recessed part of the modification with respect to the recessed part of the lead frame shown in FIG. It is sectional drawing which shows the method of individualization after the collective molding in the manufacturing method of the semiconductor device of other embodiment of this invention. (A), (b), (c) is a figure which shows the structure of LGA which is a semiconductor device assembled by the manufacturing method of the semiconductor device of other embodiment of this invention, (a) is a top view, ( b) is a side view, and (c) is a bottom view. It is an expanded sectional view which shows the structure of LGA shown in FIG. It is a top view which shows the structure of the wiring board used for the assembly of LGA shown in FIG. (A), (b) is a figure which shows the structure of the C section of the wiring board shown in FIG. 13, (a) is an enlarged plan view of the surface side (chip mounting side), (b) is an enlarged bottom view. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  1A and 1B are views showing a structure of a QFN which is an example of a semiconductor device assembled by a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view, FIG. 1B is a side view, and FIG. 2 is a bottom view, FIG. 2 is an enlarged cross-sectional view showing the structure of the QFN shown in FIG. 1, FIG. 3 is a process flow diagram showing an example of an assembly procedure in manufacturing the QFN shown in FIG. 1, and FIG. FIG. 5 is a diagram showing an example of a state after molding in the assembly procedure shown in FIG. 3, (a) is a plan view, (b) is a side view, 6 is a diagram showing an example of a state during cutting in the assembly procedure shown in FIG. 3, (a) is a partial cross-sectional view before cutting, (b) is an enlarged partial cross-sectional view of part A of (a), c) is a partial sectional view after cutting, and FIG. 7 is the lead frame shown in FIG. FIG. 8 is a diagram showing the shape of a concave portion of a modified example with respect to the concave portion of the beam, where (a) is a partial cross-sectional view before cutting, (b) is an enlarged partial cross-sectional view of portion B of FIG. 9 is a partial plan view showing the shape of a modified lead frame with respect to the lead frame shown, and FIG. 9 is an enlarged partial sectional view showing the shape of a recessed portion of the modified example with respect to the recessed portion of the lead frame shown in FIG.

  1 uses a lead frame (thin plate member) 1 shown in FIG. 4 and a surface (chip mounting) which is one side of the lead frame 1. 1 is a single-sided resin-sealed small semiconductor package in which the sealing portion 3 shown in FIG. 1 is formed on the side, and a plurality of leads are provided on the peripheral portion of the back surface 3a of the sealing portion 3. The peripheral surface 1d of the peripheral surface 1d is also exposed, and QFN5 will be described as an example of the semiconductor device.

  Therefore, each lead 1a of the QFN 5 functions as both an inner lead embedded in the sealing portion 3 and an outer lead exposed at the peripheral edge of the back surface 3a of the sealing portion 3.

  The detailed configuration of the QFN 5 will be described with reference to FIGS. 1 and 2. A tab (1) having a sealing portion 3 formed by resin-sealing the semiconductor chip 2 and a chip support surface 1 c that supports the semiconductor chip 2 ( A chip mounting portion) 1b, a tab suspension lead 1e that supports the tab 1b and is exposed at the four corners of the peripheral portion of the back surface 3a of the sealing portion 3, and is disposed around the tab 1b, and A plurality of leads 1a arranged along the peripheral edge of the back surface 3a of the sealing portion 3 so as to expose the connected surface 1d and the cut ends of the leads 1a and the tab suspension leads 1e when the lead frame 1 is cut. In addition, the cutting burr 1i shown in FIG. 6C that is retracted without protruding from the connected surface 1d of the lead 1a or the tab suspension lead 1e, the pad 2a that is the surface electrode of the semiconductor chip 2, and the corresponding With lead 1a Consisting wire 4 which for bonding to be connected.

  That is, when the cutting portion 1k of the lead frame 1 shown in FIG. 4 and FIG. 5 is formed with the concave portion 1j as a thin portion as shown in FIG. As shown in FIG. 6 (c), the tip of the cutting burr 1i formed in the state is retracted without protruding from the connected surface 1d of the lead 1a or the tab suspension lead 1e. The flatness of the connected surface 1d of the lead 1a and the tab suspension lead 1e can be improved, and as a result, the mountability of the QFN 5 can be improved.

  As shown in FIG. 2, the semiconductor chip 2 is fixed on the chip support surface 1c of the tab 1b by a die bond material (for example, silver paste) 12.

  Further, a solder plating layer 10 having a thickness of about 10 μm is formed on the connected surface 1 d of the lead 1 a which is an external terminal arranged along the peripheral edge of the back surface 3 a of the sealing portion 3 of the QFN 5.

  The tab 1b, the tab suspension lead 1e, and each lead 1a are formed of a thin plate material such as copper, for example, and the thickness is about 0.15 to 0.2 mm.

  Further, the wire 4 that connects the pad 2a of the semiconductor chip 2 and the corresponding lead 1a is, for example, a gold wire.

  Moreover, the sealing part 3 is formed by resin sealing by a molding method, and the sealing resin used at that time is, for example, a thermosetting epoxy resin.

  Next, a method for manufacturing QFN 5 (semiconductor device) according to the present embodiment will be described with reference to a process flow diagram shown in FIG.

First, a tab 1b, which is a plurality of chip mounting portions that can support the semiconductor chip 2 shown in FIG. 2, a tab suspension lead 1e that supports the tab 1b at its corners, a periphery of the tab 1b, and a resin seal It consists of a plurality of leads 1a having a connected surface 1d exposed at the peripheral edge of the back surface 3a of the sealing portion 3 when stopped, and a cutting portion 1k that partitions the tab 1b and the surrounding leads 1a. A recess 1j as shown in FIG. 6 corresponding to the dicing line 1h for division is formed in the cutting portion 1k.
A lead frame 1 which is a thin plate member shown in FIG. 4 in which is formed is prepared (step S1).

  In addition, the dotted line part shown in FIG. 4 is the mold line 1n after a mold.

  Further, as shown in FIG. 6B, the recess 1j has a depth when the basic thickness (T) of the lead 1a is 0.2 mm and the width (L1) of the blade 6 is 100 μm, for example. (Z1 or Z2) is approximately 30 μm, and the width (L2) of the recess 1j is approximately 150 μm. That is, the width of the recess 1 j is larger (wider) than the width of the blade 6.

However, when a plurality of recesses 1j are formed and regarded as one recess 1j, the distance from the recess 1j at one end to the recess 1j at the opposite end may be made larger than the width of the blade 6.

  Further, the depth of the recess 1j is not limited to 30 μm, but is set according to the amount (height) of the generated cutting burr 1i.

  Further, the recess 1j is formed in the cut portion 1k of the lead frame 1 corresponding to the dicing line 1h shown in FIG. 5 (a). At that time, as shown in FIGS. 6 (a) and 6 (b). It is preferable to be formed on both the front and back surfaces, so that the size of the cutting burr 1i during cutting can be made as small as possible.

  Therefore, when cutting into QFN pieces, the recess 1j formed corresponding to the dicing line 1h is cut by moving the blade 6 in the X direction and the Y direction along the recess 1j.

  Note that the recess 1j may be formed only on either the front surface 1g or the back surface 11 of the lead frame 1, as shown in the modification of FIGS. 9 (a) and 9 (b).

  The recesses 1j are preferably formed in at least two rows at approximately the same interval as the thickness of the dividing blade 6, as shown in the modified examples of FIGS. 7 (a) and 7 (b).

  In this way, at the time of cutting, the edge of the blade 6, that is, the peripheral portions on both the front and back sides of the blade 6 can be arranged in the recessed portions of the recess 1j, respectively, and the size of the cutting burr 1i formed by cutting is made as small as possible. can do.

  However, the number of the recesses 1j may be two or more.

  Further, as shown in the modified example of FIG. 8, a lead frame 1 in which a cut portion 1k is formed with a recess 1j corresponding to a dicing line 1h and a through hole 1m corresponding to an orthogonal position of the dicing line 1h. Also good.

  As a result, even if the blade 6 is cut twice at a location orthogonal to the dicing line 1h by traveling in the X direction and the Y direction, the cutting burr 1i generated there can be reduced.

  In addition, what is provided in the orthogonal location of the dicing line 1h does not necessarily have to be the through hole 1m, and may be a groove (other recess) deeper than the recess 1j.

  Here, the lead frame 1 is a strip-like elongated multiple body capable of manufacturing a plurality of QFNs 5 from a single lead frame 1, and is further arranged in a matrix arrangement on the single lead frame 1. The QFN 5 can be manufactured. Therefore, a plurality of package regions corresponding to one QFN 5 are formed in a matrix arrangement on one lead frame 1.

  The lead frame 1 is a thin plate material formed of, for example, copper (Cu) and the thickness thereof is, for example, about 0.15 to 0.2 mm. However, it is not limited to these.

  Thereafter, a semiconductor chip 2 having a semiconductor integrated circuit formed on the main surface 2b is prepared, and die bonding (step S2) in which the back surface 2c of the semiconductor chip 2 and the chip support surface 1c of the tab 1b of the lead frame 1 are bonded ( (Also called pellet bonding or chip mounting).

  That is, the semiconductor chip 2 is mounted on the chip support surface 1 c of the tab 1 b of the lead frame 1.

  At that time, the semiconductor chip 2 is fixed to the tab 1 b of the lead frame 1 with the main surface 2 b facing upward via a die bond material (for example, silver paste) 12.

  Subsequently, as shown in FIG. 2, the pad 2a of the semiconductor chip 2 and the bonding surface 1f of the lead 1a corresponding to the pad 2a are wire-bonded by a bonding wire 4 (step S3).

  Thereafter, the semiconductor chip 2 is resin-sealed by a mold shown in step S4 (here, transfer mold) to form the sealing portion 3 on the surface 1g side of the lead frame 1 (single-sided molding is performed).

  Here, the mold is performed using the mold die in which the cavity of the mold die and the QFN 5 have a one-to-one correspondence.

  As a result, as shown in FIGS. 5A and 5B, a plurality of sealing portions 3 are formed in a matrix arrangement on the lead frame 1.

  After that, lead cutting (separation) shown in step S5 for cutting and separating each lead 1a and tab suspension lead 1e protruding from the sealing portion 3 from the lead frame 1 is performed.

  At that time, the blade 6 for division is run in the X direction and the Y direction on the recess 1j formed corresponding to the dicing line 1h in the cutting part 1k of the lead frame 1, and each QFN5 (here, each tab 1b). To split).

  At the time of cutting, as shown in FIG. 6 (b), the blade 6 travels in the recess 1j. Therefore, the cutting burr 1i shown in FIG. 6 (c) is protruded from the connected surface 1d of the lead 1a. Can be divided without

  As shown in FIGS. 7A and 7B, the recesses 1j are formed in at least two rows at approximately the same interval as the thickness of the dividing blade 6, so that the edge of the blade 6, that is, the blade 6 is formed. Both of the peripheral edge portions can be arranged and cut at the recessed portions of the recesses 1j, whereby the size of the cutting burr 1i can be reduced.

  Further, as shown in FIG. 8, through holes 1m are formed at the orthogonal positions of the dicing line 1h of the cutting portion 1k, so that the blade 6 travels in the X direction and the Y direction at an orthogonal position of the dicing line 1h. Even when the cutting is performed twice, the cutting burr 1i generated there can be reduced.

  That is, the cutting burr 1i formed at the corner of the QFN 5 can be reduced.

  By dividing into pieces, the QFN 5 shown in FIGS. 1 and 2 is completed (step S6).

  According to the manufacturing method of QFN 5 (semiconductor device) of the present embodiment, the following operational effects are obtained.

  That is, a recess 1j corresponding to the dicing line 1h is formed in the cut portion 1k of the lead frame 1 capable of supporting the semiconductor chip 2, and the size of the cut burr 1i is reduced by dividing the recess 1j by the blade 6. Thus, it is possible to prevent the cutting burr 1i from protruding to the connected surface 1d in each lead 1a (including the tab suspension lead 1e).

  As a result, the flatness of the connected surface 1d of the lead 1a can be improved, and therefore, the mountability of the QFN 5 can be improved.

  In addition, since the recesses 1j are formed in two rows at approximately the same interval as the thickness of the blade 6 in the cutting portion 1k, the edge portion of the blade 6 can be disposed in the recess 1j at the time of cutting.

  As a result, the size of the cutting burr 1i can be reliably reduced, and the protrusion of the cutting burr 1i to the connected surface 1d can be further prevented in each lead 1a.

  Thereby, the flatness of the to-be-connected surface 1d of the lead 1a can be further improved, and the mountability of the QFN 5 can be improved.

  Further, as in the present embodiment, the thin plate member is the lead frame 1, and in the cut portion 1k, as shown in FIG. 8, the concave portion 1j corresponding to the dicing line 1h and the orthogonal position of the dicing line 1h are supported. By forming the through-hole 1m, the size of the cut portion 1k formed at that time can be reduced even if it is cut twice in the X direction and the Y direction at a location orthogonal to the dicing line 1h. it can.

  Thereby, in the lead 1a at the corner portion of the QFN 5 (in particular, the tab suspension lead 1e in this case), it is possible to reliably prevent the cutting burr 1i from protruding to the connected surface 1d.

  As a result, the flatness of the lead 1a at the corner of the QFN 5 and the connected surface 1d of the tab suspension lead 1e can be improved, and the mountability of the QFN 5 can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above-described embodiment, as illustrated in FIG. 5, the case where a plurality of sealing portions 3 are formed on the lead frame 1 by molding a region corresponding to one QFN 5 in different cavities has been described. As a manufacturing method of QFN5, in the molding process of step S4 shown in FIG. 3, a region corresponding to a plurality of QFN5 is molded in a lump like the molding method of another embodiment shown in FIG. After that, the batch sealing portion 7 and the lead frame 1 formed thereby may be divided and cut together using a blade 6 into individual pieces.

  Even in the manufacturing method using the batch molding, the size of the cutting burr 1i can be reduced by forming the recess 1j in the cutting portion 1k of the lead frame 1, and the QFN 5 assembled by the batch molding can be reduced. Mountability can be improved.

  In the above-described embodiment, the thin plate member is the lead frame 1 and the semiconductor device manufactured using the lead frame 1 is the QFN 5. However, the semiconductor device includes a cut portion 1k and a recess 1j. A semiconductor device other than the QFN 5 may be used as long as it is manufactured using the lead frame 1 formed with.

  Further, the thin plate member is not limited to the lead frame 1 but may be the wiring board 8 as in other embodiments shown in FIGS.

  Here, the semiconductor device shown in FIGS. 11A, 11B, and 12C and FIG. 12 is an LGA (Land Grid Array) assembled by using the wiring board 8 which is a multi-chip substrate shown in FIG. 11.

  In the wiring substrate 8 shown in FIG. 13, the region corresponding to each LGA 11 is the package substrate 9 shown in FIGS. 14A and 14B, and a wiring in which a thin portion similar to the recess 1 j shown in FIG. 6 is formed. Using the substrate 8, the semiconductor chip 2 is mounted on each package substrate 9 of the wiring substrate 8, further connected by the wire 4, and then batch-molded, and then the blade 6 on the thin portion of the wiring substrate 8. Each package substrate 9 is divided into individual pieces, and an assembly assembled thereby is an LGA 11 shown in FIGS.

  The package substrate 9 of the LGA 11 is formed by forming a copper wiring 9b on a base material 9a made of glass-filled epoxy resin or the like, and covering the copper wiring 9b with a solder resist 9c which is an insulating film. On the back surface 9e, which is the surface opposite to the surface to be formed, flat external leads 9d are arranged in an array as shown in FIG.

  In the LGA 11, since the back surface 9e of the package substrate 9 and the exposed surface of the external lead 9d are substantially the same height as shown in FIG. 12, the cutting burr 1i (FIG. 12) generated when the wiring substrate 8 is cut. 6 (c)).

  Therefore, it is very effective to form a thin portion similar to the recess 1j shown in FIG.

  The semiconductor device assembled using the wiring board 8 may be a BGA (Ball Grid Array) or the like.

  The present invention is suitable for a semiconductor device manufacturing technique.

1 Lead frame (thin plate member)
1a Lead 1b Tab (chip mounting part)
1c Chip support surface 1d Connected surface 1e Tab suspension lead 1f Bonding surface 1g Surface 1h Dicing line 1i Cutting burr (burr)
DESCRIPTION OF SYMBOLS 1j Concave part 1k Cutting part 1l Back surface 1m Through-hole 1n Mold line 2 Semiconductor chip 2a Pad 2b Main surface 2c Back surface 3 Sealing part 3a Back surface 4 Wire 5 QFN (semiconductor device)
6 Blade 7 Batch sealing part 8 Wiring board (thin plate member)
9 Package substrate 9a Base material 9b Copper wiring 9c Solder resist 9d External lead 9e Back surface 10 Solder plating layer 11 LGA (semiconductor device)
12 Die bond materials

Claims (14)

(A) A lead frame having a chip mounting portion having a semiconductor chip mounted on the surface, a suspension lead having one end connected to the chip mounting portion, and a plurality of leads arranged around the chip mounting portion is prepared. Process,
(B) electrically connecting a plurality of pads formed on the surface of the semiconductor chip and the plurality of leads by a plurality of wires, respectively;
(C) forming a sealing body covering the semiconductor chip, the wire, a part of the chip mounting portion, and a part of the lead;
(D) cutting the lead with a dicing blade,
The lead has a first portion and a second portion that is thinner and narrower than the first portion;
In the step (b), the wire is electrically connected to the first portion of the lead,
In the step (d), the second portion of the lead is cut. A method of manufacturing a semiconductor device according to claim 1,
The step (c) is performed so that the second portion of the lead is covered with the sealing body. A method of manufacturing a semiconductor device according to claim 2,
In the step (d), the sealing body and the second portion of the lead are cut at the same time. A method of manufacturing a semiconductor device according to claim 1,
The step (c) is performed so that the second portion of the lead is positioned outside the sealing body. A method of manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the second portion of the lead has a recess formed on a surface of the lead. A method of manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the second portion of the lead has a recess formed on the back surface of the lead. A method of manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the second portion of the lead has recesses formed on the front and back surfaces of the lead. A method of manufacturing a semiconductor device according to claim 5, 6 or 7,
The method of manufacturing a semiconductor device, wherein a width of the recess is wider than a width of the dicing blade. A method of manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the lead frame includes a plurality of packages formed in a matrix arrangement and is separated into packages by performing the step (d). A method of manufacturing a semiconductor device according to claim 9,
The method of manufacturing a semiconductor device, wherein the second portion of the lead is located between the packages. A method of manufacturing a semiconductor device according to claim 9,
In the step (d), the dicing blade is advanced along a dicing line between the packages. A method of manufacturing a semiconductor device according to claim 9,
The method of manufacturing a semiconductor device, wherein the second portion of the lead is in a position overlapping a dicing line in a plan view. A method for manufacturing a semiconductor device according to claim 11, comprising:
A method of manufacturing a semiconductor device, wherein a through hole is provided in a portion of the lead frame corresponding to an orthogonal portion of the dicing line. A method for manufacturing a semiconductor device according to claim 11, comprising:
A first recess is provided in the second portion of the lead, and a second recess is provided in a portion of the lead frame corresponding to an orthogonal position of the dicing line. The method of manufacturing a semiconductor device, wherein the depth is deeper than the depth of the first recess.

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