JP2010177305A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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Abstract
Description
本発明は、絶縁膜に形成された凹部を、銅または銅合金の導電部材で充填した半導体装置、及びその製造方法に関する。 The present invention relates to a semiconductor device in which a recess formed in an insulating film is filled with a conductive member of copper or copper alloy, and a method for manufacturing the same.
配線に用いられる銅は、従来の配線材料であるアルミニウムに比べて加工が困難であることから、銅パターンの形成に、ダマシン法またはデュアルダマシン法が用いられる。ダマシン法またはデュアルダマシン法では、絶縁膜に形成したビアホールや配線溝等の凹部内を充填する銅膜を形成した後、不要な銅膜を除去することにより、銅パターンが形成される。銅膜の形成には、量産性とコストとの観点から、一般的に電解めっき法が用いられる。電解めっきを行う前に、電極として用いる銅からなるシード層がスパッタリング等により形成される。 Since copper used for wiring is more difficult to process than aluminum, which is a conventional wiring material, a damascene method or a dual damascene method is used to form a copper pattern. In the damascene method or the dual damascene method, after forming a copper film filling a recess such as a via hole or a wiring groove formed in an insulating film, a copper pattern is formed by removing an unnecessary copper film. For the formation of the copper film, an electrolytic plating method is generally used from the viewpoint of mass productivity and cost. Before electrolytic plating, a seed layer made of copper used as an electrode is formed by sputtering or the like.
基板全面に形成した銅膜をリフローさせることによって、凹部を銅部材で充填する方法が知られている(特許文献1)。平坦面上から凹部内に銅をリフローさせるために、凹部の内面と銅との濡れ性を、平坦面と銅との濡れ性よりも高くする処理が行われる。例えば、凹部の内面のバリアメタル膜の表面粗さが、平坦面上のバリアメタル膜の表面粗さよりも大きくされる。または、凹部の内面にのみ、銅との濡れ性の高い材料からなる導電膜が形成される。 A method is known in which a recess is filled with a copper member by reflowing a copper film formed on the entire surface of the substrate (Patent Document 1). In order to reflow copper into the recess from the flat surface, a process of making the wettability between the inner surface of the recess and copper higher than the wettability between the flat surface and copper is performed. For example, the surface roughness of the barrier metal film on the inner surface of the recess is made larger than the surface roughness of the barrier metal film on the flat surface. Alternatively, a conductive film made of a material having high wettability with copper is formed only on the inner surface of the recess.
また、配線をAl系材料で形成する場合に、下地となるTiN/Ti系バリアメタル膜の表面粗さを増加させる方法が知られている(特許文献2)。 Also, a method for increasing the surface roughness of a TiN / Ti-based barrier metal film serving as a base when a wiring is formed of an Al-based material is known (Patent Document 2).
半導体集積回路の高集積化及び微細化に伴い、ビアホールの微細化及びアスペクト比の増加が進んでいる。ビアホールの微細化及び高アスペクト比化が進むと、銅からなるシード層でビアホールの内面を連続的に覆うことが困難になる。例えば、ビアホールの内面に付着した銅が平坦な膜にならず、離散的に分布する複数の島状部分が形成される。島状部分が離散的に分布すると、電解めっき用の電極として機能しなくなる。 With the high integration and miniaturization of semiconductor integrated circuits, the miniaturization of via holes and the increase in aspect ratio are progressing. As the via hole is miniaturized and the aspect ratio is increased, it becomes difficult to continuously cover the inner surface of the via hole with a seed layer made of copper. For example, the copper adhering to the inner surface of the via hole does not become a flat film, and a plurality of island-like portions distributed discretely are formed. If the island-shaped portions are distributed discretely, they will not function as an electrode for electrolytic plating.
上述の課題を解決する半導体装置は、
半導体基板の上に形成された絶縁膜と、
前記絶縁膜に形成された凹部と、
前記凹部の内面を覆う第1の導電膜と、
前記第1の導電膜の表面に離散的に分布し、銅に対して、前記第1の導電膜の濡れ性よりも高い濡れ性を有する導電材料からなる島状組織と、
前記凹部を充填する銅または銅合金からなる導電部材と
を有する。
A semiconductor device that solves the above problems is as follows.
An insulating film formed on the semiconductor substrate;
A recess formed in the insulating film;
A first conductive film covering an inner surface of the recess;
An island-like structure made of a conductive material that is discretely distributed on the surface of the first conductive film and has a wettability higher than that of the first conductive film with respect to copper;
And a conductive member made of copper or a copper alloy filling the recess.
上述の課題を解決する半導体装置の製造方法は、
半導体基板の上に形成された絶縁膜に凹部を形成する工程と、
前記凹部の内面を第1の導電膜で覆う工程と、
前記導電膜の表面に離散的に分布し、銅に対して、前記第1の導電膜の濡れ性よりも高い濡れ性を有する導電材料からなる島状組織を形成する工程と、
前記凹部を、銅または銅合金からなる導電部材で埋め込む工程と
を有する。
A method of manufacturing a semiconductor device that solves the above-described problems is as follows.
Forming a recess in an insulating film formed on a semiconductor substrate;
Covering the inner surface of the recess with a first conductive film;
A step of forming an island structure made of a conductive material that is discretely distributed on the surface of the conductive film and has a wettability higher than that of the first conductive film with respect to copper;
Filling the recess with a conductive member made of copper or a copper alloy.
上述の課題を解決する半導体装置の他の製造方法は、
半導体基板の上に形成された絶縁膜に凹部を形成する工程と、
前記凹部の内面を第1の導電膜で覆う工程と、
前記導電膜の表面を、銅に対する前記第1の導電膜の濡れ性よりも、銅に対する濡れ性が高い導電材料からなる第2の導電膜で覆う工程と、
前記第2の導電膜の表面を荒らす工程と、
前記第2の導電膜の表面を荒らした後、前記凹部を、銅または銅合金からなる導電部材で埋め込む工程と
を有する。
Another method for manufacturing a semiconductor device that solves the above problems is as follows.
Forming a recess in an insulating film formed on a semiconductor substrate;
Covering the inner surface of the recess with a first conductive film;
Covering the surface of the conductive film with a second conductive film made of a conductive material having higher wettability with respect to copper than the wettability of the first conductive film with respect to copper;
Roughening the surface of the second conductive film;
And after the surface of the second conductive film is roughened, the recess is filled with a conductive member made of copper or a copper alloy.
銅または銅合金を堆積させる下地表面の濡れ性が高まり、凹部内を、銅または銅合金で安定して埋め込むことが可能になる。 The wettability of the base surface on which copper or copper alloy is deposited is increased, and the recess can be stably filled with copper or copper alloy.
図面を参照しながら、実施例1及び実施例2について説明する。 Example 1 and Example 2 will be described with reference to the drawings.
図1A〜図1Iを参照して、実施例1による半導体装置の製造方法について説明する。 With reference to FIGS. 1A to 1I, a method of manufacturing a semiconductor device according to the first embodiment will be described.
図1Aに示すように、シリコン等の半導体基板10の表層部に、シャロートレンチアイソレーション(STI)等により、素子分離絶縁膜11を形成する。素子分離絶縁膜11で囲まれた活性領域が画定される。活性領域内に、MOSFET12を形成する。 As shown in FIG. 1A, an element isolation insulating film 11 is formed on the surface layer portion of a semiconductor substrate 10 such as silicon by shallow trench isolation (STI) or the like. An active region surrounded by the element isolation insulating film 11 is defined. A MOSFET 12 is formed in the active region.
MOSFET12を覆うように、半導体基板10の上に、酸化シリコン等からなる層間絶縁膜15を形成する。層間絶縁膜15に複数のビアホールを形成し、このビアホール内をタングステン(W)等で充填することにより、導電プラグ16を形成する。ビアホールの直径は、例えば50nm程度である。導電プラグ16は、それぞれMOSFET12のソース、ドレイン等に接続される。 An interlayer insulating film 15 made of silicon oxide or the like is formed on the semiconductor substrate 10 so as to cover the MOSFET 12. By forming a plurality of via holes in the interlayer insulating film 15 and filling the via holes with tungsten (W) or the like, the conductive plugs 16 are formed. The diameter of the via hole is, for example, about 50 nm. The conductive plugs 16 are connected to the source and drain of the MOSFET 12, respectively.
図1Bに示すように、層間絶縁膜15の上に、2層目の層間絶縁膜20を形成する。層間絶縁膜20には、例えばポーラスシリカ等の所謂Low−k材料が用いられる。層間絶縁膜20は、例えば塗布法により形成される。 As shown in FIG. 1B, a second interlayer insulating film 20 is formed on the interlayer insulating film 15. For the interlayer insulating film 20, a so-called Low-k material such as porous silica is used. The interlayer insulating film 20 is formed by, for example, a coating method.
図1Cに示すように、層間絶縁膜20に複数の凹部21を形成する。凹部21の底面に、導電プラグ16の上端が露出する。以下の図1D〜図1Hには、1つの凹部21を拡大した断面図を示す。 As shown in FIG. 1C, a plurality of recesses 21 are formed in the interlayer insulating film 20. The upper end of the conductive plug 16 is exposed on the bottom surface of the recess 21. In the following FIGS. 1D to 1H, enlarged sectional views of one recess 21 are shown.
図1Dに示すように、層間絶縁膜20の上面、及び凹部21の内面を覆うように、第1の導電膜22を形成する。第1の導電膜22は、凹部21内に充填される銅の拡散を防止するバリアメタル膜として機能する。第1の導電膜22には、例えばTaが用いられる。Ta膜の形成には、例えばDCスパッタリング、化学気相成長(CVD)、原子層堆積(ALD)等を用いることができる。 As shown in FIG. 1D, a first conductive film 22 is formed so as to cover the upper surface of the interlayer insulating film 20 and the inner surface of the recess 21. The first conductive film 22 functions as a barrier metal film that prevents diffusion of copper filling the recess 21. For example, Ta is used for the first conductive film 22. For forming the Ta film, for example, DC sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like can be used.
DCスパッタリングでTa膜を形成する場合の成膜条件は、例えば下記の通りである。
・DC電力 25kW
・スパッタリングガス Ar
・圧力 0.1Pa
・成膜厚さ 5nm
CVDでTa膜を形成する場合の成膜条件は、例えば下記の通りである。
・原料 ペンタキスジメチルアミノタンタリウム(PDMAT)
・原料容器温度 80℃
・キャリアガス H2
・流量 200sccm
・基板温度 150℃〜350℃(典型的には270℃)
・圧力 100Pa
・成膜厚さ 2nm〜10nm(典型的には5nm)
ALDでTa膜を形成する場合には、原料ガスを含むキャリアガスを、流量100sccmで1秒間供給する工程と、キャリアガスのみを、流量100sccmで1秒間供給する工程とを、交互に10周期分繰り返す。成膜条件は、例えば下記の通りである。
・原料 ペンタキスジメチルアミノタンタリウム(PDMAT)
・原料容器温度 80℃
・キャリアガス H2
・基板温度 100℃〜300℃(典型的には240℃)
・圧力 100Pa
・成膜厚さ 3nm
なお、Ta原料として、PDMATに代えて、Cp2TaH3、Ta(OC2H5)5、Ta(i−OC3H7)5、Ta(OCH3)5、タンタルハロゲン化物(TaCl5、TaF5、TaBr5、TaI5)、Ta[NC(CH3)2C2H5][N(CH3)2]3等を用いることも可能である。
The film formation conditions when the Ta film is formed by DC sputtering are, for example, as follows.
・ DC power 25kW
・ Sputtering gas Ar
・ Pressure 0.1Pa
・ Film thickness 5nm
The film formation conditions when the Ta film is formed by CVD are, for example, as follows.
・ Raw material Pentakisdimethylamino tantalum (PDMAT)
・ Raw material temperature 80 ℃
・ Carrier gas H 2
・ Flow rate 200sccm
-Substrate temperature 150 ° C to 350 ° C (typically 270 ° C)
・ Pressure 100Pa
・ Film thickness 2nm-10nm (typically 5nm)
In the case of forming a Ta film by ALD, a step of supplying a carrier gas containing a source gas at a flow rate of 100 sccm for 1 second and a step of supplying only a carrier gas at a flow rate of 100 sccm for 1 second are alternately performed for 10 cycles. repeat. The film forming conditions are, for example, as follows.
・ Raw material Pentakisdimethylamino tantalum (PDMAT)
・ Raw material temperature 80 ℃
・ Carrier gas H 2
-Substrate temperature 100 ° C to 300 ° C (typically 240 ° C)
・ Pressure 100Pa
・ Film thickness 3nm
As Ta raw materials, instead of PDMAT, Cp 2 TaH 3 , Ta (OC 2 H 5 ) 5 , Ta (i-OC 3 H 7 ) 5 , Ta (OCH 3 ) 5 , tantalum halide (TaCl 5 , TaF 5 , TaBr 5 , TaI 5 ), Ta [NC (CH 3 ) 2 C 2 H 5 ] [N (CH 3 ) 2 ] 3, or the like can also be used.
なお、第1の導電膜22に、Ta以外に、バリアメタルとしての機能を持つ他の材料を用いてもよい。例えばTa、W、Mo、Ti、またはZrを含む金属、合金、窒化物等を用いることができる。 In addition to Ta, another material having a function as a barrier metal may be used for the first conductive film 22. For example, a metal, alloy, nitride, or the like containing Ta, W, Mo, Ti, or Zr can be used.
図1Eに示すように、第1の導電膜22の表面上に離散的に分布する導電材料からなる島状組織25を形成する。島状組織25には、銅に対して、第1の導電膜22の濡れ性よりも高い濡れ性を有する導電材料が用いられる。濡れ性は、平坦面上に付着した溶融した銅の接触角を測定することにより評価することができる。具体的には、島状組織25の導電材料が露出した平坦面上に、溶融した銅を付着させたときの接触角が、第1の導電膜22の材料が露出した平坦面上に、溶融した銅を付着させたときの接触角よりも小さい。 As shown in FIG. 1E, an island-like structure 25 made of a conductive material that is discretely distributed is formed on the surface of the first conductive film 22. For the island-like structure 25, a conductive material having wettability higher than that of the first conductive film 22 is used for copper. Wettability can be evaluated by measuring the contact angle of molten copper deposited on a flat surface. Specifically, the contact angle when the molten copper is deposited on the flat surface where the conductive material of the island-like structure 25 is exposed is melted on the flat surface where the material of the first conductive film 22 is exposed. Smaller than the contact angle when copper is deposited.
島状組織25には、例えばCoが用いられる。Co膜は、例えばCVD、交互供給法等により形成することができる。 For the island structure 25, for example, Co is used. The Co film can be formed by, for example, CVD or an alternate supply method.
Coの島状組織をCVDで形成する場合の成長条件は、例えば下記の通りである。
・原料 ジコバルトヘキサカルボニルt−ブチルアセチレン(CCTBA)
・原料容器温度 60℃
・キャリアガス H2
・基板温度 220℃
・圧力 100Pa
この条件でCoを成長させると、第1の導電膜22の表面において核生成が生じ、その後、核が成長する。核の成長に伴って、核同士が繋がり膜が形成される。島状組織25を形成する際には、核同士が繋がる前に成長を停止させる。すなわち、インキュベーションタイム中に、成長を停止させる。
The growth conditions for forming the Co island structure by CVD are, for example, as follows.
・ Raw material Dicobalt Hexacarbonyl t-butylacetylene (CCTBA)
・ Raw material container temperature 60 ℃
・ Carrier gas H 2
・ Board temperature 220 ℃
・ Pressure 100Pa
When Co is grown under these conditions, nucleation occurs on the surface of the first conductive film 22, and then nuclei grow. As the nuclei grow, the nuclei are connected to form a film. When the island-like structure 25 is formed, the growth is stopped before the nuclei are connected. That is, the growth is stopped during the incubation time.
上述の条件で、第1の導電膜22の表面の被覆率が約50%の島状組織25が形成される。島状組織25を構成する粒子の各々は、ほぼ半球状であり、その高さは2nm以下である。 Under the above-described conditions, an island-like structure 25 having a coverage of about 50% on the surface of the first conductive film 22 is formed. Each of the particles constituting the island-like structure 25 is substantially hemispherical, and its height is 2 nm or less.
Coの島状組織を交互供給法で形成する場合には、原料ガスの供給、原料ガスのパージ、アンモニア(NH3)ガスの供給、アンモニアガスのパージをこの順番に12周期分繰り返す。原料ガスの供給時には、ガス流量を250sccmとし、供給時間を0.5秒とする。アンモニアガスの供給時には、ガス流量を200sccmとし、供給時間を1秒とする。パージガスの供給時には、流量を200sccmとし、供給時間を1秒とする。成長条件は、例えば下記の通りである。
・原料 ジコバルトヘキサカルボニルt−ブチルアセチレン(CCTBA)
・原料容器温度 60℃
・キャリアガス Ar
・パージガス H2
・基板温度 220℃
・圧力 100Pa
上述の条件で、第1の導電膜22の表面の被覆率が約50%の島状組織25が形成される。交互供給法を採用すると、CVDを採用した場合に比べて、島状組織25を構成する各粒子を微細化させることができる。なお、アンモニアガスに代えて、他の還元性ガスを用いてもよい。
When forming an island structure of Co by the alternate supply method, the supply of the source gas, the purge of the source gas, the supply of ammonia (NH 3 ) gas, and the purge of ammonia gas are repeated in this order for 12 cycles. When supplying the source gas, the gas flow rate is set to 250 sccm, and the supply time is set to 0.5 seconds. When supplying ammonia gas, the gas flow rate is set to 200 sccm, and the supply time is set to 1 second. When supplying the purge gas, the flow rate is 200 sccm, and the supply time is 1 second. The growth conditions are, for example, as follows.
・ Raw material Dicobalt Hexacarbonyl t-butylacetylene (CCTBA)
・ Raw material container temperature 60 ℃
・ Carrier gas Ar
・ Purge gas H 2
・ Board temperature 220 ℃
・ Pressure 100Pa
Under the above-described conditions, an island-like structure 25 having a coverage of about 50% on the surface of the first conductive film 22 is formed. When the alternate supply method is employed, each particle constituting the island-like structure 25 can be made finer than when CVD is employed. Instead of ammonia gas, other reducing gas may be used.
図1Fに示すように、島状組織25が形成された基板上に、銅からなるシード層30を、例えばスパッタリングにより形成する。シード層30は、平坦面上における厚さが20〜50nmになるように成膜する。このとき、凹部21の内面において、シード層30の厚さは2〜3nmになる。島状組織25を形成することなく、Taからなる第1の導電膜22の上に、直接、シード層30を形成すると、凹部21の内面では、連続した膜にならず、銅の粒子が離散的に分布する構造が得られる。本実施例では、銅に対する濡れ性の高い島状組織25を形成しているため、凹部21の内面におけるシード層30の厚さが2〜3nmであっても、連続した膜になる。 As shown in FIG. 1F, a seed layer 30 made of copper is formed, for example, by sputtering on the substrate on which the island-like structure 25 is formed. The seed layer 30 is formed so that the thickness on the flat surface is 20 to 50 nm. At this time, the thickness of the seed layer 30 is 2 to 3 nm on the inner surface of the recess 21. If the seed layer 30 is formed directly on the first conductive film 22 made of Ta without forming the island-like structure 25, the inner surface of the recess 21 does not form a continuous film, and the copper particles are discrete. Resulting in a distributed structure. In this embodiment, since the island-like structure 25 having high wettability with respect to copper is formed, even if the thickness of the seed layer 30 on the inner surface of the recess 21 is 2 to 3 nm, a continuous film is obtained.
図1Gに示すように、シード層30を電極として用いて、その上に銅または銅合金を電解めっきすることにより、配線膜31を形成する。凹部21内が、配線膜31で充填される。層間絶縁膜22の上面よりも上方に堆積している第1の導電膜22、島状組織25、シード層30、及び配線膜31を、化学機械研磨(CMP)により除去する。 As shown in FIG. 1G, a wiring film 31 is formed by electrolytically plating copper or a copper alloy on the seed layer 30 as an electrode. The recess 21 is filled with the wiring film 31. The first conductive film 22, the island-like structure 25, the seed layer 30, and the wiring film 31 deposited above the upper surface of the interlayer insulating film 22 are removed by chemical mechanical polishing (CMP).
図1Hに示すように、凹部21内に、銅または銅合金からなる配線31aが残る。また、凹部21の内面は、第1の導電膜22で覆われたままであり、第1の導電膜22の表面に、島状組織25が分布している。島状組織25は、シード層30で覆われている。シード層30と配線31aとは、共に銅または銅合金で形成されているため、両者を明確に区別することは困難である。従って、シード層30と配線31aとを含む銅部材と、バリアメタル膜として機能する第1の導電膜22との界面に、島状組織25が配置された構造が得られ。 As shown in FIG. 1H, the wiring 31 a made of copper or a copper alloy remains in the recess 21. Further, the inner surface of the recess 21 is still covered with the first conductive film 22, and the island-like structure 25 is distributed on the surface of the first conductive film 22. The island-like structure 25 is covered with the seed layer 30. Since both the seed layer 30 and the wiring 31a are formed of copper or a copper alloy, it is difficult to clearly distinguish them from each other. Therefore, a structure in which the island-like structure 25 is arranged at the interface between the copper member including the seed layer 30 and the wiring 31a and the first conductive film 22 functioning as a barrier metal film is obtained.
図1Iに示すように、配線31aは、例えば、それぞれ導電プラグ16を介して、MOSFET12のソース及びドレインに接続される。 As shown in FIG. 1I, the wiring 31a is connected to the source and drain of the MOSFET 12 via, for example, the conductive plug 16, respectively.
次に、図2A、図2B、及び図3A〜図3Eを参照して、島状組織25の効果、及び好ましい被覆率について説明する。 Next, with reference to FIG. 2A, FIG. 2B, and FIGS. 3A-3E, the effect of the island-like structure 25 and a preferable coverage will be described.
図2Aに、島状組織25を構成する1つの島状部分25Aの概略斜視図を示す。島状部分25Aの各々の形状は、ほぼ半球状である。半球状の島状部分25Aの底面の面積をSとすると、島状部分25Aの球状曲面の面積はその2倍の2Sになる。すなわち、島状組織25の露出した表面の面積は、島状組織25が被覆してる下地表面の面積の約2倍になると考えることができる。 FIG. 2A shows a schematic perspective view of one island-like portion 25 </ b> A constituting the island-like tissue 25. Each shape of the island-like portion 25A is substantially hemispherical. Assuming that the area of the bottom surface of the hemispherical island-shaped portion 25A is S, the area of the spherical curved surface of the island-shaped portion 25A is twice that of 2S. That is, it can be considered that the area of the exposed surface of the island-like structure 25 is approximately twice the area of the base surface covered with the island-like structure 25.
図2Bに、島状組織25の被覆率と、露出した下地表面及び島状組織25の表面の面積との関係を示す。島状組織25の被覆率が0%である場合、すなわち島状組織25が形成されていない場合に、下地の第1の導電膜22の露出した表面の面積を正規化して100とする。島状組織25の被覆率が50%である場合には、第1の導電膜22の露出した表面の面積は50になる。島状組織25で被覆されている領域の面積も50であり、島状組織25の露出した表面の面積は、その2倍の100になる。同様に、島状組織25の被覆率が75%のとき、第1の導電膜22の露出した表面の面積は25になり、島状組織25の露出した表面の面積は150になる。 FIG. 2B shows the relationship between the coverage of the island-like structure 25 and the area of the exposed base surface and the surface of the island-like structure 25. When the coverage of the island-like structure 25 is 0%, that is, when the island-like structure 25 is not formed, the area of the exposed surface of the underlying first conductive film 22 is normalized to 100. When the coverage of the island-like structure 25 is 50%, the exposed surface area of the first conductive film 22 is 50. The area of the region covered with the island structure 25 is also 50, and the area of the exposed surface of the island structure 25 is 100, which is twice that area. Similarly, when the coverage of the island-like structure 25 is 75%, the exposed surface area of the first conductive film 22 is 25, and the exposed surface area of the island-like structure 25 is 150.
島状組織25の被覆率が100%である状態は、第1の導電膜22の全面が連続膜で覆われている状態を意味する。この場合、連続膜の表面の面積は、下地表面の面積と等しくなる。すなわち、島状組織25の露出した表面の面積は100である。 A state where the coverage of the island-like structure 25 is 100% means a state where the entire surface of the first conductive film 22 is covered with a continuous film. In this case, the surface area of the continuous film is equal to the area of the underlying surface. That is, the area of the exposed surface of the island-like structure 25 is 100.
図3Aに、基板50の表面に液滴51が付着している状態を示す。液滴51の接触角をθとする。液滴51の縁上の一点である作用点Pに働く界面張力のうち、基板50と液滴51との界面に沿う張力をγLSとし、液滴51と気体との界面に沿う張力をγVLとし、基板50と気体との界面に沿う張力をγVSとする。 FIG. 3A shows a state where the droplet 51 is attached to the surface of the substrate 50. Let the contact angle of the droplet 51 be θ. Of the interfacial tension acting on the point of action P, which is one point on the edge of the droplet 51, the tension along the interface between the substrate 50 and the droplet 51 is γ LS, and the tension along the interface between the droplet 51 and the gas is γ LS. The tension along the interface between the substrate 50 and the gas is γ VS.
基板50の表面の凹凸度をrとし、作用点Pが液滴51の外方に向かってdxだけ変位したときのエネルギ変化をdEとし、このときの接触角をθとすると、以下の式が成り立つ。ここで、凹凸度rは、表面が完全な平面であると仮定したときの表面積に対する実際の表面積の割合である。 Assuming that the unevenness of the surface of the substrate 50 is r, the energy change when the action point P is displaced by dx toward the outside of the droplet 51 is dE, and the contact angle at this time is θ, the following equation is obtained. It holds. Here, the degree of unevenness r is the ratio of the actual surface area to the surface area when the surface is assumed to be a perfect plane.
平衡状態では、dE/dx=0であるから、下記の式が得られる。 Since dE / dx = 0 in the equilibrium state, the following equation is obtained.
基板50の表面が平坦であるときの接触角をθFとする。基板50の表面が平坦である場合には、r=1であるから、以下の式が成り立つ。 Let θ F be the contact angle when the surface of the substrate 50 is flat. When the surface of the substrate 50 is flat, since r = 1, the following equation is established.
式2と式3とからγLS、γVS、γVLが消去されて、以下の式が得られる。 Γ LS , γ VS , and γ VL are eliminated from Equation 2 and Equation 3, and the following equation is obtained.
基板50の表面が平坦ではない場合、凹凸度rは1より大きい。従って、以下の式が成り立つ。 When the surface of the substrate 50 is not flat, the unevenness r is greater than 1. Therefore, the following equation holds.
cosθFが正のとき、すなわち平坦面上の接触角θFが0°<θF<90°のとき、θ<θFとなり、cosθFが負のとき、すなわち90°<θF<180°のとき、θ>θFとなる。 When cos θ F is positive, that is, when the contact angle θ F on the flat surface is 0 ° <θ F <90 °, θ <θ F and when cos θ F is negative, that is, 90 ° <θ F <180 °. In this case, θ> θ F.
図3Bに示すように、平坦面上における接触角θFが0°<θF<90°のとき、図3Cに示すように、表面に凹凸が付されている場合の接触角θは、θFよりも小さくなる。これは、濡れ性が高まることを意味する。逆に、図3Dに示すように、平坦面上における接触角θFが90°<θF<180°のとき、図3Eに示すように、表面に凹凸が付されている場合の接触角θは、θFよりも大きくなる。これは、濡れ性が低下することを意味する。 As shown in FIG. 3B, when the contact angle θ F on the flat surface is 0 ° <θ F <90 °, the contact angle θ when the surface is uneven as shown in FIG. Smaller than F. This means that wettability is increased. On the contrary, as shown in FIG. 3D, when the contact angle θ F on the flat surface is 90 ° <θ F <180 °, the contact angle θ when the surface is uneven as shown in FIG. 3E. It is larger than θ F. This means that wettability is reduced.
Coの表面に対する銅の接触角は90°未満である。このため、Co膜の表面を粗くすと、表面が平坦な場合に比べて濡れ性が高まる。 The contact angle of copper with the Co surface is less than 90 °. For this reason, when the surface of the Co film is roughened, the wettability is improved as compared with the case where the surface is flat.
図2Bに戻って説明を続ける。島状組織25の被覆率が75%の場合と、100%の場合とを比較すると、被覆率が75%の方が、島状組織25の表面の面積が大きいことが分かる。このため、被覆率が75%である場合に、シード層30の下地表面の、銅に対する濡れ性は、平坦なCo膜の表面の、銅に対する濡れ性よりも高いと考えられる。 Returning to FIG. 2B, the description will be continued. Comparing the case where the coverage of the island-like structure 25 is 75% and the case where it is 100%, it can be seen that the surface area of the island-like structure 25 is larger when the coverage is 75%. For this reason, when the coverage is 75%, the wettability of the base layer of the seed layer 30 with respect to copper is considered to be higher than the wettability of copper with the surface of the flat Co film.
また、島状組織25の被覆率が50%の場合と、100%の場合とを比較すると、島状組織25の表面の面積は等しい。また、被覆率50%の場合には、第1の導電膜22の表面が露出した領域も存在する。このため、島状組織25の被覆率が50%の場合に、シード層30の下地表面の、銅に対する濡れ性は、平坦なCo表面の、銅に対する濡れ性と等しいか、それよりも高いと考えられる。 Further, when the coverage of the island-like structure 25 is 50% and when it is 100%, the surface area of the island-like structure 25 is equal. When the coverage is 50%, there is a region where the surface of the first conductive film 22 is exposed. For this reason, when the coverage of the island-like structure 25 is 50%, the wettability of the seed layer 30 with respect to the copper is equal to or higher than the wettability of the flat Co surface with respect to copper. Conceivable.
上述の考察から、島状組織25の被覆率を50%以上にすることが好ましいことがわかる。島状組織25は、第1の導電膜22の、銅に対する濡れ性よりも高い濡れ性を有する材料で形成されている。このため、島状組織25の被覆率が50%未満であっても、平坦な第1の導電膜22の上にシード層30を直接成長させる場合に比べると、島状組織25を配置することによって、シード層30の下地表面の、銅に対する濡れ性が高められていることは明白である。 From the above consideration, it can be seen that the coverage of the island-like structure 25 is preferably 50% or more. The island-like structure 25 is formed of a material having a wettability higher than that of the first conductive film 22 with respect to copper. For this reason, even if the coverage of the island-like structure 25 is less than 50%, the island-like structure 25 is arranged as compared with the case where the seed layer 30 is directly grown on the flat first conductive film 22. Thus, it is apparent that the wettability of the base surface of the seed layer 30 with respect to copper is enhanced.
島状組織25を構成する各々の島状部分の寸法が、第1の導電膜22の上にシード層30を直接形成する際に生成される銅の島状部分の寸法程度、またはそれよりも大きい場合には、島状組織25を配置することの十分な効果が得られない。一般的に、Ta等のバリアメタル膜上に銅を成長させたときに形成される銅の島状部分の寸法は、5nm〜8nm程度である。従って、島状組織25を構成する各々の粒子の高さを2nm以下、より好ましくは1nm以下とすることが好ましい。 The size of each island-shaped portion constituting the island-like structure 25 is about the size of the copper island-shaped portion generated when the seed layer 30 is directly formed on the first conductive film 22, or more than that. If it is large, a sufficient effect of arranging the island-like structures 25 cannot be obtained. In general, the size of a copper island-shaped portion formed when copper is grown on a barrier metal film such as Ta is about 5 nm to 8 nm. Therefore, the height of each particle constituting the island-like structure 25 is preferably 2 nm or less, more preferably 1 nm or less.
次に、図4A〜図4Cを参照して、Ta、Ti、及びCoに対する銅の密着性について評価を行った結果について説明する。 Next, with reference to FIG. 4A to FIG. 4C, the results of evaluating the adhesion of copper to Ta, Ti, and Co will be described.
Ta、Ti、及びCo膜の上に、銅膜を化学気相成長(CVD)により形成した3種類の評価用試料を作製した。ダイヤモンドのケガキ針で、試料表面に正方格子状のケガキを入れ、粘着テープで銅膜を剥離させる実験を行った。 Three types of evaluation samples were prepared by forming a copper film on the Ta, Ti, and Co films by chemical vapor deposition (CVD). An experiment was conducted in which a square lattice-shaped marking was placed on the surface of the sample with a diamond marking needle and the copper film was peeled off with an adhesive tape.
図4A〜図4Cは、それぞれTa膜上、Ti膜上、及びCo膜上に銅膜を形成した試料の銅膜剥離処理後の写真を示す。Ta膜上に銅膜を形成した場合には、図4Aに示すように、ケガキを入れた領域のみならず、それに隣接する領域の銅膜も剥離した。Ti膜上に銅膜を形成した場合には、図4Bに示すように、ケガキを入れた領域の銅膜は剥離したが、それに隣接する領域の銅膜に剥離は生じていない。Co膜上に銅膜を形成した場合には、図4Cに示すように、ケガキを入れた領域の銅膜も剥離していない。 4A to 4C show photographs after a copper film peeling process of samples in which a copper film is formed on a Ta film, a Ti film, and a Co film, respectively. When the copper film was formed on the Ta film, as shown in FIG. 4A, not only the region where the marking was made, but also the copper film in the adjacent region was peeled off. When a copper film is formed on the Ti film, as shown in FIG. 4B, the copper film in the region where the marking is made peels off, but the copper film in the region adjacent thereto does not peel off. When the copper film is formed on the Co film, as shown in FIG. 4C, the copper film in the region where the marking is made is not peeled off.
この評価結果から、銅膜の密着性は、下地表面がCo、Ti、Taの順に高いことがわかる。密着性が高いということは、濡れ性も高いと考えられる。この評価結果から、島状組織25の導電材料として、濡れ性の観点から、TaよりもTiが適しており、TiよりもCoが適していることがわかる。なお、島状組織25には、Co、Ti、Zr、Mn、またはRuを含む導電材料を用いてもよい。 From this evaluation result, it can be seen that the adhesion of the copper film is higher in the order of Co, Ti, and Ta in the base surface. High adhesion is considered high wettability. From this evaluation result, it is understood that Ti is more suitable than Ta and Co is more suitable than Ti from the viewpoint of wettability as the conductive material of the island-like structure 25. Note that the island-like structure 25 may be made of a conductive material containing Co, Ti, Zr, Mn, or Ru.
バリアメタル膜として機能する第1の導電膜22と島状組織25とに同一の材料を用いると、島状組織25の成長時に核生成が生じることなく、成長当初から全面を覆う膜が形成されてしまう。島状部分が離散的に分布する島状組織25を形成するためには、島状組織25に、第1の導電膜22とは異なる材料を用いる必要がある。例えば、第1の導電膜22に金属Tiを用いた場合、島状組織25に金属Tiを用いることはできない。ただし、第1の導電膜22にTiの窒化物(TiN)を用いた場合、島状組織25に金属Tiを用いることは可能である。 When the same material is used for the first conductive film 22 and the island-like structure 25 that function as a barrier metal film, nucleation does not occur during the growth of the island-like structure 25, and a film that covers the entire surface from the beginning of growth is formed. End up. In order to form the island-like structure 25 in which the island-like portions are discretely distributed, it is necessary to use a material different from that of the first conductive film 22 for the island-like structure 25. For example, when metal Ti is used for the first conductive film 22, metal Ti cannot be used for the island structure 25. However, when Ti nitride (TiN) is used for the first conductive film 22, it is possible to use metal Ti for the island structure 25.
また、シード層30を連続膜にするために、島状組織25の材料として、銅に対して、第1の導電膜22の濡れ性よりも高い濡れ性を有するものを選択することが好ましい。一例として、第1の導電膜22にTaを用いた場合には、島状組織25に、TiやCoを用いることが好ましい。また、第1の導電膜22にTiを用いた場合には、島状組織25にCoを用いることが好ましい。 Further, in order to make the seed layer 30 a continuous film, it is preferable to select a material having a wettability higher than that of the first conductive film 22 with respect to copper as a material of the island-like structure 25. As an example, when Ta is used for the first conductive film 22, it is preferable to use Ti or Co for the island-like structure 25. Further, when Ti is used for the first conductive film 22, it is preferable to use Co for the island-like structure 25.
上記実施例1において、図1Dに示した第1の導電膜22を形成した後、図1Eに示した島状組織25を形成する前に、Arプラズマを用いた逆スパッタを行って、第1の導電膜22の表面を粗面化してもよい。さらに、図1Eに示した島状組織25を形成した後、図1Fに示したシード層30を形成する前に、Arプラズマを用いた逆スパッタを行い、表面をさらに粗面化してもよい。表面の粗面化により、銅に対する濡れ性をより高めることができ、かつコンタクト抵抗を低減させることができる。島状組織25の形成にCVD法を用いた場合には、島状組織25の脱酸素、脱炭素処理を兼ねて、水素に代表される還元性プラズマを用いて表面の粗面化を行ってもよい。 In the first embodiment, after the first conductive film 22 shown in FIG. 1D is formed and before the island-like structure 25 shown in FIG. 1E is formed, reverse sputtering using Ar plasma is performed to obtain the first The surface of the conductive film 22 may be roughened. Further, after forming the island-like structure 25 shown in FIG. 1E and before forming the seed layer 30 shown in FIG. 1F, reverse sputtering using Ar plasma may be performed to further roughen the surface. By roughening the surface, the wettability to copper can be further increased, and the contact resistance can be reduced. When the CVD method is used to form the island-like structure 25, the surface of the island-like structure 25 is roughened by using a reducing plasma typified by hydrogen in combination with the deoxygenation and decarbonization treatment of the island-like structure 25. Also good.
上記実施例1では、図1Fに示した工程で、スパッタリングによりシード層30を形成し、図1Gに示した工程で、電解めっきにより配線膜31を形成した。電解めっきを行う代わりに、スパッタリングのみによって凹部21内を銅で埋め込んでもよい。また、CVDのみによって凹部21内を銅で埋め込んでもよい。この場合には、島状組織25を配置することにより、銅による埋込特性を向上させることができる。 In Example 1, the seed layer 30 was formed by sputtering in the step shown in FIG. 1F, and the wiring film 31 was formed by electrolytic plating in the step shown in FIG. 1G. Instead of performing electroplating, the recess 21 may be filled with copper only by sputtering. Further, the recess 21 may be filled with copper only by CVD. In this case, by placing the island-like structure 25, the embedding characteristics with copper can be improved.
実施例1では、配線用の凹部21内を銅または銅合金で埋め込んだが、銅または銅合金を埋め込む他の工程でも、島状組織25を利用することが可能である。例えば、シングルダマシン法において、層間コンタクト用のビアホール内を埋め込む工程や、デュアルダマシン法において、ビアホールと配線溝とを同時に埋め込む工程に、島状組織25を利用することができる。 In the first embodiment, the concave portion 21 for wiring is filled with copper or a copper alloy, but the island-like structure 25 can be used in other processes for filling copper or a copper alloy. For example, in the single damascene method, the island-like structure 25 can be used for the step of filling the via hole for the interlayer contact or the step of simultaneously filling the via hole and the wiring groove in the dual damascene method.
次に、図5A〜図5Fを参照して、実施例2による半導体装置の製造方法について説明する。 Next, with reference to FIGS. 5A to 5F, a method for manufacturing a semiconductor device according to Example 2 will be described.
図5Aに示す第1の導電膜22を形成するまでの工程は、図1Dに示した第1の導電膜22を形成するまでの実施例1の工程と共通である。第1の導電膜22の表面を、第2の導電膜40で覆う。第2の導電膜40には、銅に対して、第1の導電膜22の濡れ性よりも高い濡れ性を有する導電材料が用いられる。一例として、第1の導電膜22にTiやTaを用いた場合、第2の導電膜40にはCoが用いられる。第2の導電膜40は、例えば、スパッタリング、CVD等で形成される。 The process until the first conductive film 22 shown in FIG. 5A is formed is the same as the process of Example 1 until the first conductive film 22 shown in FIG. 1D is formed. The surface of the first conductive film 22 is covered with the second conductive film 40. For the second conductive film 40, a conductive material having a wettability higher than that of the first conductive film 22 is used for copper. As an example, when Ti or Ta is used for the first conductive film 22, Co is used for the second conductive film 40. The second conductive film 40 is formed by sputtering, CVD, or the like, for example.
図5Bに示すように、第2の導電膜40を、Arプラズマで逆スパッタする。図5Cに示すように、逆スパッタにより、第2の導電膜40の表面が粗くなる。逆スパッタの条件は、例えば下記の通りである。
・圧力 0.1Pa
・RF電力 1kW
・ウエハバイアス 500W
第2の導電膜40の成膜直後の表面の二乗平均平方根粗さは約0.7nmであったが、Arによる逆スパッタ後の表面の二乗平均平方根粗さは約1.3nmであった。このように、逆スパッタにより第2の導電膜40の表面が粗くなっていることが確認された。第2の導電膜40の成膜にCVD法を用いた場合には、第2の導電膜40の脱酸素、脱炭素処理を兼ねて、水素に代表される還元性プラズマを用いて表面の粗面化を行ってもよい。
As shown in FIG. 5B, the second conductive film 40 is reverse sputtered with Ar plasma. As shown in FIG. 5C, the surface of the second conductive film 40 becomes rough by reverse sputtering. The reverse sputtering conditions are, for example, as follows.
・ Pressure 0.1Pa
・ RF power 1kW
・ Wafer bias 500W
The root mean square roughness of the surface immediately after deposition of the second conductive film 40 was about 0.7 nm, but the root mean square roughness of the surface after reverse sputtering with Ar was about 1.3 nm. As described above, it was confirmed that the surface of the second conductive film 40 was roughened by reverse sputtering. When the CVD method is used to form the second conductive film 40, the surface of the second conductive film 40 is roughened by using a reducing plasma typified by hydrogen, which also serves as a deoxidation and decarbonization process for the second conductive film 40. Surfaceization may be performed.
図5Dに示すように、表面が粗くなった第2の導電膜40の上に、銅からなるシード層30を形成する。シード層30の形成は、図1Fに示した実施例1のシード層30の形成方法と同一である。 As shown in FIG. 5D, a seed layer 30 made of copper is formed on the second conductive film 40 having a rough surface. The formation of the seed layer 30 is the same as the formation method of the seed layer 30 of Example 1 shown in FIG. 1F.
図5Eに示すように、シード層30を電極として銅または銅合金を電解めっきすることにより、配線膜31を形成する。その後、層間絶縁膜22の上面よりも上方に堆積している第1の導電膜22、第2の導電膜40、シード層30、及び配線膜31を、CMPにより除去する。 As shown in FIG. 5E, the wiring film 31 is formed by electroplating copper or a copper alloy using the seed layer 30 as an electrode. Thereafter, the first conductive film 22, the second conductive film 40, the seed layer 30, and the wiring film 31 deposited above the upper surface of the interlayer insulating film 22 are removed by CMP.
図4Fに示すように、凹部21内に、銅または銅合金からなる配線31aが残る。 As shown in FIG. 4F, the wiring 31 a made of copper or copper alloy remains in the recess 21.
第2の導電膜40の材料の平坦な表面上の銅の接触角が90°未満である場合には、図3B〜図3Cを参照して説明したように、表面を粗面化することによって濡れ性を高めることができる。このため、シード層30が薄い場合でも、シード層30が島状に分断されることなく、膜状に形成することが可能である。第2の導電膜40の、銅に対する濡れ性が、第1の導電膜22の、銅に対する濡れ性よりも高い。このため、第1の導電膜22の表面を粗面化してその上にシード層30を直接形成する場合に比べて、シード層30の下地表面の、銅に対する濡れ性をより高めることができる。 When the contact angle of copper on the flat surface of the material of the second conductive film 40 is less than 90 °, the surface is roughened as described with reference to FIGS. 3B to 3C. The wettability can be increased. For this reason, even when the seed layer 30 is thin, the seed layer 30 can be formed in a film shape without being divided into island shapes. The wettability of the second conductive film 40 to copper is higher than the wettability of the first conductive film 22 to copper. For this reason, compared with the case where the surface of the 1st electrically conductive film 22 is roughened and the seed layer 30 is directly formed on it, the wettability with respect to the copper of the base surface of the seed layer 30 can be improved more.
第2の導電膜40の表面を粗くする処理は、配線用の凹部21内を銅または銅合金で埋め込む工程以外に、銅を埋め込む他の工程にも適用することが可能である。例えば、シングルダマシン法において、ビアホール内を埋め込む工程や、デュアルダマシン法において、ビアホールと配線溝とを同時に埋め込む工程に、第2の導電膜40の表面を粗くする処理を適用することができる。 The treatment for roughening the surface of the second conductive film 40 can be applied to other processes for embedding copper in addition to the process of embedding the recesses 21 for wiring with copper or a copper alloy. For example, a process of roughening the surface of the second conductive film 40 can be applied to a process of filling a via hole in a single damascene method or a process of filling a via hole and a wiring trench simultaneously in a dual damascene method.
以上実施例に沿って本発明を説明したが、本発明はこれらに制限されるものではない。例えば、種々の変更、改良、組み合わせ等が可能なことは当業者に自明であろう。 Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
10 半導体基板
11 素子分離絶縁膜
12 MOSFET
15 層間絶縁膜
16 導電プラグ
20 層間絶縁膜
21 凹部
22 第1の導電膜
25 島状組織
30 シード層
31 配線膜
31a 配線
40 第2の導電膜
50 基板
51 液滴
DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Element isolation insulating film 12 MOSFET
15 Interlayer insulating film 16 Conductive plug 20 Interlayer insulating film 21 Recess 22 First conductive film 25 Island-like structure 30 Seed layer 31 Wiring film 31a Wiring 40 Second conductive film 50 Substrate 51 Droplet
Claims (5)
前記絶縁膜に形成された凹部と、
前記凹部の内面を覆う第1の導電膜と、
前記第1の導電膜の表面に離散的に分布し、銅に対して、前記第1の導電膜の濡れ性よりも高い濡れ性を有する導電材料からなる島状組織と、
前記凹部を充填する銅または銅合金からなる導電部材と
を有する半導体装置。 An insulating film formed on the semiconductor substrate;
A recess formed in the insulating film;
A first conductive film covering an inner surface of the recess;
An island-like structure made of a conductive material that is discretely distributed on the surface of the first conductive film and has a wettability higher than that of the first conductive film with respect to copper;
A semiconductor device having a conductive member made of copper or a copper alloy filling the recess.
前記島状組織が、Co、Ti、Zr、Mn、Ruからなる群より選択された少なくとも1つの金属元素を含む請求項1に記載の半導体装置。 The first conductive film includes at least one metal element selected from the group consisting of Ta, W, Mo, Ti, and Zr;
The semiconductor device according to claim 1, wherein the island-like structure includes at least one metal element selected from the group consisting of Co, Ti, Zr, Mn, and Ru.
前記凹部の内面を第1の導電膜で覆う工程と、
前記導電膜の表面に離散的に分布し、銅に対して、前記第1の導電膜の濡れ性よりも高い濡れ性を有する導電材料からなる島状組織を形成する工程と、
前記凹部を、銅または銅合金からなる導電部材で埋め込む工程と
を有する半導体装置の製造方法。 Forming a recess in an insulating film formed on a semiconductor substrate;
Covering the inner surface of the recess with a first conductive film;
A step of forming an island structure made of a conductive material that is discretely distributed on the surface of the conductive film and has a wettability higher than that of the first conductive film with respect to copper;
And a step of filling the recess with a conductive member made of copper or a copper alloy.
前記凹部の内面を第1の導電膜で覆う工程と、
前記導電膜の表面を、銅に対する前記第1の導電膜の濡れ性よりも、銅に対する濡れ性が高い導電材料からなる第2の導電膜で覆う工程と、
前記第2の導電膜の表面にArプラズマ処理または還元性プラズマ処理を施す工程と、
前記第2の導電膜の表面にArプラズマ処理または還元性プラズマ処理を施した後、前記凹部を、銅または銅合金からなる導電部材で埋め込む工程と
を有する半導体装置の製造方法。 Forming a recess in an insulating film formed on a semiconductor substrate;
Covering the inner surface of the recess with a first conductive film;
Covering the surface of the conductive film with a second conductive film made of a conductive material having higher wettability with respect to copper than the wettability of the first conductive film with respect to copper;
Performing Ar plasma treatment or reducing plasma treatment on the surface of the second conductive film;
A method of manufacturing a semiconductor device, comprising: subjecting the surface of the second conductive film to Ar plasma treatment or reducing plasma treatment, and then filling the concave portion with a conductive member made of copper or a copper alloy.
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