JP2010171163A - Semiconductor device and electronic instrument - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein when forming a TFT having a GOLD structure, as a length of a region wherein an intermediate concentration layer overlaps with a gate electrode (hereinafter, to be referred to a "GOLD length"), a leakage current between a source and a drain pinching a channel region configuring a transistor increases to cause increase of power consumption, and further a reduction in the graphic quality occurs, because of a reduction of time which can hold a graphic signal which is conspicuous, when a liquid crystal device or an organic EL device is applied. <P>SOLUTION: Concerning the GOLD length of the TFT, the length at both ends in a TFT width direction is made shorter than the length at a center part. At an end part in the width direction of an island silicon layer, more defective levels are generated for carriers exist than in the center part in the width direction. The GOLD length in the region is shortened, as compared with the center part so that carrier generation from the defective level is suppressed, and leakage current is reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and an electronic apparatus.

  In a liquid crystal device, an organic EL (electroluminescence) device, or the like, a pixel switching operation or the like is performed using an integrated circuit including a transistor as a semiconductor device. As a transistor structure, a transistor in which a channel region or the like is formed using an island-shaped amorphous silicon layer disposed on an insulator, a polycrystalline silicon layer, or a single crystal silicon layer has been put into practical use. In order to improve the hot carrier resistance of a transistor, a transistor structure including a GOLD (Gate-Overlapped LDd) structure in which a gate electrode and an LDD region (intermediate concentration layer) overlap is proposed as described in Patent Document 1. ing. An example of a method for manufacturing a GOLD structure is described in Patent Document 2. By using the GOLD structure, it is possible to disperse the electric field inside the transistor, and generation of hot carriers can be suppressed.

JP-A-9-45930 JP 2000-294787 A

  When a transistor having a GOLD structure is formed, a source-drain region sandwiching a channel region constituting the transistor as the length of a region where the intermediate concentration layer and the gate electrode overlap (hereinafter referred to as “GOLD length”) becomes longer. The leakage current increases, and the power consumption increases. In addition, there is a problem that the video quality is deteriorated due to a decrease in the time for which the video signal can be held, which becomes remarkable when applied to a liquid crystal device or an organic EL device.

  The mechanism of increase in leakage current accompanying the increase in GOLD length is considered to be due to the following mechanism. The electric field concentrates at the end in the width direction of the island-like silicon layer. In addition, there are more defect levels that generate carriers at the end in the width direction of the silicon layer than in the center in the width direction. When a GOLD structure is formed in this region, the GOLD structure is depleted, so that carriers are generated from this defect level and a leakage current is generated.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples. Here, “upper” is defined as “a direction from the insulator toward the semiconductor layer”.

  Application Example 1 A semiconductor device according to this application example includes a substrate using an insulator or a substrate covered with an insulator, an island-shaped semiconductor layer disposed on the insulator, and a surface of the semiconductor layer. A gate electrode arranged in a shape crossing the semiconductor layer in a first direction in a plan view, and a gate insulating layer sandwiched between the semiconductor layer and the gate electrode in a normal direction of the semiconductor layer And a source region and a drain region containing impurities that generate carriers of the same polarity and are disposed in the semiconductor layer with the gate electrode interposed therebetween in a plan view as viewed from the semiconductor layer surface, The channel region disposed inside the gate electrode in a plan view, and the channel region and the source region, and the channel region and the drain region in a plan view viewed in the semiconductor layer surface. An intermediate concentration layer including an impurity that generates carriers having the same polarity as that of the source region and the drain region, and having a resistivity between the channel region and the source region and the drain region. And a length in a second direction intersecting the first direction of an overlapping portion of the intermediate concentration layer and the gate electrode in a plan view as viewed from the semiconductor layer surface is at least the source region A center in the first direction of the channel region in a region where the gate electrode and the semiconductor layer overlap at least at one end along the second direction of the semiconductor layer, on one side of the side and the drain region side The length of the overlapping portion of the intermediate concentration layer and the gate electrode at the portion is shorter than the length in the second direction.

  According to this, the length of the intermediate concentration layer is reduced at least on one side of the source region side and the drain region side and at least one end length compared to the central portion, thereby suppressing the depletion layer length at the end portion. It is done. Therefore, the generation of carriers in the depletion layer is suppressed, and the leakage current due to the defect level located at the channel end can be reduced.

  Application Example 2 In the semiconductor device according to the application example described above, the length in the second direction of the overlapping portion between the intermediate concentration layer and the gate electrode is at least on the source region side and the drain region side. On one side, both ends of the semiconductor layer along the second direction are shorter than the length of the overlapping portion of the intermediate concentration layer and the gate electrode in the central portion in the second direction. .

  According to the application example described above, the depletion layer length at the end portion can be suppressed by shortening the length of the intermediate concentration layer at least one side of the source region side and the drain region side as compared with the central portion. Therefore, the generation of carriers in the depletion layer is suppressed, and the leakage current due to the defect level located at the channel end can be reduced.

  Application Example 3 In the semiconductor device according to the application example described above, the length in the second direction of the overlapping portion between the intermediate concentration layer and the gate electrode is on both sides of the source region side and the drain region side. And at least at one end, the length of the overlapping portion of the intermediate concentration layer and the gate electrode at the central portion is shorter than the length in the second direction.

  According to the application example described above, the length of the intermediate concentration layer is reduced at least on both sides of the source region side and the drain region side and at one end compared to the center portion, so that the depletion layer length of the end portion is reduced. Is suppressed. Therefore, the generation of carriers in the depletion layer is suppressed, and the leakage current due to the defect level located at the channel end can be reduced.

  Application Example 4 In the semiconductor device according to the application example described above, the length of the overlapping portion of the intermediate concentration layer and the gate electrode in the second direction is the center portion on both sides and both ends. The length of the overlapping portion between the intermediate concentration layer and the gate electrode is shorter than the length in the second direction.

  According to the application example described above, the length of the intermediate concentration layer is at least on both sides of the source region side and the drain region side, and the lengths of both ends are reduced compared to the central portion, so that the depletion layer length of the end portion Is suppressed. Therefore, the generation of carriers in the depletion layer is suppressed, and the leakage current due to the defect level located at the channel end can be reduced.

  Application Example 5 In the semiconductor device according to the application example described above, the intermediate concentration layer is at least one side of the central portion below the gate electrode in a plan view as viewed from the semiconductor layer surface. And it has the shape which shortened the length of the said 2nd direction at least at the said one end, It is characterized by the above-mentioned.

  According to the application example described above, the intermediate concentration layer can suppress the generation of carriers in the depletion layer at least at one end rather than the central portion, and can reduce the leakage current due to the defect level located at the channel end portion. It becomes possible.

  Application Example 6 In the semiconductor device according to the application example described above, the gate electrode is at least on one side and at least on the one end with respect to the central portion in a plan view as viewed on the semiconductor layer surface. It has the shape which shortened the length of the 2nd direction, It is characterized by the above-mentioned.

  According to the application example described above, the length of the depletion layer at the end is reduced by reducing the length of the gate electrode at least on one side of the source region side and the drain region side and at least one end compared to the center portion. Is suppressed. Therefore, the generation of carriers in the depletion layer is suppressed, and the leakage current due to the defect level located at the channel end can be reduced. In addition, at least at the end of the electrically weak channel at one end of the channel region in the width direction, the intermediate concentration layer that does not overlap with the gate electrode is longer than that at the center when viewed in the channel direction. Since the intermediate concentration layer functions as an electric field relaxation layer, at least at one end in the width direction of the channel region, the electric field strength applied to the transistor as the semiconductor device can be reduced, and at the same time the leakage current caused by impact ionization and the like is reduced, Reliability can be ensured.

  Application Example 7 In the semiconductor device according to the application example described above, the intermediate concentration layer is at least one side below the central portion under the gate electrode in a plan view as viewed from the semiconductor layer surface. And at least at the one end, it has a shape in which the length in the second direction is shortened, and the gate electrode is at least one side of the central portion in a plan view as viewed from the semiconductor layer surface, And it has the shape which shortened the length of the said 2nd direction at least at the said one end, It is characterized by the above-mentioned.

  According to the application example described above, the length of the intermediate concentration layer is at least one side of the source region side and the drain region side and the length of at least one end is shortened compared to the central portion, so that the depletion layer at the end portion is reduced. The length is suppressed. In addition, the length of the depletion layer at the end can be suppressed by reducing the length of the gate electrode at least on one side of the source region side and the drain region side and by shortening the length of at least one end as compared with the central portion. Therefore, the generation of carriers in the depletion layer is suppressed, and the leakage current due to the defect level located at the channel end can be reduced.

  In the region where the length of the gate electrode is shortened, a transistor is formed in which the length of the intermediate concentration layer that does not overlap with the gate electrode is longer than that of the central portion. Since the intermediate concentration layer functions as an electric field relaxation layer, the electric field strength applied to the transistor can be reduced, and leakage current caused by impact ionization or the like can be reduced. Since the length of the channel region is increased and the length of the electric field relaxation layer is increased, it is possible to suppress the occurrence of leakage current at least at one end in the first direction of the electrically weak channel region. It becomes.

  Application Example 8 In the semiconductor device according to the application example described above, the intermediate concentration layer has a smooth outline in a region overlapping the gate electrode in a plan view as viewed from the semiconductor layer surface. It is characterized by.

  According to the application example described above, electric field concentration in the intermediate concentration layer can be prevented. By making the shape of the intermediate concentration layer have a smooth contour shape in a plan view as seen from the semiconductor layer surface, it is possible to suppress the generation of carriers due to the electric field concentration occurring at the corners. Therefore, the occurrence of leakage current can be suppressed.

  Application Example 9 In the semiconductor device according to the application example described above, the gate electrode has a smooth outline in a region overlapping the semiconductor layer in a plan view as viewed from the semiconductor layer surface. Features.

  According to the application example described above, it is possible to prevent the concentration of the electric field directly under the gate electrode. By making the shape of the gate electrode have a smooth contour shape in a plan view as seen from the semiconductor layer surface, generation of carriers due to electric field concentration occurring at the corners can be suppressed. Therefore, the occurrence of leakage current can be suppressed.

  Application Example 10 An electronic apparatus according to this application example includes the semiconductor device described above.

  According to this, the electronic device is configured using a semiconductor device in which leakage current is suppressed. Therefore, in the organic light emitting device and the liquid crystal display device, the display image quality is improved, and when used in a memory device or a logic circuit device, power consumption can be reduced.

Hereinafter, embodiments embodying the present invention will be described with reference to the drawings.
(First Embodiment: Semiconductor Device with Changed Planar Shape of Intermediate Concentration Layer)
Hereinafter, a thin film transistor (hereinafter referred to as TFT) as a semiconductor device according to the present embodiment will be described with reference to the drawings. 1A is a plan view of a TFT, FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A, and FIG. 1C is a line BB ′ of FIG. It is sectional drawing. The TFT 100 includes a substrate 101, a channel region 102, an intermediate concentration layer 103, a gate insulating layer 104, a gate electrode 105, a source / drain region 106, and a semiconductor layer 107. The gate electrode 105 is formed so as to cross the semiconductor layer 107, and this crossing direction is defined as a first direction of the present invention. Note that in FIG. 1A, the description of the gate insulating layer 104 is omitted in order to improve visibility. The lengths of L1 and L2 in the second direction crossing the first direction indicate the GOLD length. A region where the intermediate concentration layer 103 and the gate electrode 105 overlap in a plan view of the substrate 101 is referred to as a GOLD region. Here, in the region where the gate electrode 105 and the semiconductor layer 107 overlap in the plan view of the substrate 101, the length of the gate electrode 105 in the second direction is about 10 μm, and the width of the gate electrode 105 (length in the first direction). Has a value of about 10 μm. The GOLD length L1 is about 0.5 μm, and L2 is about 2 μm. The width (the length in the first direction) taking the GOLD length L1 is about 1 μm. Here, the value of the GOLD length L1 and the range of the width that takes the GOLD length L1 are determined by factors such as the length and width of the gate electrode 105 of the TFT 100, hot carrier resistance, leakage current standards, and the like. Note that the numbers shown are examples. For example, in order to further suppress the leakage current, it is effective to shorten the GOLD length L1. On the other hand, in order to increase the hot carrier resistance, it is effective to increase the GOLD length L1.

  The substrate 101 supports the semiconductor layer 107, and includes a source / drain region 106, an intermediate concentration layer 103, and a channel region 102. As a material forming the semiconductor layer 107, amorphous silicon, single crystal silicon, polycrystalline silicon, or the like can be used. In this embodiment, polycrystalline silicon having a layer thickness of about 50 nm is used.

The channel region 102 controls the current flowing through the source / drain region 106. The gate insulating layer 104 controls an electric field generated in the gate insulating layer 104 by a potential applied to the gate electrode 105 and controls the conductivity of the channel region 102. In this embodiment, no impurity is introduced into the channel region 102 (non-doped). It is preferable to use a silicon oxide layer for the gate insulating layer 104. When the breakdown voltage of the TFT 100 is set to about 15 V, it is preferable to form the gate insulating layer 104 with a thickness of about 100 nm. The source / drain region 106 has a function of guiding current from the external electrode (not shown) into the TFT 100. Impurities are introduced into the source / drain regions 106 at a concentration of about 3 × 10 ²⁰ cm ⁻³ . The intermediate concentration layer 103 is located between the source / drain region 106 and the channel region 102 in a plan view of the substrate 101, and is applied to the source / drain region 106 between the source / drain region 106 and the channel region 102. It has a function of relaxing the electric field strength caused by the generated potential. Impurities are introduced into the intermediate concentration layer 103 at a concentration of about 2 × 10 ¹⁸ cm ⁻³ .

  In the present embodiment, the GOLD length L1 at both ends in the width direction (first direction) of the TFT 100 is shorter than the GOLD length L2 at the center. Therefore, at both ends in the width direction of the TFT 100, generation of leakage current due to generation of carriers due to defect levels, which is caused by depletion of the GOLD region, can be suppressed. The defect level is mainly formed by dangling bonds at both ends in the width direction of the TFT 100. Therefore, the leakage current of the TFT 100 can be reduced by making the GOLD length L1 at both ends in the width direction of the TFT 100 shorter than the GOLD length L2 at the center.

(Modification: First Embodiment)
Hereinafter, a modification according to the first embodiment will be described. FIGS. 2A and 2B are plan views of TFTs for explaining this modification. In the first embodiment, the intermediate concentration layer 103 is formed on both sides of the source / drain region 106 and on both sides in the width direction of the TFT 100, but this is formed by cutting out at least one corner. Even if the shape is used, the leakage current can be reduced. FIG. 2A is a plan view of the TFT 100A when only one corner is cut out. Similarly, even if a plurality of corners are selected, the leakage current can be similarly reduced.

  Further, as shown in FIG. 2B, a curvature is given to the planar shape of the intermediate concentration layer 103 in the TFT 100B, and in the region where the intermediate concentration layer 103 and the gate electrode 105 overlap, the intermediate concentration layer 103 has a smooth outline. You may form so that it may have. In this case, planar electric field concentration at the notched portion can be avoided, and the leakage current can be further reduced.

  Moreover, you may form so that at least one part of the notched part may have a smooth outline. Even in this case, it is possible to avoid planar electric field concentration at the notched portion, and it is possible to reduce the leakage current.

  Further, the source / drain region 106 may coincide with or overlap with the gate electrode 105, and in this case also, the leakage current can be reduced. In this case, since the GOLD length is the length of the region where the intermediate concentration layer 103 and the gate electrode 105 overlap, the distance from the end portion of the source / drain region 106 instead of the end portion of the gate electrode 105 is used. become.

Second Embodiment: Semiconductor Device with Changed Planar Shape of Gate Electrode
Hereinafter, the TFT as the semiconductor device according to the present embodiment will be described with reference to the drawings. Since this embodiment has many parts in common with the first embodiment, description of the common parts is omitted to avoid duplication. 3A is a plan view of the TFT, FIG. 3B is a cross-sectional view taken along line AA ′ of FIG. 3A, and FIG. 3C is a line BB ′ of FIG. 3A. It is sectional drawing. The TFT 100 </ b> C includes a substrate 101, a channel region 102, an intermediate concentration layer 103, a gate insulating layer 104, a gate electrode 105, a source / drain region 106, and a semiconductor layer 107. In the present embodiment, the GOLD length L1 at both ends in the width direction of the TFT 100C is made shorter than the GOLD length L2 at the center by changing the gate electrode 105 instead of changing the shape of the intermediate concentration layer 103. Yes. The gate length of the TFT 100C is 10 μm at the center in the width direction, and the gate width is 10 μm. And the width | variety which takes GOLD length L1 is about 1 micrometer.

  Here, the value of the GOLD length L1 and the range of the width that takes the GOLD length L1 are determined by factors such as the length and width of the gate electrode 105 of the TFT 100C, hot carrier resistance, leakage current standards, and the like. Note that the numbers shown are examples. For example, in order to further suppress the leakage current, it is effective to shorten the GOLD length L1. On the other hand, in order to increase the hot carrier resistance, it is effective to increase the GOLD length L1.

  In the present embodiment, since the intermediate concentration layer 103 functions as an electric field relaxation layer of the TFT 100C, it is possible to reduce the electric field strength applied to the TFT 100C, and to reduce leakage current caused by impact ionization and the like. Since the length of the electric field relaxation layer is increased, it is possible to suppress the occurrence of leakage current accompanying the generation of carriers due to impact ionization.

(Modification: Second Embodiment)
Hereinafter, modified examples according to the second embodiment will be described. 4A and 4B are plan views of TFTs for explaining the present modification. In the second embodiment, the gate electrode 105 is formed on both sides of the source / drain region 106 and on both sides in the width direction of the TFT 100C, but this is a shape with at least one corner cut out. It is possible to reduce the leakage current even if is used. FIG. 4A is a plan view of the TFT 100D when only one corner is cut out. Similarly, even if a plurality of corners are selected, the leakage current can be similarly reduced.

  Further, as shown in FIG. 4B, a curvature is given to the planar shape of the gate electrode 105 in the TFT 100E, and the gate electrode 105 has a smooth contour line in a region where the intermediate concentration layer 103 and the gate electrode 105 overlap. You may form in. In this case, planar electric field concentration at the notched portion can be avoided, and the leakage current can be further reduced.

  Moreover, you may form so that at least one part of the notched part may have a smooth outline. Even in this case, it is possible to avoid planar electric field concentration at the notched portion, and it is possible to reduce the leakage current.

  Further, the source / drain region 106 may coincide with or overlap with the gate electrode 105, and in this case also, the leakage current can be reduced. In this case, since the GOLD length is the length of the region where the intermediate concentration layer 103 and the gate electrode 105 overlap, the distance from the end portion of the source / drain region 106 instead of the end portion of the gate electrode 105 is used. become.

(Third embodiment: a semiconductor device in which the planar shape of the intermediate concentration layer and the planar shape of the gate electrode are changed)
Hereinafter, the TFT as the semiconductor device according to the present embodiment will be described with reference to the drawings. Since this embodiment has many parts in common with the first embodiment, description of the common parts is omitted to avoid duplication. 5A is a plan view of the TFT, FIG. 5B is a cross-sectional view taken along line AA ′ of FIG. 5A, and FIG. 5C is a line BB ′ of FIG. 5A. It is sectional drawing. The TFT 100F includes a substrate 101, a channel region 102, an intermediate concentration layer 103, a gate insulating layer 104, a gate electrode 105, a source / drain region 106, and a semiconductor layer 107. In the present embodiment, by changing the shapes of both the intermediate concentration layer 103 and the gate electrode 105, the GOLD length L1 at both ends in the width direction of the TFT 100F is made shorter than the GOLD length L2 at the center. The gate length of the TFT 100F is 10 μm at the center in the width direction, and the gate width is 10 μm. And the width | variety which takes GOLD length L1 is about 1 micrometer.

  Here, the value of the GOLD length L1 and the range of the width that takes the GOLD length L1 are determined by factors such as the length and width of the gate electrode 105 of the TFT 100F, hot carrier resistance, leakage current standards, and the like. Note that the numbers shown are examples. For example, in order to further suppress the leakage current, it is effective to shorten the GOLD length L1. On the other hand, in order to increase the hot carrier resistance, it is effective to increase the GOLD length L1.

  In the present embodiment, since the intermediate concentration layer 103 functions as an electric field relaxation layer of the TFT 100F, the electric field strength applied to the TFT 100F can be reduced, and leakage current caused by impact ionization or the like can be reduced. Since the length of the electric field relaxation layer is increased, it is possible to suppress the generation of leakage current accompanying the generation of carriers due to impact ionization.

(Modification: Third Embodiment)
Hereinafter, a modification according to the third embodiment will be described. FIGS. 6A, 6B, and 7 are plan views of TFTs for explaining the present modification. In the third embodiment, the intermediate concentration layer 103 and the gate electrode 105 are formed in a shape in which both sides of the source / drain region 106 and both sides in the width direction of the TFT 100F are cut out. It is possible to reduce the leakage current even if a shape with at least one corner cut out is used. FIG. 6A is a plan view of the TFT 100 </ b> G when the intermediate concentration layer 103 and the gate electrode 105 are cut out only at one corner. As for the position where the intermediate concentration layer 103 and the gate electrode 105 are cut, different corners may be cut as shown in FIG. 6A, or the same corner as the TFT 100H shown in FIG. You may cut it out. Further, like the TFT 100H shown in FIG. 6B, the notch width between the intermediate concentration layer 103 and the gate electrode 105 may be changed to form a width that takes the GOLD length L1 ′. Similarly, even if a plurality of corners are selected, the leakage current can be similarly reduced.

  Further, as shown in FIG. 7, a curvature is given to the planar shape of the gate electrode 105 in the TFT 100 </ b> J, and in the region where the intermediate concentration layer 103 and the gate electrode 105 overlap, the intermediate concentration layer 103 and the gate electrode 105 have a smooth contour line. You may form so that it may have. In this case, planar electric field concentration at the notched portion can be avoided, and the leakage current can be further reduced.

  Moreover, you may form so that at least one part of the notched part may have a smooth outline. Even in this case, it is possible to avoid planar electric field concentration at the notched portion, and it is possible to reduce the leakage current.

  Further, the source / drain region 106 may coincide with or overlap with the gate electrode 105, and in this case also, the leakage current can be reduced. In this case, since the GOLD length is the length of the region where the intermediate concentration layer 103 and the gate electrode 105 overlap, the distance from the end portion of the source / drain region 106 instead of the end portion of the gate electrode 105 is used. become.

(Fourth Embodiment: Electronic Device)
Hereinafter, electronic devices using TFTs as the semiconductor device described above will be described with reference to the drawings. 8A to 8C are schematic views illustrating specific examples of electronic devices including the TFT 100, the TFTs 100A to 100H, and 100J (see FIGS. 1 to 7). The TFT 100 and the TFTs 100A to 100H and 100J are collectively referred to as the TFT 30.

  FIG. 8A is a schematic diagram of a mobile personal computer including the TFT 30. The personal computer 2000 includes a liquid crystal panel 300 including a TFT 30 and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002.

  FIG. 8B is a schematic diagram of a mobile phone including the organic EL panel 400 including the TFT 30. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and an organic EL panel 400 as a display unit. By operating the scroll button 3002, the screen displayed on the organic EL panel 400 is scrolled.

  FIG. 8C is a schematic diagram of a personal digital assistant (PDA) to which the organic EL panel 400 including the TFT 30 is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and an organic EL panel 400 as a display unit. When the power switch 4002 is operated, various kinds of information such as an address book and a schedule book are displayed on the organic EL panel 400.

  The TFT 30 can also be used for a liquid crystal panel, a data processing circuit, or the like as a mounting example other than the organic EL panel 400. Further, the present invention is not limited to an optical application and can be used as a logic circuit or an arithmetic circuit.

1A is a plan view of a TFT according to the first embodiment, FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line BB in FIG. 'Line sectional view. (A), (b) is a top view of TFT which shows the modification concerning 1st Embodiment. FIG. 3A is a plan view of a TFT according to the second embodiment, FIG. 3B is a cross-sectional view taken along the line AA ′ in FIG. 3A, and FIG. 'Line sectional view. (A), (b) is a top view of TFT which shows the modification concerning 2nd Embodiment. FIG. 5A is a plan view of a TFT according to the third embodiment, FIG. 5B is a cross-sectional view taken along the line AA ′ in FIG. 5A, and FIG. 5C is a cross-sectional view taken along line BB in FIG. 'Line sectional view. (A), (b) is a top view of TFT which shows the modification concerning 3rd Embodiment. Sectional drawing for demonstrating another modification in 3rd Embodiment. Schematic which shows the specific example of the electronic device containing TFT.

  30 ... TFT, 100 ... TFT, 100A ... TFT, 100B ... TFT, 100C ... TFT, 100D ... TFT, 100E ... TFT, 100F ... TFT, 100G ... TFT, 100J ... TFT, 101 ... substrate, 102 ... channel region, 103 ... Intermediate concentration layer, 104 ... Gate insulating layer, 105 ... Gate electrode, 106 ... Source / drain region, 107 ... Semiconductor layer, 300 ... Liquid crystal panel, 400 ... Organic EL panel, 2000 ... Personal computer, 2001 ... Power switch, 2002 DESCRIPTION OF SYMBOLS ... Keyboard, 2010 ... Main part, 3000 ... Mobile phone, 3001 ... Operation button, 3002 ... Scroll button, 4000 ... Information portable terminal, 4001 ... Operation button, 4002 ... Power switch.

Claims (10)

A substrate using an insulator or a substrate covered with an insulator;
An island-shaped semiconductor layer disposed on the insulator;
A gate electrode disposed in a shape crossing the semiconductor layer in a first direction in a plan view as viewed from the semiconductor layer surface;
A gate insulating layer sandwiched between the semiconductor layer and the gate electrode in a normal direction of the semiconductor layer;
A source region and a drain region including impurities that generate carriers of the same polarity, disposed in the semiconductor layer, with the gate electrode interposed therebetween in a plan view as viewed from the semiconductor layer surface;
A channel region disposed inside the gate electrode in a plan view as viewed from the semiconductor layer surface;
The channel region, the source region, and the drain region that are disposed between the channel region and the source region and between the channel region and the drain region in a plan view as viewed from the semiconductor layer surface. An intermediate concentration layer containing impurities that generate carriers having the same polarity as the source region and the drain region, and a resistivity between
The length in the second direction intersecting the first direction of the overlapping portion of the intermediate concentration layer and the gate electrode in a plan view as viewed from the semiconductor layer surface is at least the source region side and the drain region. The intermediate portion at the center in the first direction of the channel region in a region where the gate electrode and the semiconductor layer overlap at least at one end along the second direction of the semiconductor layer A semiconductor device, wherein an overlapping portion between a concentration layer and the gate electrode is shorter than a length in the second direction.   2. The semiconductor device according to claim 1, wherein a length of the overlapping portion of the intermediate concentration layer and the gate electrode in the second direction is at least one side of the source region side and the drain region side. A semiconductor device, wherein both ends of the semiconductor layer along the second direction are shorter than the length in the second direction of the overlapping portion of the intermediate concentration layer and the gate electrode at the central portion.   2. The semiconductor device according to claim 1, wherein a length in the second direction of an overlapping portion between the intermediate concentration layer and the gate electrode is at least on both sides of the source region side and the drain region side, and at least The semiconductor device according to claim 1, wherein, at the one end, a length in the second direction of an overlapping portion of the intermediate concentration layer and the gate electrode at the central portion is shorter.   4. The semiconductor device according to claim 1, wherein a length of the overlapping portion of the intermediate concentration layer and the gate electrode in the second direction is on both sides and on both ends. 5. A semiconductor device, wherein a length of the overlapping portion of the intermediate concentration layer and the gate electrode in the central portion is shorter than the length in the second direction.   5. The semiconductor device according to claim 1, wherein the intermediate concentration layer is at least above the central portion under the gate electrode in a plan view as viewed from the semiconductor layer surface. A semiconductor device having a shape in which the length in the second direction is shortened on one side and at least at one end.   5. The semiconductor device according to claim 1, wherein the gate electrode is at least one side and at least one end of the gate electrode in a plan view as viewed from the semiconductor layer surface. A semiconductor device having a shape in which the length in the second direction is shortened.   7. The semiconductor device according to claim 5, wherein the intermediate concentration layer is at least on one side and at least on the one side with respect to the central portion under the gate electrode in a plan view as viewed from the surface of the semiconductor layer. The one end has a shape in which the length in the second direction is shortened, and the gate electrode is at least one side and at least one side than the central portion in a plan view as viewed from the semiconductor layer surface. A semiconductor device having a shape in which the length in the second direction is shortened at the one end.   8. The semiconductor device according to claim 5, wherein the intermediate concentration layer has a smooth outline in a region overlapping with the gate electrode in a plan view as viewed from the semiconductor layer surface. 9. A semiconductor device characterized by that.   8. The semiconductor device according to claim 6, wherein the gate electrode has a smooth contour line in a region overlapping the semiconductor layer in a plan view as viewed from the semiconductor layer surface. Semiconductor device.   An electronic apparatus comprising the semiconductor device according to claim 1.

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