JP2010170363A - Semiconductor integrated circuit for regulator - Google Patents

Abstract

In a regulator IC having a control terminal for on / off control of a circuit from outside, it is possible to prevent a rush current from flowing toward an output terminal immediately after startup by a control signal.
A control circuit including a voltage control element (Q1) connected between a voltage input terminal and an output terminal, an error amplifier (11) for controlling the voltage control element according to a feedback voltage, and an error In a regulator IC comprising a constant voltage circuit (12, Dz) for generating a reference voltage input to an amplifier, and an external control terminal (CE) to which a control signal for instructing on / off of the control circuit is input, Connected between the external control terminal and the input terminal of the error amplifier, receives the voltage of the external control terminal and the constant voltage of the constant voltage circuit, and changes the output voltage of the error amplifier to a voltage input to the error amplifier. A rush current prevention circuit that controls the rush current to suppress the rush current is provided.
[Selection] Figure 1

Description

  The present invention relates to a technique for reducing a rush current in a DC power supply apparatus and further a voltage regulator for converting a DC voltage, for example, a technique effective for use in a semiconductor integrated circuit (regulator IC) constituting a series regulator.

  There is a series regulator (hereinafter abbreviated as a regulator) as a power supply device that outputs a DC voltage of a desired potential by controlling a transistor provided between a DC voltage input terminal and an output terminal. A capacitor having a relatively large capacitance value is connected to the output terminal of the regulator IC that constitutes such a regulator in order to keep the output voltage constant regardless of the load variation.

  For this reason, it is known that a relatively large current (a so-called rush current) flows when the regulator is started to charge the capacitor in a discharged state at once. As an invention for reducing the rush current at the start-up of the regulator, there are inventions described in Patent Document 1 and Patent Document 2, for example.

JP 2005-045647 A JP 2007-179345 A

  The regulator is connected to the gate terminal of the voltage control transistor as shown in FIG. 4 in order to limit the output current not to exceed a predetermined value even when an accident such as a short circuit occurs on the load side. An overcurrent protection circuit such as a limiter circuit 13 is often provided. However, the limiter circuit is a function that works effectively in a steady state, and the limiter does not function effectively in a state immediately after startup. As a result of detailed investigations by the present inventors, the magnitude of the rush current varies depending on the capacitance value on the output side and the current limit value of the overcurrent protection circuit. It has been found that there is a problem that rush current may flow.

  In the regulator IC as shown in FIG. 4 having a chip enable terminal CE for controlling on / off of the chip from the outside, the regulator is started by raising the CE terminal. A simulation was performed on the assumption that the rush current could be reduced by connecting an external time constant circuit to the circuit and slowing the rise of the CE signal supplied from the CPU or the like. As a result, as shown in FIG. 5, it became clear that although the rush current can be suppressed to some extent, the rush current cannot be completely suppressed only by the time constant circuit.

  The present invention has been made paying attention to the problems as described above, and the object thereof is to constitute a DC power supply device such as a series regulator having a control terminal for externally turning on / off the circuit. An object of the present invention is to prevent a rush current from flowing toward an output terminal immediately after startup by a control signal in a semiconductor integrated circuit.

  To achieve the above object, the present invention controls a voltage control element connected between a voltage input terminal to which a DC voltage is input and an output terminal, and the voltage control element in accordance with an output feedback voltage. A control circuit including an error amplifier, a constant voltage circuit for generating a reference voltage input to the error amplifier, and an external control terminal to which a control signal for instructing on / off of the control circuit is input from the outside. The regulator semiconductor integrated circuit is connected between the external control terminal and the input terminal of the error amplifier, receives the voltage of the external control terminal and the constant voltage generated by the constant voltage circuit, and supplies the error amplifier to the error amplifier. A rush current prevention circuit for controlling the rush current by controlling the input voltage so that the change in the output voltage of the error amplifier becomes gradual is provided.

  According to the regulator semiconductor integrated circuit having the above-described configuration, it is avoided that the voltage control element is rapidly brought into a low resistance state at the time of start-up by the control signal, thereby causing a rush current to flow toward the output terminal. Can be prevented.

  Preferably, the rush current prevention circuit includes a time constant circuit that moderates a voltage change of the external control terminal, and a constant voltage that is controlled by an output of the time constant circuit and is generated by the constant voltage circuit. And voltage transmission means for transmitting to the input terminal of the amplifier. As a result, the rush current prevention circuit can be configured with a relatively simple circuit having a small number of elements.

  Here, the voltage transmission means may be a field effect transistor, and the output of the time constant circuit may be applied to the gate terminal of the transistor. The time constant circuit includes a first transistor and a resistance element connected in series between a power supply voltage terminal and a ground potential terminal, and a control terminal of the first transistor is connected to the external control terminal. It may be configured as follows.

  Preferably, the first transistor and the resistance element are made of a depletion type field effect transistor, the gate terminal of the first transistor is connected to the external control terminal, the drain terminal is connected to the power supply voltage terminal, The gate terminal of the field effect transistor as the resistance element is configured to be connected to the ground potential terminal. Thereby, the regulator excellent in the rush current suppression characteristic is realizable.

  In addition, a time constant circuit composed of a discrete resistance element and a capacitance element is connected to the outside of the external control terminal, and the control signal is input to the external control terminal via the time constant circuit. To do. Thereby, the rush current suppression characteristic can be further improved.

  As described above, according to the present invention, in a semiconductor integrated circuit constituting a DC power supply device such as a series regulator having a control terminal for externally turning on and off the circuit, an output terminal immediately after startup by a control signal There is an effect that the rush current can be prevented from flowing toward.

It is a circuit block diagram which shows one Embodiment of the series regulator IC to which this invention is applied. It is a timing chart which shows the change of the voltage of each part of the regulator of FIG. It is a circuit block diagram which shows the modification of the regulator of FIG. It is a circuit block diagram which shows an example of the conventional series regulator IC. 5 is a timing chart showing changes in voltages at various parts of the regulator in FIG. 4.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of a series regulator to which the present invention is applied. In the figure, a portion surrounded by a one-dot chain line is formed as a semiconductor integrated circuit (IC) 10 on a semiconductor chip such as single crystal silicon.

  In the regulator IC 10 of the present embodiment, a voltage control transistor Q1 composed of a P-channel MOSFET (field effect transistor) is connected between a voltage input terminal IN to which a DC voltage VDD is applied and an output terminal OUT. Between the output terminal OUT and the ground terminal GND to which the ground potential is applied, bleeder resistors R1 and R2 for dividing the output voltage are connected in series. The voltage divided by the bleeder resistors R1 and R2 is fed back to the non-inverting input terminal of the error amplifier 11 that controls the gate terminal of the voltage control transistor Q1. The error amplifier 11 controls the voltage control transistor Q1 according to the potential difference between the feedback voltage and the reference voltage Vref so as to control the output voltage to a desired potential.

  Further, the regulator IC 10 of this embodiment includes a Zener diode Dz for generating a reference voltage Vref, a bias circuit 12 for supplying a bias current to the Zener diode Dz and the error amplifier 11, and a gate of the voltage control transistor Q1. A limiter circuit 13 is provided which is connected to the terminal and limits the output current. The limiter circuit 13 causes the gate voltage to exceed a certain level when the output current increases due to a short circuit of the load, the output voltage decreases, and the error amplifier 11 attempts to decrease the gate voltage so that more current flows through the transistor Q1. The output current is limited by clamping so that it does not fall.

  Furthermore, the regulator IC 10 of the present embodiment includes a chip enable terminal CE to which a control signal EN for externally turning on and off the chip is input, and the error amplifier according to the control signal EN input to the terminal. A rush current prevention circuit 14 is provided for preventing the rush current by delaying the rise of the reference voltage Vref applied to the inverting input terminal 11.

  The bias circuit 12 is configured to be turned on / off by a signal input to the chip enable terminal CE. Also connected to the chip enable terminal CE is a time constant circuit composed of a resistor R0 and a capacitor C0 made of external discrete components in order to moderate the rise of the control signal EN supplied from a CPU (not shown). Has been.

  The rush current prevention circuit 14 includes a depletion type MOSFETs Q2 and Q3 connected in series between the voltage input terminal IN and the ground terminal GND, a gate terminal connected to a connection node N1 between Q2 and Q3, and a drain terminal. And an N-channel MOSFET Q4 connected to the cathode terminal of the Zener diode Dz. The source voltage of the MOSFET Q4 is applied to the inverting input terminal of the error amplifier 11 as a reference voltage Vref. Transistors other than Q2 and Q3 (Q1 and Q4 and transistors constituting the internal circuit) are enhancement type MOSFETs.

  In these MOSFETs Q2, Q3, and Q4, a ground potential is applied to the substrate (back gate), and the threshold voltage changes due to the substrate effect so that the on-resistance does not change due to the displacement of the source potential. is there. Q2 has its gate terminal connected to the chip enable terminal CE, Q3 has its gate terminal connected to the ground terminal GND, and is always turned on, and the power supply voltage VDD is divided by the ratio of the on-resistance of Q2 and Q3. This potential appears at node N1.

  The MOSFET Q2 of the rush current prevention circuit 14 is a depletion type, and since the power supply voltage VDD is applied to its drain terminal, if the source terminal is at the ground potential, it is turned on even when the ground potential is applied to the gate terminal. However, when Q2 is turned on, the potential of the node N1 rises and the gate terminal becomes a relatively negative potential, so that it is quickly turned off. Therefore, in a standby state in which a low level signal is input to the chip enable terminal CE, the MOSFET Q2 is turned off and Q3 is turned on, and the node N1 is at a potential close to the ground potential and Q4 is turned off.

  When the control signal EN input to the chip enable terminal CE changes from the low level to the high level (VDD), the potential of the CE terminal becomes gentle as shown in FIG. 2A by the action of the time constant times (R0, C0). The reverse voltage (zener voltage) of the Zener diode Dz rises when a current flows from the bias circuit 12 with a slight delay after rising (see FIG. 2B), and Q2 changes to the ON state and the potential of the node N1 Rises. Since the potential of the node N1 at this time is a value obtained by dividing the power supply voltage VDD by the ratio of the on-resistance of Q2 and Q3 and is lower than VDD, Q2 maintains the on state.

  Further, since the parasitic capacitance including the gate capacitance of the MOSFET Q4 is connected to the node N1, the potential of the node N1 gradually increases. When the threshold voltage of Q4 is exceeded, Q4 is turned on, and its on-resistance gradually decreases as the potential of the node N1 increases, so that the Zener voltage generated at the node N2 becomes an error via Q4. The reference voltage Vref is transmitted to the inverting input terminal of the amplifier 11, and the input potential of the amplifier rises slowly (see FIG. 2C).

  As described above, even when the input control signal EN of the chip enable terminal CE rapidly changes to high level at the time of activation, the input potential of the inverting input terminal of the error amplifier 11 rises slowly, so that the voltage control transistor Q1 The gate voltage is lowered slowly and the on-resistance is gradually reduced. As a result, the rush current that flows toward the output terminal during startup is suppressed.

  In addition, in this embodiment, since an external time constant circuit composed of RC is connected to the chip enable terminal CE, the potential change itself of the chip enable terminal CE is delayed, so that the inverting input of the error amplifier 11 is input. The rising of the reference voltage Vref applied to the terminal is further moderated, thereby preventing a rush current. As a result of simulations by the present inventors, the rush current exceeding 200 mA flows in the regulator of FIG. 4, but in the regulator of this embodiment, the rush current may be reduced to about 40 mA which is 1/5 or less. I understood.

  FIG. 3 shows a modification of the regulator of the above embodiment.

  The regulator of this modification uses an enhancement type N-channel MOSFET instead of the MOSFET Q2 in the embodiment of FIG. 1, and replaces the MOSFET Q3 with a resistor R3. Also in the regulator configured as in this modified example, similarly to the regulator of FIG. 1, the rise of the reference voltage Vref input to the error amplifier 11 at the time of start-up can be moderated and the rush current can be suppressed. is there.

  Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments. For example, in the circuit of FIG. 1, it is possible to omit the MOSFET Q4, connect the nodes N1 and N2 directly, connect a capacitor between the coupling node and the ground point, and loosen the rise of Vref. . However, in that case, an external capacitor is preferably used as a capacitive element from the viewpoint of reducing the chip size, and a dedicated external terminal for connecting the capacitor may be provided. According to the above-described embodiment, there is an advantage that the rush current can be suppressed without adding such a dedicated external terminal.

  Furthermore, in the above-described embodiment, a MOSFET is used as the voltage control transistor Q1, but a bipolar transistor may be used instead of the MOSFET. In the above embodiment, an on-chip element is used as the voltage control transistor Q1. However, since a relatively large current flows through this transistor, the transistor is configured to be connected as an external element. You may do it.

  In the above embodiment, the bleeder resistors R1 and R2 that divide the output voltage are provided inside the chip. However, an external resistor is provided and the voltage divided outside the chip is input from the external terminal to the error amplifier 11. It is also possible to configure it.

  Furthermore, in the above-described embodiment, the example applied to the regulator IC having the chip enable terminal CE has been described. However, in the regulator IC not having the chip enable terminal CE, the power supply rising detection circuit for detecting the rising of the input DC voltage VDD, and The rush current prevention circuit 14 shown in FIGS. 1 and 3 may be provided so that the rise of the reference voltage Vref input to the error amplifier 11 is moderated to suppress the rush current.

  Although the example which applied this invention to the series regulator was demonstrated in the above description, it is not limited to it to this invention, For example, it utilizes for regulators, such as a charging device which charges storage batteries, such as a lithium ion battery. be able to.

10 Regulator IC
11 Error Amplifier 12 Bias Circuit 13 Limiter Circuit 14 Rush Current Prevention Circuit Q1 Voltage Control Transistor

Claims (6)

A voltage control element connected between a voltage input terminal to which a DC voltage is input and an output terminal; a control circuit including an error amplifier that controls the voltage control element in accordance with an output feedback voltage; and the error A regulator semiconductor integrated circuit comprising a constant voltage circuit for generating a reference voltage input to an amplifier, and an external control terminal for receiving a control signal for instructing on / off of the control circuit from the outside,
Connected between the external control terminal and the input terminal of the error amplifier, receives the voltage of the external control terminal and the constant voltage generated by the constant voltage circuit, and converts the voltage input to the error amplifier to the error amplifier A regulator semiconductor integrated circuit comprising a rush current prevention circuit that suppresses a rush current by controlling so that a change in the output voltage of the capacitor is moderate.   The rush current prevention circuit includes a time constant circuit that moderates a voltage change of the external control terminal, and a constant voltage that is controlled by an output of the time constant circuit and is generated by the constant voltage circuit to an input terminal of the error amplifier. 2. The regulator semiconductor integrated circuit according to claim 1, further comprising a voltage transmission means for transmitting the regulator.   3. The regulator semiconductor integrated circuit according to claim 2, wherein the voltage transmission means is composed of a field effect transistor, and an output of the time constant circuit is applied to a gate terminal of the transistor.   The time constant circuit includes a first transistor and a resistance element connected in series between a power supply voltage terminal and a ground potential terminal, and a control terminal of the first transistor is connected to the external control terminal. The semiconductor integrated circuit for a regulator according to claim 2 or 3.   The first transistor and the resistance element are depletion type field effect transistors, the gate terminal of the first transistor is connected to the external control terminal, the drain terminal is connected to the power supply voltage terminal, and the electric field as the resistance element 5. The regulator semiconductor integrated circuit according to claim 4, wherein a gate terminal of the effect transistor is connected to the ground potential terminal.   A time constant circuit composed of a discrete resistance element and a capacitance element is connected to the outside of the external control terminal, and the control signal is input to the external control terminal via the time constant circuit. 6. The semiconductor integrated circuit for a regulator according to claim 1, wherein the regulator is a semiconductor integrated circuit.

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