JP2010153905A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which electric interference applied from the outside is reduced enough and which includes a formed capacitance element that exhibits a desired characteristic. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 1 including its principal surface 1a, a plurality of wirings 11 which are formed in a capacitance forming region 22 regulated on the principal surface 1a and are extended in a predetermined direction, a plurality of wirings 12 which are adjacent to wirings 11p disposed in the periphery of the capacitance forming region 22 and are extended in the predetermined direction and whose potentials are fixed, and an insulating layer 5 formed on the principal surface 1a which fills the gap between each two of the plurality of wirings 11 and fills the gap between each wiring 12 and each wiring 11 adjacent to each other. The plurality of wirings 11, 12 are disposed in a flat plane 21 present in parallel with the principal surface 1a, separately by nearly equal intervals, and are disposed in parallel with each other in a nearly orthogonal direction to the predetermined direction. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device including a capacitor element using a wiring layer.

  In recent years, with the miniaturization of processes, capacitive elements using parasitic capacitance between wirings have started to be used, and a semiconductor integrated circuit device having such a capacitive element is disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-177056. (Patent Document 1). The semiconductor integrated circuit device disclosed in Patent Document 1 includes first and second electrodes that constitute a capacitive element, and a dielectric film sandwiched between the first and second electrodes. A plurality of first and second electrodes are arranged so as to face each other in the planar direction and the thickness direction of the semiconductor substrate.

  Japanese Laid-Open Patent Publication No. 2002-1000073 discloses a capacitive element forming method in which at least two wirings provided in the same wiring layer are arranged close to each other and the capacitance between the lines obtained thereby is a capacitive element. (Patent Document 2).

  Furthermore, Japanese Patent Application Laid-Open No. 2003-152085 discloses a semiconductor device and a method for manufacturing the same for the purpose of preventing coupling of noise to the MIM capacitor (Patent Document 3). The semiconductor device disclosed in Patent Document 3 includes a semiconductor substrate, a capacitive element provided above the semiconductor substrate, and a shield layer formed at least above or below the capacitive element. In another semiconductor device, a laminated film electrically connected to the shield layer is formed in the same layer as the capacitor element, and the laminated film functions in the same manner as the shield layer.

  Further, another document discloses a capacitive element using an interlayer capacitance of a wiring layer (Non-Patent Document 1).

JP 2001-177056 A Japanese Patent Laid-Open No. 2002-1000073 Japanese Patent Laid-Open No. 2003-152085

Roberto Aparicio et al., “Capacity Limits and Matching Properties of Integrated Capacitors” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.37, NO.3, MARCH 2002, pp. 384-393

  However, in the semiconductor integrated circuit device disclosed in Patent Document 1 and the capacitor element method disclosed in Patent Document 2, no countermeasure is taken to reduce interference from the external circuit with respect to the capacitor element. For this reason, there is a problem that the capacitance of the capacitive element fluctuates, and in particular, as the external circuit mentioned in the digital section and the like is increased in speed, countermeasures against such a problem have become more necessary. Yes.

  In addition, in the semiconductor integrated circuit devices disclosed in Patent Documents 1 to 3, if the wiring layer and the silicon gate layer are arranged in a coarse and dense manner, a difference in etching progress occurs due to the coarse and dense. For this reason, the finish of the process may be uneven. Further, when the area such as the active region formed on the main surface of the semiconductor substrate does not satisfy a predetermined ratio with respect to an arbitrary fixed region on the main surface, a film can be formed flat on the main surface. Can not. For this reason, when forming a capacitive element on the film | membrane, it becomes difficult to control etching appropriately. For these reasons, it is not possible to form a capacitive element that exhibits desired characteristics.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described problems, and to provide a semiconductor device in which a capacitance element that exhibits desired characteristics is formed while sufficiently reducing external electrical interference. It is.

  A semiconductor device according to the present invention includes a semiconductor substrate including a main surface, a plurality of first wirings formed in a capacitance formation region defined on the main surface and extending in a predetermined direction, and a periphery of the capacitance formation region Adjacent to the first wiring arranged in the direction, extending in a predetermined direction, and fixed to the plurality of second wirings, and formed on the main surface and adjacent to each other between the plurality of first wirings. And an insulator layer filling between the first wiring and the second wiring. The plurality of first wirings and the plurality of second wirings are arranged at substantially equal intervals in a first plane parallel to the main surface, and are arranged side by side in a direction substantially perpendicular to a predetermined direction.

  According to the present invention, it is possible to provide a semiconductor device in which an external electric interference is sufficiently reduced and a capacitor element exhibiting desired characteristics is formed.

It is sectional drawing of the semiconductor device in Embodiment 1 of this invention. FIG. 2 is a plan view of the semiconductor device along the line II-II in FIG. 1. It is sectional drawing along the III-III line | wire in FIG. It is sectional drawing along the IV-IV line in FIG. It is sectional drawing which shows the semiconductor device in Embodiment 2 of this invention. FIG. 6 is a plan view of the semiconductor device along the arrow VI-VI line in FIG. 5. It is sectional drawing along the VII-VII line in FIG. It is sectional drawing which shows the semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows the semiconductor device in Embodiment 4 of this invention. FIG. 10 is a plan view of the semiconductor device along the arrow XX line in FIG. 9. It is sectional drawing along the XI-XI line in FIG. It is sectional drawing along the XII-XII line | wire in FIG. It is sectional drawing which shows the semiconductor device in Embodiment 5 of this invention. It is sectional drawing which shows the semiconductor device in Embodiment 6 of this invention. It is sectional drawing which shows the semiconductor device in Embodiment 7 of this invention. It is sectional drawing which shows the semiconductor device in Embodiment 8 of this invention. It is sectional drawing which shows the semiconductor device in Embodiment 9 of this invention. It is sectional drawing which shows the semiconductor device in Embodiment 10 of this invention. It is sectional drawing which shows the semiconductor device in Embodiment 11 of this invention. It is sectional drawing which shows the semiconductor device in Embodiment 12 of this invention. It is sectional drawing which shows the semiconductor device in Embodiment 13 of this invention. It is sectional drawing which shows the semiconductor device in Embodiment 14 of this invention. FIG. 23 is a plan view of the semiconductor device along the line XXIII-XXIII in FIG. 22. It is sectional drawing which shows the semiconductor device in Embodiment 15 of this invention. It is sectional drawing which shows the semiconductor device in Embodiment 16 of this invention. It is a top view which shows the semiconductor device manufactured by the design method of the semiconductor device in Embodiment 17 of this invention. FIG. 27 is a plan view illustrating a modification of the semiconductor device illustrated in FIG. 26. FIG. 27 is a plan view illustrating another modification of the semiconductor device illustrated in FIG. 26. FIG. 27 is a plan view showing still another modification of the semiconductor device shown in FIG. 26. FIG. 27 is a plan view showing still another modification of the semiconductor device shown in FIG. 26.

Embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view of the semiconductor device along the line II-II in FIG.

  1 and 2, the semiconductor device includes a semiconductor substrate 1 having a main surface 1a, a plurality of wirings 11 formed in a capacitor formation region 22 on the main surface 1a, and outside the capacitor formation region 22. A plurality of formed wirings 12 and an insulator layer 5 formed on main surface 1a and filling between each of the plurality of wirings 11 and 12 are provided. The plurality of wirings 11 and 12 are made of metal such as copper (Cu) and aluminum (Al), polysilicon, or the like, for example. The insulator layer 5 is made of, for example, a silicon oxide film or silicon doped with TEOS (tetraethyl orthosilicate), BPTEOS, FSG (F-doped silicate glass), phosphorus (P) or boron (B) at a predetermined concentration. It is formed from a nitride film.

  A p-type semiconductor substrate 1 is formed with a p-well 2 extending from the main surface 1a to a predetermined depth. An isolation oxide film 3 is formed on the main surface 1 a of the semiconductor substrate 1 so as to be located in the p well 2. On the main surface 1a, active regions 4 that are located on both sides of the isolation oxide film 3 and connected to the ground potential are formed at a predetermined depth. The isolation oxide film 3 extends and extends below the capacitance forming region 22 where the plurality of wirings 11 are formed, and the active region 4 extends below the plurality of wirings 12.

  The plurality of wirings 11 and 12 are formed on a plane 21 extending in parallel to the main surface 1a at a position spaced from the main surface 1a. A plurality of planes 21 are defined at equal intervals (hereinafter, layers in which the plurality of planes 21 are respectively defined are referred to as M (metal) 1 layer, M2 layer, M3 layer, etc. in order from the main surface 1a). The area between the main surface 1a and the M1 layer is called a CT (contact) layer, and the areas between the M layers adjacent to each other are called a V (via hole) layer, a V2 layer, a V3 layer,. The plurality of wirings 11 and 12 are formed in each layer from the M1 layer to the M4 layer so that the main surface 1a overlaps and is projected onto the main surface 1a when viewed from the front of FIG.

  Each of the plurality of wirings 11 extends in a predetermined direction (a direction indicated by an arrow 23 in FIG. 2) on the plane 21. The plurality of wirings 11 are arranged at an equal distance from each other in a direction orthogonal to the direction in which the wirings 11 extend (the direction indicated by the arrow 24 in FIG. 2).

  On the plane 21, wirings 15 and 16 extending in the direction indicated by the arrow 24 are formed at positions spaced apart from each other. The wirings 15 and 16 extend between the active regions 4 formed on both sides of the isolation oxide film 3. The plurality of wirings 11 includes a plurality of wirings 11 n that branch from the wiring 15 and extend toward the wiring 16, and a plurality of wirings 11 m that branch from the wiring 16 and extend toward the wiring 15. The plurality of wirings 11m and 11n are arranged in a comb-teeth shape alternately arranged.

  Each of the plurality of wirings 12 extends on the plane 21 in the same direction as the direction in which the plurality of wirings 11 extend. The plurality of wirings 12 are formed adjacent to the wirings 11 p arranged on the periphery of the capacitance forming region 22 among the plurality of wirings 11. That is, the plurality of wirings 12 are positioned at both ends of the plurality of wirings 11 in the direction in which the plurality of wirings 11 are arranged. The distance that the wiring 11p and the wiring 12 are separated is equal to the distance that the plurality of wirings 11 are separated from each other.

  FIG. 3 is a cross-sectional view taken along line III-III in FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. 1 to 4, a plurality of wirings 11 and 12 adjacent to the upper and lower layers are connected by via holes 14 and 13 formed in the V1 to V3 layers, respectively. In FIG. 2, via holes 14 and 13 formed in the V3 layer are indicated by broken lines. The wiring 12 formed in the M1 layer and the active region 4 formed in the main surface 1a are further connected by a contact 10 formed in the CT layer. Wirings 15 and 16 adjacent to the upper and lower layers are connected by a via hole 17 formed from the V1 layer to the V3 layer.

  With the configuration described above, the plurality of wirings 11m have the same potential at a potential drawn from a predetermined position of the M4 layer wiring 16, and the plurality of wirings 11n have a potential drawn from a predetermined position of the M4 layer wiring 15. At the same potential. For this reason, by providing a potential difference between the wirings 11m and 11n, between the wirings 11m and 11n adjacent to each other in each plane 21 defined from the M1 layer to the M4 layer, a wiring having the insulating layer 5 as a dielectric layer. An interspace 8 is formed. In addition, by arranging the plurality of wirings 11 in a comb-teeth shape, the plurality of wirings 11m and 11n can be set to a predetermined potential all at once even though a large number of wirings 11 are formed. Can do.

  At this time, by forming the plurality of wirings 11 on the plurality of planes 21, the inter-wiring capacitance 8 having a larger capacitance value can be formed in a limited region on the main surface 1a. The plurality of wirings 11 are arranged side by side in a direction orthogonal to the direction in which the wirings 11 extend. For this reason, the distance which the wiring 11 adjoins can be set long, and a big capacitance value can be obtained.

  Further, since the plurality of wirings 12 are connected to the p-well 2 that is the ground potential via the active region 4, they are fixed to the ground potential. For this reason, the plurality of wirings 12 function as a shield for the capacitance forming region 22 and play a role of shielding electrical interference (noise) from an external circuit provided around the capacitance forming region 22. At this time, since the plurality of wirings 12 are arranged at both ends of the plurality of wirings 11, it is possible to reliably shield noise from external circuits arranged on both sides of the capacitance forming region 22.

  In FIG. 1, the parasitic capacitance 6 formed between the main surface 1a of the semiconductor substrate 1 and the plurality of wirings 11 provided in the M1 layer, and between the plurality of wirings 11p and the plurality of wirings 12 are illustrated. The parasitic capacitance 7 formed in FIG.

  The semiconductor device according to the first embodiment of the present invention includes a semiconductor substrate 1 including a main surface 1a and a plurality of first wirings formed in a capacitance forming region 22 defined on the main surface 1a and extending in a predetermined direction. Adjacent to the wiring 11 as the first wiring, the insulating layer 5 formed on the main surface 1a and filling between each of the plurality of wirings 11, and the wiring 11p as the first wiring disposed on the periphery of the capacitance forming region 22. And a plurality of wirings 12 extending in a predetermined direction and fixed in potential, as second wirings. The plurality of wirings 11 and 12 are arranged at substantially equal intervals in a plane 21 as a first plane parallel to the main surface 1a.

  The plurality of wirings 11 and 12 are arranged side by side in a substantially perpendicular direction to a predetermined direction. The plurality of wirings 12 are provided at both ends of the plurality of wirings 11 arranged in the plane 21. The plurality of wirings 11 and 12 are formed in a plurality of planes 21 spaced from each other.

  In this embodiment, the case where the plurality of wirings 12 are fixed to the ground potential has been described. However, the plurality of wirings 12 may be fixed to the power supply potential depending on the type of the lower well, for example. . Moreover, although the case where the plurality of planes 21 are defined at equal intervals from each other has been described, for example, the distance between the M1 layer and the M2 layer may be different from the distance between the M2 layer and the M3 layer. . Moreover, although the case where the plurality of wirings 11 and 12 are formed in the four layers from the M1 layer to the M4 layer has been described, the plurality of wirings 11 and 12 may be formed in one or more layers.

  For example, when a p-well is formed on the main surface 1a of the p-type semiconductor substrate 1, the p-well may be fixed to the ground potential, or when an n-well is formed on the main surface 1a. The n well may be fixed at the power supply potential and the semiconductor substrate 1 may be fixed at the ground potential. Further, when the n well is formed on the main surface 1a of the n-type semiconductor substrate 1, the n well may be fixed at the power supply potential, and when the p well is formed on the main surface 1a, The p well may be fixed to the ground potential and the semiconductor substrate 1 may be fixed to the power supply potential.

  According to the semiconductor device configured as described above, the plurality of wirings 11 constituting the inter-wiring capacitance 8 and the plurality of wirings 12 functioning as shields are formed at equal intervals. For this reason, the wiring arrangement does not become dense between the center portion and both end portions of the capacitance forming region 22 on the plane 21. As a result, when the plurality of wirings 11 and 12 are formed, etching proceeds at a uniform rate at any position of the capacitance forming region 22, so that a uniform finished shape can be obtained. Further, since the potentials of the plurality of wirings 12 are fixed, the influence of noise from an external circuit on the inter-wiring capacitance 8 can be reduced. That is, in the present embodiment, the plurality of wirings 12 simultaneously serve as a dummy element that enables a uniform process and as a shield that shields noise from the outside. For the reasons described above, it is possible to form the inter-wiring capacitor 8 that exhibits the desired characteristics without variation in the capacitance value.

(Embodiment 2)
The semiconductor device according to the second embodiment of the present invention basically has the same structure as that of the semiconductor device according to the first embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  FIG. 5 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. FIG. 6 is a plan view of the semiconductor device taken along line VI-VI in FIG. FIG. 7 is a cross-sectional view along the line VII-VII in FIG. In addition, the cross-sectional shape along the IV-IV line in FIG. 6 is the same as the cross-sectional shape shown in FIG. In FIG. 6, the via hole 13 formed in the V3 layer is represented by a broken line.

  With reference to FIGS. 5 to 7, in the present embodiment, a plurality of wirings 11 adjacent to the upper and lower layers are not connected by via holes, and the space between them is filled with insulator layer 5. When the main surface 1a is viewed from the front of FIG. 6, the plurality of wirings 11 are projected on the main surface 1a with the wirings 11 formed on the M1 layer and the M3 layer overlapping, and are formed on the M2 layer and the M4 layer. The wirings 11 are overlapped and projected onto the main surface 1a.

  For example, when a cross section taken along the line VII-VII in FIG. 6 shown in FIG. 7 is viewed, the M1 layer and the M3 layer branch from the wiring 16 provided in each layer and extend to the wiring 15m. Is formed. In the M2 layer and the M4 layer, a wiring 11n branched from the wiring 15 provided in each layer and extending toward the wiring 16 is formed. That is, in the present embodiment, the plurality of wirings 11m and 11n are arranged in a comb-teeth shape alternately arranged on both the plane 21 and the plane orthogonal to the plane 21.

  With this configuration, in the present embodiment, in addition to the formation of the inter-wiring capacitance 8a between the wirings 11m and 11n adjacent to each other on the plane 21, between the wirings 11m and 11n adjacent to the upper and lower layers An inter-wiring capacitor 8b is formed.

  According to the semiconductor device configured as described above, the same effects as those described in the first embodiment can be obtained. In addition, since capacitance is formed between wirings adjacent to the upper and lower layers, a larger capacitance value can be realized in a limited region on the main surface 1a.

(Embodiment 3)
The semiconductor device according to the third embodiment of the present invention basically has the same structure as that of the semiconductor device according to the first embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

FIG. 8 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. Referring to FIG. 8, n well 34 is formed on both sides of p well 2 in semiconductor substrate 1 of the present embodiment. The p-well 2 is formed so as to be located immediately below the plurality of wirings 11 and 12 in the horizontal direction and the depth direction in FIG. An n ⁺ well 31 is formed in the semiconductor substrate 1 at a predetermined depth from the main surface 1a. The n ⁺ well 31 is formed over the entire position corresponding to the lower layer of the n well 34 and the p well 2 in the horizontal direction and the depth direction of the paper surface of FIG. The n ⁺ well 31 extends parallel to the n well 34 and the p well 2.

When the p well 2 is not used for fixing the potentials of the plurality of wirings 12, at least the capacitance forming region 22 is projected on the main surface 1a in the lateral direction and the depth direction of the paper surface of FIG. What is necessary is just to form over the area | region. Similarly, the n ⁺ well 31 only needs to be formed over at least the entire region where the capacitance forming region 22 is projected onto the main surface 1a.

On main surface 1 a, isolation oxide film 3 is formed at the boundary between n well 34 and p well 2, and active region 4 is further formed at n well 34. The active region 4 is formed on the main surface 1a and is connected via a contact 10 to a wiring 33 fixed at a power supply potential. With this configuration, the n ⁺ well 31 is fixed at the power supply potential.

According to the semiconductor device configured as described above, the same effects as those described in the first embodiment can be obtained. In addition, by providing the n ⁺ well 31 whose potential is fixed to the semiconductor substrate 1, it is possible to effectively shield noise transmitted mainly from the back surface side of the semiconductor substrate 1 to the capacitance forming region 22. It should be noted that the same effect as that obtained by the n ⁺ well 31 can be obtained by the p well 2 whose potential is fixed.

Note that the potential fixing is not limited to that described in the present embodiment, and when an n well is formed in the main surface 1a of the semiconductor substrate 1 and ap ⁺ well is formed in the lower layer, a plurality of n wells are formed via the n well. The wiring 12 may be fixed at the power supply potential and the p ⁺ well may be fixed at the ground potential. Thereby, there can exist an effect similar to the above-mentioned.

(Embodiment 4)
The semiconductor device according to the fourth embodiment of the present invention basically has the same structure as the semiconductor device according to the first and third embodiments. Hereinafter, the description of the overlapping structure will not be repeated.

  FIG. 9 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention. FIG. 10 is a plan view of the semiconductor device along the line XX in FIG. 11 is a cross-sectional view taken along the line XI-XI in FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. In FIG. 10, the via hole 13 formed in the V4 layer is represented by a broken line.

  Referring to FIGS. 9 to 12, in the present embodiment, a plane 37 extending in parallel to main surface 1a is defined at the position of M5 layer spaced apart from M4 layer by a predetermined distance. The plane 37 is defined such that the capacitance forming region 22 is located between the plane 37 and the main surface 1a. A plurality of wirings 38 are formed on the plane 37. In the plane 37, the plurality of wirings 38 extend in the same direction (the direction indicated by the arrow 23 in FIG. 10) as the direction in which the plurality of wirings 11 extend. The plurality of wirings 38 are arranged at an equal distance from each other in a direction orthogonal to the direction in which the wirings 38 extend (the direction indicated by the arrow 24 in FIG. 10).

  On the plane 37, wirings 41 and 42 extending in the direction indicated by the arrow 24 are formed at positions spaced from each other. The plurality of wirings 38 includes a plurality of wirings 38n that branch from the wiring 41 and extend toward the wiring 42, and a plurality of wirings 38m that branch from the wiring 42 and extend toward the wiring 41. Wirings 38m and 38n are arranged in a comb-teeth shape alternately. The plurality of wirings 38m and 38n are formed so as to overlap with the plurality of wirings 11m and 11n and the plurality of wirings 12 and projected onto the main surface 1a when the main surface 1a is viewed from the front of FIG. ing.

  The wiring 12 provided in the M4 layer and the wiring 38 provided in the M5 layer above the wiring 12 are connected by the via hole 13. With the above configuration, the plurality of wirings 12 and 38 are fixed to the ground potential.

  In FIG. 9, the parasitic capacitance 39 formed between the wiring 38 and the wiring 11 provided in the M4 layer is indicated by a dotted line.

  According to the semiconductor device configured as described above, the same effects as those described in the first and third embodiments can be obtained. In addition, since the plurality of wirings 38 that cover the capacitance forming region 22 from above function as a shield for the capacitance forming region 22 together with the plurality of wirings 12, it is possible to more reliably shield noise from the external circuit.

(Embodiment 5)
The semiconductor device according to the fifth embodiment of the present invention basically has the same structure as that of the semiconductor device according to the fourth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  13 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention. Referring to FIG. 13, in the present embodiment, wiring 11p provided at a position adjacent to a plurality of wirings 12 whose potentials are fixed (position surrounded by a two-dot chain line 46) is connected to a low impedance node. ing. That is, the plurality of wirings 11m including the wiring 11p in FIG. 13 are connected to a relatively low impedance node, and the plurality of wirings 11n not including the wiring 11p are connected to a relatively high impedance node.

  According to the semiconductor device configured as described above, the same effects as those described in the fourth embodiment can be obtained. In addition, with respect to the parasitic capacitance 7 formed between the wiring 11p and the wiring 12, the plurality of wirings 11p are connected to a relatively low impedance node, so that the influence of the parasitic capacitance 7 can be reduced. As a result, high accuracy of the circuit using the inter-wiring capacitance 8 can be realized. For example, the capacitance ratio of the inter-wiring capacitance 8 is shifted due to the parasitic capacitance 7, or the inter-wiring capacitance 8 is used by an amplifier. It is possible to prevent deviation from a desired transmission rate when used in an integrator.

(Embodiment 6)
The semiconductor device according to the sixth embodiment of the present invention basically has the same structure as that of the semiconductor device according to the fourth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  14 is a sectional view showing a semiconductor device according to the sixth embodiment of the present invention. Referring to FIG. 14, in the present embodiment, a potential 12 is connected to a fixed wiring 12 through a via hole 13, and a wiring 38 provided in the M5 layer, a wiring 11m and a via hole 14 formed in the M4 layer are connected. And the wirings 11m provided in the M5 layer are alternately formed. The plurality of wirings 11m include a wiring 11p provided at a position adjacent to the plurality of wirings 12 whose potential is fixed (a position surrounded by a two-dot chain line 51). The plurality of wirings 11m are connected to a relatively low impedance node, and the plurality of wirings 11n are connected to a relatively high impedance node.

  According to the semiconductor device configured as described above, the same effects as those described in the fourth embodiment can be obtained. In addition, the potential-fixed wiring 38 can function as a shield for the capacitance forming region 22 and the influence of the parasitic capacitance 7 can be reduced similarly to the effect described in the fifth embodiment.

(Embodiment 7)
The semiconductor device according to the seventh embodiment of the present invention basically has the same structure as that of the semiconductor device according to the fourth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  15 is a sectional view showing a semiconductor device according to the seventh embodiment of the present invention. Referring to FIG. 15, in the present embodiment, a plurality of floating wirings 57 spaced from each other are formed at the position of the M4 layer sandwiched between the wirings 12 at both ends (position surrounded by a two-dot chain line 56). Has been. The plurality of floating wirings 57 extend in the depth direction of the paper surface shown in FIG. The floating wiring 57 is provided in a state in which the periphery is completely covered with the insulating layer 5 and is set to a floating potential. That is, the floating wiring 57 having a floating potential is formed in the M5 layer, and is positioned between the wiring 38 having the fixed potential and the wiring 11 provided in the M3 layer.

  According to the semiconductor device configured as described above, the same effects as those described in the fourth embodiment can be obtained. In addition, the parasitic capacitance 39 (see FIG. 9) formed between the wiring 11 and the wiring 38 can be reduced by providing the floating wiring 57 having a floating potential at the above-described position. As a result, high accuracy of the circuit using the interwiring capacitance 8 can be realized.

(Embodiment 8)
The semiconductor device according to the eighth embodiment of the present invention basically has the same structure as that of the semiconductor device according to the fourth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  FIG. 16 is a sectional view showing a semiconductor device according to the eighth embodiment of the present invention. Referring to FIG. 16, in the present embodiment, a plurality of floating wirings 59 spaced apart from each other are formed at the position of the M1 layer sandwiched between wirings 12 at both ends (position surrounded by a two-dot chain line 58). Has been. The plurality of floating wirings 59 extend in the depth direction of the paper surface shown in FIG. The floating wiring 59 is provided in a state in which the periphery is completely covered with the insulator layer 5 and is set to a floating potential. That is, the floating wiring 59 having a floating potential is positioned between the wiring 11 provided in the M2 layer and the main surface 1a of the semiconductor substrate 1.

  According to the semiconductor device configured as described above, the same effects as those described in the fourth embodiment can be obtained. In addition, by providing the floating wiring 59 having a floating potential at the above-described position, the parasitic capacitance 6 (see FIG. 9) formed between the wiring 11 and the main surface 1a can be reduced. . As a result, high accuracy of the circuit using the interwiring capacitance 8 can be realized.

(Embodiment 9)
The semiconductor device according to the ninth embodiment of the present invention basically has the same structure as that of the semiconductor device according to the fourth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  FIG. 17 is a sectional view showing a semiconductor device according to the ninth embodiment of the present invention. Referring to FIG. 17, in the present embodiment, a plurality of floating wirings 61 are formed at positions (layers surrounded by a two-dot chain line 60) from the M1 layer to the M4 layer adjacent to the plurality of wirings 12. . The plurality of floating wirings 61 extend in the depth direction of the paper surface shown in FIG. The floating wiring 61 is provided in a state in which the periphery is completely covered with the insulating layer 5 and is set to a floating potential. That is, the floating wiring 61 having a floating potential is positioned between the wiring 11p provided in each of the layers M1 to M4 and the wiring 12 whose potential is fixed.

  According to the semiconductor device configured as described above, the same effects as those described in the fourth embodiment can be obtained. In addition, the parasitic capacitance 7 (see FIG. 9) formed between the wiring 11 and the wiring 12 can be reduced by providing the floating wiring 61 having a floating potential at the above-described position. As a result, high accuracy of the circuit using the interwiring capacitance 8 can be realized.

(Embodiment 10)
The semiconductor device according to the tenth embodiment of the present invention basically has the same structure as that of the semiconductor device according to the fourth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  18 is a sectional view showing a semiconductor device according to the tenth embodiment of the present invention. Referring to FIG. 18, in the present embodiment, no wiring is provided at the position of the M4 layer sandwiched between wirings 12 at both ends (the position surrounded by a two-dot chain line 63), and the position is an insulator. Filled by layer 5. For this reason, the distance from the wiring 38 provided in the M5 layer to the wiring 11 adjacent to the wiring 38 (the wiring 11 provided in the M3 layer) is larger than the distance between the wirings 11 adjacent in the vertical direction.

  According to the semiconductor device configured as described above, the same effects as those described in the fourth embodiment can be obtained. In addition, a parasitic capacitance 39 is formed between the wiring 11 and the wiring 38 by providing a large distance between the wiring 11 and the wiring 38 without providing a wiring in the M4 layer (see FIG. 9). Can be reduced. As a result, high accuracy of the circuit using the interwiring capacitance 8 can be realized.

(Embodiment 11)
The semiconductor device according to the eleventh embodiment of the present invention basically has the same structure as that of the semiconductor device according to the seventh embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  19 is a sectional view showing a semiconductor device according to the eleventh embodiment of the present invention. Referring to FIG. 19, in the present embodiment, every other plurality of floating wirings 57 are formed at the position of the M4 layer sandwiched between wirings 12 at both ends. The plurality of floating wirings 57 are not arranged in a portion where the parasitic capacitance leads to deterioration in circuit accuracy (a portion that becomes a high impedance node when the circuit is assembled), but is arranged in a portion that becomes a low impedance node.

  According to the semiconductor device configured in this way, compared with the semiconductor device in the seventh embodiment, it is possible to further reduce the accuracy deterioration of the high impedance node due to the parasitic capacitance. Further, in the M4 layer where the floating wiring 57 is thinned out, the occupation ratio of the wiring can be ensured as compared with the case shown in FIG. 18, and therefore, the M5 layer positioned on the M4 layer can be formed more flatly.

(Embodiment 12)
The semiconductor device according to the twelfth embodiment of the present invention basically has the same structure as that of the semiconductor device according to the fourth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  20 is a sectional view showing a semiconductor device according to the twelfth embodiment of the present invention. Referring to FIG. 20, in the present embodiment, no wiring is provided at the position of the M1 layer sandwiched between wirings 12 at both ends (position surrounded by a two-dot chain line 66), and the position is an insulator. Filled by layer 5. For this reason, the distance from the main surface 1a of the semiconductor substrate 1 to the wiring 11 adjacent to the main surface 1a (the wiring 11 provided in the M2 layer) is larger than the distance between the wirings 11 adjacent in the vertical direction.

  According to the semiconductor device configured as described above, the same effects as those described in the fourth embodiment can be obtained. In addition, the parasitic capacitance 6 (see FIG. 9) formed between the wiring 11 and the main surface 1a is obtained by providing a large distance between the wiring 11 and the main surface 1a without providing the wiring in the M1 layer. Can be reduced. As a result, high accuracy of the circuit using the interwiring capacitance 8 can be realized.

(Embodiment 13)
The semiconductor device according to the thirteenth embodiment of the present invention basically has the same structure as that of the semiconductor device according to the eighth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  21 is a sectional view showing a semiconductor device according to the thirteenth embodiment of the present invention. Referring to FIG. 21, in this embodiment, every other plurality of floating wirings 59 are formed at the position of the M1 layer sandwiched between wirings 12 at both ends. The floating wiring 59 is not disposed in a portion where the parasitic capacitance leads to deterioration in circuit accuracy (a portion that becomes a high impedance node when the circuit is assembled), but is disposed in a portion that becomes a low impedance node.

  According to the semiconductor device configured in this way, compared with the semiconductor device in the eighth embodiment, it is possible to further reduce deterioration in accuracy of the high impedance node due to parasitic capacitance. Further, in the M1 layer where the floating wiring 59 is thinned out, the occupation ratio of the wiring can be ensured as compared with the case shown in FIG. 20, so that the M2 layer positioned on the M1 layer can be formed more flatly.

(Embodiment 14)
The semiconductor device in the fourteenth embodiment of the present invention basically has the same structure as that of the semiconductor device in the fourth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  22 is a sectional view showing a semiconductor device according to the fourteenth embodiment of the present invention. 23 is a plan view of the semiconductor device taken along the line XXIII-XXIII in FIG. In FIG. 23, the via hole 13 formed in the V4 layer is represented by a broken line. Referring to FIGS. 22 and 23, in the present embodiment, the ratio of the area occupied by active region 4 to a region 71 on main surface 1a on which a plurality of wirings 11 and 12 are formed immediately above is predetermined. Meet the rate.

  The predetermined occupancy here refers to a specific region (an active region or main surface 1a formed by implanting impurities into the main surface 1a) that is defined so that the main surface 1a is finished flat in the manufacturing process of the semiconductor device. (Including the region where the polysilicon film is formed in contact with the substrate). The predetermined occupation ratio is, for example, 25% or more, 50% or more, or 75% or more.

  The semiconductor device according to the fourteenth embodiment of the present invention includes active region 4 as a specific region defined on main surface 1a. The ratio of the area occupied by the active region 4 to the region 71 on the main surface 1a on which the plurality of wirings 11 and 12 are formed immediately above is a certain value or more.

  According to the semiconductor device configured as described above, the same effects as those described in the fourth embodiment can be obtained. In addition, since the active region 4 is formed so as to satisfy a predetermined occupation ratio, a film (in this embodiment, the insulator layer 5) can be formed flat on the main surface 1a. Thereby, since the several wiring 11 and 12 can be formed on a flat film | membrane, the wiring 11 and 12 can be finished in a more uniform shape.

(Embodiment 15)
The semiconductor device according to the fifteenth embodiment of the present invention basically has the same structure as that of the semiconductor device according to the fourteenth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  24 is a sectional view showing a semiconductor device according to the fifteenth embodiment of the present invention. Referring to FIG. 24, in the present embodiment, isolation oxide film 3 is formed at a position on main surface 1a where active region 4 is formed in FIG. The isolation oxide film 3 is located immediately below the wiring 11n having a relatively high impedance, while the active region 4 is located directly below the wiring 11m having a relatively low impedance. .

  According to the semiconductor device configured as described above, the same effects as those described in the fourteenth embodiment can be obtained. In addition, the influence of the parasitic capacitance 6 formed between the wiring 11n of the high impedance node and the main surface 1a can be reduced.

(Embodiment 16)
The semiconductor device according to the sixteenth embodiment of the present invention basically has the same structure as that of the semiconductor device according to the fifteenth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  FIG. 25 is a cross sectional view showing a semiconductor device according to the sixteenth embodiment of the present invention. Referring to FIG. 25, in this embodiment, a polysilicon film 73 is formed immediately below wiring 11m having a relatively low impedance, and just below wiring 11n having a relatively high impedance. An isolation oxide film 3 is formed.

  Even with the semiconductor device configured as described above, the same effects as those described in the fifteenth embodiment can be obtained.

(Embodiment 17)
FIG. 26 is a plan view showing a semiconductor device manufactured by the semiconductor device design method according to the seventeenth embodiment of the present invention. Referring to FIG. 26, semiconductor device 83 has a shape in which extraction terminal cells 80 and 81 and unit capacitor cell 82 arranged between extraction terminal cells 80 and 81 are combined in the Y direction. The lead terminal cells 80 and 81 have a wiring structure on the wiring 41 and 42 side of the semiconductor device shown in FIG. 10, and the unit capacity cell 82 has a wiring structure having a predetermined width between the wiring 41 and the wiring 42. . The lengths in the X direction of the lead terminal cells 80 and 81 and the unit capacity cell 82 are determined so as to satisfy the predetermined occupation ratio described in the fourteenth embodiment.

  27 and 28 are plan views showing modifications of the semiconductor device shown in FIG. Referring to FIG. 27, semiconductor device 84 has a shape in which lead terminal cells 80 and 81 and two unit capacity cells 82 arranged between lead terminal cells 80 and 81 are combined in the Y direction. . Referring to FIG. 28, semiconductor device 85 has a shape in which extraction terminal cells 80 and 81 and ten unit capacity cells 82 arranged between extraction terminal cells 80 and 81 are combined in the Y direction. Have.

  29 and 30 are plan views showing still another modification of the semiconductor device shown in FIG. Referring to FIG. 29, semiconductor device 86 has a shape in which four semiconductor devices 85 shown in FIG. 28 are connected in parallel, and a polysilicon layer 87 extending in a strip shape is disposed at each end thereof. Has been. The polysilicon layer 87 is provided in order to ensure the occupation ratio when there is no gate layer around the capacitance forming region.

  Referring to FIG. 30, semiconductor device 90 has substantially the same shape as semiconductor device 86 in FIG. 29, but at both ends thereof, two polysilicon layers 88 extending in a strip shape and divided at the center. Are arranged respectively. In the polysilicon layer 87 shown in FIG. 29, when the occupation ratio becomes too large, a polysilicon layer 88 divided by an appropriate size is used.

  The semiconductor device design method according to the seventeenth embodiment of the present invention is a semiconductor device design method using the semiconductor device described in the fourteenth to sixteenth embodiments. A method for designing a semiconductor device includes a step of unitizing a semiconductor device as a unit capacity cell and a step of combining a plurality of unit capacity cells.

  According to the semiconductor device design method configured as described above, since the shape of the semiconductor device is determined by combining cells satisfying a predetermined occupation ratio, the entire semiconductor device always satisfies the predetermined occupation ratio. . Therefore, it is possible to design a semiconductor device that satisfies a predetermined occupancy without going through a complicated design process. As a result, a semiconductor device having an inter-wiring capacitance with a small process variation can be obtained.

  Note that the semiconductor device according to the present invention may be configured by appropriately combining the embodiments described above, and in that case, the effects described in the combined embodiments can be similarly obtained. For example, when the configuration satisfying the occupation ratio shown in FIG. 22 is applied to the semiconductor device shown in FIG. 13, the effects described in the fifth and fourteenth embodiments can be achieved.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 1a Main surface, 4 Active area | region, 5 Insulator layer, 11,11m, 11n, 11p, 12,38 wiring, 21,37 plane, 22 capacitance formation area, 31n ⁺ well, 57,59,61 Floating wiring, 71 region, 73 polysilicon film.

Claims (14)

A semiconductor substrate including a main surface;
A plurality of first wirings formed in a capacitance forming region defined on the main surface and extending in a predetermined direction;
A plurality of second wirings adjacent to the first wiring arranged at the periphery of the capacitance forming region, extending in the predetermined direction, and fixed in potential;
An insulating layer which is formed on the main surface and fills between each of the plurality of first wirings and between the adjacent first wiring and second wiring;
The plurality of first wirings and the plurality of second wirings are arranged at substantially equal intervals in a first plane parallel to the main surface and arranged side by side in a direction substantially perpendicular to the predetermined direction. A semiconductor device.   2. The semiconductor device according to claim 1, wherein the plurality of second wirings are provided at both ends of the plurality of first wirings arranged in the first plane.   3. The semiconductor device according to claim 1, wherein the plurality of first wirings and the plurality of second wirings are formed in the plurality of first planes spaced from each other.   The plurality of first wirings includes a first wiring arranged such that a distance from the main surface to the first wiring adjacent to the main surface is larger than a distance between the plurality of first planes. The semiconductor device according to claim 3.   Floating disposed at least one position between the first wiring and the main surface and between the first wiring and the second wiring, extending in the predetermined direction, and having a floating potential The semiconductor device according to claim 1, further comprising a wiring. A plurality of third wirings extending in a predetermined direction spaced apart from each other in a second plane parallel to the main surface;
The semiconductor device according to claim 1, wherein the capacitance formation region is located between the second plane and the main surface.   The semiconductor device according to claim 6, further comprising a floating wiring that is disposed between the first wiring and the third wiring, extends in the predetermined direction, and has a floating potential. The plurality of first wirings and the plurality of second wirings are formed in the plurality of first planes spaced from each other,
The plurality of first wirings are arranged such that a distance from the second plane to the first wiring adjacent to the second plane is larger than a distance between the plurality of first planes. The semiconductor device according to claim 6, comprising: The semiconductor substrate includes a first well layer of a first conductivity type that is electrically connected to the second wiring and extends to the main surface;
The semiconductor device according to claim 1, wherein the first well layer is fixed to one of a ground potential and a power supply potential. The semiconductor substrate further includes a second well layer of a second conductivity type extending in parallel with the first well layer at a position immediately below the capacitance forming region and away from the main surface,
The semiconductor device according to claim 9, wherein the second well layer is fixed at a potential different from a potential at which the first well layer is fixed among a ground potential and a power supply potential.   11. The semiconductor device according to claim 1, wherein the first wiring arranged at the periphery of the capacitance forming region has a lower impedance than the plurality of other first wirings.   The semiconductor substrate includes a specific region defined on the main surface, and an area occupied by the specific region with respect to a region of the main surface on which the plurality of first wirings and the plurality of second wirings are formed immediately above The semiconductor device according to claim 1, wherein the ratio of is a certain value or more.   The specific region is located immediately below the first wiring having a relatively small impedance and is shifted from directly below the first wiring having a relatively large impedance. Semiconductor device.   The plurality of first wirings include a comb tooth extending in one direction from a wiring fixed at a first potential, and another wiring extending in a direction opposite to the comb tooth from another wiring fixed at a second potential. 14. The semiconductor device according to claim 1, wherein the comb teeth are arranged in a comb tooth shape alternately interleaved with each other.

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