JP2010147381A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, capable of improving a recovery operation by reducing recovery loss which has limits in a trench contact structure. <P>SOLUTION: A lifetime killer 13 is formed in a p-type base region 3 or an n<SP>-</SP>-type drift layer 2 by irradiation of an electron beam or a helium beam. With this configuration, disappearance of carriers can be expedited by an action of the lifetime killer 13 at recovery operation. Thus, the depth of the contact trench 10 can be prevented from being deepened too much and recovery loss can be reduced, and recovery characteristics can be improved while preventing deterioration in withstand voltage between a collector and an emitter due to punch through of a base region 3 below the contact trench 10. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device in which an IGBT (insulated gate field effect transistor) and a free wheel diode (simply referred to as a diode) are formed in the same chip.

Conventionally, in a semiconductor device including an IGBT and a diode on the same chip, an n ⁺ type layer serving as a cathode layer is formed in the diode formation region, and a p ⁺ type layer serving as a collector layer is formed in the IGBT formation region. In Patent Document 1, for such a semiconductor device in which an IGBT and a diode are integrated, a trench contact portion is further formed between a plurality of trench gates, and functions as an emitter electrode and an anode electrode in the trench contact portion. It is disclosed that the recovery loss Err is reduced and the recovery operation is improved by bringing the upper electrode into Schottky contact.
JP 2007-214541 A

  However, the improvement in the recovery operation depends on the depth of the trench contact. If the depth of the trench contact is increased to improve the recovery operation, the surface density of the channel under the trench contact decreases. For this reason, the p-type base region under the trench contact is punched through, which decreases the collector-emitter breakdown voltage, and there is a limit to the improvement in the recovery operation.

  Further, when the depth of the trench contact is increased, the aspect ratio defined by the depth (= depth / width) with respect to the width of the trench contact is increased. For this reason, if the upper electrode functioning as the emitter electrode and the anode electrode is made of Al, which is a general electrode material, the electrode surface cannot be flattened, and bonding defects may occur due to unevenness of the electrode surface. . Therefore, a treatment such as filling the trench contact with a tungsten plug (W-Plug) or the like is necessary so that the electrode surface can be flattened, resulting in a complicated manufacturing process and an increase in manufacturing cost.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device manufacturing method capable of improving the recovery operation by reducing the recovery loss that has been limited in the trench contact structure.

  In order to achieve the above object, in the first aspect of the present invention, a diode is constituted by a PN junction formed by the first conductivity type layer (1b) and the drift layer (2) and the second conductivity type base region, In the manufacturing method of the semiconductor device in which the IGBT and the diode are integrated, the lifetime killer (13) is formed by irradiating the base region (3) and the drift layer (2) with an electron beam or a helium beam. It is characterized by including a process.

  Thus, by forming the lifetime killer (13) by electron beam irradiation or helium beam irradiation, the disappearance of carriers can be accelerated during the recovery operation by the action of the lifetime killer (13). For this reason, it is possible to reduce the recovery loss without increasing the depth of the contact trench (10) too much, and the base region (3) under the contact trench (10) is punched through. Recovery characteristics can be improved while suppressing a decrease in collector-emitter breakdown voltage due to.

  The invention according to claim 2 is characterized in that, in the step of forming the lifetime killer (13), irradiation with an electron beam or a helium beam is performed using a mask (15) in which only a diode formation region is opened. .

  As described above, since it is necessary to accelerate the disappearance of carriers in order to improve the recovery characteristics, particularly in the diode formation region, the electron beam irradiation may be performed only in this region.

  According to the third aspect of the present invention, in the step of forming the lifetime killer (13), using the mask (15) having a smaller aperture ratio in the IGBT formation region than in the diode formation region, electron beam irradiation or helium beam It is characterized by performing irradiation.

  Thus, by using the mask (15) having a smaller aperture ratio in the IGBT formation region than in the diode formation region, the formation amount of the lifetime killer (13) can be adjusted by the difference in the aperture ratio. In this way, it is possible to reduce the amount of lifetime killer (13) formed in the IGBT formation region while providing many lifetime killer (13) in the diode formation region.

  For example, as described in claim 4, in the step of forming the lifetime killer (13), the lifetime killer (13) can be formed by electron beam irradiation of 10 to 100 KGy.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of a semiconductor device in which an IGBT and a diode according to the present embodiment are integrated. Hereinafter, a semiconductor device in which the IGBT and the diode according to the present embodiment are integrated will be described with reference to FIG.

  The semiconductor device shown in FIG. 1 is an integrated IGBT and diode. An IGBT and a diode are formed in a cell region of the semiconductor device, and a breakdown voltage structure is formed in an outer peripheral region provided so as to surround the outer periphery. In FIG. 1, a part of the cell region, specifically, an IGBT is formed. Only the vicinity of the boundary position between the region and the diode formation region is shown.

As shown in FIG. 1, p ⁺⁺ -type collector layer 1a and the n ⁺⁺ type cathode layer on the surface of the (first conductivity type layer) 1b, from p ⁺⁺ -type collector layer 1a and the n ⁺⁺ type cathode layer 1b Also, an n ⁻ type drift layer 2 having a low impurity concentration is provided. For example, the p ⁺⁺ type collector layer 1a has a p type impurity concentration of about 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ , and the n ⁺⁺ type cathode layer 1b has an n type impurity concentration of 1 × 10 ¹⁷ to 1 × 1. × 10 ²⁰ cm ^-3 approximately, n ^- -type drift layer 2, n-type impurity concentration is set to about 1 × 10 ¹⁴ cm ^-3.

A p-type base region 3 is formed in the surface layer portion of the n ⁻ -type drift layer 2. For example, the p-type base region 3 has a thickness of about 5 μm and an impurity concentration of about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ .

Then, a plurality of gate trenches 4 are formed so as to penetrate the p-type base region 3 and reach the n ⁻ -type drift layer 2, and the p-type base region 3 is separated into a plurality by the gate trench 4. Has been. Specifically, the gate trenches 4 are formed at a plurality of predetermined pitches (intervals), for example, a stripe structure in which the gate trenches 4 extend in parallel in the depth direction (the vertical direction on the paper) of FIG. Alternatively, it is formed in an annular structure by extending in parallel and then being routed at the tip.

The p-type base region 3 is divided into a plurality of portions by the adjacent gate trenches 4, and n ⁺ -type emitter regions 5 are formed in contact with the side surfaces of the gate trenches 4 in the surface layer portion of each divided p-type base region 3 The body p layer 6 is formed at a position spaced from the side surface of the gate trench 4. The n ⁺ -type emitter region 5 is exposed by being formed on the outermost surface of the p-type base region 3, and the n-type impurity concentration on the surface is about 1 × 10 ²⁰ cm ⁻³ . The body p layer 6 is formed at a position deeper than the n ⁺ -type emitter region 5, and the p-type impurity concentration at the surface is about 1 × 10 ²⁰ cm ⁻³ . The n ⁺ -type emitter region 5 and the body p-layer 6 are sufficiently higher in concentration than the p-type base region 3.

The n ⁺ -type emitter region 5 has a higher impurity concentration than the n ⁻ -type drift layer 2, terminates in the p-type base region 3, and is disposed so as to be in contact with the side surface of the gate trench 4. Yes. More specifically, the structure extends in a rod shape along the longitudinal direction of the gate trench 4 and terminates inside the tip of the gate trench 4.

  Each gate trench 4 includes a gate insulating film 7 formed so as to cover the inner wall surface of each gate trench 4, and a gate composed of doped Poly-Si formed on the surface of the gate insulating film 7. It is embedded with the electrode 8.

  Among these, the gate electrode 8 is electrically connected to each other in a cross section different from that in FIG. 1, and is connected to a gate wiring (not shown) through a doped Poly-Si layer (not shown) formed on the interlayer insulating film 9. ) Is electrically connected.

Further, contact trenches 10 are formed at positions different from the gate trenches 4 formed in the IGBT formation region and the diode formation region, specifically, between the gate trenches 4. The contact trench 10 is shallower than the gate trench 4 and reaches the p-type base region 3 that passes through the n ⁺ -type emitter region 5 and the body p-layer 6 and is located below the body p-layer 6. It is said to be deep. For example, the contact trench 10 has a depth of 1 to 1.5 μm and a width of 1 to 1.5 μm.

An upper electrode 11 is formed so as to be embedded on the surface of interlayer insulating film 9 and n ⁺ -type emitter region 5 and in contact trench 10. The upper electrode 11 functions as an emitter electrode in the IGBT and also functions as an anode electrode in the diode. The upper electrode 11 is electrically connected to the n ⁺ -type emitter region 5 and is connected to the body p layer through the contact trench 10. 6 and the p-type base region 3 are also electrically connected. The upper electrode 11 is made of Al, for example, and is in ohmic contact with the n ⁺ -type emitter region 5 and the body p-layer 6 having a high impurity concentration, and the p-type base region having a low impurity concentration. 3 is in Schottky contact.

Further, a lower electrode 12 is formed on the back side of the p ⁺⁺ type collector layer 1a and the n ⁺⁺ type cathode layer 1b. The lower electrode 12 functions as a collector electrode in the IGBT and also functions as a cathode electrode in the diode, and is in ohmic contact with both the p ⁺⁺ type collector layer 1a and the n ⁺⁺ type cathode layer 1b. .

A lifetime killer 13 by electron beam irradiation is formed in the p-type base region 3 and the n ⁻ -type drift layer 2 in the IGBT formation region and the diode formation region. With such a structure, a semiconductor device in which the IGBT and the diode according to the present embodiment are integrated is configured.

A semiconductor device having such a structure is basically manufactured by irradiating an electron beam after forming a basic element structure by a manufacturing method similar to the conventional one. For example, an n-type semiconductor substrate is prepared, a p-type base region 3, an n ⁺ -type emitter region 5 and a body p-layer 6 are formed on the main surface side, and then a gate trench 4 is formed. A trench gate structure is formed by forming the gate insulating film 7 and the gate electrode 8 in the trench 4 for use. Further, after performing the step of forming the interlayer insulating film 9 and the step of forming the contact trench 10, the upper electrode 11 is formed. Then, after thinning the n-type semiconductor substrate from the back side, a p ⁺⁺ collector layer 1a and an n ⁺⁺ cathode layer 1b are formed by ion implantation of p-type impurities or n-type impurities, and further below A basic element structure is formed by forming the electrode 12.

  Then, an electron beam irradiation process is performed. FIG. 2A is a cross-sectional view schematically showing the electron beam irradiation process, and FIG. 2B is a plan view of the mask 15 used in the electron beam irradiation process. Although FIG. 2B is not a cross-sectional view, the mask 15 is hatched to make the drawing easier to see.

  As shown in FIG. 2B, in the electron beam irradiation process, the mask 15 is used to cover the outer peripheral region where the breakdown voltage structure is formed and to expose the IGBT formation region and the diode formation region. The lifetime killer 13 is formed by irradiating an electron beam from the main surface side (or back surface side) of the element. The electron beam dose at this time is set according to the required recovery characteristics, but in this embodiment, it is about 10 to 100 KGy.

  Thereby, the semiconductor device of this embodiment shown in FIG. 1 can be manufactured. Since the basic element structure is already known, the detailed description of the manufacturing method has only been briefly described. Of course, it may be manufactured by other manufacturing methods.

Thus, in the semiconductor device in which the IGBT and the diode according to the present embodiment are integrated, in the IGBT formation region and the diode formation region, the p-type base region 3 and the n ⁻ -type drift layer 2 are irradiated by electron beam irradiation. A lifetime killer 13 is formed. For this reason, the following effects can be acquired. This effect will be described in comparison with a conventional semiconductor device in which the lifetime killer 13 is not formed.

  FIG. 3 shows a switching circuit created for investigating recovery loss in a method of manufacturing a semiconductor device in which an IGBT and a diode are integrated.

  As shown in FIG. 3, two semiconductor devices in which an IGBT and a diode are integrated are prepared. Each semiconductor device has a structure in which the cathodes and anodes of the diodes 22 and 23 are connected to the collectors and emitters of the IGBTs 20 and 21. The emitter of one IGBT 20 and the collector of the other IGBT 21 are connected, and the collectors of the IGBTs 20 and 21 are connected to a constant voltage source Ecc via inductors L1 and L2. A pulsed voltage VG is applied to the gate of the other IGBT 21 through the input resistor Rg.

  Using such a switching circuit, first, the voltage VG is applied to the gate of the IGBT 21 to turn on the IGBT 21. As a result, a current flows between the collector and the emitter of the IGBT 21 from the power source Ecc through the path A. Next, the application of the voltage VG to the gate of the IGBT 21 is stopped, and the IGBT 21 is turned off. Thereby, a current flows from the inductor L2 to the diode 22 through the path B based on the transient phenomenon. Subsequently, when the voltage VG is applied to the gate of the IGBT 21 again to turn on the IGBT 21, the path B is interrupted. At this time, the recovery loss of the diode 22 can be obtained by measuring the current flowing through the diode 22 in the reverse direction.

  FIG. 4 is a graph showing the result of measuring the recovery loss of a diode provided in a conventional semiconductor device by the above method, and shows the relationship between the depth of the contact trench 10 and the recovery loss. FIG. 5 is a graph showing the depth of the contact trench 10 and the collector-emitter (CE) breakdown voltage. The relative value of the breakdown voltage when the depth of the contact trench 10 is 0 μm is set to 1. It is shown.

  As shown in FIG. 4, the recovery loss decreases as the contact trench 10 becomes deeper. That is, since the Schottky contact portion having a rectifying action is made at the contact point with the upper electrode 11, the recovery current at the time of reverse recovery becomes smaller and the recovery loss than when all the connection points are in ohmic contact. Can be reduced. The magnitude of such a recovery current depends on the depth of the contact trench 10, and the greater the depth of the contact trench 10, the smaller the magnitude of the recovery current and the lower the recovery loss.

  However, on the other hand, as shown in FIG. 5, when the contact trench 10 becomes deep, for example, the depth becomes 2 μm or more, the breakdown voltage between the collector and the emitter rapidly decreases. This is because when the contact trench 10 is deepened, the thickness of the p-type base region 3 in the lower portion of the contact trench 10 is reduced, and punch-through is caused.

  For this reason, the reduction in recovery loss and the collector-emitter breakdown voltage are in a trade-off relationship, and it is necessary to set the depth of the contact trench 10 based on these relationships.

  On the other hand, FIG. 6 is a graph showing the result of measuring the recovery loss of the diode provided in the semiconductor device of the present embodiment by the above method, and shows the relationship between the depth of the contact trench 10 and the recovery loss.

As shown in this figure, it can be confirmed that the recovery loss can be reduced even if the depth of the contact trench 10 is shallow. This is because the lifetime killer 13 by electron beam irradiation is formed in the p-type base region 3 and the n ⁻ -type drift layer 2 in the semiconductor device of the present embodiment. This is because the disappearance of the carrier can be accelerated during the recovery operation. For this reason, it is possible to reduce the recovery loss without increasing the depth of the contact trench 10 too much, and the collector-emitter caused by the punch-through of the p-type base region 3 under the contact trench 10. The recovery characteristic can be improved while suppressing the decrease in the inter-layer withstand voltage.

  As a result, the depth of the contact trench 10 may be reduced, so that the aspect ratio defined by the depth (= depth / width) with respect to the width of the trench contact is reduced, and the upper electrode 11 is generally used. Even if it is made of Al which is a simple electrode material, the electrode surface can be planarized. Therefore, the unevenness of the electrode surface can be suppressed, and it is possible to eliminate the cause of bonding failure. Further, in order to flatten the electrode surface, it is no longer necessary to embed the contact trench 10 with a tungsten plug (W-Plug) or the like, and it is possible to prevent the manufacturing process from becoming complicated and the manufacturing cost from increasing. It becomes.

(Second Embodiment)
A second embodiment of the present invention will be described. The present embodiment is different from the first embodiment in the electron beam irradiation process, specifically, the region where the electron beam irradiation is performed, and the other aspects are the same as those in the first embodiment. Only the parts different from the form will be described.

  FIG. 7A is a cross-sectional view schematically showing the electron beam irradiation process performed in this embodiment, and FIG. 7B is a plan view of the mask 15 used in the electron beam irradiation process. Although FIG. 7B is not a cross-sectional view, the mask 15 is hatched to make the drawing easier to see.

As shown in FIG. 7B, in the electron beam irradiation process of this embodiment, a mask 15 that covers the outer peripheral region and the IGBT formation region where the breakdown voltage structure is formed and exposes only the diode formation region is used. The lifetime killer 13 is formed by irradiating an electron beam from the main surface side (or back surface side) of the element. Thereby, the lifetime killer 13 by electron beam irradiation can be formed in the p-type base region 3 and the n ⁻ -type drift layer 2 in the diode formation region.

  As described above, since it is particularly a diode formation region that needs to expedite the disappearance of carriers in order to improve the recovery characteristics, even if the electron beam irradiation is performed only in this region, the first embodiment is different from the first embodiment. Similar effects can be obtained.

In addition, when the electron beam irradiation is also performed on the IGBT formation region, the characteristics of the IGBT change, and the characteristics of the IGBT are adjusted by adjusting the dose amount when forming the p ⁺⁺ type collector layer 1a. However, it is possible to eliminate the need for such adjustment.

(Third embodiment)
A third embodiment of the present invention will be described. This embodiment is also a modification of the electron beam irradiation process, specifically, the region where electron beam irradiation is performed with respect to the first embodiment, and the other aspects are the same as those of the first embodiment. Only the parts different from the form will be described.

  FIG. 8A is a cross-sectional view schematically showing the electron beam irradiation process performed in this embodiment, and FIG. 8B is a plan view of the mask 15 used in the electron beam irradiation process. Although FIG. 8B is not a cross-sectional view, the mask 15 is hatched to make the drawing easier to see.

  As shown in FIG. 8B, in the electron beam irradiation process of the present embodiment, in addition to the outer peripheral region where the breakdown voltage structure is formed, a part of the IGBT formation region is covered and the diode formation region is completely exposed. The lifetime killer 13 is formed by irradiating the mask 15 with an electron beam from the main surface side (or the back surface side) of the element. Thereby, the formation amount of the lifetime killer 13 by the electron beam irradiation in the diode formation region and the IGBT formation region can be adjusted.

  Thus, by using the mask 15 having a smaller aperture ratio in the IGBT formation region than in the diode formation region, the formation amount of the lifetime killer 13 can be adjusted by the difference in aperture ratio. In this way, it is possible to reduce the amount of lifetime killer 13 formed in the IGBT formation region while providing many lifetime killer 13 in the diode formation region.

(Other embodiments)
In each of the above embodiments, the electron beam irradiation is performed as a process for forming the lifetime killer 13. However, the lifetime killer 13 is also formed by performing helium (He) beam irradiation instead of the electron beam. Can be formed.

In the above embodiment, an n-channel type IGBT in which the first conductivity type is an n-type and the second conductivity type is a p-type has been described as an example. However, for a p-channel type IGBT in which the conductivity type of each part is reversed. The present invention can also be applied. In this case, the IGBT forming region becomes an n ⁺⁺ type collector layer, and a p − type drift layer, an n type base region, and a p ⁺ type emitter region are formed thereon. In the diode forming region, a p ⁺⁺ type anode region is formed. As a result, a PN junction having the p-type drift layer as an anode and the n-type base region as a cathode is formed.

In the present invention, the first conductivity type layer refers to the back side of the diode formation region, that is, the n ⁺⁺ type cathode layer 1b and the p channel type in the case of a diode formed on the same chip as the n channel type IGBT. In the case of a diode formed of the same chip as the IGBT, it means a p ⁺⁺ type anode layer.

It is a figure which shows the cross-sectional structure of the semiconductor device which integrated IGBT and diode concerning 1st Embodiment of this invention. (A) is sectional drawing which showed the electron beam irradiation process typically, (b) is a top view of the mask 15 used in the case of an electron beam irradiation process. It is the switching circuit created in order to investigate the recovery loss of the manufacturing method of the semiconductor device with which IGBT and the diode were integrated. It is the graph which showed the relationship between the depth of the contact trench 10 of a conventional semiconductor device, and recovery loss. It is the graph which investigated the depth of the contact trench 10, and the breakdown voltage between collector-emitters (CE). It is the graph which showed the relationship between the depth of the contact trench of the semiconductor device of 1st Embodiment, and a recovery loss. (A) is sectional drawing which showed the electron beam irradiation process typically, (b) is a top view of the mask 15 used in the case of an electron beam irradiation process. (A) is sectional drawing which showed the electron beam irradiation process typically, (b) is a top view of the mask 15 used in the case of an electron beam irradiation process.

Explanation of symbols

1a p ⁺⁺ type collector layer 1b n ⁺⁺ type cathode layer 2 n ⁻ type drift layer 3 p type base region 4 gate trench 5 n ⁺ type emitter region 6 body p layer 7 gate insulating film 8 gate electrode 9 interlayer insulating film 10 contact trench 11 upper electrode 12 lower electrode 13 lifetime killer 15 mask

Claims (4)

A first conductivity type layer (1b) provided in the diode formation region and a second conductivity type collector layer (1a) formed in the IGBT formation region;
A first conductivity type drift layer (2) disposed on the first conductivity type layer (1b) and the collector layer (1a);
A second conductivity type base region (3) formed on the drift layer (2);
A gate trench (4) that is formed to penetrate the base region (3) and reach the drift layer (2), thereby separating the base region (3) into a plurality of parts;
A first conductivity type emitter region (5) formed in the base region (3) separated into a plurality, and in contact with the side surface of the gate trench (4) in the base region (3); ,
A plurality of base regions (3) separated into a plurality of regions, spaced apart from the side surfaces of the gate trench (4) in the base region (3), and having a higher concentration than the base region. A body layer (6) of two conductivity types;
A gate insulating film (7) formed on the surface of the gate trench (4);
A gate electrode (8) formed on the gate insulating film (7) in the gate trench (4);
A contact trench (10) that penetrates the emitter region (5) and the body layer (6) to reach the base region (3) at a position different from the gate trench (4);
An upper electrode (11) electrically connected to the emitter region (5) and also electrically connected to the base region (3) by being embedded in the contact trench (10);
A lower electrode (12) formed on the back side of the collector layer (1a),
The gate formed in the collector layer (1a), the drift layer (2), the base region (3), the emitter region (5) and the gate trench (4) provided in the IGBT formation region The electrode (7) constitutes an IGBT,
A diode is formed by a PN junction formed by the first conductivity type layer (1b) and the drift layer (2) and the second conductivity type base region (3), and the IGBT and the diode are integrated. A method for manufacturing a semiconductor device comprising:
Manufacturing of a semiconductor device comprising a step of forming a lifetime killer (13) by irradiating the base region (3) and the drift layer (2) with an electron beam or a helium beam Method.   The step of forming the lifetime killer (13) is characterized in that the electron beam irradiation or the helium beam irradiation is performed using a mask (15) in which only the diode formation region is opened. The manufacturing method of the semiconductor device of description.   In the step of forming the lifetime killer (13), the electron beam irradiation or the helium beam irradiation is performed using a mask (15) having a smaller aperture ratio in the IGBT formation region than in the diode formation region. The method of manufacturing a semiconductor device according to claim 1.   4. The semiconductor according to claim 1, wherein in the step of forming the lifetime killer (13), the lifetime killer (13) is formed by electron beam irradiation of 10 to 100 KGy. Device manufacturing method.

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