JP2010141143A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a memory cell size while preventing a contact plug at the lower layer of a capacitive element from oxidizing. <P>SOLUTION: A semiconductor device includes: interlayer dielectrics 106 and 109 formed on a semiconductor substrate 101; a first contact plug 110 penetrating the interlayer dielectrics 106 and 109 to be connected to the semiconductor substrate 101; an insulating hydrogen barrier film 111 formed on the interlayer dielectrics 106 and 109 so as to cover the first contact plug 110; a second contact plug 112 penetrating the insulating hydrogen barrier film 111 to be connected to the first contact plug 110; an oxygen barrier film 113 formed on the insulating hydrogen barrier film 111 to be connected to the second contact plug 112 and cover the second contact plug 112; and a capacitive element 117 formed on the oxygen barrier film 113. The second contact plug 112 has a smaller diameter than the first contact plug 110. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a dielectric memory element having a stacked structure having a capacitor element on a contact plug and a manufacturing method thereof.

  In a dynamic random access memory (DRAM) device or a ferroelectric non-volatile memory (Ferroelectric Random Access Memory: FeRAM) device, a film is formed in order to develop characteristics of a dielectric film that is a capacitive insulating film. Although it is necessary to perform heat treatment later in a high-temperature oxygen atmosphere, a capacitor with a stacked structure having a capacitor element on the contact plug has a problem that the contact plug is oxidized during the heat treatment to increase resistance. .

  On the other hand, conventionally, a method has been used in which an oxygen barrier film for preventing permeation of oxygen is disposed between the contact plug and the lower electrode of the capacitive element to prevent the contact plug from being oxidized. Furthermore, various films or their laminated films have been studied as oxygen barrier films for the purpose of improving oxygen barrier properties and preventing film peeling.

  Conventionally, for example, Patent Document 1 discloses a structure capable of achieving both improvement in oxygen barrier properties and prevention of film peeling as shown in FIG.

  FIG. 12A shows a schematic cross section of a conventional semiconductor device.

  In FIG. 12A, in the formation region of the element partitioned by the shallow trench isolation (STI) region 402 formed in the semiconductor substrate 401, a gate electrode 404 with a gate insulating film 403 interposed therebetween, respectively. A transistor including impurity diffusion layers 405 formed in regions on both sides of the gate electrode 404 in the semiconductor substrate 401 is formed.

  A first interlayer insulating film 406 is formed on the semiconductor substrate 401 so as to cover the transistor. The film thickness of the first interlayer insulating film is 0.5 μm.

  A first contact plug 407 that penetrates the first interlayer insulating film 406 and is connected to the impurity diffusion layer 405 is formed in the first interlayer insulating film 406.

  On the first interlayer insulating film 406, a conductive film 408 connected to the first contact plug 407 is selectively formed. The film thickness of the conductive film 408 is 0.1 μm.

  A second interlayer insulating film 409 is formed over the first interlayer insulating film 406 including the conductive film 408. The film thickness of the upper portion of the conductive film 408 in the second interlayer insulating film 409 is 0.3 μm.

  In addition, a second contact plug 410 that penetrates the second interlayer insulating film 409 and is connected to the conductive film 408 is formed in the second interlayer insulating film 409.

  An oxygen barrier film 411 is formed so as to cover the second contact plug 410 and its peripheral portion on the second interlayer insulating film 409. The oxygen barrier film 411 is composed of titanium (Ti), titanium nitride (TiN), and titanium (Ti) sequentially formed from the lower layer.

  On the oxygen barrier film 411, a ferroelectric capacitor element 415 including a lower electrode 412, a ferroelectric film 413, and an upper electrode 414 is formed. A third interlayer insulating film 416 is formed on the second interlayer insulating film 409 including the ferroelectric capacitor element 415.

As described above, since the ferroelectric film 413 does not exhibit good ferroelectric characteristics when formed, it is necessary to perform heat treatment in a high-temperature oxygen atmosphere. In the prior art, by using a Ti / TiN / Ti laminated structure as the oxygen barrier film 411, oxygen at the time of heat treatment reaches the second contact plug 410 through a path indicated by a dashed arrow. While preventing high resistance, peeling of the oxygen barrier film 411 and the lower electrode 412 is prevented.
JP 2002-280523 A JP 2000-349252 A JP 2002-151656 A

  However, the conventional semiconductor device has the problems shown in FIGS.

  In the prior art, the oxygen barrier structure prevents oxygen during the heat treatment for crystallizing the ferroelectric film 413 from reaching the second contact plug 410 through the path indicated by the broken arrow. However, after the oxygen diffuses toward the semiconductor substrate 401 at the interface between the ferroelectric capacitor element 415 and the third interlayer insulating film 416, as shown by the solid arrow in FIG. The film 411 proceeds in the lateral direction while oxidizing the periphery from the side surface of the lowermost layer Ti. When the oxidation of Ti proceeds to the second contact plug 410, the surface of the second contact plug 410 is oxidized to increase the resistance.

  FIG. 12C shows the relationship between the distance X from the lowermost Ti side surface of the oxygen barrier film 411 shown in FIG. 12A to the second contact plug 410 and the contact yield. FIG. 12C shows the case where the lowermost layer of the oxygen barrier film is Ti and the case of titanium aluminum nitride (TiAlN), respectively.

  In the case where the lowermost layer of the oxygen barrier film is Ti of the conventional example, when the distance X is smaller than 0.60 μm, the oxidation from the side surface of Ti reaches the contact plug, and high resistance is generated. . It can also be seen that even when the lowermost layer of the oxygen barrier film is TiAlN, when the distance X is smaller than 0.35 μm, oxidation from the side surface of TiAlN reaches the contact plug, and high resistance is generated.

  Therefore, in order to manufacture a ferroelectric memory device with a high yield, when using the conventional Ti as the lowermost layer of the oxygen barrier film, it is necessary to secure a distance X of 0.60 μm or more.

  FIG. 12B shows a schematic plan view corresponding to the structure of a conventional semiconductor device when the distance X is 0.60 μm, and the dimensions of each part. The distance X is 0.60 μm, the distance between the oxygen barrier films is 0.24 μm, and the second contact plug has a dimension of 0.28 μm. Element type) is about 5.92 μm 2.

  Further, although the distance between the gate electrode and the first contact plug needs to be 0.10 μm or more, in the memory cell size shown in FIG. 12B, the distance is as large as 0.13 μm. That is, the memory cell size is determined by the capacitor element size.

  Therefore, in order to further reduce the memory cell size, it is necessary to further reduce the distance X. However, if the size is simply reduced, there arises a problem that the contact yield deteriorates as described above.

  In order to solve this problem, various solutions have been studied so far.

  For example, Patent Document 2 proposes a method of forming silicon nitride serving as an oxygen permeation preventive film on the side surface of the lowermost barrier metal film of the oxygen barrier film.

  However, in this method, when silicon nitride is formed on the side surface of the barrier metal film, after silicon nitride is formed on the patterned barrier metal film, the barrier metal film is formed by a chemical mechanical polishing (CMP) method. An additional step of polishing until the film is exposed is necessary. For this reason, the cost increases due to an increase in the number of processes, pattern peeling at the time of CMP, and yield deterioration due to scratches are caused. Furthermore, it is necessary to completely cover the upper surface of the barrier metal film with the lower electrode, and the lower electrode has to be formed larger than the barrier metal film in consideration of a shift at the time of pattern alignment, which increases the cell size.

  As another method, for example, Patent Document 3 proposes a method of using TiAlN whose oxidation proceeds slowly in the lowermost layer of the oxygen barrier film.

  However, in this method, as shown in FIG. 12C and described above, when the memory cell size is further reduced and the distance X from the edge of the TiAlN film to the contact plug becomes smaller than 0.35 μm, oxygen is contacted. In order to reach the plug, the contact plug is oxidized as in the case of using Ti.

  FIG. 12B shows a two-transistor-two-capacitance element type dielectric memory using the conductive film 408 at the center of the figure as a lower bit line of the dielectric memory as shown in FIG. Thus, since the space between the gate electrode and the contact plug needs to be 0.10 μm or more and the width of the gate electrode is 0.32 μm, the distance between the contact plugs provided on both sides of the transistor is 0.52 μm or less. I can't do it.

  In this state, if the size of the capacitive element is further reduced, the memory cell size is determined by the underlying transistor and contact layout, and the contact plug is shifted from the center of the capacitive element to the periphery of the figure. Must be formed. In this case, the distance X is minimized at a portion close to the peripheral portion in the figure, and the progress of oxidation from the side surface becomes a problem at the peripheral portion.

  Therefore, in view of the above-described conventional problems, an object of the present invention is to obtain a semiconductor device capable of reducing the memory cell size while preventing oxidation of a contact plug under the capacitor element. .

  In order to achieve the above object, according to the present invention, the semiconductor device is configured such that the diameter of the second conduct plug on the barrier film side is smaller than the diameter of the first conduct plug on the substrate side.

  Specifically, a first semiconductor device of the present invention includes an interlayer insulating film formed on a semiconductor substrate, a first contact plug that penetrates the interlayer insulating film and is connected to the semiconductor substrate, and an interlayer insulating film. An insulating hydrogen barrier film formed on the film so as to cover the first contact plug; a second contact plug penetrating the insulating hydrogen barrier film and connected to the first contact plug; An oxygen barrier film connected to the second contact plug and formed to cover the second contact plug on the hydrogen barrier film; and a capacitor element formed on the oxygen barrier film, The diameter of the second contact plug is smaller than the diameter of the first contact plug.

  According to the first semiconductor device of the present invention, the second contact plug is formed so as to penetrate the insulating hydrogen barrier film, and the amount of film loss and erosion during CMP when forming the contact plug is reduced. Therefore, the insulating hydrogen barrier film can be formed thin.

  As a result, the second contact plug can be easily formed smaller than the first contact plug, so that the memory cell size can be reduced while keeping the distance between the side surface of the oxygen barrier film and the contact plug the same. .

  In the first semiconductor device of the present invention, the insulating hydrogen barrier film is preferably thinner than the interlayer insulating film.

  A second semiconductor device of the present invention includes a first interlayer insulating film formed on a semiconductor substrate, a first contact plug that penetrates the first interlayer insulating film and is connected to the semiconductor substrate, A conductive film formed on the first interlayer insulating film so as to be connected to the first contact plug; a second interlayer insulating film formed on the first interlayer insulating film so as to cover the conductive film; A second contact plug penetrating through the second interlayer insulating film and connected to the conductive film; and a second contact plug connected to the second contact plug and on the second interlayer insulating film. An oxygen barrier film formed so as to cover and a capacitor element formed on the oxygen barrier film, wherein a diameter of the second contact plug is smaller than a diameter of the first contact plug .

  According to the second semiconductor device of the present invention, since the diameter of the second contact plug is smaller than the diameter of the first contact plug, the distance between the side surface of the oxygen barrier film and the contact plug is kept the same. The memory cell size can be reduced.

  A third semiconductor device of the present invention includes a first interlayer insulating film formed on a semiconductor substrate, a first contact plug that penetrates the first interlayer insulating film and is connected to the semiconductor substrate, A conductive film formed on the first interlayer insulating film so as to be connected to the first contact plug; a second interlayer insulating film formed on the first interlayer insulating film so as to cover the conductive film; A second contact plug penetrating through the second interlayer insulating film and connected to the conductive film; and a second contact plug connected to the second contact plug and on the second interlayer insulating film. An oxygen barrier film formed so as to cover and a capacitive element formed on the oxygen barrier film, the first contact plug is provided at a position different from the center position in the plane of the oxygen barrier film; The second contact plug is on the oxygen barrier film. Characterized in that provided at the center of the plane.

  According to the third semiconductor device of the present invention, even if the first contact plug is provided at a position different from the center position of the capacitor element, the second contact plug can be provided at the center position of the oxygen barrier film. A large distance X between the side surface of the oxygen barrier film and the contact plug can be secured. For this reason, the memory cell size can be further reduced while the distance between the side surface of the oxygen barrier film and the contact plug is kept the same.

  In the third semiconductor device of the present invention, the second contact plug preferably has a diameter smaller than that of the first contact plug.

  In the second semiconductor device and the third semiconductor device of the present invention, the thickness of the upper portion of the conductive film in the second interlayer insulating film is larger than the thickness of the upper portion of the semiconductor substrate in the first interlayer insulating film. Thin is preferred.

  In the second semiconductor device and the third semiconductor device of the present invention, the second interlayer insulating film is preferably an insulating hydrogen barrier film.

  In the second semiconductor device and the third semiconductor device of the present invention, the second interlayer insulating film includes an insulating film made of silicon oxide formed in a portion other than the conductive film in the same layer as the conductive film, and a conductive film And an insulating hydrogen barrier film formed so as to cover the insulating film made of silicon oxide.

  In the first semiconductor device, the second semiconductor device, and the third semiconductor device of the present invention, the insulating hydrogen barrier film is preferably made of a titanium aluminum oxide film or a silicon nitride film.

  In the first semiconductor device, the second semiconductor device, and the third semiconductor device of the present invention, the aspect ratio value of the second contact plug is preferably 1 or less.

  In the second semiconductor device and the third semiconductor device of the present invention, it is preferable that the conductive film is formed of the same film as the bit line arranged below the capacitor.

  In the first semiconductor device, the second semiconductor device, and the third semiconductor device of the present invention, the capacitor element is formed on the lower electrode, the capacitor insulating film formed on the lower electrode, and the capacitor insulating film. It is preferable that the upper electrode is formed.

  In the first semiconductor device, the second semiconductor device, and the third semiconductor device of the present invention, the capacitor insulating film is preferably made of a ferroelectric.

  According to a first method of manufacturing a semiconductor device of the present invention, a step (a) of forming an interlayer insulating film on a semiconductor substrate, and a first contact plug penetrating the interlayer insulating film and connected to the semiconductor substrate are formed. A step (b), a step (c) of forming an insulating hydrogen barrier film on the interlayer insulating film so as to cover the first contact plug, and a first contact plug penetrating the insulating hydrogen barrier film. A step (d) of forming a second contact plug to be connected to the substrate, and an oxygen barrier film is formed on the insulating hydrogen barrier film so as to connect to the second contact plug and cover the second contact plug A step (e) of forming a lower electrode, a capacitive insulating film and an upper electrode in order from the lower layer on the oxygen barrier film, and forming a capacitive element from the lower electrode, the capacitive insulating film and the upper electrode (f) And a step (d) In, wherein the formation to be smaller than the diameter of the diameter of the second contact plug first contact plug.

  According to the first method of manufacturing a semiconductor device of the present invention, the second contact plug is formed in the insulating hydrogen barrier film, and the amount of film loss and erosion during CMP when the contact plug is formed can be reduced. Therefore, the insulating hydrogen barrier film can be formed thin. As a result, the second contact plug can be easily made smaller than the first contact plug, and the memory cell size can be reduced while maintaining the same distance between the side surface of the oxygen barrier and the contact plug.

  In the first method for manufacturing a semiconductor device of the present invention, in step (c), the insulating hydrogen barrier film is preferably formed thinner than the interlayer insulating film.

  In the second method for manufacturing a semiconductor device of the present invention, a step (a) of forming a first interlayer insulating film on a semiconductor substrate, and the first interlayer insulating film are penetrated and connected to the semiconductor substrate. A step (b) of forming a first contact plug, and a step of forming a conductive film on the first interlayer insulating film so as to connect to the first contact plug and cover the first contact plug (c) ), A step (d) of forming a second interlayer insulating film so as to cover the conductive film on the first interlayer insulating film, and a step of connecting the conductive film with the conductive film through the second interlayer insulating film A step (e) of forming a second contact plug, and a step of forming an oxygen barrier film on the second interlayer insulating film so as to connect to the second contact plug and cover the second contact plug ( f) and a lower electrode and a capacitive insulating film on the oxygen barrier film in order from the lower layer. Forming a capacitor element from the lower electrode, the capacitor insulating film, and the upper electrode, and in step (e), the diameter of the second contact plug is set to the first contact plug. It is characterized in that it is formed smaller than the diameter.

  According to the second method for manufacturing a semiconductor device of the present invention, since the diameter of the second contact plug is smaller than the diameter of the first contact plug, the distance between the side surface of the oxygen barrier film and the contact plug is kept the same. The memory cell size can be reduced as it is.

  In the manufacturing method of the second semiconductor device of the present invention, in step (d), the film thickness of the upper part of the conductive film in the second interlayer insulating film is the film of the upper part of the semiconductor substrate in the first interlayer insulating film. It is preferable to form it thinner than the thickness.

  In the second method for manufacturing a semiconductor device of the present invention, in step (d), an insulating film made of silicon oxide is formed on the conductive film, and then the silicon oxide is used until the conductive film is exposed by CMP. It is preferable to include a step of polishing the insulating film to be planarized and a step of forming an insulating hydrogen barrier film on the insulating film made of silicon oxide including the conductive film.

  In the second method for manufacturing a semiconductor device of the present invention, in the step (c), it is preferable to form a bit line disposed below the capacitor element together with the conductive film.

  According to a third method of manufacturing a semiconductor device of the present invention, there is provided a step (a) of forming a first interlayer insulating film on a semiconductor substrate, and a step of penetrating the first interlayer insulating film and connected to the semiconductor substrate. A step (b) of forming a first contact plug, and a step of forming a conductive film on the first interlayer insulating film so as to be connected to the first contact plug and cover the first contact plug (c) And (d) forming a second interlayer insulating film so as to cover the conductive film on the first interlayer insulating film, and connecting the conductive film through the second interlayer insulating film A step (e) of forming a second contact plug, and a step of forming an oxygen barrier film on the second interlayer insulating film so as to connect to the second contact plug and cover the second contact plug (F) and a lower electrode and a capacitor insulation in order from the lower layer on the oxygen barrier film And forming a capacitive element from the lower electrode, the capacitive insulating film, and the upper electrode, and in the step (f), the first contact plug is in-plane with the oxygen barrier film. The oxygen barrier film is formed so that the second contact plug is disposed at a position different from the central position and the second contact plug is disposed at a central position in the plane of the oxygen barrier film.

  According to the third method for manufacturing a semiconductor device of the present invention, even if the first contact plug is provided at a position different from the center position of the capacitive element, the second contact plug can be provided at the center position of the oxygen barrier film. Therefore, a large distance X between the side surface of the oxygen barrier film and the contact plug can be secured. For this reason, the memory cell size can be further reduced while the distance between the side surface of the oxygen barrier film and the contact plug is kept the same.

  In the third method for manufacturing a semiconductor device of the present invention, in the step (e), the diameter of the second contact plug is preferably smaller than the diameter of the first contact plug.

  In the third method of manufacturing a semiconductor device of the present invention, in step (d), the film thickness of the upper part of the conductive film in the second interlayer insulating film is the film of the upper part of the semiconductor substrate in the first interlayer insulating film. It is preferable to form it thinner than the thickness.

  In the third method of manufacturing a semiconductor device according to the present invention, in step (d), after an insulating film made of silicon oxide is formed on the conductive film, the silicon oxide is used until the conductive film is exposed by CMP. Preferably, the method includes a step of polishing the insulating film to be planarized and a step of forming an insulating hydrogen barrier film on the conductive film and the insulating film made of silicon oxide.

  In the third method for manufacturing a semiconductor device of the present invention, in the step (c), it is preferable to form a bit line disposed below the capacitor element together with the conductive film.

  In the second and third semiconductor device manufacturing methods of the present invention, the second interlayer insulating film is preferably formed of an insulating hydrogen barrier film.

  In the first, second and third semiconductor device manufacturing methods of the present invention, the insulating hydrogen barrier film is preferably a titanium aluminum oxide film or a silicon nitride film.

  In the first, second, and third semiconductor device manufacturing methods of the present invention, it is preferable that the aspect ratio value of the second contact plug is 1 or less.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, in a dielectric memory having a stacked structure having a capacitor element on a contact plug, the memory cell size can be reduced while preventing the contact plug under the capacitor element from being oxidized. It becomes.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described.

  FIG. 1A shows a cross-sectional structure of a semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1A, a semiconductor substrate 101 made of, for example, silicon (Si) is formed with shallow trench isolation (STI) regions 102 that partition each element formation region. Are formed of a gate electrode 104 with a gate insulating film 103 interposed therebetween and an impurity diffusion layer 105 functioning as a source region or a drain region formed in regions on both sides of the gate electrode 104 in the semiconductor substrate 101. A transistor is formed. The film thickness of the gate electrode 104 is, for example, 0.2 μm.

A first interlayer insulating film 106 made of silicon oxide having a thickness of about 0.5 μm is formed on the semiconductor substrate 101 so as to cover the transistor. Here, the silicon oxide is so-called BPSG (Boron-Phospho-Silicate Glass) in which boron (B) and phosphorus (P) are added, or so-called HDP which is formed by high-density plasma and boron and phosphorus are not added. -NSG (High Density Plasma-Non Silicate Glass), or ozone _{(O 3) O 3} may be used to -NSG used in an oxidizing atmosphere.

  A third contact plug 107 electrically connected to the impurity diffusion layer 105 is formed on one impurity diffusion layer 105 of the transistor in the first interlayer insulating film 106. For the third contact plug 107, tungsten (W), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN) is preferably used. Further, titanium (Ti), nickel (Ni) or cobalt (Co) silicide metal, copper (Cu), or doped polycrystalline silicon may be used.

  A bit wiring 108 made of tungsten or polycrystalline silicon is selectively formed on the first interlayer insulating film 106 having a planarized upper surface, which is electrically connected to the third contact plug 107. The film thickness of the bit wiring 108 is, for example, 100 nm. A second interlayer insulating film 109 is formed on the first interlayer insulating film 106 so as to cover the bit wiring 108. The second interlayer insulating film 109 is made of, for example, silicon oxide, and the film thickness of the upper portion of the bit wiring 108 of the second interlayer insulating film 109 is, for example, 200 nm.

  In addition, a first contact plug 110 that penetrates the laminated film of the second interlayer insulating film 109 and the first interlayer insulating film 106 and is electrically connected to the other diffusion layer of the transistor is formed.

  On the second interlayer insulating film 109 including the first contact plug 110, an insulating hydrogen barrier film 111 having a film thickness of about 0.2 μm is formed. Here, as the insulating hydrogen barrier film, a titanium aluminum oxide (TiAlO) film formed by a sputtering method, a silicon nitride film formed by a plasma chemical vapor deposition (CVD) method or a thermal CVD method. (SiN) may be used.

  With this insulating hydrogen barrier film, it is possible to prevent hydrogen generated in the wiring formation process or the like after forming the capacitive element from entering from the lower side of the capacitive element and reducing and deteriorating the dielectric film.

  In the insulating hydrogen barrier film 111, a second contact plug 112 that penetrates the insulating hydrogen barrier film 111 and is electrically connected to the first contact plug 110 is formed. Note that the second contact plug 112 may be formed using the same material as that used for the third contact plug 107 or the first contact plug 110 described above. The present embodiment is characterized in that the planar area of the second contact plug 112 is smaller than the planar area of the first contact plug 110 and is at least connected to the first contact plug 110.

On the insulating hydrogen barrier film 111 whose upper surface is flattened, an oxygen barrier film 113 that is electrically connected to the second contact plug 112 and covers the second contact plug 112 and its peripheral portion is provided. Is formed. The oxygen barrier film 113 is a laminated film made of Ti / TiN / Ti. The lowermost layer Ti plays a role of relaxing stress concentration on the second contact plug 112. Further, TiN not only suppresses the material of the second contact plug 112 from diffusing into the dielectric film and prevents oxygen from diffusing into the second contact plug 112, but also on the second contact plug 112. This serves to suppress the floating of the lower electrode 114 in the region. In addition, the uppermost Ti layer plays a role in improving adhesion to the lower electrode 114. The oxygen barrier film 113 includes, for example, titanium aluminum nitride (TiAlN), titanium aluminum oxynitride (TiAlON), titanium nitride (TiN), iridium oxide (IrO _x ), iridium (Ir), ruthenium oxide (RuO _x ), Ruthenium (Ru) or titanium (Ti) may be used. Moreover, you may use the laminated structure which consists of at least 2 of these. Here, x in the general formulas of iridium oxide and ruthenium oxide is a positive real number.

  On the oxygen barrier film 113, a lower electrode 114 made of, for example, a noble metal film or an oxide, nitride or oxynitride having conductivity of the noble metal is formed. The lower electrode 114 includes platinum (Pt), iridium (Ir), ruthenium (Ru), gold (Au), silver (Ag), palladium (Pd), rhodium (Rh), osmium (Os) or their conductivity. An oxide, a nitride, or an oxynitride having bismuth may be used. Moreover, it is good also as a laminated structure which consists of at least 2 of these.

On the lower electrode 114, for example, a capacitive insulating film 115 having a thickness of 0.07 μm is formed. In the capacitor insulating film 115, a barium strontium titanate (Ba _x Sr _1-x TiO ₃ ) (provided that x is 0 ≦ x ≦ 1, hereinafter referred to as BST) based dielectric, Lead zirconium titanate (Pb (Zr _x Ti _1-x ) O ₃ ) (where x is 0 ≦ x ≦ 1, hereinafter referred to as PZT) or lead lanthanum zirconium titanate (Pb _y La _1-y Perovskite dielectric materials containing lead such as (Zr _x Ti _1-x ) O ₃ (where x and y are 0 ≦ x, y ≦ 1), or strontium bismuth tantalate (Sr _1-y Bi _{2 +} xTa ₂ O ₉ ) (where x, y are 0 ≦ x, y ≦ 1, hereinafter referred to as SBT) or bismuth lanthanum titanate (Bi _4-x La _x Ti ₂ O ₁₂ ) (where x is 0 ≦ x ≦ 1 That.) By using a perovskite dielectric body containing bismuth, such as can be manufactured nonvolatile memory device.

For the capacitor insulating film 115 made of a ferroelectric material, a compound having a perovskite structure represented by a general formula ABO ₃ (however, A and B are different elements) can be used.

  Here, the element A is, for example, lead (Pb), barium (Ba), strontium (Sr), calcium (Ca), lanthanum (La), lithium (Li), sodium (Na), potassium (K), magnesium. (Mg) and at least one selected from the group consisting of bismuth (Bi), and the element B is, for example, titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta), tungsten (W ), Iron (Fe), nickel (Ni), scandium (Sc), cobalt (Co), hafnium (Hf), magnesium (Mg), and molybdenum (Mo).

  Further, the capacitor insulating film 115 is not limited to a single-layer ferroelectric film, and a plurality of ferroelectric films having different compositions may be used, and furthermore, different compositions may be inclined.

In addition, the capacitor insulating film 115 is not limited to a ferroelectric, and silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), niobium pentoxide (Nb ₂ O ₅ ), tantalum pentoxide (Ta ₂ O). ₅ ) or aluminum oxide (Al ₂ O ₃ ) or the like may be used.

  An upper electrode 116 is formed on the capacitor insulating film 115. For the upper electrode 116, for example, a noble metal or an oxide, nitride, or oxynitride having conductivity of the noble metal may be used. Specifically, the upper electrode 116 includes platinum (Pt), iridium (Ir), ruthenium (Ru), gold (Au), silver (Ag), palladium (Pd), rhodium (Rh), osmium (Os). Or an oxide, nitride, or oxynitride having conductivity.

  A third interlayer insulating film 118 is formed on the insulating hydrogen barrier film 111 and the capacitor element 117.

  Below, the manufacturing method of the semiconductor device which has said structure is demonstrated.

  2A to 2F, FIGS. 3A to 4F, and FIGS. 4A to 4D show the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. Yes.

  First, as shown in FIG. 2A, an STI region 102 that partitions a plurality of element formation regions is selectively formed on the semiconductor substrate 101. Subsequently, a gate insulating film 103 made of, for example, silicon oxide or silicon oxynitride and having a thickness of about 3 nm, and a gate electrode having a thickness of about 200 nm containing polycrystalline silicon, metal, or metal silicide are formed in each element formation region. 104 are sequentially formed. Subsequently, impurity ions are ion-implanted using the gate electrode 104 as a mask to form an impurity diffusion layer 105 which is a source region or a drain region, whereby transistors are formed.

Next, as shown in FIG. 2B, an insulating film made of BPSG, HDP-NSG, or O ₃ -NSG having a film thickness of about 1.0 μm is formed by CVD, and then CMP is performed. Then, the surface of the formed insulating film is planarized to form the first interlayer insulating film 106 having a thickness of 0.5 μm.

  Next, as shown in FIG. 2C, a third contact hole 119 exposing one impurity diffusion layer 105 of each transistor is formed in the first interlayer insulating film 106 by lithography and dry etching. . The diameter of the third contact hole 119 is 0.28 μm.

  Next, as shown in FIG. 2D, a contact plug is formed so that the third contact hole 119 is filled on the first interlayer insulating film 106 by sputtering, CVD, or plating. A film (not shown) is formed. For the contact plug formation film, a metal such as tungsten, a metal nitride such as titanium nitride, a metal silicide such as titanium silicide, copper, or polycrystalline silicon may be used. In addition, before forming the contact plug formation film, for example, from the laminated film of titanium and titanium nitride or the laminated film of tantalum and tantalum nitride sequentially laminated from the semiconductor substrate 101 side, for example, inside the third contact hole 119. An adhesion layer may be formed. The contact plug formation film thus formed is subjected to CMP until the first interlayer insulating film 106 is exposed, so that the contact plug formation film is electrically connected to one impurity diffusion layer 105 of each transistor. A third contact plug 107 connected to is formed.

  Next, as shown in FIG. 2E, for example, tungsten or polycrystalline is formed on the first interlayer insulating film 106 by a sputtering method, a CVD method, or a low pressure CVD (LP-CVD) method. A bit wiring formation film 108A made of silicon is formed.

  Next, as shown in FIG. 2F, patterning is performed so that the bit wiring formation film 108A is connected to the third contact plug 107 by lithography and etching, and the bit wiring formation film 108A is then connected to the bit wiring. 108 is formed. At this time, when the bit wiring 108 is made of tungsten, for example, an etching gas in which a chlorine-based gas and a fluorine-based gas are mixed may be used. When the bit wiring 108 is made of polycrystalline silicon, a fluorine-based gas is used. Good. In the case where tungsten is used for the bit wiring 108, an adhesion layer made of, for example, a laminated film of titanium and titanium nitride sequentially laminated from the semiconductor substrate 101 side may be formed before the tungsten film is formed. The film thickness of the bit wiring 108 is, for example, 100 nm.

  Next, as shown in FIG. 3A, a second layer of BPSG or the like having a film thickness of about 500 nm is formed on the first interlayer insulating film 106 so as to cover each bit wiring 108 by the CVD method. An interlayer insulating film 109 is formed. Thereafter, a CMP process is performed to planarize the surface of the second interlayer insulating film 109. Note that the film thickness of the upper portion of the bit wiring 108 in the second interlayer insulating film 109 is, for example, 200 nm.

  Next, as shown in FIG. 3B, a third contact plug 107 of each transistor is formed on the laminated film of the first interlayer insulating film 106 and the second interlayer insulating film 109 by lithography and dry etching. A first contact hole 120 exposing the other impurity diffusion layer 105 different from the impurity diffusion layer 105 connected to is formed. The diameter of the first contact hole 120 is 0.28 μm.

  Next, as shown in FIG. 3C, a contact plug is formed so that the first contact hole 120 is filled on the second interlayer insulating film 109 by sputtering, CVD, or plating. A film (not shown) is formed. As described above, a metal such as tungsten, a metal nitride such as titanium nitride, a metal silicide such as titanium silicide, copper, or polycrystalline silicon may be used for the contact plug formation film. Further, before forming the contact plug formation film, the first contact hole 120 is made of, for example, a laminated film of titanium and titanium nitride or a laminated film of tantalum and tantalum nitride sequentially laminated from the semiconductor substrate 101 side. An adhesion layer may be formed. A CMP process is performed on the formed contact plug formation film until the second interlayer insulating film 109 is exposed, so that the first contact plug formation film is electrically connected to the impurity diffusion layer 105. One contact plug 110 is formed.

Next, as shown in FIG. 3D, an insulating hydrogen barrier film 111 having a thickness of 0.15 μm is formed on the second interlayer insulating film 109 including the first contact plug 110. As this insulating hydrogen barrier film, TiAlO may be formed by sputtering, or Si ₃ N ₄ film may be formed by plasma CVD or thermal CVD.

  As described above, when the insulating hydrogen barrier film is provided on the lower side of the capacitive element, hydrogen generated in the wiring forming process after the capacitive element is formed enters from the lower side of the capacitive element, and the dielectric film is reduced and deteriorated. Can be prevented.

  Next, as shown in FIG. 3E, a second contact hole 121 exposing the upper surface of the first contact plug 110 is formed in the insulating hydrogen barrier film 111 by lithography and dry etching. The diameter of the second contact hole is, for example, 0.16 μm, which is smaller than the first contact hole 120 formed to a diameter of 0.28 μm in FIG. 3B and is connected to at least the first contact plug 110. To form. Furthermore, it is preferably located within the upper surface of the first contact plug 110.

  Next, as shown in FIG. 3F, the second contact hole is filled so that the second contact hole 121 is filled on the insulating hydrogen barrier film 111 by sputtering, CVD, or plating. A plug forming film 112A is formed. Here, the second contact plug formation film 112 </ b> A may be made of the same material as the third contact plug 107 or the first contact plug 110. Further, an adhesion layer made of a laminated film of titanium nitride and titanium or a laminated film of tantalum nitride and tantalum may be formed inside the second contact hole 121 before forming the contact plug forming film.

  Next, as shown in FIG. 4A, the second contact plug formation film 112A is subjected to CMP until the insulating hydrogen barrier film 111, which is a base film, is exposed. Form. Here, shapes after CMP are shown for a case where the base film is a silicon oxide film (A) and a case where the base film is an insulating hydrogen barrier film (B). The silicon oxide film is illustrated for comparison. Further, in order to draw a plurality of contact plugs, the magnification is reduced with respect to the previous drawings, and components other than the first contact plug 110 and the second contact plug 112 are omitted. Further, for easy understanding, the surface of the base film before CMP is drawn so as to be aligned with a reference line (two-dot chain line in the drawing).

  When the base film is an insulating hydrogen barrier film, the amount of film reduction (I) and the amount of erosion (II) are smaller than when the base film is a silicon oxide film. Can be as thin as 150 nm in the case of an insulating hydrogen barrier film. In CMP, a chemical action that oxidizes a film by an oxidant contained in a slurry and an action that removes a film that is physically oxidized by an abrasive are used together, and the underlying film is an insulating hydrogen barrier film. In this case, since it is difficult to oxidize due to its denseness and stability, the polishing rate becomes very slow compared with silicon oxide, and such a difference occurs. Also, after polishing, cleaning with hydrofluoric acid (HF) is performed for the purpose of removing wafer particles, slurry or other contaminants. At this time, since the silicon oxide is etched by HF, the insulating hydrogen barrier film is not wet etched, so that the required film thickness difference is further increased.

  Next, as shown in FIG. 4B, the entire surface of the insulating hydrogen barrier film 111 is formed by, for example, sputtering, CVD, or metal organic chemical vapor deposition (MOCVD). An oxygen barrier formation film 113A having a thickness of 250 nm and preventing oxidation of the second contact plug 112 is formed. The oxygen barrier film 113 is a laminated film of Ti / TiN / Ti.

  Next, a lower electrode made of a noble metal such as platinum or iridium or an oxide, nitride or oxynitride having conductivity of the noble metal and having a film thickness of about 100 nm is formed on the oxygen barrier forming film 113A by sputtering. A formation film 114A is formed.

  Next, a capacitive insulating film formation film 115A made of, for example, a ferroelectric material and having a film thickness of 70 nm is formed on the lower electrode formation film 114A by a metal organic compound deposition (MOD) method, a sputtering method, an MOCVD method, or the like. Is deposited. A ferroelectric material such as BST, PZT, or SBT is preferably used for the capacitor insulating film formation film 115A.

  Next, the upper electrode formation film 116A having a thickness of 60 nm is formed by sputtering under the same film formation conditions as the lower electrode formation film 114A.

  Next, as shown in FIG. 4C, the oxygen barrier formation film 113A, the lower electrode formation film 114A, and the capacitive insulation are performed by lithography and dry etching using a mixed gas of chlorine-based gas and fluorine-based gas. The film forming film 115A and the upper electrode forming film 116A are patterned to form an oxygen barrier film 113, a lower electrode 114, a capacitor insulating film 115, and an upper electrode 116, respectively. As a result, a capacitor element 117 including the lower electrode 114, the capacitor insulating film 115, and the upper electrode 116 is formed.

  In this example, the oxygen barrier film 113, the lower electrode 114, the capacitor insulating film 115, and the upper electrode 116 are etched at once. However, the step of etching the oxygen barrier film 113 and the lower electrode 114, the capacitor insulating film 115, You may divide into the process of etching the upper electrode 116.

  Next, as shown in FIG. 4D, a third interlayer insulating film 118 made of BPSG or the like is formed on the insulating hydrogen barrier film 111 so as to cover the capacitor element 117 by, for example, 1. The film is formed with a thickness of 0 μm. Thereafter, the surface of the formed third interlayer insulating film 118 is planarized by CMP. The thickness of the third interlayer insulating film 118 after planarization over the capacitor 117 is preferably 100 nm to 300 nm.

  Subsequently, heat treatment is performed at a high temperature and in an oxygen atmosphere in order to crystallize the capacitor insulating film 115 and improve the film quality. This heat treatment may be annealing using a furnace, or rapid thermal annealing (RTA). The heating temperature is preferably 600 ° C. or higher and 850 ° C. or lower.

  Thereafter, although not shown in the figure, the other interlayer diffusion layer 105 is connected to the laminated film including the third interlayer insulating film 118, the insulating hydrogen barrier film 111, the second interlayer insulating film 109, and the first interlayer insulating film 106. A contact plug to be formed is formed, and then a wiring made of general aluminum (Al) or copper (Cu) is formed.

  In general, when the interlayer insulating film for forming the contact plug is thick, that is, the aspect ratio is large, the etching gas is difficult to enter the hole, and so-called etch stop is likely to occur. In addition, when the contact hole is deep, the plug formation film cannot be sufficiently embedded in the hole, and a conduction failure is likely to occur. However, in this embodiment, as described above, by using the insulating hydrogen barrier film 111 as the interlayer insulating film for forming the second contact plug 112, the interlayer insulating film for forming the second contact plug 112 is changed. Can be thinned. In the present embodiment, the thickness of the first interlayer insulating film 106 that forms the first contact plug 110 is 0.8 μm, whereas the insulating hydrogen barrier film that forms the second contact plug 112. The film thickness of 111 is 0.15 μm. As a result, the second contact plug 112 can be formed smaller than the first contact plug 110, and the memory cell size can be reduced accordingly.

  FIG. 1B shows a plan view and dimensions of each part in the present embodiment. Here, it is described that the memory cell size can be reduced by forming the diameter of the second contact plug 112 smaller than the diameter of the first contact plug 110 with respect to the conventional example.

As shown in FIG. 1B, when the diameter of the second contact plug 112 is 0.16 μm, the required distance between the side surface of the oxygen barrier film 113 and the second contact plug 112 is the conventional example. Is the same. For this reason, the memory cell can be made smaller by the amount that the contact plug is made smaller. In the present embodiment, the memory cell size is 5.12 μm ² , and can be reduced to about 86% of the conventional example.

  Further, the distance between the second contact plug 112 and the gate electrode 104 and the distance between the first contact plug 110 and the gate electrode 104 are 0.10 μm. If the size of the capacitor is further reduced, the second contact plug 112 112 cannot be provided at the center position of the oxygen barrier film 113.

In the present embodiment, the insulating hydrogen barrier film 111 is formed thinner than the laminated film composed of the first interlayer insulating film 106 and the second interlayer insulating film 109, so that the second contact plug 112 is formed small. be able to. Here, the value of the aspect ratio of the second contact plug 112 is preferably 1 or less. By doing so, the second contact plug 112 can be easily formed small. In the present embodiment, the diameter of the second contact plug 112 is 0.16 μm, the height is 0.15 μm, and the aspect ratio value is 1 or less. For this reason, the second contact plug 112 can be easily formed smaller than the first contact plug 110.
(Second Embodiment)
The semiconductor device according to the second embodiment of the present invention will be described below.

  FIG. 5A shows a cross-sectional structure of a semiconductor device according to the second embodiment of the present invention.

  In FIG. 5A, the layer structure from the semiconductor substrate 101 to the first interlayer insulating film 106 is the same as the layer structure from the semiconductor substrate 101 to the first interlayer insulating film 106 according to the first embodiment. Therefore, repeated description is omitted.

  A first conductive film 202B and a second conductive film, which are electrically connected to the first contact plug 201 and made of tungsten or polycrystalline silicon, are formed on the first interlayer insulating film 106 whose upper surface is planarized. 202C is selectively formed. On the first interlayer insulating film 106, a second interlayer insulating film 203 is formed so as to cover the first conductive film 202B and the second conductive film 202C. The second interlayer insulating film 203 is made of, for example, silicon oxide, and the film thickness of the upper portions of the first conductive film 202B and the second conductive film 202C is, for example, 150 nm. A second contact plug 204 that is electrically connected to the first conductive film 202B is formed in the second interlayer insulating film 203. Here, the diameter of the second contact plug is smaller than the diameter of the first contact plug.

  On the second interlayer insulating film 203 whose upper surface is flattened, the second contact plug 204 is electrically connected to the second contact plug 204 and on the second interlayer insulating film 203. A plurality of oxygen barrier films 205 are formed to cover 204 and the peripheral portions thereof. The oxygen barrier film 205 is a laminated film of Ti / TiN / Ti.

  On the oxygen barrier film 205, a lower electrode 206 made of, for example, a noble metal film or an oxide, nitride, or oxynitride having conductivity of the noble metal is formed. On the lower electrode 206, a capacitor insulating film 207 having a film thickness of, for example, 70 nm is formed. An upper electrode 208 is formed on the capacitor insulating film 207. In addition, a third interlayer insulating film 210 is formed on the second interlayer insulating film 203 so as to fill the capacitor element 209.

  Below, the manufacturing method of the semiconductor device which has said structure is demonstrated.

  6A to 6E and FIGS. 7A to 7C show a method for manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

  In the present embodiment, the manufacturing method from the semiconductor substrate 101 to the first contact plug 201 is the same as the steps from FIG. 2A to FIG. 2D in the first embodiment, and thus repeated description is omitted. To do.

  First, as shown in FIG. 6A, a conductive film formation film 202A made of, for example, tungsten or polycrystalline silicon is formed on the first interlayer insulating film 106 by sputtering, CVD, or LP-CVD. .

  Next, as shown in FIG. 6B, the conductive film formation film 202A is patterned by the lithography method and the etching method so as to be connected to the first contact plug 201. A first conductive film 202B and a second conductive film 202C are formed. The film thickness of the first conductive film 202B and the second conductive film 202C is, for example, 100 nm.

  Next, as shown in FIG. 6C, a BPSG film having a thickness of about 500 nm is formed on the interlayer insulating film 106 so as to cover the first conductive film 202B and the second conductive film 202C by the CVD method. After the second interlayer insulating film 203 made of, for example, is formed, a CMP process is performed to flatten the surface. Note that the film thickness of the upper portion of the first conductive film 202B and the second conductive film 202C in the second interlayer insulating film 203 is, for example, 200 nm. Here, the second conductive film 202C serves as a bit wiring, and the first conductive film 202B serves as a connection portion that connects the second contact plug 204 and the first contact plug 201 formed in the subsequent steps.

  Next, as shown in FIG. 6D, a second contact hole 211 exposing the first conductive film 202B is formed in the second interlayer insulating film 203 by lithography and dry etching. The diameter of the contact hole is, for example, 0.16 μm.

  Next, as shown in FIG. 6E, a contact plug is formed so that the second contact hole 211 is filled on the second interlayer insulating film 203 by sputtering, CVD, or plating. A film (not shown) is formed, and then the contact plug formation film is subjected to CMP until the second interlayer insulating film 203 is exposed, thereby forming the first contact plug formation film. A second contact plug 204 that is electrically connected to the conductive film 202B is formed.

  Next, as shown in FIG. 7A, the second contact plug 204 having a thickness of, for example, 250 nm is formed on the entire surface of the second interlayer insulating film 203 by, for example, sputtering, CVD, or MOCVD. An oxygen barrier formation film 205A for preventing oxidation of the film is formed. The oxygen barrier formation film 205A is a laminated film of Ti / TiN / Ti.

  Next, by sputtering, the oxygen barrier forming film 205A is made of a noble metal such as platinum or iridium or an oxide, nitride or oxynitride having conductivity of the noble metal, and has a thickness of about 100 nm, for example. An electrode formation film 206A is formed.

  Next, a capacitive insulating film forming film 207A made of, for example, a ferroelectric material and having a film thickness of, for example, 40 nm is formed on the lower electrode forming film 206A by the MOD method, the sputtering method, the MOCVD method, or the like.

  Next, an upper electrode formation film 208A having a film thickness of, for example, 60 nm is formed by sputtering, under the same film formation conditions as the lower electrode formation film 206A.

  Next, as shown in FIG. 7B, the oxygen barrier formation film 205A, the lower electrode formation film 206A, and the capacitance insulation are formed by lithography and dry etching using a mixed gas of chlorine-based gas and fluorine-based gas. The film forming film 207A and the upper electrode forming film 208A are patterned to form an oxygen barrier film 205, a lower electrode 206, a capacitive insulating film 207, and an upper electrode 208, respectively. As a result, a capacitor element 209 including the lower electrode 206, the capacitor insulating film 207, and the upper electrode 208 is formed.

  In this example, the oxygen barrier film 205, the lower electrode 206, the capacitor insulating film 207, and the upper electrode 208 are etched at once, but the step of etching the oxygen barrier film 205 and the lower electrode 206, You may divide into the process of etching the upper electrode 208. FIG.

  Next, as shown in FIG. 7C, by CVD, the second interlayer insulating film 203 is made of BPSG or the like having a film thickness of, for example, 1.0 μm so as to cover the capacitor element 209. Three interlayer insulating films 210 are formed. Thereafter, the surface of the formed third interlayer insulating film 210 is planarized by CMP. The thickness of the upper portion of the capacitor 209 in the third interlayer insulating film 210 after planarization is preferably 100 nm to 300 nm.

  Subsequently, heat treatment is performed at a high temperature and in an oxygen atmosphere in order to crystallize the capacitor insulating film 207 and improve the film quality. This heat treatment may be annealing using a furnace or RTA. The heating temperature is preferably 600 ° C. or higher and 850 ° C. or lower.

  Thereafter, although not shown, a contact plug connected to the other impurity diffusion layer 105 is formed in the laminated film composed of the third interlayer insulating film 210, the second interlayer insulating film 203, and the first interlayer insulating film 106, A wiring made of general Al or Cu is formed.

  FIG. 5B shows a plan view and dimensions of each part in the present embodiment. Here, as compared with the conventional example, it will be described that the memory cell size can be reduced by forming the diameter of the second contact plug 204 smaller than the diameter of the first contact plug 201.

As shown in FIG. 5B, when the second contact plug 204 is formed with a thickness of 0.16 μm, the required distance between the side surface of the oxygen barrier film 205 and the second contact plug 204 is the same as in the conventional example. For this reason, the memory cell can be made smaller by the amount that the contact plug is made smaller. In this embodiment, the memory cell size is 5.12 μm ² , which can be reduced to about 86% of the conventional example.

  In addition, it is preferable that the film thickness of the upper part of the first conductive film 202B and the second conductive film 202C in the second interlayer insulating film 203 is smaller than the film thickness of the first interlayer insulating film 106. In this case, the second contact plug 204 can be easily formed smaller than the first contact plug 201.

  In addition, an insulating hydrogen barrier film is preferably used as the second interlayer insulating film 203. In this case, since the amount of film loss and the amount of erosion during CMP for forming the contact plug can be reduced, the insulating hydrogen barrier film can be formed thin. Thereby, the second contact plug 204 can be easily formed smaller than the first contact plug 201.

In addition, the step of forming the first conductive film 202B and the second conductive film 202C is preferably formed together with a bit wiring (capacitor element underlying bit line) arranged below the capacitor 209. This bit wiring is a wiring for reading or rewriting the storage data of the capacitive element, and there is a capacitive element upper bit line arranged above the capacitive element and a capacitive element lower bit line arranged below the capacitive element. . In particular, the structure disposed under the capacitor element is effective for miniaturization of the memory cell. By using this bit line also as the conductive film, there is no additional process and a low-cost semiconductor device is manufactured. Is possible.
(Modification of the semiconductor device manufacturing method according to the second embodiment)
8A to 8E show a modification of the method for manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

  This step corresponds to the step of forming the second interlayer insulating film shown in FIG. 6C in the method for manufacturing the semiconductor device according to the second embodiment of the present invention, and the description of the other steps is omitted. To do.

  First, as shown in FIG. 8A, a silicon oxide film 212 is formed so as to cover the first conductive film 202B, and the first conductive film 202B is formed by CMP using the first conductive film 202B as a stopper. The silicon oxide film 212 is polished so as to be flush with the upper surface.

  Next, as illustrated in FIG. 8B, an insulating hydrogen barrier film 213 is formed over the first conductive film 202 </ b> B and the silicon oxide film 212. The thickness of the insulating hydrogen barrier film 213 is, for example, 100 nm.

  Next, as shown in FIG. 8C, a second contact hole 211 that penetrates the insulating hydrogen barrier film 213 and has the first conductive film 202B as a bottom surface is formed by lithography and dry etching. . The diameter of the second contact hole is, for example, 0.14 μm.

  Next, as illustrated in FIG. 8D, a second contact plug formation film 204 </ b> A is formed on the insulating barrier film 213 so as to fill the second contact hole 211.

  Next, as shown in FIG. 8E, the second contact plug formation film 204A other than the second contact hole 211 is removed, and a second contact plug 204 is formed.

In this method, when the insulating hydrogen barrier film 213 is formed as the second interlayer insulating film, the insulating hydrogen barrier film 213 is compared with the manufacturing method in which the second interlayer insulating film is polished and planarized by the CMP method. Since the film 213 is not polished, variations in the insulating hydrogen barrier film 213 are small and the film thickness can be further reduced, so that the contact plug can be further reduced.
(Third embodiment)
A semiconductor device according to the third embodiment of the present invention will be described below.

  FIG. 9A shows a cross-sectional structure of a semiconductor device according to the third embodiment of the present invention.

  In FIG. 9A, the layer structure from the semiconductor substrate to the first interlayer insulating film is the same as the layer structure from the semiconductor substrate 101 to the first interlayer insulating film 106 according to the first embodiment. Therefore, repeated description is omitted.

  A first conductive film 302B and a second conductive film, which are electrically connected to the first contact plug 301 and made of tungsten or polycrystalline silicon, are formed on the first interlayer insulating film 106 whose upper surface is planarized. 302C is selectively formed. On the first interlayer insulating film 106, a second interlayer insulating film 303 is formed so as to cover the first conductive film 302B and the second conductive film 302C. The second interlayer insulating film 303 is made of, for example, silicon oxide, and the thickness of the upper portion of the first conductive film 302B and the second conductive film 302C is 150 nm. In addition, a second contact plug 304 that is electrically connected to the first conductive film 302B is formed in the second interlayer insulating film 303.

In addition, the second contact plug 304 is electrically connected to the second contact plug 304 on the second interlayer insulating film 303 whose upper surface is flattened, and the second contact plug 304 is formed on the second interlayer insulating film 303. A plurality of oxygen barrier films 305 are formed to cover 304 and its peripheral portions. The oxygen barrier film 305 is a laminated film made of, for example, titanium aluminum nitride (TiAlN), iridium (Ir), and iridium oxide (IrO _x ) from the bottom.

  On the oxygen barrier film 305, a lower electrode 306 made of, for example, a noble metal or an oxide, nitride, or oxynitride having conductivity of the noble metal is formed. On the lower electrode 306, a capacitive insulating film 307 having a thickness of 60 nm, for example, is formed. An upper electrode 308 is formed on the capacitor insulating film 307. In addition, a third interlayer insulating film 310 is formed on the second interlayer insulating film 303 so as to fill the capacitor 309.

  In the third embodiment, the first contact plug 301 is formed so as to be shifted from the center position of the second contact plug 304 to the opposite side of the gate electrode 104 via the first conductive film 302B.

  Below, the manufacturing method of the semiconductor device which has said structure is demonstrated.

  10A to 10D and FIGS. 11A to 11D show a method for manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps.

  In the present embodiment, the manufacturing method from the semiconductor substrate 101 to the first contact plug 107 is the same as the steps from FIG. 2A to FIG. 2D in the first embodiment, and thus repeated description is omitted.

  First, as shown in FIG. 10A, a conductive film formation film 302A made of, for example, tungsten or polycrystalline silicon is formed on the first interlayer insulating film 106 by sputtering, CVD, or LP-CVD. .

  Next, as shown in FIG. 10B, the conductive film formation film 302A is patterned so as to be connected to the first contact plug 301 by a lithography method and an etching method. The conductive film 302B and the second conductive film 302C are formed. The film thickness of the first conductive film 302B and the second conductive film 302C is, for example, 100 nm. Here, the inner end portion of the first conductive film 302 </ b> B is formed so as to overlap with the upper end portion of the gate electrode 104.

  Next, as illustrated in FIG. 10C, the film thickness is approximately over the first interlayer insulating film 106 so as to cover the first conductive film 302 </ b> B and the second conductive film 302 </ b> C by a CVD method. After the second interlayer insulating film 303 made of 500 nm BPSG or the like is formed, a CMP process is performed to planarize the surface. Note that the film thickness of the upper portion of the first conductive film 302B and the second conductive film 302C in the second interlayer insulating film 303 is, for example, 150 nm. Here, the second conductive film 302C serves as a bit wiring, and the first conductive film 302B serves as a connection portion that connects the second contact plug 305 and the first contact plug 301 formed in the subsequent steps.

  Next, as shown in FIG. 10D, the end portion of the first conductive film 302B on the second conductive film 302C side is exposed to the second interlayer insulating film 303 by lithography and dry etching. A second contact hole 311 is formed. The diameter of the second contact hole is, for example, 0.16 μm.

  Next, as shown in FIG. 11A, a contact plug is formed so that the second contact hole 311 is filled on the second interlayer insulating film 303 by sputtering, CVD, or plating. A film (not shown) is formed, and then CMP processing is performed on the contact plug formation film until the second interlayer insulating film 303 is exposed to form the contact plug formation film. A second contact plug 304 that is electrically connected to the conductive film 302B is formed.

Next, as shown in FIG. 11B, the second contact plug 304 is prevented from being oxidized on the entire surface of the second interlayer insulating film 303 by, for example, sputtering, CVD, or MOCVD. For example, an oxygen barrier formation film 305A having a thickness of 250 nm is formed. The oxygen barrier formation film 305A is a laminated film made of, for example, titanium aluminum nitride (TiAlN), iridium (Ir), and iridium oxide (IrO _x ) from the bottom.

  Next, by sputtering, a lower electrode having a thickness of about 100 nm is formed on the oxygen barrier forming film 306A from a noble metal such as platinum or iridium or an oxide, nitride or oxynitride having the noble metal conductivity. A film 306A is formed.

  Next, a capacitive insulating film forming film 307A made of, for example, a ferroelectric material and having a thickness of, for example, 40 nm is formed on the lower electrode forming film 306A by MOD method, sputtering method, MOCVD method, or the like.

  Next, an upper electrode formation film 308A having a film thickness of, for example, 60 nm is formed by sputtering under the same film formation conditions as the lower electrode formation film 306A.

  Next, as shown in FIG. 11C, the oxygen barrier formation film 305A, the lower electrode formation film 306A, and the capacitance insulation are performed by lithography and dry etching using a mixed gas of chlorine-based gas and fluorine-based gas. The film forming film 307A and the upper electrode forming film 308A are patterned to form an oxygen barrier film 305, a lower electrode 306, a capacitive insulating film 307, and an upper electrode 308, respectively. As a result, a capacitor element 309 including the lower electrode 306, the capacitor insulating film 307, and the upper electrode 308 is formed.

  In this example, the oxygen barrier film 305, the lower electrode 306, the capacitor insulating film 307, and the upper electrode 308 are etched at once. However, the process of etching the oxygen barrier film 305 and the lower electrode 306, the capacitor insulating film 307, You may divide into the process of etching the upper electrode 308. FIG.

  Next, as shown in FIG. 11D, a CVD method is used to cover the capacitor element 309 on the second interlayer insulating film 303, and the first film having a film thickness of 1.0 μm, for example, made of BPSG. The third interlayer insulating film 310 is formed. Thereafter, the surface of the formed third interlayer insulating film 310 is planarized by CMP. The thickness of the upper portion of the capacitor in the third interlayer insulating film 310 after planarization is preferably 100 nm to 300 nm.

  Subsequently, heat treatment is performed at a high temperature and in an oxygen atmosphere in order to crystallize the capacitor insulating film 307 and improve the film quality. This heat treatment may be annealing using a furnace or RTA. The heating temperature is preferably 600 ° C. or higher and 850 ° C. or lower.

  Thereafter, although not shown, a contact plug made of a laminated film of the third interlayer insulating film 310, the second interlayer insulating film 303 and the first interlayer insulating film 106 is formed to be connected to the other impurity diffusion layer 105. A wiring made of general Al or Cu is formed.

  In the present embodiment, even when the first contact plug 301 is provided at a position different from the center position of the capacitor 309, the second contact plug 304 can be provided at the center of the oxygen barrier film 305. A large distance X between the side surface of the barrier film 305 and the second contact plug 304 can be secured.

  FIG. 9B shows a plan view and dimensions of each part in the present embodiment. Here, in the third embodiment, since the size of the capacitive element 309 is small, the first contact plug 301 is disposed at a position shifted from the center of the oxygen barrier film 305. When the second contact plug 304 is disposed immediately above the first contact plug 301 as in the conventional example, the distance between the side surface of the oxygen barrier film 305 and the contact plug decreases in a certain direction, and the contact yield deteriorates. The distance not to be able to be secured at this point. In contrast, in the present embodiment, the size of the capacitor 309 is kept small by interposing the first conductive film 302B between the first contact plug 301 and the second contact plug 304. Therefore, even if the first contact plug 301 is disposed at a position shifted from the center of the oxygen barrier film 305, the second contact plug 304 can be provided at the center position of the oxygen barrier film 305. The distance between the side surface and the second contact plug 304 can be increased.

In this embodiment, since TiAlN is used for the lowermost layer of the oxygen barrier film 305, there is no problem even if the distance X is reduced to 0.35 μm. The space between the oxygen barrier films 305 is 0.24 μm, the diameter of the second contact plug 304 is 0.16 μm, and the memory cell size is 2.42 μm ² , which is about 41% of the conventional example. Can be reduced.

  In addition, it is preferable that the film thickness on the conductive film in the second interlayer insulating film is smaller than the film thickness of the first interlayer insulating film. In this case, the second contact plug 304 can be easily formed smaller than the first contact plug 301.

  In addition, an insulating hydrogen barrier film is preferably used for the second interlayer insulating film 303. In this case, since the amount of film loss and the amount of erosion at the time of CMP for forming the second contact plug 304 can be reduced, the insulating hydrogen barrier film can be formed thin. Thereby, the second contact plug can be easily made smaller than the first contact plug.

  In addition, the step of forming the first conductive film 302B and the second conductive film 302C is preferably formed together with a bit wiring (capacitor element lower bit line) arranged in a lower layer of the capacitor. Thereby, there is no additional process, and a low-cost semiconductor device can be manufactured.

  The semiconductor device and the manufacturing method thereof according to the present invention can reduce the size of the memory cell while preventing the oxidation of the contact plug under the capacitive element, and in particular, the dielectric of the stack type structure having the capacitive element on the contact plug. The present invention is useful for a semiconductor device including a body memory element and a manufacturing method thereof.

(A) is sectional drawing which shows the structure of the semiconductor device which concerns on the 1st Embodiment of this invention. (B) is a top view which shows the structure of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A) is sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. (B) is a top view which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (A)-(e) is sectional drawing which shows the modification of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (A) is sectional drawing which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. (B) is a top view which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention in process order. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention in process order. (A) is sectional drawing which shows the structure of the conventional semiconductor device. (B) is a top view which shows the structure of the conventional semiconductor device. (C) is a diagram showing the relationship between the overlap between the oxygen barrier film and the contact plug and the contact yield.

Explanation of symbols

101 Semiconductor substrate 102 Shallow trench isolation region 103 Gate insulating film 104 Gate electrode 105 Impurity diffusion layer 106 First interlayer insulating film 107 Third contact plug 108A Bit wiring forming film 108 Bit wiring 109 Second interlayer insulating film 110 First Contact plug 111 Insulating hydrogen barrier film 112A Second contact plug formation film 112 Second contact plug 113A Oxygen barrier formation film 113 Oxygen barrier film 114A Lower electrode formation film 114 Lower electrode 115A Capacitance insulation film formation film 115 Capacitance insulation film 116A Upper electrode formation film 116 Upper electrode 117 Capacitor element 118 Third interlayer insulating film 119 Third contact hole 120 First contact hole 121 Second contact hole 201 First contact plug 02A Conductive film formation film 202B First conductive film 202C Second conductive film 203 Second interlayer insulating film 204A Second contact plug formation film 204 Second contact plug 205A Oxygen barrier formation film 205 Oxygen barrier film 206A Lower electrode Formation film 206 Lower electrode 207A Capacitance insulation film formation film 207 Capacitance insulation film 208A Upper electrode formation film 208 Upper electrode film 209 Capacitor element 210 Third interlayer insulation film 211 Second contact hole 212 Silicon oxide film 213 Insulating hydrogen barrier film 301 First contact plug 302A Conductive film forming film 302B First conductive film 302C Second conductive film 303 Second interlayer insulating film 304 Second contact plug 305A Oxygen barrier forming film 305 Oxygen barrier film 306A Lower electrode forming film 306 Lower electrode 3 7A capacitor insulating film formation film 307 capacitor insulating film 308A forming the upper electrode film 308 upper electrode 309 capacitive element 310 third interlayer insulating film 311 second contact hole

Claims (27)

An interlayer insulating film formed on the semiconductor substrate;
A first contact plug passing through the interlayer insulating film and connected to the semiconductor substrate;
An insulating hydrogen barrier film formed on the interlayer insulating film so as to cover the first contact plug;
A second contact plug penetrating the insulating hydrogen barrier film and connected to the first contact plug;
An oxygen barrier film formed on the insulating hydrogen barrier film so as to be connected to the second contact plug and to cover the second contact plug;
A capacitive element formed on the oxygen barrier film,
The semiconductor device according to claim 1, wherein the second contact plug has a diameter smaller than that of the first contact plug.   The semiconductor device according to claim 1, wherein the insulating hydrogen barrier film is thinner than the interlayer insulating film. A first interlayer insulating film formed on the semiconductor substrate;
A first contact plug penetrating the first interlayer insulating film and connected to the semiconductor substrate;
A conductive film formed on the first interlayer insulating film so as to be connected to the first contact plug;
A second interlayer insulating film formed on the first interlayer insulating film so as to cover the conductive film;
A second contact plug penetrating through the second interlayer insulating film and connected to the conductive film;
An oxygen barrier film formed on the second interlayer insulating film so as to be connected to the second contact plug and to cover the second contact plug;
A capacitive element formed on the oxygen barrier film,
The semiconductor device according to claim 1, wherein the second contact plug has a diameter smaller than that of the first contact plug. A first interlayer insulating film formed on the semiconductor substrate;
A first contact plug passing through the first interlayer insulating film and connected to the semiconductor substrate;
A conductive film formed on the first interlayer insulating film so as to be connected to the first contact plug;
A second interlayer insulating film formed on the first interlayer insulating film so as to cover the conductive film;
A second contact plug penetrating through the second interlayer insulating film and connected to the conductive film;
An oxygen barrier film formed on the second interlayer insulating film so as to be connected to the second contact plug and to cover the second contact plug;
A capacitive element formed on the oxygen barrier film,
The first contact plug is provided at a position different from the center position in the plane of the oxygen barrier film, and the second contact plug is provided at a center position in the plane of the oxygen barrier film. A featured semiconductor device.   The semiconductor device according to claim 4, wherein a diameter of the second contact plug is smaller than a diameter of the first contact plug.   5. The film thickness of the upper part of the conductive film in the second interlayer insulating film is smaller than the film thickness of the upper part of the semiconductor substrate in the first interlayer insulating film. The semiconductor device described.   The semiconductor device according to claim 3, wherein the second interlayer insulating film is an insulating hydrogen barrier film.   The second interlayer insulating film is formed so as to cover the insulating film made of silicon oxide formed in a portion excluding the conductive film in the same layer as the conductive film, and the conductive film and the insulating film 5. The semiconductor device according to claim 3, comprising an insulating hydrogen barrier film.   The semiconductor device according to claim 1, wherein the insulating hydrogen barrier film is made of titanium aluminum oxide or a silicon nitride film.   6. The semiconductor device according to claim 1, wherein an aspect ratio value of the second contact plug is 1 or less.   5. The semiconductor device according to claim 3, wherein the conductive film is formed of the same film as a bit line disposed below the capacitive element.   5. The capacitive element according to claim 1, wherein the capacitive element includes a lower electrode, a capacitive insulating film formed on the lower electrode, and an upper electrode formed on the capacitive insulating film. 2. The semiconductor device according to claim 1.   The semiconductor device according to claim 12, wherein the capacitive insulating film is made of a ferroelectric. Forming an interlayer insulating film on the semiconductor substrate (a);
Forming a first contact plug penetrating the interlayer insulating film and connected to the semiconductor substrate;
(C) forming an insulating hydrogen barrier film on the interlayer insulating film so as to cover the first contact plug;
Forming a second contact plug penetrating the insulating hydrogen barrier film and connected to the first contact plug;
Forming an oxygen barrier film on the insulating hydrogen barrier film so as to connect to the second contact plug and cover the second contact plug;
A step (f) of forming a lower electrode, a capacitive insulating film and an upper electrode in order from the lower layer on the oxygen barrier film, and forming a capacitive element from the lower electrode, the capacitive insulating film and the upper electrode;
In the step (d), the diameter of the second contact plug is formed smaller than the diameter of the first contact plug.   15. The method of manufacturing a semiconductor device according to claim 14, wherein in the step (c), the insulating hydrogen barrier film is formed thinner than the interlayer insulating film. Forming a first interlayer insulating film on the semiconductor substrate (a);
Forming a first contact plug penetrating through the first interlayer insulating film and connected to the semiconductor substrate;
Forming a conductive film on the first interlayer insulating film so as to connect to the first contact plug and cover the first contact plug;
Forming a second interlayer insulating film on the first interlayer insulating film so as to cover the conductive film (d);
Forming a second contact plug penetrating the second interlayer insulating film and connected to the conductive film;
Forming an oxygen barrier film on the second interlayer insulating film so as to be connected to the second contact plug and cover the second contact plug;
A step (g) of forming a lower electrode, a capacitive insulating film and an upper electrode in order from the lower layer on the oxygen barrier film, and forming a capacitive element from the lower electrode, the capacitive insulating film and the upper electrode;
In the step (e), the diameter of the second contact plug is formed smaller than the diameter of the first contact plug.   In the step (d), the film thickness of the upper part of the conductive film in the second interlayer insulating film is formed thinner than the film thickness of the upper part of the semiconductor substrate in the first interlayer insulating film. A method for manufacturing a semiconductor device according to claim 16. The step (d)
Forming an insulating film made of silicon oxide on the conductive film, and then polishing the insulating film using a chemical mechanical polishing method until the conductive film is exposed to planarize the insulating film;
The method for manufacturing a semiconductor device according to claim 16, further comprising: forming an insulating hydrogen barrier film on the insulating film including the conductive film.   The method for manufacturing a semiconductor device according to claim 16, wherein in the step (c), a bit line disposed below the capacitor element is formed together with the conductive film. Forming a first interlayer insulating film on the semiconductor substrate (a);
Forming a first contact plug penetrating through the first interlayer insulating film and connected to the semiconductor substrate;
Forming a conductive film on the first interlayer insulating film so as to connect to the first contact plug and cover the first contact plug;
Forming a second interlayer insulating film on the first interlayer insulating film so as to cover the conductive film (d);
Forming a second contact plug penetrating the second interlayer insulating film and connected to the conductive film;
Forming an oxygen barrier film on the second interlayer insulating film so as to connect to the second contact plug and cover the second contact plug;
A step (g) of forming a lower electrode, a capacitive insulating film and an upper electrode in order from the lower layer on the oxygen barrier film, and forming a capacitive element from the lower electrode, the capacitive insulating film and the upper electrode;
In the step (f), the first contact plug is disposed at a position different from the center position in the plane of the oxygen barrier film, and the second contact plug is disposed at a center position in the plane of the oxygen barrier film. As described above, a method of manufacturing a semiconductor device, wherein the oxygen barrier film is formed.   21. The method of manufacturing a semiconductor device according to claim 20, wherein in the step (e), the diameter of the second contact plug is smaller than the diameter of the first contact plug.   In the step (d), the film thickness of the upper part of the conductive film in the second interlayer insulating film is formed thinner than the film thickness of the upper part of the semiconductor substrate in the first interlayer insulating film. A method for manufacturing a semiconductor device according to claim 20. The step (d)
Forming an insulating film made of silicon oxide on the conductive film, and then polishing the insulating film using a chemical mechanical polishing method until the conductive film is exposed to planarize the insulating film;
The method for manufacturing a semiconductor device according to claim 20, further comprising: forming an insulating hydrogen barrier film on the insulating film including the conductive film.   21. The method of manufacturing a semiconductor device according to claim 20, wherein in the step (c), a bit line disposed below the capacitor element is formed together with the conductive film.   21. The method of manufacturing a semiconductor device according to claim 16, wherein the second interlayer insulating film is formed of an insulating hydrogen barrier film.   26. The method of manufacturing a semiconductor device according to claim 14, wherein the insulating hydrogen barrier film is a titanium aluminum oxide film or a silicon nitride film.   21. The method of manufacturing a semiconductor device according to claim 14, wherein an aspect ratio value of the second contact plug is 1 or less.

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