JP2010141005A - Method of designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of designing a semiconductor integrated circuit increasing the degree of freedom in design change after arranging and interconnecting of the semiconductor integrated circuit to improve performance. <P>SOLUTION: The method includes an arranging and interconnecting step S1 of arranging and interconnecting a standard cell, a timing analysis step S2 of performing timing analysis on arranging and interconnecting data obtained at the standard cell arranging and interconnecting step S1, a gate array cell insertion step S3 of inserting a gate array cell into a path including a violation on the arranging and interconnecting data based on a result obtained at the timing analysis step S2, replacement standard cell extracting steps (S5-S8) of extracting a replacement standard cell which is logically equivalent to the gate array cell from the arranging and interconnecting data when another violation occurs in the violation-including path by inserting the gate array cell, and a standard cell replacing step S9 of replacing the gate array cell with the replacement standard cell due to design change of a wiring layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to a method for designing a semiconductor integrated circuit in which performance is improved by changing the design of a wiring layer after placement and routing of a standard cell.

  In recent years, with the increase in scale of semiconductor integrated circuits and the complexity of design constraints, an increase in design development period has become a problem. For this reason, various design changes have been developed to shorten the design period.

  As a design method for shortening the design period, a semiconductor integrated circuit design method is disclosed in which a physical design change of a transistor layer is performed after placement and routing of a standard cell (see, for example, Patent Document 1). According to this design method, there is no need to change the placement and routing, and the design period can be shortened. However, on the other hand, the degree of freedom of design change is low, and performance improvement may not be achieved.

Also, as a design method to shorten the design period that is generally used, when it is judged that a certain performance improvement can be achieved at the time of standard cell placement and routing, and further performance improvement can be achieved only by changing the wiring layer There is a method in which the design of the transistor layer is finished and the final desired performance improvement is achieved only by changing the design of the wiring layer. Thereby, the mask can be manufactured based on the design data of the transistor layer simultaneously with the design change of the wiring layer, so that the design efficiency can be improved. Performance improvement by changing the design of the wiring layer is usually performed by inserting a gate array cell in a path between standard cells. However, with this method, only the gate array cell is used to change the design of the wiring layer. Therefore, the design flexibility is low, and the desired performance improvement cannot be achieved when the gate array cell cannot be placed near the path where the performance improvement is required. There is. As described above, when the performance improvement cannot be realized only by the design change of the wiring layer, the design change of the transistor layer is also required, and a large design change is required.
JP 2004-86763 A.

  Accordingly, an object of the present invention is to provide a method for designing a semiconductor integrated circuit that improves the degree of freedom of design change after the placement and wiring of the semiconductor integrated circuit and improves the performance.

  According to one aspect of the present invention, there is provided a semiconductor integrated circuit design method including a placement and routing process for placing and routing standard cells, and a first timing analysis for performing timing analysis on placement and routing data obtained by the standard cell placement and routing process. And a gate array cell insertion step of inserting a gate array cell into a path including a violation on the placement and routing data based on a result of the first timing analysis step, and the violation by inserting the gate array cell A replacement standard cell extracting step of extracting a replacement standard cell logically equivalent to the gate array cell from the placement and routing data when another violation occurs in the path including the gate array cell, and the replacement A standard cell replacement step of replacing the standard cell by changing the design of the wiring layer.

  ADVANTAGE OF THE INVENTION According to this invention, the design method of the semiconductor integrated circuit which raises the freedom degree of the design change after the arrangement | positioning wiring of a semiconductor integrated circuit, and aims at a performance improvement can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment)
According to the embodiment of the present invention, when there is a path including a timing violation (for example, a hold time violation path) in the layout information after the placement and routing of the standard cell, a design method for converging this timing violation by changing the design of the wiring layer About.

  An embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a design flowchart of a method for designing a semiconductor integrated circuit according to an embodiment of the invention. FIG. 2 schematically shows the layout of the standard cell and the gate array cell after placement and routing. A square (for example, reference numerals 1 and 5) in FIG. 2 schematically shows a standard cell or a gate array cell. Further, arrows (for example, reference numerals 3 and 23) in FIG. 2 schematically indicate paths between standard cells or between standard cells and gate array cells.

  Hereinafter, a design method for converging a hold time violation when there is a hold time violation path in the placement and routing data 10 after the placement and routing of the standard cell will be described with reference to FIG.

  The hold time is the minimum time that the input signal to the standard cell must be held after the change of the clock signal when the standard cell is synchronized with the clock signal. The hold time violation means that the input signal to the standard cell changes in a time shorter than the hold time.

  The setup time, which will be described later, is the minimum time that the input signal to the standard cell must be held before the clock signal changes when the standard cell is synchronized with the clock signal. The setup time violation means that the input signal to the standard cell changes in a time shorter than the setup time.

  In the standard cell placement and routing step S1, the placement and routing data 10 is obtained by placing standard cells and wiring between standard cells. Redundant gate array cells are arranged in the space between standard cells. By inserting this redundant gate array cell into a path between standard cells arranged and wired, it can be used to change the logic of the semiconductor integrated circuit.

  In the static timing analysis step S2, static timing analysis is performed on the placement and routing data 10. Thereby, a timing violation path on the placement and routing data 10 is extracted. As a result of the static timing analysis, for example, a hold time violation path 3 including a hold time violation is extracted from the placement and routing data 10 (FIG. 2A). Here, the hold time violation path 3 is a path between the standard cell 1 and the standard cell 2, and it is assumed that a hold time violation occurs in the standard cell 2. The hold time violation can be converged by inserting a gate array cell such as a delay cell in the hold time violation path.

  In the gate array cell insertion step S3, first, the gate array cell 5 (for example, delay cell) arranged on the placement and routing data 10 is extracted. Next, the gate array cell 5 is inserted into the path 3 between the standard cell 1 and the standard cell 2 so that the hold time violation in the standard cell 2 is converged. Thereby, the placement and routing data 10 is changed to the placement and routing data 20 (FIG. 2B). Also, the gate array cell name 50 of the gate array cell 5 inserted at this time is held by the gate array cell name holding step S11.

  Next, in the static timing analysis step S4, static timing analysis is performed on the placement and routing data 20 that has been changed by inserting the gate array cell 5 into the path 3. As a result of the static timing analysis, when the hold time violation and setup time violation of path 3 have converged, the design is completed. As a result of static timing analysis, although the hold time violation of path 3 has converged by inserting the gate array cell 5, conversely, when the setup time violation has occurred, the setup time violation is converged by the following steps. Plan. As a case where the setup time violation occurs due to the insertion of the gate array cell, for example, the gate array cell 5 cannot be arranged in the vicinity of the path 3 including the timing violation. In this case, since the wiring length of the path 3 becomes long in order to insert the gate array cell 5, a setup time violation may occur.

  The next replacement standard cell extraction step includes replacement standard cell candidate extraction step S5, timing analysis step S6, replacement standard cell candidate information extraction step S7, and replacement standard cell candidate narrowing-down step S8. By this step, the extracted replacement standard cell is replaced with the gate array cell 5 to converge the setup time violation of the path 3.

  First, in the replacement standard cell candidate extraction step S5, the gate array cell name 50 of the gate array cell 5 held in the gate array cell name holding step S11 is referred to and a standard cell equivalent in logic to the gate array cell 5 is arranged. Extracted from the wiring data 20. The extracted standard cell becomes a replacement standard cell candidate. At this time, distance information from the path 3 of each replacement standard cell candidate is also extracted.

  Next, in a timing analysis step S6, static timing analysis is performed on the placement and routing data 20, and information on timing margins of replacement standard cell candidates is extracted. The timing margin refers to the setup time and hold time margin for the replacement standard cell candidate.

  Next, in the replacement standard cell candidate information extraction step S7, based on the result of the replacement standard cell candidate extraction step S5 and the timing analysis S6, the distance information of the replacement standard cell candidate from the path 3, and the timing margin A candidate list 51 having information is generated. FIG. 4 shows an example of the candidate list 51. As shown in FIG. 4, the candidate list 51 includes information on timing margins (setup time and hold time) of each replacement standard cell candidate and information on the distance from the violation path 3.

  Next, in the replacement standard cell candidate narrowing-down step S8, one replacement standard cell optimum for replacement is narrowed down from the candidate list 51. In the replacement standard cell candidate narrowing step S <b> 8, first, replacement standard cell candidates that satisfy the timing margin set from the candidate list 51 are extracted. For this reason, the size of the timing margin does not matter for replacement standard cell candidates that satisfy the set timing margin. Next, a replacement standard cell candidate having a timing margin is ranked in order from the closest (neighboring) distance from the path 3. This rank is set as the candidate rank of the replacement standard cell candidate, and the replacement standard cell candidate having the highest candidate rank (the replacement standard cell candidate having the shortest distance from the path 3) is set as the optimum replacement standard cell. The distance from the path 3 is defined by the distance of the path 3 when the replacement standard cell candidate is inserted into the path 3. That is, in FIG. 2, when the standard cell 1 and the standard cell 2 are inserted in the path 3, the replacement standard cell candidate inserted from the standard cell 1 and the replacement standard cell candidate to be inserted from the standard cell 1 to the standard cell 2 are inserted. Given by the sum of distances. Here, for example, it is assumed that the standard cell 25 is extracted as the replacement standard cell. The standard cell 25 is a standard cell inserted in a path 23 between the standard cell 21 and the standard cell 22.

  Next, in the standard cell replacement step S9, the replacement standard cell 25 narrowed down in the replacement standard cell candidate narrowing step S8 and the gate array cell 5 inserted in the gate array cell insertion step S3 are changed by changing the design of the wiring layer. Replace. As a result, the standard cell 25 is inserted into the path 3 between the standard cell 1 and the standard cell 2 (FIG. 2C). further. The gate array cell 5 is inserted into the path 23 between the standard cell 21 and the standard cell 22 (FIG. 2 (d)). The placement and routing data 20 is changed to the placement and routing data 30 by the standard cell replacement step S9 (FIGS. 2 (c) and 2 (d). Note that the placement and routing data 30 is shown in FIG. 2) and FIG. 2D focusing on the path 23, FIG. 2C and FIG. 2D schematically show the same placement and routing data 30. FIG.

  Next, in the static timing analysis S10, static timing analysis is performed on the placement and routing data 30 in which the standard cell 25 and the gate array cell 5 are replaced. According to the static timing analysis, the timing violation of the path 3 between the standard cell 1 and the standard cell 2 in which the standard cell 25 is inserted and the path 23 between the standard cell 21 and the standard cell 22 in which the gate array cell 5 is inserted. Judgment. As a result of the timing analysis, when the hold time violation and the setup time violation of the path 3 and the path 23 have converged, the design ends. As a result of the timing analysis, if a hold time violation or a setup time violation has occurred in either path 3 or path 23, the process returns to the replacement standard cell candidate narrowing step S8.

  In the replacement standard cell candidate narrowing-down step S8, the standard cell having the next replacement order in the candidate list 51 is selected and set as the replacement standard cell. For example, it is assumed that the standard cell 35 is extracted as the next standard cell. The standard cell 35 is a standard cell inserted in a path 33 between the standard cell 31 and the standard cell 32 (FIG. 3A).

  Next, in the standard cell replacement process S9, the standard cell 35 and the gate array cell 5 are replaced by a design change of the placement and routing, thereby converging timing violations. As a result, the standard cell 35 is inserted into the path 3 between the standard cell 1 and the standard cell 2 (FIG. 3B). Further, the gate array cell 5 is inserted into the path 33 between the standard cell 31 and the standard cell 32 (FIG. 3C). Thereby, the placement and routing data 30 is changed to become placement and routing data 40 (FIGS. 3B and 3C). FIG. 3C focusing on 33 is shown separately, but FIG. 3B and FIG. 3C schematically show the same placement and routing data 40.

  Next, in the static timing analysis S10, a static timing analysis is performed on the placement and routing data 40, and a timing violation of the path 3 and the path 33 is determined. As a result of the timing analysis, when the hold time violation and the setup time violation of the path 3 and the path 33 have converged, the design ends. As a result of the timing analysis, if a hold time violation or a setup time violation has occurred in any of the path 3 and the path 33, the process returns to the replacement standard cell candidate narrowing step S8 and the same operation is repeated. This process is performed until the timing violation of the path including the path 3 and the replacement standard cell converges.

  According to the embodiment of the present invention, when there is a hold time violation in the placement and routing data after the placement and routing, the hold layer violation is first converged by using the gate array cell by changing the design of the wiring layer. When a setup time violation occurs by using an array cell, the standard cell is used to converge the setup time violation. Thus, in this embodiment, since the standard cell is used for the design change of the wiring layer, it is possible to improve the performance by increasing the degree of freedom of the design change and converging the setup time violation and the hold time violation.

  The semiconductor integrated circuit design method described above can be executed as a program prepared in advance by a computer such as a personal computer or a workstation. This program is stored in various storage media and executed by being read from the storage media by a computer. The program may be a transmission medium that can be distributed through a network such as the Internet.

  The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.

3 is a design flowchart of a method for designing a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a layout showing standard cells, gate array cells, and paths after placement and routing of the semiconductor integrated circuit according to the embodiment of the present invention. FIG. 3 is a schematic diagram of a layout showing standard cells, gate array cells, and paths after placement and routing of the semiconductor integrated circuit according to the embodiment of the present invention. It is explanatory drawing which showed the candidate list | wrist of the replacement standard cell candidate which concerns on embodiment of this invention.

Explanation of symbols

10, 20, 30 Placement and routing data 1, 2, 21, 22, 25, 31, 32, 35 Standard cell 3, 23, 33 Pass 5 Gate array cell 50 Gate array cell name 51 Candidate list S1 Standard cell placement and routing step S3 Gate array cell insertion step S2, S4, S6, S10 Static timing analysis step S5 Replacement standard cell candidate extraction step S7 Replacement standard cell candidate information extraction step S8 Replacement standard cell candidate narrowing step S9 Standard cell replacement step S11 Gate array cell Name retention process

Claims (5)

Place and route process to place and route standard cells;
A first timing analysis step for performing timing analysis on the placement and routing data obtained by the standard cell placement and routing step;
Based on the result of the first timing analysis step, a gate array cell insertion step of inserting a gate array cell into a path including a violation on the placement and routing data;
Replacement standard cell extraction for extracting a replacement standard cell logically equivalent to the gate array cell from the placement and routing data when another violation occurs in the path including the violation by inserting the gate array cell Process,
A method for designing a semiconductor integrated circuit, comprising: the gate array cell; and a standard cell replacement step of replacing the replacement standard cell by a design change of a wiring layer. A second timing analysis step for performing timing analysis on the placement and routing data changed by the standard cell replacement step after the standard cell replacement step;
As a result of the second timing analysis step, if a timing violation has occurred in at least one of the paths where the replacement standard cell and the gate array cell are replaced, a standard cell different from the replacement standard cell is selected. 2. The method of designing a semiconductor integrated circuit according to claim 1, wherein the gate array cell is extracted as a replacement standard cell and replaced by a design change of a wiring layer.   3. The method of designing a semiconductor integrated circuit according to claim 1, wherein the replacement standard cell is in the vicinity of the path including the violation, and the inserted path has a timing margin. The replacement standard cell extraction step includes:
A replacement standard cell candidate extracting step of extracting a standard cell logically equivalent to the gate array cell as a replacement standard cell candidate;
A third timing analysis step of extracting timing margin information of paths including replacement standard cell candidates by performing timing analysis on the placement and routing data;
5. A replacement standard cell candidate narrowing-down step for extracting an optimal replacement standard cell based on the information obtained by the replacement standard cell candidate extraction step and the information obtained by the third timing analysis step. The method for designing a semiconductor integrated circuit according to any one of claims 1 to 3. The process of narrowing down the replacement standard cell candidates is as follows:
Extracting a replacement standard cell candidate satisfying a predetermined timing margin from the result of the third timing analysis; extracting a replacement standard cell candidate closest to the path including the violation from the replacement standard cell candidate; 5. The method of designing a semiconductor integrated circuit according to claim 4, wherein an optimum replacement standard cell is extracted by the following.

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