JP2010140130A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device excluding, before arbitration, an access request to be restrained upon an exclusive process, and of quickly determining an access request that should be accepted by arbitration. <P>SOLUTION: Address information or the like that is the subject of exclusive access is held in an exclusive information buffer (81) and address information that initiators (60, 61, 62) output is compared with the address information held. In this way, a pinpoint exclusive process targeting the address that is the subject of the exclusive address is achieved. Prior to an arbitration process, exclusion of an access request upon an exclusive process is carried out. Thus, the access request that should be restrained upon the exclusive process is prevented from undergoing an arbitration process, and the time from when the initiator makes an access request until the access request is accepted is reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to exclusive processing of access to a shared resource in a bus interface, and uses, for example, a microcomputer integrated in a semiconductor integrated circuit, a data processing device in a system-on-chip (SOC), a chipset, and a multichip. The present invention relates to a technology that is effective when applied to a packet-switched bus interface by split transaction in a semiconductor device such as a system-in-package data processing module.

  The bus interface includes a packet exchange method using a split transaction in addition to an interlock method in which other requests are not accepted during a bus access request. In this method, a circuit that requests access transmits a request packet including the contents of the access request to a circuit that responds to the access request, and the circuit that responds to the access request requests a response packet including the response contents. The process of transmitting to the circuit is performed. A series of processing including a request packet and a response packet is referred to as a transaction, and one transaction is separated for each packet transfer, thereby improving the bus access efficiency. A circuit that requests access is called an initiator, and a circuit that answers the access request is called a target. Some types of circuits have both initiator and target functions. The initiator and target have a packet router that relays request packets and response packets. The packet router performs arbitration when a plurality of initiators request access to one target, and performs control to invalidate subsequent access requests for exclusive control of shared resources. When exclusive processing is performed in units of resources, a protocol has been adopted in which during the exclusive processing, an initiator other than the initiator that received the exclusive processing request is prevented from accessing the target that is the exclusive access execution target. That's right. For example, if the target is a memory controller, all other initiator accesses to the memory are inhibited during the exclusion process.

  Japanese Patent Application Laid-Open No. 2004-228561 describes an exclusive processing for access to a shared resource in a multi-CPU system. According to this, instead of exclusive control for each CPU, when the CPU requests exclusive processing, control is performed to exclude an access request from another CPU for the access target area of the CPU.

JP-A-5-225117

  In the multi-core SOC (SOC in which a plurality of CPUs are mounted on one chip) which is expected to spread in the future, exclusive processing is used more frequently than in the case of a single-core SOC (SOC in which a single CPU is mounted on one chip). Therefore, in the exclusive processing of the target unit, it is considered that the reduction of the exclusive processing unit is necessary because the transfer performance (bus access performance) is greatly reduced due to the exclusive processing. In Patent Document 1, this point is taken into consideration, and exclusive control is performed in units of address areas.

  However, in the technique described in Patent Document 1, a permission candidate signal is first generated in the bus arbitration unit based on the priority and the access request competition state with respect to the access request, and address information related to the access request of the permission candidate is selected. Control is performed to determine whether the selected address information overlaps the address area of the exclusive control target that has been accepted earlier, and if so, the bus use non-permission is returned to the CPU that is the first permission candidate. I do. In short, it becomes clear after the arbitration process whether the access request should be suppressed by the exclusion process. For this reason, with the technique described in Patent Document 1, the access request that should be suppressed along with the exclusion process cannot be eliminated before arbitration, and the access request that should be accepted by arbitration cannot be determined quickly. For this reason, the processing efficiency with respect to the access request is low, and this results in hindering the speeding up of data processing.

  In addition, in the packet-switched bus interface using split transactions, the initiator simply waits even when an access request involving an exclusive process is temporarily suppressed. However, when the technique described in Patent Document 1 is applied thereto. Assuming that, an initiator such as a CPU that does not accept an access request will be returned with a bus non-permission signal, and the initiator will not simply wait, but will need to perform a process such as making an access request again, Initiator implementation is more complicated than usual.

  An object of the present invention is to provide a semiconductor device that can eliminate an access request to be suppressed along with exclusion processing before arbitration, and can quickly determine an access request to be accepted by arbitration. .

  Another object of the present invention is to provide a semiconductor device that has high processing efficiency with respect to access requests and can contribute to speeding up of data processing in this respect.

  Still another object of the present invention is to provide a semiconductor device in which the initiator can simply wait and the initiator can be easily mounted even when an access request involving an exclusive process is temporarily suppressed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the address information to be exclusively accessed is stored, and the address information output from the initiator is compared with the stored address information. This realizes pinpoint exclusion processing for the address that is the target of exclusive access.

  Prior to the arbitration process, the access request associated with the exclusion process is eliminated. For this reason, it is possible to prevent an access request that should be suppressed along with the exclusion process from being arbitrated, and to shorten the time from when the initiator makes an access request until the access request is accepted.

  In the present invention, the exclusive processing circuit is mounted on all of the plurality of packet routers constituting the hierarchical interconnect. As a result, it is possible to perform exclusive processing at the pinpoint without causing a hang-up (falling into a state where the access request cannot be processed), and access that is not suppressed by the exclusive processing along with this pinpoint exclusive processing. The request is not suppressed until the completion of the access request that requires exclusive processing.

  Further, according to the present invention, an interrupt is generated upon detecting that an unauthorized access is made to an exclusive access. This facilitates software and hardware debugging.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the access request that should be suppressed along with the exclusion process can be eliminated before the arbitration, and the access request that should be accepted by the arbitration can be determined quickly.

  The processing efficiency for the access request is high, and in this respect, it can contribute to speeding up of data processing.

  Even when an access request involving exclusive processing is temporarily suppressed, the initiator can simply wait and the initiator can be easily implemented.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] << Exclusive control by address comparison >>
A semiconductor device according to the present invention responds to an access request with a plurality of initiators capable of requesting access, a plurality of targets capable of responding to access, and a request packet provided from the initiator requesting access. A request resource that performs control given to the target, and a packet router that includes a response resource that performs control to return a response packet given from the target responding to the access request to the initiator of the access request source. The request resource (80) of the packet router includes an exclusive information buffer (81), comparison circuits (90, 91, 92), an access request invalidation circuit (100, 101, 102), and an arbitration circuit (80). The exclusive information buffer holds exclusive information indicating that there is an exclusive processing request from the request source and access information included in the request packet when a request packet (REQPCKT) including an exclusive processing request is received. The comparison circuit compares the information stored in the exclusive information buffer with the access information included in the request packet given from the initiator, and outputs the comparison result. The access request invalidation circuit invalidates an access request that is different from the accepted access request accompanied by the exclusive processing request by maximizing the range in which the access target addresses overlap based on the comparison result by the comparison circuit. The arbitration circuit inputs the access request validated by the access request invalidation circuit, arbitrates for the conflicting access request, accepts one access request, and requests corresponding to the accepted access request Performs control to give packets to the target.

  According to the above, access information such as address information subject to exclusive access is held, the access information output by the initiator is compared with the held access information, and the range where the access target addresses overlap is maximized. Since the access request is invalidated, pinpoint exclusive processing for an address finer than the target unit can be realized.

  Prior to the processing of the arbitration circuit, selective invalidation processing for an access request accompanied by an exclusive processing request is performed, so that an access request that should be suppressed by exclusive control is targeted for arbitration processing by the arbitration circuit. However, this point contributes to shortening the time from when the initiator makes an access request until the access request is accepted.

[2] << Grant signal processing by arbitration circuit >>
In the semiconductor device of Item 1, for example, when the arbitration circuit outputs a grant signal (GNT) for each initiator and an access request is input from the initiator, the access request is validated by the access request invalidation circuit. And when an access request from the initiator is accepted by arbitration, the grant signal is asserted, and the access request is invalidated by the access request invalidation circuit, or an access request from the initiator by arbitration Is not asserted, the grant signal is deasserted.

  Regardless of the invalidation of the access request, the arbitration circuit asserts the grant signal only when the access request from the initiator is accepted, so that the initiator that receives this asserts whether it has been accepted or invalidated after the access request. Without waiting for the grant signal to be asserted.

  Therefore, in the packet-switched bus interface by split transaction, even if an access request accompanied by an exclusive process is temporarily suppressed, the initiator only has to wait, and there is no need for a process such as making an access request again. Even if the invalidation is adopted, the initiator can be easily implemented.

[3] << Understanding grant signal by initiator >>
In the semiconductor device according to Item 2, for example, when the initiator requests access, the initiator determines that the access request is not accepted because the input grant signal is in the deasserted state, and the input grant signal is in the asserted state. Therefore, it is determined that the access request has been accepted.

[4] << Exclusive control by address comparison >>
In the semiconductor device according to item 1, the access information held by the exclusive information buffer is, for example, access target address information. In this case, the access request invalidation circuit is accepted by maximizing a range where the access target addresses overlap. A new access request from an initiator different from the access request accompanying the exclusive processing request is invalidated (FIG. 5).

[5] << Exclusive control by process ID comparison >>
In the semiconductor device according to Item 1, the access information held by the exclusive information buffer is, for example, access target address information and process ID information of a process using the access target address information. In this case, the access request invalidation circuit includes: An access request having a process ID different from that of an access request accompanied by an accepted exclusive processing request is invalidated by maximizing a range in which the access target addresses overlap. For exclusive access requests by the same initiator, it is possible to deal with invalidation of access requests in consideration of the process ID.

[6] << Number of entries in exclusive information buffer >>
6. The semiconductor device according to item 5, wherein the exclusive information buffer has a storage capacity capable of storing access information for each access request accompanied by an exclusive processing request that can be received in parallel by the arbitration circuit. In short, the access information held by the exclusive information buffer includes, for example, access target address information and process ID information of a process using the access target address information. In this case, the access request invalidation circuit invalidates an access request having a process ID different from that of an access request accompanied by an accepted exclusive processing request, while maximizing a range where the access target addresses overlap. Even when one initiator requests access with a plurality of exclusive processing requests and is accepted in parallel, invalidation of the access request can be dealt with.

[7] << Exclusive control by address information and byte enable comparison >>
In the semiconductor device according to Item 1, the access information held by the exclusive information buffer includes, for example, access target address information indicating a head of a plurality of bytes to be accessed, and a byte indicating the validity within a plurality of bytes of the access target range in bytes. This is enable information (BE). At this time, the access request invalidation circuit is accepted by maximizing the range that overlaps the valid address in the byte enable information within the access target range of multiple bytes starting from the address of the access target address information. The access request different from the access request with the exclusive processing request is invalidated. This makes it possible to cope with invalidation of the access request even when the access address is specified by the head address and byte enable (FIG. 6).

[8] << Exclusive control by process ID comparison >>
In the semiconductor device according to Item 1, the access information held by the exclusive information buffer includes, for example, access target address information indicating a head of a plurality of bytes to be accessed and validity within a plurality of bytes to be accessed in bytes. This is process ID information of a process using byte enable information and address information to be accessed. At this time, the access request invalidation circuit is accepted by maximizing the range that overlaps the valid address in the byte enable information within the access target range of multiple bytes starting from the address of the access target address information. An access request having a process ID different from that of the access request accompanied by the exclusive processing request is invalidated. As a result, it is possible to deal with invalidation of the access request in consideration of the case where the access address is specified by the head address and byte enable, and in consideration of the process ID for the exclusive access request by the same initiator.

[9] << Number of entries in exclusive information buffer >>
In the semiconductor device of Item 8, the exclusive information buffer has a storage capacity capable of storing access information for each access request accompanied by an exclusive processing request that can be received in parallel by the arbitration circuit. In short, the access information held by the exclusive information buffer includes, for example, a head address to be accessed, byte enable information, and process ID information of a process related to the access request. In this case, the access request invalidation circuit invalidates an access request having a process ID different from that of an access request accompanied by an accepted exclusive processing request, while maximizing a range where the access target addresses overlap. Even when one initiator requests access to a plurality of exclusive processes and is accepted in parallel, invalidation of the access request can be dealt with.

[10] << Exclusive control register >>
The semiconductor device according to Item 1 further includes an exclusive control register (27) that holds an attribute of access to be subjected to exclusive control. The access request invalidation circuit, based on the comparison result by the comparison circuit and the access attribute information held in the exclusive control register, accepts an exclusive processing request that has been accepted with a maximum range of overlapping addresses to be accessed. An access request different from the accompanying access request is invalidated. It becomes possible to set the access request invalidation condition in the exclusive control register in a programmable manner (FIG. 7).

[11] << Access attribute set in exclusive control register >>
In the semiconductor device of item 10, for example, an access direction is set in the exclusive control register as an access attribute. The access request invalidation circuit, based on the comparison result by the comparison circuit and the access attribute information held in the exclusive control register, accepts an exclusive processing request that has been accepted with a maximum range of overlapping addresses to be accessed. Unlike the accompanying access request, the access request in the access direction set in the exclusive control register is invalidated. An access request can be invalidated for a specific access direction.

[12] << Access attribute set in exclusive control register >>
In the semiconductor device of Item 10, for example, identification information of an initiator is set in the exclusive control register as an access attribute. The access request invalidation circuit, based on the comparison result by the comparison circuit and the access attribute information held in the exclusive control register, accepts an exclusive processing request that has been accepted with a maximum range of overlapping addresses to be accessed. Different from the accompanying access request, the access request from the initiator set in the exclusive control register is invalidated. An access request can be invalidated only for a specific initiator.

[13] << Debugging support for accesses competing for exclusive processing >>
The semiconductor device according to Item 1 includes a plurality of CPUs that can function as the initiator, a memory that can function as the target, and an interrupt controller. The memory is a shared memory of the plurality of CPUs. When the packet router receives a request packet accompanied by an exclusive processing request for the shared memory from one CPU, the access request accompanied by the accepted exclusive processing request is within a range overlapping with the access target address. The interrupt controller is notified that there is a different write access request. It is possible to notify a device for debugging support through an interrupt that there has been a write access competing for exclusive processing by the CPU.

[14] << Debugging support for accesses competing for exclusive processing >>
The semiconductor device according to Item 1 includes a memory that can function as the target and an interrupt controller. The memory is a shared memory of a plurality of initiators. When the packet router receives a request packet accompanied by an exclusive processing request for the shared memory from a single initiator, the write access is different from the accepted access request accompanied by the exclusive processing request within a range overlapping with the access target address. Notify the interrupt controller that there has been a request. It is possible to notify a device for debugging support through an interrupt that there has been a write access competing for exclusive processing by one initiator.

[15] << Combination of exclusive control for each target unit >>
A semiconductor device according to another aspect responds to an access request with a plurality of initiators capable of requesting access, a plurality of targets capable of responding to access, and a request packet provided from the initiator requesting access. A first request resource (131) and a second request resource (132) for performing control given to the target, and a response resource for performing control to return a response packet given from the target responding to the access request to the initiator of the access request source A packet router. Only request packets directed to a specific target are distributed to the first request resource. Request packets for a plurality of other targets are distributed to the second request resource. The first and second request resources, when receiving a request packet including an exclusive processing request, exclusive information indicating that there is an exclusive processing request from the request source and exclusive information that holds access information included in the request packet An information buffer, a comparison circuit that compares the information stored in the exclusive information buffer with access information included in a request packet given from the initiator, and outputs the comparison result, and based on the comparison result by the comparison circuit The access request invalidation circuit for invalidating the access request different from the access request accompanied by the accepted exclusive processing request and the access request invalidation circuit is made effective by maximizing the range where the access target addresses overlap. Enter an access request and arbitrate for conflicting access requests It accepts one access request has a arbitration circuitry for controlling to provide targeting request packets corresponding to the received access request.

  Since only request packets targeted for a specific target are distributed to the first request resource, address comparison is not required for exclusive control in units of targets, and other initiators are issued for the target. It may be determined whether or not the exclusive processing request has already been accepted.

[16] << Exclusive processing of layered router >>
A semiconductor device according to another aspect provides a plurality of initiators capable of requesting access, a plurality of targets capable of responding to access, and a request packet provided from the initiator to a target responding to the access request A plurality of packet routers including a request resource for performing control and a response resource for performing control to return a response packet given from a target responding to the access request to the initiator of the access request source. When the plurality of packet routers are connected in series in a plurality of layers via a relay circuit, the request resource of each packet router accepts an exclusive processing request accompanying an access request for a required target from the initiator. (FIG. 10).

  If the packet router upstream of the access request (closer to the initiator) does not have an exclusive processing mechanism among multiple packet routers that make up the hierarchical interconnect, exclusive processing from one initiator connected to the upstream packet router A hang-up occurs when another initiator connected to the packet router at the same layer transmits an access request to the same address as the access request following the access accompanied by the request. This is because when the relay circuit (queuing buffer) between the packet routers sends the request packet of the one initiator to the packet router, the lower layer packet router suppresses the access request of the other initiator by the exclusive process. In addition, the access request for notifying the exclusive process stop request from the one initiator cannot be transmitted to the downstream packet router without passing through the relay circuit.

  If the packet router downstream of the access request does not have an exclusive processing function, the downstream packet router does not accept the exclusive processing request from the initiator connected to the upstream packet router having the exclusive processing function, thus guaranteeing the exclusivity. Can not do it.

[17]
In the semiconductor device according to Item 16, when the request resource of the packet router having the exclusive processing function receives the request packet including the exclusive processing request, the exclusive information indicating that there is an exclusive processing request from the request source and the request packet An exclusive information buffer that holds the access information included in the information, a comparison circuit that compares the information stored in the exclusive information buffer with the access information included in the request packet provided from the initiator, and outputs the comparison result; An access request invalidation circuit for invalidating an access request different from an access request accompanied by an exclusive processing request accepted based on a comparison result by the comparison circuit, maximizing a range in which access target addresses overlap; and the access Access request validated by request invalidation circuit Type, performs arbitration over competing access requests, accepting a single access request, having, an arbitration circuit for performing control for providing the target a request packet that is corresponding to the received access request.

[18] << Exclusive processing of hierarchical routers >>
A semiconductor device according to another aspect provides a plurality of initiators capable of requesting access, a plurality of targets capable of responding to access, and a request packet provided from the initiator to a target responding to the access request A plurality of packet routers including a request resource for performing control and a response resource for performing control to return a response packet given from a target responding to the access request to the initiator of the access request source. When the plurality of packet routers are connected in series in a plurality of layers through a relay circuit, the request resource of each of the packet routers has an exclusive processing function for receiving an exclusive processing request for a required target from the initiator. . Initiators requesting access with exclusive processing requests are aggregated and coupled to packet routers in the same hierarchy (FIGS. 11 and 12).

  When initiators that make exclusive processing requests are mixed with initiators that do not make exclusive processing requests and are distributed to upstream and downstream packet routers, when upstream and downstream initiators request exclusive access for the same address, An access request from an initiator that does not require exclusive processing on the upstream side is suppressed regardless of whether or not it should be suppressed by the exclusive access request. This is because in the relay circuit, the access request for the exclusive processing request to be transferred from the upstream initiator to the downstream packet router first is prevented from being transmitted to the downstream side until the exclusive access of the downstream initiator ends. It is to be done.

[19]
In the semiconductor device according to Item 18, when the request resource of the packet router having the exclusive processing function receives the request packet including the exclusive processing request, the exclusive information indicating that there is an exclusive processing request from the request source and the request packet An exclusive information buffer that holds the access information included in the information, a comparison circuit that compares the information stored in the exclusive information buffer with the access information included in the request packet provided from the initiator, and outputs the comparison result; An access request invalidation circuit for invalidating an access request different from an access request accompanied by an exclusive processing request accepted based on a comparison result by the comparison circuit, maximizing a range in which access target addresses overlap; and the access Access request validated by request invalidation circuit Type, performs arbitration over competing access requests, accepting a single access request, having, an arbitration circuit for performing control for providing the target a request packet that is corresponding to the received access request.

2. Details of Embodiments Embodiments will be further described in detail.

《Packet exchange by split transaction》
FIG. 2 illustrates the concept of a packet switching system using split transactions. In this system, an initiator (INIT) 1 as a master sends a request packet (REQPCKT) as an access request to a target (TGET) 2 as a slave, and the target sends a response packet (RESPCKT) as an access response to the initiator. By doing so, transfer is performed. The packet router (PCKTTR) 3 arbitrates request packets and response packets that are transferred simultaneously. The packet router 3 accesses a request resource (REQRSC) 3A for performing control to give a request packet given from the initiator 1 requesting access to the target 2 responding to the access request and a response packet given from the target 2 responding to the access request. A response resource (RESRSC) 3B for performing control to be returned to the requesting initiator 1 is provided. In an actual system, an appropriate number of initiators 1 and targets 2 are arranged. In addition, the initiator 1 and the target 2 do not necessarily need to be separate circuits, and may be the initiator 1 in one aspect and the target 2 in another aspect in system operation, for example, DMAC (direct memory) The access controller is the target 2 when data transfer conditions are set by the CPU, and the initiator 1 when DMA transfer is performed according to the set transfer conditions.

  The request packet REQPCKT includes, for example, signals of request REQ, grant GNT, end of packet EOP, lock LCK, address ADD, opcode OPC, data DATA, byte enable BE, and source SRC.

  The request REQ indicates that the initiator outputs a valid value to LCK, ADD, OPC, DATA, BE, SRC, etc., among signals used for request packet transfer of the initiator port. When both this signal and GNT are asserted, the request packet is transferred from the initiator to the packet router. When this signal is in the non-asserted state, the packet router ignores the above signals. The initiator can assert this signal regardless of the state of GNT, but once it is asserted, it must be held in the asserted state until GNT is asserted and the transfer of the first cell of the request packet is complete.

  The grant signal GNT indicates that the corresponding target can receive the cell of the request packet. When both REQ and this signal are asserted, the cell of the request packet is transferred from the initiator to the packet router. The packet router can assert and deassert this signal regardless of the state of REQ.

  The end-of-packet EOP indicates that the initiator is outputting the final cell of the request packet to the initiator port. The target must make the request packet end condition a detection condition that this signal is in the asserted state, not the number of transferred cells. The initiator must hold this signal at a constant value from the start of the cell transfer until the cell transfer is completed.

  The lock LCK is a signal that requests that the system be locked in order to execute a transaction exclusively (a series of processing from the transfer of a request packet to the reception of a response packet). At the time of request packet transmission, the initiator asserts this signal when accessing the target exclusively, and deasserts (negates) this signal when canceling the exclusive access request. The packet router that supports exclusive transaction execution transfers the request packet in which this signal is asserted to the target until the request packet in which this signal from the same initiator is deasserted is transferred. Do not forward request packets from other initiators to the target.

  The address signal ADD indicates the target address of the transaction. The minimum unit for addressing by this signal is 8 bytes.

  The opcode OPC is a signal indicating the type of transaction such as load or store and the transfer size. The initiator holds this signal at a constant value while REQ is asserted from the start of the transfer of the request packet until the transfer of the request packet is completed.

  Data DATA is data transferred from the initiator to the target.

  The byte enable BE is 8-bit data that specifies a byte to be processed by the target. As for the relationship between byte enable and address, for example, byte enable bits BE_0,..., BE_7 correspond to byte addresses 0 + 8n,.

  The source SRC is an identifier output by the initiator so that the initiator of the transmission destination of the response packet can be specified when the packet router relays the response packet. The target stores the value of this signal when receiving a request packet, and outputs it as R_SRC described later when transmitting a corresponding response packet. Then, the packet router determines the transmission destination of the response packet based on R_SRC. Therefore, the initiator VC must output this signal so that the response packet is always returned to itself.

  The response packet RESPCKT includes, for example, each signal of response valid R_VLD (response request R_REQ), response grant R_GNT, response end of packet R_EOP, response lock R_LCK, response opcode R_OPC, response data R_DATA, and response source R_SRC.

  The response request R_REQ indicates the validity of R_RCK, R_OPC, R_DATA, R_SRC, etc. output by the target. The target can assert this signal regardless of the value of R_GNT. However, once this signal is asserted, this signal must be held in an asserted state until R_GNT is asserted and transfer of the first cell of the response packet is completed.

  The response valid R_VLD is a signal indicating the validity of the response packet, and is a signal for indicating to the initiator that R_EOP, R_LCK, R_OPC, R_DATA, etc. are valid.

  Response end of packet R_EOP indicates that the last cell of the response packet is output to the initiator.

  Response lock R_LCK indicates whether or not the response packet received by the initiator has been transmitted exclusively. The response lock R_LCK must be held at a constant value while R_VLD is in the asserted state after the transfer of the response packet is completed until the transfer of the response packet is completed. A packet router that supports exclusive transaction execution transmits another response packet in which this signal is asserted until another response packet in which this signal is deasserted from the same target. Do not forward response packets from the target to the initiator.

  The response opcode R_OPC is a response opcode indicating the result of a transaction such as load or store.

  Response data R_DATA is data transferred to the initiator.

  The response source R_SRC is a signal having the same value as the source SRC output by the initiator when the corresponding request packet is transmitted, and R_VLD is in an asserted state from the start of the transfer of the response packet until the transfer of the response packet is completed. The interval is held at a constant value. This signal is an identifier for enabling the destination of the response packet (initiator) to be specified when the packet router routes the response packet. The target stores the value of SRC when receiving the request packet, and outputs it as R_SRC when transmitting the corresponding response packet. The packet router determines the transmission destination of the response packet based on R_SRC.

  The response grant R_GNT indicates that a response packet can be received.

<Microcomputer and chipset>
FIG. 3 shows a block diagram of a chip set including a microcomputer to which packet switching by split transaction is applied and an expansion device used for expansion of peripheral functions. The chip set may be modularized, or may be mounted as a simple multi-chip on the motherboard.

  The microcomputer 10 and the expansion device 11 are formed on different semiconductor chips, and constitute a chip set with dual chips.

  The microcomputer 10 has hierarchized packet routers 12 and 13 for transferring data by packet exchange by split transaction, and a queuing buffer (QUEBUF) as a relay circuit between the packet routers 12 and 13. 14 is arranged. Here, the expansion device 11 also employs a packet switching method based on split transactions, and is provided with a packet router 15. Although not particularly limited, the microcomputer 10 and the expansion device 11 are connected by serial input / output circuits (SIO) 30 and 40.

  A central processing unit (CPU) 20 to 23, an interrupt controller (INTC) 24, a ROM access controller (ROMC) 25, a peripheral control unit (PRPHC) 26, and a routing controller register (RCREG) 27 are connected to the packet router 12. . For example, a ROM 50 is externally attached to the ROMC 25.

  The packet router 13 includes a display control unit (DISPC) 31, a hard disk control unit (HDDC) 32, a direct memory access controller (DMAC) 33, a flash memory controller (FMRYC) 34, a synchronous DRAM controller (DMRYC) 35, A peripheral control unit (PRPHC) 36 and SIO 30 are connected. A hard disk (HDD) 51 is externally attached to the HDDC 32, a display (DISP) 52 is externally attached to the DISPC 31, a flash memory (FMRY) 51 is externally attached to the FMRYC 34, and a synchronous DRAM (DMRY) 54 is attached to the DMRYC 35. Is externally attached.

  Peripheral control units (PRPHC) 41 to 44 and a routing controller register (RCREG) 45 are connected to the packet router 15.

  In the routing control register 27, control data for the packet routers 12 and 13 is set in a programmable manner by the CPU 20, for example, and the set control data is supplied to the packet routers 12 and 13. Similarly, in the routing control register 45, control data for the packet router 15 is set in a programmable manner by the CPU 20, for example, and the set control data is supplied to the packet router 45. The routing control register 27 functions as an exclusive control register that holds an attribute of access to be subjected to exclusive control by a request resource described later.

  The queuing buffer 14 temporarily holds the request packet received by the packet router 12 in the FIFO form. The first request packet currently held by the queuing buffer 14 is output to the packet router 13, and the packet router 13 accepts the request packet, so that the queuing buffer 14 recognizes that the request packet has been read. Further, the queuing buffer 14 temporarily holds the response packet received by the packet router 13 in the FIFO form. The response packet that is initially held by the queuing buffer 14 is output to the packet router 12, and the packet router 12 accepts the response packet, so that the queuing buffer 14 recognizes that the response packet has been read.

  In the microcomputer 10, the packet routers 12 and 13 are hierarchized into two layers. The packet router 12 is an upper layer and the packet router 13 is a lower layer for a transaction based on a packet request. In the chip set, the packet router 15 is a lower layer of the packet router 13.

  Here, in each circuit module constituting the chip set of FIG. 3, which is the initiator and which is determined from the target by the bus master function and the bus slave function, for example, as described above, the DMAC 33 becomes the initiator according to its operation mode. The RCREG 27 functions only as a target.

  In the chipset of FIG. 3, the packet routers 12, 13, and 15 invalidate subsequent access requests for arbitration when a plurality of initiators request access to one target and for exclusive control over shared resources and the like. Control to perform. For example, the CPU of the microcomputer 10 performs read-modify-write on the semaphore when a TAS (Test And Set) instruction is executed. The CPU requests exclusion processing from the packet router when performing semaphore read access by the TAS command as an initiator, and notifies the packet router of completion of exclusion processing when performing write access in the latter half of the TAS command. In the case where exclusive processing is performed in units of resources, a protocol that suppresses access to an exclusive access target by an initiator other than the initiator that has received an exclusive processing request in units of targets has been conventionally employed. In a multi-core SOC (an SOC in which a plurality of CPUs are mounted on one chip) such as the microcomputer 10, exclusive processing is used more frequently than a single-core SOC (an SOC in which a single CPU is mounted on one chip). It can be considered. In the exclusive processing of the target unit, the transfer performance (bus access performance) decreases greatly due to the exclusive processing. Therefore, in the chip set of FIG. 3, exclusive control of at least the address area unit is performed in order to reduce the exclusive processing unit. It is like that. Hereinafter, a specific example of the packet router will be described focusing on exclusive processing.

<< Request resource for address comparison >>
FIG. 1 specifically illustrates the basic configuration of the request resource (REQRSC) 80 of the packet routers 12, 13, and 15. The request resource 80 is an example of the request resource 3A. Here, for easy understanding, an example in which three initiators 60, 61, 62 and three targets 70, 71, 72 are connected to the request resource 80 is shown.

  The request resource 80 includes an exclusive information buffer (EXCLBUF) 81, comparison circuits (COMP) 90, 91, 92, access request invalidation circuits (DSABL) 100, 101, 102, and an arbitration circuit (ARBTR) 82. The arbitration circuit 82 includes an arbitration logic (ARBLGC) 83 and a selector (SLCTR) 84.

  For example, as illustrated in FIG. 4, the exclusive information buffer 81 receives the request packet in which the lock LCK as the exclusive processing request is asserted, and responds to the exclusive processing request corresponding to the initiator number INITID as the request source. It holds exclusive information EXCL indicating presence / absence, address information ADD included in the request packet, access data size DSZ, and byte enable BE. The exclusive control register 27 holds the target initiator number TGINIT shown in FIG. 4 and information on the access direction R / W such as read or write. The access data size DSZ is data used when the entire address range is not specified by address information and is specified by the head address and the access data size. The information corresponding to the target initiator number TGINIT and the access direction R / W is not the information specified by the request packet in the first place, but the data specified by the CPU in the exclusive control register 27. The target initiator number TGINIT of the initiator ID # 0 is “# 1 = 1/0, # 2 = 1/0”, where 1 means the exclusive process target and 0 means the exclusive process non-target. For example, the target initiator number TGINIT of the initiator ID # 0 is “11”, that is, “# 1 = 1, # 2 = 1”. In response to the exclusive processing request output by the initiator # 0, the initiator ID # 1, # 2 Any access request from any of these will be subject to exclusion processing. The target initiator number TGINIT of the initiator ID # 1 is “# 0 = 1/0, # 2 = 1/0”. For example, the target initiator number TGINIT of the initiator ID # 1 is “01”, that is, “# 0 = 0, # 2 = 1 ”and the exclusive processing request output from the initiator # 1 is not subject to the exclusive processing for the access request from the initiator ID # 0, but the access request from the initiator ID # 2 On the other hand, it is subject to exclusive processing.

  For example, the comparison circuits 90, 91, and 92 compare the information stored in the exclusive information buffer 81 and the like with the address information included in the request packet provided from the corresponding initiators 60, 61, and 62, and the comparison result is obtained. Output. For example, the comparison circuit 90 compares the entry data held by the exclusive information buffer 81 and having the initiator IDs # 1 and # 2 with the data included in the request packet output from the initiator 60 and corresponding to the entry data. . The comparison circuit 91 compares the entry data held by the exclusive information buffer 81 and having initiator IDs # 0 and # 2 with the data included in the request packet output from the initiator 60 and corresponding to the entry data. The comparison circuit 92 compares the entry data held by the exclusive information buffer 81 with the initiator IDs # 0 and # 1 and the data included in the request packet output from the initiator 60 and corresponding to the entry data. Here, each comparison circuit 90, 91, 92 outputs a high level (“H”) unless the comparison condition matches the exclusion condition.

  The access request invalidation circuits (DSABL) 100, 101, 102 invalidate the corresponding access request when the outputs of the corresponding comparison circuits 90, 91, 92 are "L". That is, the access request invalidation circuit 100 takes the logical product of the output of the comparison circuit 90 and the request REQ from the initiator 69, and when access is requested by the high level of the request REQ, the output of the comparison circuit 90 is If it is not “H”, the access request by the corresponding request REQ is invalidated. The access request invalidation circuit 101 takes the logical product of the output of the comparison circuit 91 and the request REQ, and when access is requested by the high level of the request REQ, the output of the comparison circuit 91 is not “H”. The access request by the corresponding request REQ is invalidated. The access request invalidation circuit 102 takes the logical product of the output of the comparison circuit 92 and the request REQ, and when access is requested by the high level of the request REQ, the output of the comparison circuit 92 is not “H”. The access request by the corresponding request REQ is invalidated. In short, if the access request invalidation circuits 100, 101, and 102 focus on the access target address, the access request invalidation circuits 100, 101, and 102 maximize the range in which the already received exclusive processing request and the access target address overlap based on the comparison result by the comparison circuit. The access request different from the access request with the exclusive processing request already accepted is invalidated. The range where the access target addresses overlap means that the access addresses overlap on the same initiator.

  The arbitration logic 83 receives the access request validated by the access request invalidation circuit, arbitrates the conflicting access request, and accepts one access request. The selector 84 performs control for giving a request packet corresponding to the access request received by the arbitration logic 83 to the target. Further, the selector 84 updates the information of the corresponding entry in the exclusive information buffer 81 with the information of the request packet of the access request received with the exclusive processing request.

  Although the location of the request REQ and the grant GNT in the request packet REQPCKT is clearly shown in FIG. 1, other signals are included in other signal lines.

  According to the above, access information such as address information subject to exclusive access is held, the access information output by the initiator is compared with the held access information, and the range where the access target addresses overlap is maximized. Since the access request is invalidated, pinpoint exclusive processing for an address finer than the target unit can be realized.

  Prior to the processing of the arbitration circuit, selective invalidation processing for an access request accompanied by an exclusive processing request is performed, so that an access request that should be suppressed by exclusive control is targeted for arbitration processing by the arbitration circuit. However, this point contributes to shortening the time from when the initiator makes an access request until the access request is accepted.

  In FIG. 1, the arbitration logic 83 outputs a grant GNT for each initiator, and when the access request is input from the initiator by a request REQ, the access request is validated by the access request invalidation circuit 100, and When the access request from the initiator is invalidated by arbitration, or when the access request from the initiator is not accepted by arbitration, the grant GNT is deasserted. Regardless of the invalidation of the access request, the arbitration logic 83 asserts the grant GNT only when the access request from the initiator is accepted, so that the initiator that receives this asserts whether it has been accepted or invalidated after the access request. It is only necessary to wait for the grant GNT to be asserted without sensing that. Therefore, in the packet-switched bus interface by split transaction, even if an access request accompanied by an exclusive process is temporarily suppressed, the initiator only has to wait, and there is no need for a process such as making an access request again. Even if the invalidation is adopted, the initiator can be easily implemented.

  In FIG. 1, for example, when the initiator requests access, the initiator determines that the access request is not accepted by the deasserted state of the input grant GNT, and the access is made when the input grant GNT is in the asserted state. Determine that the request has been accepted.

  FIG. 5 shows an example in which address comparison and exclusion request comparison are performed as an example of the comparison circuit (COMP # 0) 90. Reference numeral 110 denotes an address comparator that compares the address information ADD of the entry with the initiator ID # 1 in the exclusive information buffer 81 and the address ADD output from the initiator 60 with the initiator ID # 0. Output. An address comparator 111 compares the address information ADD of the entry of the initiator ID # 2 in the exclusive information buffer 81 and the address ADD output from the initiator 60 of the initiator ID # 0. Output. The AND gate 112 takes the logical product of the exclusive information EXCL of the entry of the initiator ID # 1 in the exclusive information buffer 81 and the comparison result of the address comparator 110 as two inputs. The AND gate 113 takes the logical product of the exclusive information EXCL of the entry of the initiator ID # 2 in the exclusive information buffer 81 and the comparison result of the address comparator 111 as two inputs. The exclusive information EXCL of the entry is set to “H” if the corresponding initiator requests exclusive processing. A negative OR gate (NOR gate) 114 takes the outputs of the AND gates 112 and 113 as two inputs and takes a negative OR. The access request invalidation circuit 100 is configured by an AND gate having two inputs, the request REQ output from the initiator ID # 0 and the output of the NAND gate 114. Therefore, when the initiator # 1 requests exclusive processing (INT1, EXCL (EXCLBUF) = “H”) and the comparison by the address comparator 110 is coincident, the output of the AND gate 112 is “H”. When # 2 requests exclusive processing (INT2, EXCL (EXCLBUF) = “H”) and the comparison by the address comparator 111 is coincident, the output of the AND gate 113 becomes “H”. Even in this case, the access request from the initiator # 0 is invalidated. The same applies to other comparison circuits.

  In this way, when a comparison circuit that performs address comparison and exclusion request comparison is adopted, when an access request is received from one initiator, an exclusion processing request from another initiator is already accepted for an address that overlaps with the access address. If so, the access request from the one initiator is invalidated.

  FIG. 6 shows an example in which address comparison, exclusion request comparison, and byte enable comparison are performed as an example of the comparison circuit (COMP # 0) 90. 120 is the same as the comparator 110 of FIG. 5, and 121 is the same as the comparator 111 of FIG. The comparator 125 is an address comparator that compares the byte enable BE of the entry of the initiator ID # 1 in the exclusive information buffer 81 with the byte enable BE output from the initiator 60 of the initiator ID # 0. "Is output. An address comparator 126 compares the byte enable BE of the entry of the initiator ID # 2 in the exclusive information buffer 81 with the byte enable BE output from the initiator 60 of the initiator ID # 0. Is output. The AND gate 122 takes the logical product of the exclusive information EXCL of the entry of the initiator ID # 1 in the exclusive information buffer 81, the comparison result of the address comparator 120, and the comparison result of the address comparator 125 as three inputs. The AND gate 123 takes a logical product with the exclusive information EXCL of the entry of the initiator ID # 2 in the exclusive information buffer 81, the comparison result of the address comparator 111, and the comparison result of the address comparator 111 as three inputs. The exclusive information EXCL of the entry is set to “H” if the corresponding initiator requests exclusive processing. A negative OR gate (NOR gate) 124 takes the outputs of the AND gates 122 and 123 as two inputs and takes a negative OR. The access request invalidation circuit 100 is configured by an AND gate that receives the request REQ output from the initiator ID # 0 and the output of the NAND gate 124 as two inputs. Therefore, when the initiator # 1 requests exclusive processing (INT1, EXCL (EXCLBUF) = “H”) and the comparison by the address comparator 120 and the comparison by the address comparator 125 are the same, the output of the AND gate 122 Is “H”, and when the initiator # 2 requests exclusive processing (INT2, EXCL (EXCLBUF) = “H”) and the comparison by the address comparator 121 and the comparison by the address comparator 126 are coincident, AND Since the output of the gate 123 becomes “H”, the access request from the initiator # 0 is invalidated in any case. The same applies to other comparison circuits.

  In this way, when employing a comparison circuit that performs address comparison, exclusive request comparison, and byte enable comparison, when there is an access request from one initiator, it overlaps with the designated access address, and the byte to be accessed by byte enable overlaps. If an exclusive processing request from another initiator is already accepted, the access request from the one initiator is invalidated.

  FIG. 7 shows an example of a comparison circuit (COMP # 0) 90 in which the target initiator number TGINIT is also compared with FIG. The difference from FIG. 6 is that AND gates 122 and 123 have four inputs, and the AND gate 132 related to INITID # 1 corresponds to INIT # 0 of the target initiator number TGINIT held by the entry of INITID # 1 in the exclusive information buffer 81. A value corresponding to INIT # 0 of the target initiator number TGINIT held in the entry of INITID # 2 in the exclusive information buffer 81 is input to the AND gate 133 related to INITID # 2. According to the example of FIG. 4, in the entry of INITID # 1, the target initiator number TGINIT is “# 0, # 2” = “01”, so INIT # 1, TGINIT (INIT # 0) = 0 is an AND gate. In 132, since the target initiator number TGINIT is “# 0, # 1” = “10” in the entry of INITID # 2, INIT # 2, TGINIT (INIT # 0) = 0 is supplied to the AND gate 133. . As a result, the access request from the initiator 60 (INITID # 0) is not excluded even if the exclusive processing request by the initiator 61 (INITID # 1) has already been received, and the exclusive processing by the initiator 62 (INITID # 2). If the request has already been accepted, it will be rejected.

  As described above, if address comparison or the like is performed with the target initiator number TGINIT as a comparison target, it is possible to invalidate only access requests from some initiators specified by the setting contents of the register 27.

  A specific example of the comparison circuit is an example of three initiators 60, 61, and 62 as illustrated in FIG. 1, and the configuration related to the AND gates 122 and 123 (132 and 133) according to the number of initiators. You can increase it.

<< Combination of request resource for exclusive control with target as minimum unit >>
In the above description, address comparison is used to determine whether the access target is the same as the target target of the exclusion process that has already been accepted. When invalidating access in units of targets, as illustrated in FIG. 8, request resources (REQRSC) 130 and 131 with different connections to the target are provided, and request packets to the request resources 130 and 131 are sent. A distribution circuit (PCKTSRT) 132 that performs distribution may be used. That is, target TGTs 70 and 71 are connected to the request resource 130, and one target TGT 72 is connected to the request resource 131. The distribution circuit 132 determines an access target from the access address ADD included in the request resource, supplies a request packet with the target 70 or 71 as an access target to the request resource 130, and requests a request packet with the target 72 as an access target. The resource 131 is supplied. Since the request resource 130 has the same configuration as the request resource 80 described in FIG. 1 except that the connected target is different, detailed description thereof is omitted. The request resource 131 is different from the request resource 80 of FIG. 1 in that the request resource 131 controls the exclusive processing request with the target as a minimum unit. That is, the comparison circuit 140 of the request resource 131 is illustrated in FIG. FIG. 9 shows an example of the comparison circuit (COMP # 0) 140. In the comparison circuit 140 shown in the figure, the exclusive information EXCL of the entry of the initiator ID # 1 in the exclusive information buffer 81 and the exclusive information EXCL of the entry of the initiator ID # 2 in the exclusive information buffer 81 are directly negative OR gates ( NOR gate 114. State where initiator # 1 requests exclusive processing (INT1, EXCL (EXCLBUF) = “H”), or state where initiator # 2 requests exclusive processing (INT2, EXCL (EXCLBUF) = “H”) In this case, the access request from the initiator # 0 to the target 72 is invalidated.

  Since only request packets targeting one specific target 70 are distributed to the request resource 131, address comparison is not required for exclusive control in units of targets, and other initiators issued for one target 70 are targeted. If it is determined whether or not the exclusive processing request has already been accepted, exclusive control using this as a minimum unit can be performed on one target 70.

<Exclusive control in units of initiator>
If the initiator requesting exclusive control is a CPU, there is no problem even if the packet router permits access to another address by another initiator within the exclusive control period. On the other hand, some initiators require exclusive access for the purpose of eliminating other initiators and increasing their own access frequency. For example, DMAC. For such an exclusive processing request by the initiator, exclusive processing for all accesses to the target is effective, not pinpoint exclusive processing by an address or the like. For this reason, it is preferable to mix a circuit that performs exclusive control with all accesses and a circuit that performs exclusive control with pinpoints in units of initiators that request exclusive processing.

  More specifically, if the initiator is a CPU, as described with reference to FIG. 1, exclusive processing with limited addresses is performed, and if the initiator is other than a CPU, exclusive processing without limiting addresses is performed. If the initiator is directly connected to the packet router, whether the initiator is a CPU or a non-CPU is determined at the development stage of the SOC or semiconductor device, so a circuit that identifies whether the initiator type is a CPU or a non-CPU is special. It is not necessary to provide it. When an initiator is connected to the packet router, the initiator type may be determined based on initiator identification information (sheath SRC) that is one of the attributes included in the request packet.

<< Number of entries in exclusive information buffer >>
The exclusion process must not be performed normally due to the overflow of the exclusion information buffer. Therefore, the number of entries in the exclusive information buffer 81 is equal to or greater than the total number of exclusive accesses that can be executed simultaneously by the initiator. For example, in the example of FIG. 4, one initiator ID stores one access information. When a packet router is connected to a packet router as in a hierarchical interconnect, the number of entries in the exclusive information buffer is the total number of exclusive accesses that can be executed simultaneously by all initiators connected to the packet router.

  When there are a plurality of exclusive accesses that can be executed simultaneously by one CPU, the identification may be performed using the process ID. In this case, the access information held in the exclusive information buffer includes the process ID information of the process using the access target address information together with the access target address information. In this case, the access request invalidation circuit invalidates an access request having a process ID different from that of an access request accompanied by an accepted exclusive processing request, while maximizing a range where the access target addresses overlap. For exclusive access requests by the same initiator, it is possible to deal with invalidation of access requests in consideration of the process ID.

<< Debugging support for accesses competing for exclusive processing >>
When exclusive processing is used to implement a semaphore, the following events do not usually occur for the address for which the CPU is requesting exclusive access. There is a high possibility of a malfunction. The event means that there is a write access from a CPU other than the initiator (CPU) requesting exclusive processing, and an arbitrary access from an initiator other than the CPU. As illustrated in FIG. 3, when the packet routers 12 and 13 detect the above event, the packet routers 12 and 13 output interrupt request signals IRQ1 and IRQ2 to the interrupt controller 24 and output an interrupt signal INT to the CPU 23. Thereby, it can contribute to the early detection of the malfunction of software or hardware.

<< Exclusive processing of layered router >>
FIG. 10 shows an example in which an on-chip interconnect is constructed by hierarchically combining a plurality of packet routers. For example, a queuing buffer (QUEBUF) 152 is arranged between the packet routers 150 and 151 as a relay circuit. Initiators 160 and 161 are connected to the packet router 150, and initiators 162 and 163 are connected to the packet router 151. A representatively shown target 164 is connected to the packet router 151. In this way, when a plurality of packet routers 150 and 151 are connected in series in a plurality of layers via the queuing buffer 152, the request resource of each packet router 150 and 151 is an access request from the initiator to the required target. It has an exclusive processing function that accepts an accompanying exclusive processing request. For example, the request resource is configured as described in FIG. In this case, the output of the selector 84 of the packet router 150 is connected to the upstream port of the queuing buffer 152 by, for example, wired OR. The downstream port of the queuing buffer 152 may be connected to the request resource of the packet router 151 as one initiator.

  Of the plurality of packet routers 150 and 151 constituting the hierarchical interconnect, when the packet router 150 upstream of the access request (on the side close to the initiator) does not have an exclusive processing mechanism, the one connected to the upstream packet router 150 A hang-up occurs when another initiator 161 connected to the packet router 150 in the same hierarchy transmits an access request to the same address as the access request following the access accompanying the exclusive processing request from the initiator 160. . This is because when the relay circuit (queuing buffer) 152 between the packet routers transmits the request packet of the one initiator 160 to the packet router, the lower-layer packet router 151 performs an access request of the other initiator 161 by exclusive processing. This is because an access request for notifying the exclusive processing stop request from the one initiator 160 cannot be transmitted to the downstream packet router 151 without passing through the relay circuit 152.

  If the downstream packet router 151 of the access request does not have an exclusive processing function, the downstream packet router 151 accepts the exclusive processing request from the initiators 160 and 161 connected to the upstream packet router 150 having the exclusive processing function. Therefore, exclusivity cannot be guaranteed.

  FIG. 11 and FIG. 12 show an example in which, when an on-chip interconnect is constructed by hierarchically combining a plurality of packet routers, initiators that request exclusive processing are aggregated and connected to packet routers in the same hierarchy. 11 and 12, the packet routers 150 and 151 and the queuing buffer 152 are the same as those in FIG. 10, and both the packet routers 150 and 151 have an exclusive control function. 11 and 12, initiators 170 and 171 are initiators that request exclusive processing, and initiators 172 and 173 are initiators that do not request exclusive processing. In this way, initiators that request access with exclusive processing requests are aggregated and coupled to packet routers in the same hierarchy.

  As illustrated in FIG. 13, when initiators 170 and 171 that perform exclusive processing requests are mixed with initiators 172 and 173 that do not perform exclusive processing requests and are distributed in upstream and downstream packet routers 150 and 151, When the downstream initiators 170 and 171 request exclusive access for the same address, access requests from the initiator 172 that does not request exclusive processing on the upstream side should be suppressed by the exclusive access request. Regardless of whether it is a thing or not. This is because, in the relay circuit 152, the access request for the exclusive processing request to be transferred from the upstream initiator 170 to the downstream packet router 151 first is downstream until the exclusive access of the downstream initiator 171 ends. This is because the transmission of is suppressed.

  The embodiment described above has the following effects.

  (1) Pinpoint exclusive processing can be performed for the exclusive processing target address. For this reason, the transfer performance accompanying the exclusive process can be improved. This is because, in the present invention, the exclusive processing target address is held in the exclusive information holding buffer, it is determined whether or not the access request corresponds to the exclusive processing target address, and only the corresponding access request is excluded.

  (2) Exclusive processing that is limited to exclusive processing target addresses and exclusive processing that does not limit exclusive processing target addresses (for the purpose of improving throughput) can be mixed in one SOC or chip. This is because in the present invention, the address of the access request destination can be determined by the distribution circuit, and the request packet can be easily distributed to a predetermined request resource.

  (3) A plurality of exclusive accesses by a single initiator can be processed simultaneously. This is because the process identification information (process ID) is stored in the exclusive information holding buffer, it is determined whether the access request corresponds to the exclusive process target process ID, and only the corresponding access request is excluded.

  (4) Since the access request that is suppressed along with the exclusion process is eliminated before arbitration, the access request that is suppressed along with the exclusion process is not accepted by the arbitration process. As a result, an effective access (which is not excluded with the exclusion process) is accepted early, and high data transfer performance is obtained. Because a comparison circuit is arranged for each initiator between the initiator and the arbitration circuit, access requests that should be suppressed by exclusive processing before arbitration are suppressed, and only access requests that are not suppressed by exclusive processing by the arbitration circuit are subject to arbitration. is there.

  (5) In the hierarchical interconnect, hang-up due to exclusive processing can be avoided. This is because, in an interconnect configured hierarchically using a plurality of packet routers, an upstream (closer to the initiator) packet router suppresses an access request that should be suppressed by the exclusion process. This is to prevent the request packet that is suppressed by the exclusive processing by the downstream (closer to the target) packet router from staying in the relay circuit. If an access request that is suppressed by the exclusive processing by the downstream packet router stays in the relay circuit, the access request for notifying the downstream packet router of the end of exclusive access cannot be transferred, and this causes a hang-up state.

  (6) In the hierarchical interconnect, the access that is not excluded by the exclusion process is not suppressed until the exclusion process is completed along with the exclusion process. This is because an initiator requesting exclusive control is not connected to a different packet router, so that an access request that should be suppressed by exclusive control does not inhibit processing of an access request that is not suppressed by exclusive control.

  (7) By detecting unauthorized access to the address that is the subject of exclusive processing, early detection of software or hardware problems is facilitated. An event that a CPU other than the CPU performs a write access to an address that is subject to exclusive processing by the CPU or an initiator that is a non-CPU other than the CPU does not normally occur intentionally Therefore, there is a high possibility of a malfunction. This is because it is possible to detect a write access by a CPU other than the CPU and an access by an initiator that is a non-CPU other than the CPU, and thereby assert an interrupt signal with respect to an address to be subjected to exclusion processing.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

FIG. 1 is a block diagram specifically illustrating the basic configuration of a request resource of a packet router. FIG. 2 is a block diagram illustrating the concept of a packet switching system using split transactions. FIG. 3 is a block diagram of a chip set including a microcomputer and an expansion device to which packet switching by split transaction is applied. FIG. 4 is an explanatory diagram illustrating the exclusive information held in the exclusive information buffer and the control information held in the exclusive control register. FIG. 5 is a logic circuit diagram illustrating a configuration for performing address comparison and exclusion request comparison as an example of the comparison circuit 90. FIG. 6 is a logic circuit diagram illustrating a configuration for performing address comparison, exclusion request comparison, and byte enable comparison as an example of the comparison circuit 90. FIG. 7 is a logic circuit diagram illustrating an example of the comparison circuit 90 in which the target initiator number TGINIT is also compared with that in FIG. FIG. 8 is a block diagram illustrating request resources that employ a distribution circuit to invalidate access on a target basis. FIG. 9 is a logic circuit diagram illustrating a comparison circuit for performing a control for an exclusive processing request with a target as a minimum unit. FIG. 10 is an explanatory view focusing on the exclusive processing function of the packet router when an on-chip interconnect is constructed by hierarchically combining a plurality of packet routers. FIG. 11 is an explanatory diagram focusing on the aggregated arrangement of initiators that request exclusive processing when an on-chip interconnect is constructed by hierarchically combining a plurality of packet routers. FIG. 12 is an explanatory diagram focusing on another aggregated arrangement of initiators that request exclusive processing when an on-chip interconnect is constructed by hierarchically combining a plurality of packet routers. FIG. 13 is an explanatory diagram focusing on the problem when the initiators that request exclusive processing are distributedly arranged.

Explanation of symbols

1 Initiator (INIT)
2 Target (TGET)
3 Packet router (PCKTTR)
3A Request resource (REQRSC)
3B Response resource (RESRSC)
REQPCKT request packet REQ request GNT grant ADD address BE byte enable LCK lock RESPCKT response packet 10 microcomputer 11 expansion device 12, 13 packet router 14 queuing buffer (QUEBUF)
15 Packet router 20-23 Central processing unit (CPU)
24 Interrupt controller (INTC)
25 ROM access controller (ROMC)
26 Peripheral control unit (PRPHC)
27 Routing controller register (RCREG)
31 Display controller (DISPC)
32 Hard disk controller (HDDC)
33 Direct Memory Access Controller (DMAC)
34 Flash memory controller (FMRYC)
35 Synchronous DRAM controller (DMRYC)
36 Peripheral control unit (PRPHC)
80 Request resource (REQRSC)
60, 61, 62 Initiator 70, 71, 72 Target 81 Exclusive information buffer (EXCLBUF)
90, 91, 92 Comparison circuit (COMP)
100, 101, 102 Access request invalidation circuit (DSABL)
82 Arbitration circuit (ARBTR)
83 Arbitration logic (ARBLGC)
84 Selector (SLCTR)
130, 131 Request resource (REQRSC)
150, 151 Packet router 152 Queuing buffer (QUEBUF)
160, 161, 162, 163 Initiator 170, 171, 172, 173 Initiator

Claims (19)

A request resource that controls a plurality of initiators that can request access, a plurality of targets that can respond to access, and a request packet given from the initiator that requests access to a target that responds to the access request And a packet router having a response resource for performing control to return a response packet given from a target responding to the access request to the initiator of the access request source,
The request resource, when receiving a request packet including an exclusive processing request, exclusive information indicating that there is an exclusive processing request from the request source, and an exclusive information buffer that holds access information included in the request packet;
A comparison circuit that compares the information stored in the exclusive information buffer with the access information included in the request packet given from the initiator, and outputs the comparison result;
An access request invalidation circuit that invalidates an access request different from an access request with an accepted exclusive processing request, based on a comparison result by the comparison circuit, maximizing a range in which access target addresses overlap;
The access request validated by the access request invalidation circuit is input, arbitration is performed for the conflicting access request, one access request is accepted, and the request packet corresponding to the accepted access request is targeted. A semiconductor device comprising: an arbitration circuit that performs control for providing the data;   The arbitration circuit outputs a grant signal for each initiator, and when an access request is input from the initiator, once the grant signal corresponding to the initiator of the access request source is asserted, the access request invalidation circuit 2. The semiconductor according to claim 1, wherein the assertion state of the grant signal is maintained until transfer of a request packet accompanying the access request to a response destination target is started regardless of whether the access request is validated or invalidated. apparatus.   When the initiator requests access, the initiator determines that the access request is not accepted by the deasserted state of the input grant signal, and the access request is accepted when the input grant signal is in the asserted state. The semiconductor device according to claim 1, wherein the determination is made. The access information held by the exclusive information buffer is access target address information,
2. The semiconductor device according to claim 1, wherein the access request invalidation circuit invalidates an access request from an initiator different from an access request accompanied by an accepted exclusive processing request, with a maximum range of overlapping access target addresses. . The access information held by the exclusive information buffer is access target address information and process ID information of a process using the access target address information.
2. The semiconductor device according to claim 1, wherein the access request invalidation circuit invalidates an access request having a process ID different from that of an access request accompanied by an accepted exclusive processing request, while maximizing a range in which access target addresses overlap. .   The semiconductor device according to claim 5, wherein the exclusive information buffer has a storage capacity capable of storing access information for each access request accompanied by an exclusive processing request that can be received in parallel by the arbitration circuit. The access information held by the exclusive information buffer is access target address information indicating the head of a plurality of bytes to be accessed, and byte enable information indicating the validity within the access target range of the plurality of bytes in bytes.
The access request invalidation circuit accepts an exclusive process that is accepted by maximizing a range that overlaps an address that is valid in the byte enable information within a plurality of bytes of the access target range starting from the address of the access target address information. The semiconductor device according to claim 1, wherein an access request different from an access request accompanying the request is invalidated. The access information held by the exclusive information buffer includes access target address information indicating the start of a multi-byte access target, byte enable information indicating the validity within a multi-byte access target range in bytes, and an access target address. Process ID information of the process using the information,
The access request invalidation circuit accepts an exclusive process that is accepted by maximizing a range that overlaps an address that is valid in the byte enable information within a plurality of bytes of the access target range starting from the address of the access target address information. The semiconductor device according to claim 1, wherein an access request having a process ID different from that of the access request accompanied by the request is invalidated.   9. The semiconductor device according to claim 8, wherein the exclusive information buffer has a storage capacity capable of storing access information for each access request accompanied by an exclusive processing request that can be received in parallel by the arbitration circuit. It further has an exclusive control register that holds the attribute of access to be subject to exclusive control,
The access request invalidation circuit, based on the comparison result by the comparison circuit and the access attribute information held in the exclusive control register, accepts an exclusive processing request that has been accepted with a maximum range of overlapping addresses to be accessed. The semiconductor device according to claim 1, wherein an access request different from the accompanying access request is invalidated. In the exclusive control register, an access direction is set as an access attribute,
The access request invalidation circuit, based on the comparison result by the comparison circuit and the access attribute information held in the exclusive control register, accepts an exclusive processing request that has been accepted with a maximum range of overlapping addresses to be accessed. 11. The semiconductor device according to claim 10, wherein the access request is different from the accompanying access request and invalidates the access request in the access direction set in the exclusive control register. In the exclusive control register, identification information of the initiator is set as an access attribute,
The access request invalidation circuit, based on the comparison result by the comparison circuit and the access attribute information held in the exclusive control register, accepts an exclusive processing request that has been accepted with a maximum range of overlapping addresses to be accessed. 11. The semiconductor device according to claim 10, wherein the access request is different from the accompanying access request and invalidates the access request from the initiator set in the exclusive control register. A plurality of CPUs that can function as the initiator, a memory that can function as the target, and an interrupt controller,
The memory is a shared memory of the plurality of CPUs;
When the packet router receives a request packet accompanied by an exclusive processing request for the shared memory from one CPU, the access request accompanied by the accepted exclusive processing request is within a range overlapping with the access target address. The semiconductor device according to claim 1, wherein the interrupt controller is notified of a different write access request. A memory and an interrupt controller that can function as the target;
The memory is a shared memory of a plurality of initiators,
When the packet router receives a request packet accompanied by an exclusive processing request for the shared memory from a single initiator, the write access is different from the accepted access request accompanied by the exclusive processing request within a range overlapping with the access target address. The semiconductor device according to claim 1, wherein the interrupt controller is notified of a request. A first control is performed to provide a plurality of initiators capable of requesting access, a plurality of targets capable of responding to access, and a request packet provided from the initiator requesting access to a target responding to the access request. A request router, a second request resource, and a packet router provided with a response resource for performing control to return a response packet given from a target responding to the access request to the initiator of the access request source,
The first request resource controls a request packet targeting a specific target;
The second request resource performs control on a request packet targeting a plurality of other targets,
The first and s second request resources hold exclusive information indicating that there is an exclusive processing request from the request source and access information included in the request packet when a request packet including an exclusive processing request is received. An exclusive information buffer;
A comparison circuit that compares the information stored in the exclusive information buffer with the access information included in the request packet given from the initiator, and outputs the comparison result;
An access request invalidation circuit that invalidates an access request different from an access request with an accepted exclusive processing request, based on a comparison result by the comparison circuit, maximizing a range in which access target addresses overlap;
The access request validated by the access request invalidation circuit is input, arbitration is performed for the conflicting access request, one access request is accepted, and the request packet corresponding to the accepted access request is targeted. A semiconductor device comprising: an arbitration circuit that performs control for providing the data; Multiple initiators that can request access;
Multiple targets that can respond to access,
A plurality of request resources including a request resource for performing control to give a request packet given from the initiator to a target responding to the access request and a response resource for controlling returning a response packet given from the target responding to the access request to the initiator of the access request source A packet router, and
When the plurality of packet routers are connected in series in a plurality of layers via a relay circuit, the request resource of each packet router accepts an exclusive processing request accompanying an access request for a required target from the initiator. A semiconductor device comprising: The request resource having the exclusive processing function is:
When receiving a request packet including an exclusive processing request, exclusive information indicating that there is an exclusive processing request from the request source, and an exclusive information buffer that holds access information included in the request packet;
A comparison circuit that compares the information stored in the exclusive information buffer with the access information included in the request packet given from the initiator, and outputs the comparison result;
An access request invalidation circuit that invalidates an access request different from an access request with an accepted exclusive processing request, based on a comparison result by the comparison circuit, maximizing a range in which access target addresses overlap;
The access request validated by the access request invalidation circuit is input, arbitration is performed for the conflicting access request, one access request is accepted, and the request packet corresponding to the accepted access request is targeted. The semiconductor device according to claim 16, further comprising: an arbitration circuit that performs control for giving. Multiple initiators that can request access;
Multiple targets that can respond to access,
A plurality of request resources for performing control to give a request packet given from the initiator to a target responding to the access request and a response resource for controlling to return a response packet given from the target to respond to the access request to the initiator of the access request A packet router, and
When the plurality of packet routers are connected in series in a plurality of layers through a relay circuit, the request resource of each of the packet routers has an exclusive processing function for receiving an exclusive processing request for a required target from the initiator. ,
A semiconductor device in which initiators that request access with an exclusive processing request are aggregated and coupled to packet routers in the same hierarchy. The request resource having the exclusive processing function is:
When receiving a request packet including an exclusive processing request, exclusive information indicating that there is an exclusive processing request from the request source, and an exclusive information buffer that holds access information included in the request packet;
A comparison circuit that compares the information stored in the exclusive information buffer with the access information included in the request packet given from the initiator, and outputs the comparison result;
An access request invalidation circuit that invalidates an access request different from an access request with an accepted exclusive processing request, based on a comparison result by the comparison circuit, maximizing a range in which access target addresses overlap;
The access request validated by the access request invalidation circuit is input, arbitration is performed for the conflicting access request, one access request is accepted, and the request packet corresponding to the accepted access request is targeted. The semiconductor device according to claim 18, further comprising: an arbitration circuit that performs control for giving.

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