JP2010033620A - Magnetic memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure reliability when data are written into a magnetic random access memory. <P>SOLUTION: After data are written into a memory cell, it is determined whether the data written from the outside logically coincide with data read from the memory cell (step S3). When the write data do not coincide with the logical value of the stored data in the memory cell, the data are again written into the target memory (step S4). After that, the stored data are again read out from the target memory cell and it is determined whether the write data coincide with the read data. This operation is repeated until the write data coincide with the read data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a magnetic memory, and more particularly to a memory using an MTJ element (magnetic tunnel junction element) or an MJT element (spin tunnel junction element) as a storage element. More specifically, the present invention relates to a configuration for ensuring the reliability of data writing to an MTJ element (MJT element).

  Conventionally, a flash memory is known as a semiconductor memory device for storing data in a nonvolatile manner. In this flash memory, a memory cell is composed of a stacked gate type transistor having a control gate and a floating gate. The threshold voltage of the memory cell transistor changes according to the amount of charge stored in the floating gate. The threshold voltage of the memory cell transistor is associated with stored data. At the time of data reading, a certain level of voltage is applied to the control gate. The memory cell transistor has a different amount of current flowing according to its threshold voltage. Data is read by detecting the amount of current flowing through the memory cell transistor.

  In the flash memory, data is written as follows. In accordance with the write data, charges are moved between the floating gate and the substrate region (channel region) or between the floating gate and the source / drain regions, and the accumulated charge amount of the floating gate is set according to the stored data. Therefore, in the case of a flash memory cell, charge moves through the insulating film, so that the number of times of writing is limited by the characteristics of the insulating film. In addition, since data is written by this movement of charges, there is a problem that the data writing time is long and the access time is long.

  In order to solve such a problem of the flash memory, an MRAM (Magneto-Resistive RAM) having a feature of a short access time and an unlimited number of rewrites is provided. Has been developed. This MRAM uses a variable magnetoresistive element as a memory cell element. In the variable magnetoresistive element, a laminated structure of magnetic materials called a free layer and a fixed layer is used. The resistance value differs depending on the magnetization direction of these magnetic materials, and data is stored according to the resistance value.

  Conventionally, in a current magnetic field writing MRAM as an MRAM, current is passed through digit lines and bit lines orthogonal to each other when data is written. The magnetization direction of the free layer of the variable magnetoresistive element (MTJ element (magnetic tunnel junction element)) is set by a combined magnetic field of magnetic fields induced by currents flowing through these digit lines and bit lines. The magnetization direction of the fixed layer is fixed in a fixed direction regardless of the applied magnetic field.

  In such a conventional MRAM, a constant current is required to generate a magnetic field necessary for rewriting. Therefore, as the miniaturization of the memory cell advances, the width of the power supply line becomes smaller, and accordingly, the current required for generating the magnetic field increases. As the miniaturization progresses, the distance between the variable magnetoresistive elements of the memory cell also decreases. There arises a problem that data stored in unselected memory cells changes due to a leakage magnetic field applied to the selected memory cell.

  Further, in the current magnetic field writing type memory cell, the easy magnetization axis is arranged in a direction parallel to the bit line or the digit line. In this case, in a memory cell in a half-selected state (a state in which a digit line or a bit line is selected), there arises a uniaxial disturb problem that the stored data is inverted by a magnetic field due to a current flowing through the digit line or the bit line. .

  Toggle MRAM and spin-injection magnetization reversal writing MRAM (spin torque transfer RAM; hereinafter referred to as “spin-injection MRAM”) have been developed as MRAMs that solve such a problem of uniaxial disturbance.

  In the toggle MRAM, the easy axis and the hard axis of the memory element of the memory cell are arranged at an angle of 45 ° with the digit line and the bit line. In addition, the free layer is composed of a SAF (synthetic antiferromagnetic structure) structure. In this SAF structure, two ferromagnetic layers are arranged with an antiferromagnetic coupling layer interposed therebetween. At the time of data writing, the timing of flowing current to the digit line and the bit line is shifted, and the magnetization of the free layer is rotated. Since the magnetization direction of the free layer is rotated using both the digit line and the bit line, the magnetization direction of the free layer does not rotate even when a leakage magnetic field is applied from one axis (digit line or bit line). It becomes possible to solve the problem of 1-axis disturbance.

  In spin injection magnetization reversal writing MRAM (spin injection MRAM), the spin polarization direction of electrons passing through the fixed layer concept is set by the magnetization direction of the fixed layer. The electrons whose spin polarization direction is determined flow into the free layer or are extracted from the free layer, thereby adjusting the spin polarization direction of the free layer electrons and setting the magnetization direction of the free layer accordingly.

  In a spin injection type MRAM called a spin torque transfer RAM, a current is passed through a variable magnetoresistive element (MTJ element) of a memory cell at the time of data writing. Therefore, since the electron spin is used and the magnetic field is not induced, the problem of uniaxial disturbance can be solved.

  The memory device has a plurality of memory cells. For example, in a memory device having a storage capacity of 1 megabit, about 1 million memory cells are provided. There are subtle variations in characteristics between the plurality of memory cells. Therefore, when data is rewritten to all the memory cells under the same conditions, it is necessary to set an overlapping area of a rewritable range of a plurality of memory cells as a rewrite condition. Therefore, the write condition for rewriting is in a narrow range, and the probability that a write failure will occur increases.

  Conventionally, a write verify operation for determining whether data has been correctly written at the time of data writing has been performed in a flash memory or the like.

  For example, in Patent Document 1 (Japanese Patent Laid-Open No. 10-302487), when the write verify operation is executed first and the write data and the storage data of the write target memory cell match, Then, the subsequent writing is stopped. A verify operation is performed for each write, and the write and verify operations are executed a predetermined number of times until the data stored in the write target memory cell matches the write data. For each writing, the writing pulse width is changed and writing is performed. If the data has not been written correctly even after the verification has reached the predetermined number of times, it is determined that the memory cell to be written is defective, an error flag is issued to the outside, and the writing is terminated. .

  In this patent document 1, by alternately executing writing and writing verification, writing to a memory cell that does not require writing is stopped, and threshold voltage control of the memory cell is performed for each bit. The rewriting of is to be performed stably.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2005-44454), in a flash memory, write verification after writing is performed to determine whether the threshold value of the memory cell transistor is within a predetermined range. At the time of writing after the verification, writing is executed by changing the writing pulse voltage and / or the pulse width.

  This patent document 2 maintains the threshold voltage distribution width of a memory cell after writing in a predetermined range, and takes a wide difference between the threshold voltage after writing and the threshold voltage after erasing. It is intended to suppress the deterioration of characteristics.

  Patent Document 3 (Japanese Patent Application Laid-Open No. 2004-22112) discloses a flash memory whose purpose is to perform page programming at high speed. In the configuration disclosed in Patent Document 3, writing and verifying are performed for each page of data in units of pages, and subsequent writing is stopped for the writing completion cell for each verifying.

  In Patent Document 3, writing and verification are repeated in units of a plurality of addresses. Compared to the case where writing and verify reading are performed for each address, the time required for programming is shortened, and a high-speed page program is realized.

  Patent Document 4 (Japanese Patent Laid-Open No. 2003-346484) also discloses an insulating film charge trap type memory that performs write verify. In the configuration disclosed in Patent Document 4, after a write verify, a write voltage level is adjusted and rewriting is executed for a memory cell in which writing is defective. A maximum value is set for the number of times of write verification. If the target cell is defective in writing even when the maximum value is reached, this memory cell is determined to be defective. This Patent Document 4 reduces the number of times a write pulse is applied by performing writing and verifying, and prevents the write pulse from being excessively applied to the insulating film of the memory cell transistor (NROM cell transistor). To prevent and maintain reliability.

  In Patent Document 4, it is intended to prevent an excessive voltage from being applied to a memory cell transistor (NROM transistor cell) by performing writing step by step during rewriting.

  Further, Patent Document 5 (Japanese Patent Laid-Open No. 11-86575) discloses a configuration of a flash memory for the purpose of observing the maximum time required for a data program. In the configuration disclosed in Patent Document 5, in the test mode, a preset maximum number of verifications, writing and verifying to a memory cell are executed. When the maximum number of times of writing / verifying is completed, a busy signal BUSY is issued to the outside. The maximum program time can be measured by observing the busy signal externally. As a result, the worst case program time is guaranteed as the specification value, and the system design is facilitated.

  Patent Document 6 (Japanese Patent Laid-Open No. 11-260084) discloses a flash memory that shortens the data writing time. In Patent Document 6, it is determined whether a write current value flowing during a write operation is smaller than a write completion determination value. When this write current becomes smaller than the determination value, writing is stopped. This eliminates the need to read data from the memory cell to be written after data writing and perform a verify operation, thereby shortening the writing time.

  In addition, a configuration for performing writing and write verification in a phase change memory is disclosed in Japanese Patent Application Laid-Open No. 2005-100617. This patent document 7 is directed to writing when a memory cell is set to a reset state of a high resistance state. That is, at the time of writing to the phase change memory cell, the stored value of the phase change memory cell to be written is read and compared with the write data. When the comparison result indicates a mismatch, a write current is supplied. Each time this writing is repeated, the write current amount is increased.

  This Patent Document 7 prevents erroneous reading of data even when the contact area between the lower electrode and the phase change element varies in the phase change memory cell and the resistance value varies due to incomplete non-crystallization. Plan. That is, by repeating this write and write verify, the resistance value of the phase change memory cell in the reset state is set to a predetermined value or more regardless of the contact area between the phase change element and the lower electrode. Reduce the variation in resistance value.

A configuration for performing writing and verifying in a phase change memory is shown in Patent Document 8 (Japanese Patent Laid-Open No. 2004-362761). In Patent Document 8, when writing into a low resistance set state of a phase change memory cell, the resistance value of the memory cell in the set state depends on the resistance value in the reset state, and therefore erroneous writing into the set state is not possible. Try to prevent it from happening. In Patent Document 8, the bit line voltage is monitored at the time of writing to the set state, and writing to the set state is stopped when the bit line voltage reaches a predetermined reference voltage. If the bit line voltage becomes lower than the reference voltage, it indicates that the memory cell to be written is in a low resistance set state. This suppresses variation in the resistance value of the set state after writing to the memory cell.
JP-A-10-302487 JP 2005-44454 A JP 2004-22112 A JP 2003-346484 A Japanese Patent Laid-Open No. 11-86575 JP 11-260084 A JP 2005-100617 A JP 2004-362761 A

  The above-mentioned patent documents 1 to 8 show configurations for stabilizing the writing of the flash memory, NROM or phase change memory. That is, in Patent Document 1, first, write verification is performed on a memory cell, and then data is written according to the verification result. At the time of rewriting after the write verify, the time width of the write pulse is adjusted to control the amount of charge injected into the floating gate. However, the configuration disclosed in Patent Document 1 is intended for a flash memory, and when writing is performed, floating charges (electrons) are injected, and the threshold voltage is different. For this reason, when rewriting, the cell state is different from the previous writing, so to reduce the variation in threshold voltage after writing, the write pulse width must be adjusted slightly. It is required to write. On the other hand, in the case of MRAM, in the case of writing failure, the memory cell after writing is in the same state as before writing and the starting state is the same. Therefore, as described in Patent Document 1, if the write pulse width is adjusted in small increments and the writing is repeated, the number of times of writing / writing verification increases on the contrary, and the writing time may become longer. Therefore, the configuration of Patent Document 1 cannot be applied to the MRAM as it is.

  In the configuration disclosed in Patent Document 2, charges are trapped in an insulating film in a rewritable memory cell (NROM cell), and the threshold voltage of the memory cell transistor is adjusted. Therefore, charges are accumulated in the insulating film at the time of writing, and the threshold voltage of this memory cell changes for each writing. Therefore, this Patent Document 2 cannot be applied as it is to a memory device in which a memory cell returns to a state before writing when a writing failure occurs like MRAM.

  In Patent Document 3, although a page program is shown, data is stored by changing the threshold voltage of the memory cell transistor by accumulating the charge of the floating gate. Therefore, as in Patent Documents 1 and 2, it cannot be directly applied to the data write configuration of the MRAM.

  Patent Document 4 shows a write verify in a flash memory. However, even in this case, the threshold voltage of the memory cell transistor changes for each writing. Therefore, similarly, the configuration of Patent Document 4 cannot be directly applied to the MRAM writing configuration.

  Patent Document 5 simply performs conversion and verification during the maximum program time in the test mode. In the test mode, the maximum program time during writing can be observed externally. Therefore, even in the configuration disclosed in Patent Document 5, the memory cell is a flash memory cell, and the threshold voltage of the memory cell changes with each writing. For this reason, the configuration of Patent Document 5 cannot be applied as it is to the configuration of the MRAM in which the memory cell at the time of write failure returns to the initial state (original state).

  In the configuration shown in Patent Document 6, when writing data, the write current is monitored to determine whether the writing is completed. Therefore, the configuration shown in Patent Document 6 cannot be applied to a configuration in which a current of the same magnitude flows in the bit line and the digit line regardless of the write data as in the toggle MRAM. In a spin-injection MRAM such as a spin-injection magnetization reversal writing spin-torque transfer RAM, the direction in which the write current flows changes according to the logical value of the write data. Therefore, the configuration shown in Patent Document 6 cannot be applied to the MRAM as it is.

  Patent Document 7 shows writing and verifying of a phase change memory cell. In this phase change memory cell, the resistance value in the high resistance reset state depends on the resistance value in the low resistance set state, and the resistance value of the memory cell in the set state is the resistance of the memory cell in the reset state. Depends on the value. In the MRAM, there is no direct dependency between the resistance value of the memory cell before data writing and the resistance value of the memory cell after data writing. Therefore, in the MRAM, when a configuration in which the magnitude of the write current is changed for each write verify is used, the write current is supplied even after the writing is completed, and a state where writing is performed unnecessarily occurs. . For this reason, the writing sequence of Patent Document 7 cannot be applied to the MRAM as it is.

  In the configuration disclosed in Patent Document 8, the bit line voltage of the phase change memory cell is changed from a predetermined reference voltage. Therefore, when a constant current flows regardless of the writing state as in the toggle MRAM, the configuration shown in Patent Document 8 cannot be applied. Similarly, in the spin injection type MRAM, the configuration of Patent Document 8 showing the write sequence of the phase change memory in which the direction of the current flowing through the bit line is different for each write data and the bit line current flows in one direction is It cannot be applied to.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an MRAM that can accurately write data.

  Another object of the present invention is to provide a single-axis disturb-free MRAM such as a toggle MRAM or a spin injection type MRAM that can stably write data.

  In summary, the magnetic memory (nonvolatile magnetic memory) according to the present invention performs data writing and verification at the time of data writing. If a data write failure is detected during this verify, the memory cell is in the same state as before writing, and rewriting is performed from the same state.

  That is, in one embodiment of the present invention, a magnetic memory includes a plurality of memory cells, a write system circuit that writes write data to a write target memory cell among the plurality of memory cells, A write control circuit for comparing the storage data to be written and the write data is provided. Each of the plurality of memory cells includes a variable magnetoresistive element, and stores data according to the resistance value of the variable magnetoresistive element. The write control circuit compares the stored data of the memory cell to be written with the write data after the data is written to the memory cell to be written. In accordance with the comparison result, the write circuit is selectively written to the write target memory cell. When the memory cell to be written is rewritten, it is rewritten from the same initial state as before writing.

  In the present invention, verifying whether writing has been performed correctly is performed. Therefore, it is possible to suppress the occurrence of defective data writing and to realize highly reliable data writing.

  In addition, the memory cell in which writing is defective is rewritten from the same state as the previous writing. Therefore, in one embodiment, by adjusting the write condition after verification for each write, rewrite can be performed according to variations in the characteristics of the memory cell, and accurate rewrite can be realized. it can.

[Principle configuration]
Configuration of variable magnetoresistive element of memory cell 1:
FIG. 1 is a diagram schematically showing the structure of an MTJ (Magnet Tunneling Junction) element of a toggle MRAM cell used as a variable magnetoresistive element VR included in a memory cell. In FIG. 1, the variable magnetoresistive element VR includes a free layer 1, a pinned layer 2, and a tunnel barrier layer 3 provided between the free layer 1 and the pinned layer 2. The free layer 1 includes ferromagnetic films FM1 and F2 having substantially the same magnetic moment, and a nonmagnetic film AF provided between the ferromagnetic films FM1 and FM2.

  The free layer 1 is an antiparallel coupling element (SAF) having a three-layer structure in which two ferromagnetic films FM1 and F2 sandwich a nonmagnetic layer AF. In the free layer 1, the nonmagnetic layer AF functions as an antiferromagnetic coupling layer. The ferromagnetic films FM1 and FM2 have opposite magnetization directions (anti-parallel states) due to exchange coupling in a state where no magnetic field is applied.

  The pinned layer 2 is composed of, for example, a ferromagnetic film and an antiferromagnetic film, and the magnetization direction is fixed regardless of the direction of the applied magnetic field due to the antiferromagnetic exchange coupling. The resistance value of the variable magnetoresistive element VR (MJT element: sub-chenko MJT element) differs depending on whether the magnetization directions of the ferromagnetic film FM2 and the pinned layer 2 are the same direction (parallel state) or antiparallel state. . This resistance value is made to correspond to binary information.

  In a state where no magnetic field is applied, the magnetization directions of the free layer 1 and the pinned layer 2 do not change. Also, information is simply stored by the magnetization direction. Therefore, there is no influence of leakage current or the like, and data can be stored in a nonvolatile manner.

  FIG. 2 is a diagram schematically showing the arrangement of the variable magnetoresistive elements VR in the array. A bit line BL and a digit line DL are provided for the variable magnetoresistive element VR. The bit line BL and the digit line DL are provided so as to be orthogonal to each other. The variable magnetoresistive element VR is arranged so that the easy axis XE of the variable magnetoresistive element VR forms an angle of substantially 45 ° with the bit line BL and the digit line DL. Usually, in a state where no magnetic field is applied, the magnetization direction of the variable magnetoresistive element VR is along the direction of the easy axis XE. A hard magnetization axis XH exists in a direction orthogonal to the easy magnetization axis XE.

  FIG. 3 is a diagram showing a magnetization rotation sequence of the MJT element when data is written to the toggle MRAM cell. Hereinafter, the data write operation of the memory cell will be described with reference to FIG.

  First, in period # 0, no current flows through digit line DL and bit line BL. Therefore, in the variable magnetoresistive element VR, the magnetization direction of the free layer is set and maintained according to the easy magnetization axis XE.

  In period # 1, a current is supplied only to digit line DL. Thereby, the magnetic field H1 is generated along the bit line extending direction. By this magnetic field H1, exchange coupling is broken in the free layer (spin flop state), and the combined magnetic field of the two ferromagnetic films (FM1, FM2) in the free layer is in the same direction as the induced magnetic field H1.

  In period # 2, a current is further passed through bit line BL while a current is passed through digit line DL. In this case, the magnetic field H2 is generated in a direction parallel to the digit line extending direction by the current of the bit line BL. The magnetizations of the two ferromagnetic films of the free layer rotate so that the combined magnetic field of these magnetic fields H1 and H2 and the combined magnetic field of the free layer are in the same direction.

  In period # 3, the current of digit line DL is cut off, and the current is allowed to flow only to bit line BL. In this case, only the magnetic field H2 is generated in a direction parallel to the digit line DL. Therefore, the combined magnetic field of the free layer becomes the same direction as the induced magnetic field H2 of the bit line current, and the magnetization of the free layer further rotates.

  In the period # 4, the supply of the current of the bit line BL is cut off. At this time, no current is supplied to the digit line DL. In this case, exchange coupling is dominant in the free layer, and the magnetization of the free layer is oriented and reversed in the direction of the easy axis XE.

  Therefore, in the period # 0 and the period # 4, the magnetization direction of the free layer is reversed. The resistance value of the variable magnetoresistive element VR (sub-chenko MJT element) is set by the magnetization directions of the ferromagnetic film FM2 of the free layer 1 and the pinned layer 2. Therefore, in period # 0 and period # 4, the resistance value of variable magnetoresistive element VR changes and binary data can be stored.

  As described above, in toggle MRAM, magnetization can be rotated by a unipolar current pulse, and data can be written accordingly. In this write sequence, the magnetization direction of the free layer is rotated by 180 ° in one write sequence regardless of the initial state of the variable magnetoresistive element. Therefore, when data is written to the memory cell, the stored data is read before writing, and the magnetization direction of the variable magnetoresistive element of the memory cell is reversed only when the stored data and the written data are different.

  In the variable magnetoresistive element, the easy axis of magnetization has an angle of 45 ° with respect to each of the bit line and digit line through which the write current flows. Therefore, since the bit inversion cannot be performed with only one current supply line, the problem of one-axis disturb does not occur. However, when the strength of the external magnetic field is strong, the magnetizations of the two ferromagnetic films of the free layer are both oriented in the direction of the external magnetic field, and when the magnetic field strength is reduced, these magnetizations are not always oriented in the original direction. Absent. Therefore, at the time of data writing, the optimum write magnetic field is larger than the magnetic field intensity necessary for the writing and smaller than the magnetic field intensity in which the magnetizations of the two ferromagnetic films of the free layer are directed in the same direction. Have.

  Further, at the time of data writing, a unipolar current pulse is used, and the configuration of the portion that generates the write current can be simplified.

Configuration of variable magnetoresistive element 2:
FIG. 4 is a diagram schematically showing another configuration of the variable magnetoresistive element. FIG. 4 shows the structure of an MRAM cell (spin injection MRAM) of the spin injection magnetization reversal writing system as the variable magnetoresistive element VR. The variable magnetoresistive element VR is composed of an MJT element (Magnetic Junction Tunneling element) and includes a free layer 11 and a pinned layer 12 and a tunnel insulating film 13 between the free layer 11 and the pinned layer 12.

  The free layer 11 and the pinned layer 12 are made of a ferromagnetic material. In this variable magnetoresistive element VR, when electrons flow from the pinned layer 12 into the tunnel insulating film 13, the spin directions of the electrons are aligned. By utilizing the spin torque action of the aligned electrons at this time, the direction of the spin of electrons in the free layer 11 is aligned and the magnetization direction is set. Also in this MJT element, the resistance value differs depending on the magnetization directions of the free layer 11 and the pinned layer 12, and data is stored by this resistance value.

  In the following description, a current magnetic field inversion type magnetoresistive element is referred to as an MTJ element, and a spin injection magnetic field inversion type magnetoresistive element is referred to as an MJT element.

  FIGS. 5A and 5B are diagrams schematically showing the flow of current when data is written in the MTJ element shown in FIG. In FIG. 5A, a write current Iw flows from the pinned layer 12 toward the free layer 11. In this case, the electrons e flow from the free layer 11 to the pinned layer 12. When the spin direction is different from the spin polarization direction of the pinned layer 12, the electrons e are reflected by the tunnel insulating film 13 and change the spin direction of electrons in the free layer 11 in the direction opposite to that of the pinned layer 12. Electrons e having the same spin polarization as the spin polarization direction of the pinned layer 12 pass through the pinned layer 12. Therefore, in the free layer 11, the magnetization direction is set in the direction opposite to the magnetization direction of the pinned layer 12 by the transmission of the spin torque.

  In this state, the magnetization directions of the free layer 11 and the pinned layer 12 are antiparallel, which is a high resistance state. This state is associated with, for example, a state where data “H” (logic high level) is stored.

  In FIG. 5B, a write current Iw flows from the free layer 11 toward the pinned layer 12. In this case, electrons e flow from the pinned layer 12 to the free layer 11. The electrons e are oriented in the spin polarization direction of the pinned layer 12. Therefore, the electrons e injected into the free layer 11 through the tunnel insulating film 13 have the same spin polarization direction as the spin polarization direction of the pinned layer 12. Therefore, the free layer 11 is magnetized in the same direction as the magnetization direction of the pinned layer 12. This state is a low resistance state, and is associated with, for example, a state in which data “L” (logic low level) is stored.

  At the time of data reading, a read current is passed from the free layer 11 toward the pinned layer 12. In this case, the read current is made sufficiently smaller than the write current so that the magnetization direction of the free layer 11 is not reversed by the read current.

  In the case of the variable magnetoresistive element VR shown in FIG. 4, the current-induced magnetic field is not used during data writing. That is, in the spin injection magnetization reversal writing type MRAM cell, only a current is supplied to the selected memory cell. Therefore, in the memory cell in the half-selected state, no write current flows and no leakage magnetic field exists, so that the problem of uniaxial disturbance is sufficiently suppressed.

  Both the MTJ element and the MJT element can constitute a memory that does not cause uniaxial disturbance. In the present invention, in particular, data writing is stabilized in such a one-axis disturb-free MRAM.

  FIG. 6 is a diagram showing an overall principle configuration of a magnetic memory according to the present invention. In FIG. 6, the magnetic memory includes a memory cell array 20 in which memory cells MC are arranged in a matrix. This memory cell MC may have a configuration including any of the MTJ element and the MJT element shown in FIGS. 1 and 4 as a memory element. The present invention can be applied to both the toggle MRAM cell shown in FIG. 1 and the spin injection MRAM cell shown in FIG.

  The magnetic memory further includes a write system circuit 22 that writes data to the memory cell MC, a read system circuit 23 that reads data from the memory cell, and a write circuit that controls the write operation of the write system circuit 22. Including a control circuit 24.

  Write system circuit 22 supplies a write current for writing data to a write target memory cell in accordance with write data WD. Therefore, the memory cell MC has a different internal configuration depending on the toggle MRAM cell and the spin injection MRAM cell. Here, this write circuit 22 simply indicates that the resistance value of the variable magnetoresistive element of the memory cell MC is set by supplying a write current to the memory cell MC to be written. . A specific configuration of the write circuit 22 will be described in detail in a specific embodiment described later.

  Read system circuit 23 supplies a read current to the selected memory cell at the time of data reading, and reads the stored data of the memory cell in accordance with this current value. That is, in the memory cell, the amount of current flowing varies depending on the resistance value of the variable magnetoresistive element. This amount of current is detected in read system circuit 23 to generate read data RD.

  Write control circuit 24 reads stored data RD from memory cell MC to be written through read system circuit 23, and determines whether the logic levels of read data RD and write data WD match or not. When the determination result indicates a write failure, writing is performed on the memory cell to be written according to the write data. The configuration of the write control circuit 24 will also be described in detail later in each embodiment described later.

  FIG. 7 is a flowchart showing a write operation when the magnetic memory shown in FIG. 6 is a toggle MRAM. FIG. 8 is a flowchart showing the data writing operation when the magnetic memory shown in FIG. 6 is a spin injection type MRAM. The write operation sequence of the magnetic memory shown in FIG. 6 will be described below with reference to FIGS. 7 and 8 respectively.

  First, a data write sequence in the case where the magnetic memory shown in FIG. 6 is a toggle MRAM will be described with reference to FIG.

  The write control circuit 24 monitors an external command (not shown) and determines whether data writing is designated (step S1). The command is monitored until data write is specified and waits for a write command to be given.

  When data writing is designated, write control circuit 24 drives read system circuit 23 to read data RD of the memory cell to be written in memory cell array 20 (S2).

  Next, it is determined whether the logical level of the read data RD and the write data WD is the same (step SS3). When the storage data RD of the write target memory cell MC is the same as the logical value of the write data WD, writing to the write target memory cell is not performed.

  On the other hand, if the logical values of write data WD and read data RD are different, data is written to the memory cell to be written (step S4). At the time of data writing, write control circuit 24 drives write system circuit 24 according to the determination result.

  After the data is written to the write target memory cell MC by the write system circuit 22, the write control circuit 24 again reads the data stored in the write target memory cell (step S5). In step S5, the same operation as the pre-read in step S2 is performed. Thereafter, the process returns to step S3 again to determine whether the logical values of the read data RD and the write data WD match or do not match. These operations from Step S3 to Step S5 are repeatedly executed until the logical values of the write data WD and the read data RD match.

  Next, a data write sequence when the magnetic memory shown in FIG. 6 is a spin injection type RAM will be described with reference to FIG.

  The write control circuit 24 monitors an external command and determines whether a command for instructing writing has been given (step S10).

  When data writing is instructed, write system circuit 22 writes data to memory cell MC to be written in memory cell array 20 under the control of write control circuit 24 (step S11). ). In this case, the direction of the current flowing through the MJT element of the memory cell MC is set according to the logical value of the write data.

  After completion of writing, the read system circuit 23 reads the data stored in the memory cell to be written under the control of the write control circuit 24 (step S12).

  Next, the write control circuit 24 determines whether the logical values of the read data RD and the write data WD match (step S13).

  If the determination result indicates coincidence, the writing of data to the write target memory cell is terminated. On the other hand, when the logical values of the write data and the read data are different, the process returns to step S11, and the data is written into the memory cell to be written. These verify operations from step S11 to step S13 are repeatedly executed until the logical values of the read data RD and the write data WD of the memory cell to be written match.

  As shown in FIG. 7 and FIG. 8, at the time of data writing, after detecting that the storage data of the write target memory cell matches the logical value of the write data, Stop writing to. Therefore, data can be reliably written into the memory cell to be written, and the reliability of data writing can be guaranteed.

  FIG. 9A to FIG. 9C are diagrams showing the write characteristics and defect occurrence rate of the MRAM cell. 9A to 9C, the upper graph shows the write characteristics of the memory cell, and the lower side shows the probability of occurrence of a defect. In the figures showing the write characteristics and the probability of occurrence of defects, the magnitudes of the write magnetic fields are shown to coincide. 9A to 9C show rewriting conditions for a cell having a failure occurrence probability of 1 FIT. Writing conditions with a probability of occurrence of defects greater than 1 FIT are indicated by hatching. 1 FIT indicates that a defect occurs once in 10E5 hours (100,000 hours).

  At the time of rewriting, the MRAM cell is in the same state as at the previous writing (the magnetization direction is parallel or antiparallel). An MRAM cell basically uses the magnetic polarization of a magnetic material. In the spin polarization of electrons that are the source of this magnetic polarization, the direction of spin precession changes stochastically due to the influence of heat. Therefore, as shown in FIGS. 9A to 9C, even if writing is performed under the same conditions, the probability of writing failure occurring by increasing the number of writings by this probability theory. May be reduced.

  In addition, by changing the write condition for each rewrite, the condition for reliably writing the memory cell is set when writing from the same state of each MRAM cell (MJT element and MTJ element). Thus, writing can be performed reliably.

  When the write condition is changed, the variable magnetoresistive element of the memory cell is not written from the intermediate state between the antiparallel state and the parallel state of the magnetization direction, but in the parallel state or antiparallel state before writing. Writing is performed from the state. Therefore, the initial state at the time of rewriting is the same, and there is no need to consider the problem of overwriting unlike the flash memory cell. Further, it is not necessary to perform writing that gradually changes the threshold voltage in small increments in order to eliminate this overwriting. Writing can be performed by sequentially changing the writing conditions from the optimum value at the time of writing, and accurate writing can be performed in a short time.

  As described above, according to the present invention, at the time of data writing, a verify operation is performed as to whether write data has been written correctly. Therefore, accurate writing can be ensured even when the characteristics of the memory cell change.

[Embodiment 1]
FIG. 10 schematically shows an overall configuration of the toggle MRAM according to the first embodiment of the present invention. In FIG. 10, in the memory cell array 20, memory cells MC are arranged in a matrix. Bit lines BL are provided corresponding to the columns of the memory cells, and digit lines DL and word lines WL are provided corresponding to the rows of the memory cells MC.

  Memory cell MC includes a variable magnetoresistive element VR (MTJ element) and an access transistor TRS connected in series with the variable magnetoresistive element VR. Access transistor TRS is rendered conductive when a corresponding word line WL is selected, and couples variable magnetoresistive element VR to a source line (indicated by a ground node). At the time of data writing, word line WL is in a non-selected state, and access transistor TRS is in a non-conductive state. Variable magnetoresistive element VR is arranged to correspond to the intersection of digit line DL and bit line BL. Digit line DL has one end connected to the power supply node, and bit line BL also has one end coupled to the power supply node.

  Write control circuit 24 decodes a command applied via pad PAD, generates a write instruction signal Write and a read instruction signal Read, and a write bit according to an operation mode instruction signal from command decoder 62 A timing generator 64 that generates timing control signals such as a line drive signal W_BL and a write digit line drive signal W_DL; data read from a selected memory cell of the memory cell array 20 via a read amplifier 58; and an input data latch 65 A comparator 66 is provided for comparing the given data.

  Timing generator 64 is formed of, for example, a sequence controller, and controls data write, write verify, and data read operations according to a predetermined sequence. In FIG. 10, the timing generator 64 is shown to generate a control signal related to writing.

  Write circuit 20 includes an X decoder 50 and a DL driver / WL driver 52 provided for digit line DL and word line WL, and a bit line driver 56 and a Y decoder 54 provided for bit line BL.

  The X decoder 50 decodes the internal address signal ADD (X address signal) from the address latch 69, and generates a signal designating the addressed memory cell row.

  DL driver / WL driver 52 drives digit line DL and word line WL according to the memory cell row designation signal from X decoder 50 and the write mode instruction signal from the timing generator. At the time of data writing, DL driver / WL driver 52 forms a discharge path of digit line DL corresponding to the selected memory cell row. As a result, a current flows through the digit line DL of the selected memory cell row from the power supply node to the ground node via the DL driver. The WL driver drives a word line WL arranged corresponding to the addressed memory cell row to a selected state during data reading. Accordingly, access transistor TRS is rendered conductive in the selected memory cell, and a path through which a current flows is formed between corresponding bit line BL and source line (ground node).

  The Y decoder 54 receives the internal address signal ADD (Y address signal) from the address latch 69 and generates a signal for selecting the addressed memory cell column of the memory cell array 20.

  The bit line driver 56 discharges the selected bit line at the time of data writing. When the bit line BL is not selected, the bit line driver 56 maintains the unselected bit line BL at the power supply voltage level. At the time of data reading, bit line driver 56 is in an output high impedance state.

  When reading data, read amplifier 58 compares the current flowing through the selected bit line with a reference value (voltage), and generates an internal signal indicating data stored in memory cell MC. As an example, the read amplifier compares a voltage corresponding to a current flowing through the selected bit line with a reference voltage.

  A comparison reference voltage in the read amplifier 58, a reference voltage that defines the amount of discharge current of the bit line driver 56, and a reference voltage that defines the amount of discharge current of the digit line DL of the DL driver are each generated from the Vref generation circuit 60. .

  Input data latch 65 takes in input data DI applied to pad PAD and generates internal write data. Output data latch 67 takes in the data read from read amplifier 58 and outputs it as external read data DO via the corresponding pad. The address latch 69 latches an address signal AD given from the outside through a pad, and generates an internal address signal AD (X and Y address signals). The latch timing of these latches is set by the timing generator 64. When the command specifies an access mode (data write or read mode), these latches 65, 67 and 69 are in a latched state under the control of the timing generator 64.

  FIG. 11 is a diagram more specifically showing the configuration of the main part of the toggle MRAM shown in FIG. FIG. 11 representatively shows a configuration of a portion related to bit line BL and digit line DL provided in memory cell array 20.

  In FIG. 11, X decoder 50 includes a digit line decode circuit 70 provided corresponding to digit line DL. This digit line decode circuit 70 generates an AND gate G1 for generating an activation signal at the time of writing, an AND gate G2 for decoding the X address signal XADD, and corresponding digit lines according to output signals of these AND gates G1 and G2. A NAND gate NG1 that generates a signal to be selected is included.

  AND gate G1 receives write digit line drive signal W_DL, output signal P / F of comparator 66, and write instruction signal Write. AND gate G2 receives X address signal XADD, and generates an active signal when X address signal XADD designates a corresponding digit line address.

  NAND gate NG1 generates an active state (L level) signal when the output signals of AND gates G1 and G2 are both in an active state (H level).

  The DL driver included in the DL driver / WL driver 52 includes a digit line drive circuit 72 provided for each digit line DL. Digit line drive circuit 72 discharges digit line DL when the output signal of corresponding X decode circuit 70 is at L level. Specifically, digit line drive circuit 72 has inverter circuits IVK1 and IVK2 that receive the output signal of NAND gate NG1, respectively, and a p-channel MOS transistor (insulated gate) that couples the corresponding digit line DL to the power supply node in accordance with the output signal of inverter circuit IVK1. Type field effect transistor) PQ1 and N channel MOS transistor NQ1 coupling digit line DL to the ground node in accordance with the output signal of inverter circuit IVK2.

  Inverter circuit IVK1 receives the voltage on the high-side power supply node and the voltage on the low-side power supply node (ground node) as operating power supply voltages. Inverter circuit IVK2 receives reference voltage Vref as a high-side power supply voltage. Therefore, the amplitude of the output signal of the inverter circuit IVK2 is the reference voltage Vref. By applying reference voltage Vref as an operating power supply voltage to inverter circuit IVK2, the level of the gate voltage of MOS transistor NQ1 is adjusted. As a result, the current driving capability of MOS transistor NQ1 is adjusted, and the amount of current flowing through digit line DL is adjusted.

  In digit line drive circuit 72, when the output signal of X decode circuit 70 is at L level, the output signals of inverter circuit IVK1 and inverter circuit IVK2 are at H level. In this state, MOS transistor PQ1 is turned off and MOS transistor NQ1 is turned on. MOS transistor NQ1 receives a signal of reference voltage Vref level at its gate, and discharges digit line DL with a current driving force defined by reference voltage Vref (one end of digit line DL is coupled to a power supply node). ing). A magnetic field is induced by the current flowing through the digit line.

  When the output signal of X decode circuit 70 is at H level, the output signals of inverter circuits IVK1 and IVK2 are both at L level. In this state, MOS transistor PQ1 is turned on and MOS transistor NQ1 is turned off. Therefore, both ends of digit line DL are coupled to the power supply node and maintained at the power supply voltage (VDD) level. In this state, no current flows through the digit line DL, so no magnetic field is induced.

  Y decoder 54 includes a decode control circuit 73 provided in common to the bit lines of memory cell array 20 and a Y decode circuit 74 provided corresponding to each bit line BL. Decode control circuit 73 receives OR gate G5 receiving verify read activation signal VFREN and read instruction signal Read, write bit line drive signal W_BL, output signal P / F of comparator 66, and write instruction signal Write. An AND gate G3 is included.

  Verify read activation signal VFREN is activated at the time of pre-read and at the time of write verify after writing. When normal data reading is designated, read instruction signal Read is activated (driven to H level), and verify read activation signal VFREN is activated when a verify operation (including pre-read) at the time of writing is performed. (Driven to H level). Therefore, a signal that is activated when data in memory cell MC is read is generated from OR gate OG1.

  AND gate G3 generates an active state (H level) signal when all applied signals are in an active state (H level). Therefore, the AND gate G3 generates a signal that defines a period during which a write current flows through the bit line during data writing.

  Y decode circuit 74 includes an AND gate G4 receiving Y address signal YADD, and a NAND gate NG2 receiving output signals of AND gates G3 and G4. Therefore, when Y address signal YADD designates corresponding bit line BL, Y decode circuit 74 outputs a signal that is in an active state while a write current is supplied to the corresponding bit line.

  Bit line driver 56 includes a bit line drive circuit 76 provided corresponding to each bit line BL. Bit line drive circuit 76 inverts the output signal of OR gate OG1 of decode control circuit 73, NAND circuit NK1 receiving the output signal of inverter IV3 and the output signal of NAND gate NG2, and the output of OR gate OG1 It includes a NOR circuit NRK1 that receives the signal and the output signal of NAND gate NG2. NAND circuit NK1 receives the power supply voltage and the ground voltage as the high-side and low-side power supply voltages, respectively. The NOR circuit NRK1 receives the reference voltage Vref as a high-side power supply voltage. Therefore, the amplitude of the output signal of the NAND circuit NK1 is the power supply voltage VDD level, while the amplitude of the output signal of the NOR circuit NRK1 is the reference voltage Vref level.

  Bit line drive circuit 76 further includes a P channel MOS transistor PQ2 that couples bit line BL to the power supply node according to the output signal of NAND circuit NK1, and an N channel that couples bit line BL to the ground node according to the output signal of NOR circuit NRK1. MOS transistor NQ2 is included.

  At the time of data writing, the output signal of OR gate OG1 is at L level, and accordingly, the output signal of inverter IV3 is at H level. When a write current is passed through the selected bit line BL, the output signal of the NAND gate NG2 is at L level. In this state, the output signal of the NAND circuit NK1 becomes the H level of the power supply voltage level, and the output signal of the NOR circuit NRK1 becomes the H level of the reference voltage Vref level. Therefore, MOS transistor PQ2 is turned off and MOS transistor NQ2 is turned on. Accordingly, bit line BL is discharged via MOS transistor NQ2 (one end of bit line BL is coupled to the power supply node). The amount of current flowing from the power supply node to the ground node via bit line BL is set by the voltage applied to the gate of MOS transistor NQ2, that is, the voltage level of reference voltage Vref.

  At the time of data writing, the bit line BL of the non-selected column has the output signal of the inverter IV3 at the H level and the output signal of the NAND gate NG2 at the H level, so that the MOS transistor PQ2 becomes conductive and the bit line BL Line BL is coupled at both ends to the power supply node.

  In the configuration shown in FIG. 11, read amplifier 58 includes a sense amplifier circuit 78 provided corresponding to each bit line BL. The sense amplifier circuit 78 compares the voltage of the bit line BL with the read reference voltage VREFR, the output signal of the OR circuit OG1 included in the decode control circuit 73, and the AND gate G4 included in the Y address decode circuit 74. And an AND gate G5 for generating a sense activation signal EN for activating the comparison circuit CMP.

  At the time of data reading, the output signal of NAND gate NG2 of decode circuit 74 is at H level. Therefore, in bit line drive circuit 76, the output signal of NOR circuit NRK1 is at L level, and MOS transistor NQ2 is turned off. At the time of data reading, the output signal of OR gate OG1 becomes H level, and the output signal of inverter IV3 becomes L level. Accordingly, the output signal of NAND circuit NK1 attains H level, and MOS transistor PQ2 is turned off.

  At the time of data reading, one end of bit line BL is coupled to the power supply node, and bit line drive circuit 76 enters an output high impedance state. The amount of current flowing through bit line BL is determined by the amount of current discharged through variable resistance element VR of memory cell MC and an access transistor (not shown). In sense amplifier circuit 78, the data stored in selected memory cell MC can be read by comparing the voltage of bit line BL with read reference voltage VREFR.

  Note that the sense amplifier circuit 78 is in an output high impedance state when the comparison circuit CMP is inactive, and does not adversely affect data reading from the bit line of the selected column.

  Comparator 66 includes an EXOR gate EG that receives the output signal of output data latch 67 that latches the output signal of sense amplifier circuit 78 and the input data latched by input data latch 65. The EXOR gate EG is a mismatch detection gate, and when the logical values of the latch data of the output data latch 67 and the input data latch 65 are different, the output signal P / F is set to the H level.

  Output data latch 67 outputs the data read from sense amplifier circuit 78 as external read data DO in the read mode for reading data to the outside. The path switching between the internal reading and the external reading of the output data latch 67 is executed by the timing generator 64 although the path is not clearly shown.

  The output signal P / F of the comparator 66 is also supplied to the timing generator 64. Timing generator 64 sets the write sequence in accordance with the operation mode instruction signal from command decoder 62 and verify result instruction signal P / F.

  Since command decoder 62 and address latch 69 correspond to the configuration shown in FIG. 10, detailed description thereof will not be repeated.

  FIG. 12 is a timing chart showing an operation at the time of data writing of the toggle MRAM shown in FIG. Hereinafter, the data write operation of the toggle MRAM shown in FIG. 11 will be described with reference to FIG.

  At the time of data writing, write data is given to the input data latch 65 and a write instruction (write command) is given to the command decoder 62. The address latch 69 is given a write address. In accordance with this write instruction, command decoder 62 sets write instruction signal Write to an active state. Read instruction signal Read is in an inactive state (L level).

  The memory device is a toggle MRAM, and in order to prevent data inversion and to prevent erroneous data from being written, the storage data in the memory cell to be written is read before the first writing in accordance with the write address. Executed. The timing generator 64 activates the verify read activation signal VFREN at the time of this pre-read. Accordingly, in decode control circuit 73, the output signal of OR gate OG1 attains an H level. In this state, bit line drive circuit 72 is in an output high impedance state. A word line is driven to a selected state in accordance with an X address signal XADD supplied from an address latch 69 by a word line drive circuit not shown. Next, in accordance with the Y address signal YADD, the output signal of the AND gate G4 of the Y decode circuit 74 becomes H level. Responsively, sense activation signal EN is activated, and sense amplifier circuit 78 compares a voltage corresponding to the current flowing through bit line BL with read reference voltage VREFR, and generates internal read data according to the comparison result.

  When the stored data of the memory cell to be written read from sense amplifier circuit 78 does not match the logical value of the externally written data, output signal P / F of comparator 66 is at the H level. Accordingly, NAND gates G1 and G3 are enabled in decode circuits 70 and 74, respectively. Timing generator 64 sequentially activates write digit line drive signal W_DL and write bit line drive signal W_BL in accordance with the H level verify result instruction signal P / F.

  During the H level period of write digit line drive signal W_DL, current flows from the power supply node to the ground node through corresponding digit line DL by X decode circuit 70 and digit line drive circuit 72. Bit line BL is discharged by Y decode circuit 74 and bit line drive circuit 76 in accordance with write bit line drive signal W_BL.

  When this writing is completed, the timing generator 64 activates the verify read activation signal VFREN again. Even in this case, when a write failure to memory cell MC occurs and the logical values of the write data and the stored data in the memory cell do not match, verify result instruction signal P / F is at the H level. Therefore, again, the timing generator 64 sequentially activates the drive signals W_DL and W_BL.

  After the completion of the second writing, a write verify operation is performed again to determine whether data has been written correctly. When the memory cell is normally written, the read data from output data latch 67 and the logical value of the input data from input data latch 65 match, and verify result instruction signal P / F output from comparator 66 is obtained. Becomes L level. In this case, the timing generator 64 completes the writing. Next, the write instruction signal Write is driven to an inactive state.

  On the other hand, if it is determined that writing is defective in this write verify operation, writing is executed again. This writing and write verify are repeatedly executed until the data is normally written or a predetermined write trial condition is satisfied. The write trial condition will be described later in detail.

  In the comparator 66, the verification result instruction signal P / F may be maintained at the H level in the initial state (standby state). It is sufficient that the reset values of the output data latch 67 and the input data latch 65 are set to values having different initial logical values.

  FIG. 12 shows a 1-bit data write sequence. For example, when data is sequentially written to a plurality of addresses according to one write instruction as in burst write, the address latch 69 takes in the address ADD (see FIG. 10) given first, and writes sequentially from the head address. Data may be written by updating the address. In this case, pre-read and write verify are executed for each address.

  FIG. 13 is a diagram illustrating an example of a configuration of a portion related to one word line WL. X decoder 50 includes an X address decode circuit 80 provided for each word line WL. X address decode circuit 80 includes an AND gate G6 receiving X address signal XADD, and a NAND gate NG3 receiving an output signal of OR gate OG1 and an output signal of AND gate G6 included in the word line control circuit shown in FIG. The AND gate G6 is an AND type decode circuit, and outputs an H level signal when a corresponding word line is designated by the X address signal XADD. Therefore, NAND gate NG3 outputs an L level signal when data is read or selected. When the corresponding word line WL is in a non-selected state, the output signal of X decode circuit 80 is at H level.

  In the DL driver / WL driver 52, a word line drive circuit 82 is provided corresponding to each word line WL. Word line drive circuit 82 includes a P channel MOS transistor PQ3 and an N channel MOS transistor NQ3 receiving the output signal of NAND gate NG3 at each gate. The word line WL is connected to the gate of the access transistor TRS of the memory cell MC in the corresponding row. FIG. 13 representatively shows a 1-bit memory cell.

  In word line drive circuit 82, when the output signal of X address decode circuit 80 is at L level, P channel MOS transistor PQ3 conducts to drive word line WL to the power supply voltage level. Accordingly, access transistor TRS is rendered conductive in memory cell MC, and a path is formed through which current flows from bit line BL to source line (ground node) via variable resistance element VR.

  In the non-selected state, the output signal of X address decode circuit 80 is at H level, and word line WL is maintained at the ground voltage level by MOS transistor NQ3. In this state, access transistor TRS is non-conductive in memory cell MC, and the path through which current flows through the variable magnetoresistive element (MTJ element) is blocked.

  By using the word line drive circuit and the X address decode circuit as shown in FIG. 13, a current corresponding to the resistance value of variable resistance value VR can be passed through memory cell MC during data reading. .

[Modification 1]
FIG. 14 schematically shows a structure of a write / read unit of the toggle MRAM according to the first modification of the first embodiment of the present invention. 14, read gates RG0-RGn are provided for bit lines BL0-BLn, and write column select gates WG0-WGn are provided. Read column select gates RG0-RGn are rendered conductive when read column select signals RCSL0-RCSLn are activated. Write column select gates WG0-WGn are rendered conductive when write column select signals WCSL0-WCSLn are activated.

  Read column select gates RCSL0-RCSLn are commonly coupled to internal read data line ROL. Write column select gates WG-WGn are commonly coupled to internal write data line WIL. Read column selection signals RCSL0-RCSLn are generated in accordance with Y address signal YADD during data reading. Write column select signal WCSL0 is generated in accordance with Y address signal YADD during data writing.

  Read amplifier 90 is provided for internal read data line ROL, and write driver 92 is provided for internal write data line WIL.

  The read amplifier 90 has the same configuration as the sense amplifier circuit 78 shown in FIG. The write driver 92 also has the same configuration as the bit line drive circuit shown in FIG. The operations of read amplifier 90 and write driver 92 are performed in accordance with the output signal of decode control circuit 73 shown in FIG. 11 (the output signal of gate G4 receiving Y address signal YADD is always set to the selected state). .

  In the configuration shown in FIG. 14, it is not necessary to provide a sense amplifier circuit and a bit line drive circuit for each of bit lines BL0 to BLn, and the layout area is reduced.

  Data write and read operations are performed in the same manner as the toggle MRAM shown in FIG. Read column select gate RCSLi and write column select gate WCSLi corresponding to the selected column are driven to the selected state according to the Y address signal at the time of reading and writing.

  In the configuration shown in FIG. 14, the read amplifier 90 may be provided in common to the bit lines BL0 to BLn, and the write driver 92 may be provided on a one-to-one basis for each of the bit lines BL0 to BLn. The influence of the wiring resistance of internal write data line WIL on the bit line write current can be avoided, and the bit line write current can be generated accurately.

  In addition, digit line drive circuits are individually provided for digit lines in the same manner as word line drive circuits.

[Modification 2]
FIG. 15 is a diagram schematically showing an overall configuration of the spin injection MRAM according to the second modification of the first embodiment of the present invention. In the spin injection MRAM shown in FIG. 15, in the memory cell array 22, memory cells MC are arranged in a matrix, and word lines WL and digit lines DL are provided corresponding to the memory cell rows. A bit line BL and a source line SL are provided corresponding to each column of memory cells MC.

  In the spin injection MRAM, since the magnetization direction of the memory cell is set by spin injection, it is not particularly necessary to provide the digit line DL. However, the reversal of the magnetic field is assisted by applying a magnetic field in the direction of the hard axis of the variable magnetoresistive element (MJT element) VR by the current of the digit line DL. In the spin injection MRAM, the easy magnetization axis and the hard magnetization axis of the variable magnetoresistive element VR are arranged in parallel with the bit line and the word line, respectively.

  In this MRAM, a write line circuit 20 is provided with a source line decoder 100 and a source line driver 102 in order to pass a current between the bit line BL and the source line SL. The source line driver 102 and the bit line driver 56 determine the direction of current flowing between the bit line BL and the source line SL according to the logical value of the input data.

  In the write control circuit 24, a command decoder 112, a timing generator 114, and a comparator 116 are provided in the same manner as the toggle MRAM.

  In the spin injection type MRAM, pre-reading before writing is not necessary. The command decoder 112 further generates a comparison invalidation signal 1st_Write in order to write the determination result in the comparator 116 as invalid at the first writing. With this signal 1st_Write, the comparison result of the comparator 116 is invalidated during the first data writing period, and writing is performed regardless of the logical value of the write data and the data stored in the memory cell to be written. It is. However, even in the spin injection type MRAM, when pre-reading is performed, it is not necessary to generate the signal 1st_Write, and a writing sequence similar to that of the toggle MRAM is performed. The write control circuit having the same configuration can be applied to the toggle MRAM and the spin injection MRAM.

  The timing generator 114 generates the write pulse signal W_PULSE only for the write bit line drive signal W_BL. The write time is set by the write pulse signal W_PULSE.

  The other configuration of the MRAM shown in FIG. 15 is the same as the configuration of the toggle MRAM shown in FIG. 10, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  FIG. 16 is a diagram more specifically showing a configuration of a portion related to one bit line BL, one digit line DL, and one source line SL of the spin injection MRAM shown in FIG. In the spin injection type MRAM, the direction of current flowing between the bit line BL and the source line SL differs according to the logical value of the write data. In the first data writing, in order to stop pre-reading, the comparator 116 is further provided with an OR gate OG2 that receives the output signal of the EXOR gate EG and the comparison invalidation signal 1st_Write. A verify result instruction signal P / F is output from the OR gate OG2.

  Decode control circuit 73 receives input data from input data latch 65 and verify result instruction signal P / F from comparator 116 in order to change the direction of the bit line current in accordance with the logical value of the write data. An AND gate G7 is further provided. The output signal of AND gate G7 is applied to AND gate G3. AND gate G3 receives write pulse signal W_PULSE instead of write bit line drive signal W_BL. The configurations of the bit line drive circuit 76 provided in the bit line driver 56 and the Y address decode circuit 74 provided in the Y decoder 54 are the same as the configuration of the toggle MRAM shown in FIG. Numbers are assigned and detailed description thereof is omitted.

  The configuration of the digit line drive circuit 72 included in the digit line driver that drives the digit line DL and the configuration of the digit line decode circuit 70 included in the X decoder 50 are the same as those shown in FIG. The same reference numerals are assigned and detailed description thereof is omitted.

  Source line decoder 100 includes a source line decode circuit 122 provided corresponding to each source line SL, and a source line decode control circuit 120 provided in common to source lines SL. Source line decode control circuit 120 includes an inverter IV4 that inverts latch data of input data latch 65, an AND gate G8 that receives a write verify result instruction signal P / F and an output signal of inverter IV4. When write data is at L level and write verify result instruction signal P / F is at H level, indicating a write failure, AND gate G8 generates an H level signal.

  Source decode control circuit 120 further receives AND pulse G9 receiving write pulse signal W_PULSE, the output signal of AND gate G8, and write instruction signal Write, OR gate OG3 receiving read instruction signal Read and verify read activation signal VFREN. OR gate OG4 receiving the output signals of gates OG3 and G9. When data writing is performed, the AND gate G9 outputs an H level signal during the activation period of the write pulse signal W_PLUSE. OR gate OG3 has the same function as OR gate OG1 included in bit line decode control circuit 73, and outputs an H level signal when data is read. By using this OR gate OG3, source line SL is coupled to the ground node during data reading, and a path for current to flow from bit line BL to source line SL is formed.

  Source line decode circuit 122 includes an AND gate G10 receiving Y address signal YADD, and a NAND gate NG4 receiving the output signal of OR gate OG4 and the output signal of AND gate G10. The AND gate G10 functions as an AND type decode circuit, and outputs an H level signal when the Y address signal YADD designates a corresponding column.

  Source line driver 102 includes a source line drive circuit 124 provided corresponding to each source line SL.

  Source line drive circuit 124 includes inverter circuits IVK3 and IVK4 that each receive an output signal of NAND gate NG4, and a P-channel MOS that couples corresponding source line SL to a power supply node when the output signal of inverter circuit IVK3 is at L level. Transistor PQ4 and an N channel MOS transistor NQ4 for coupling corresponding source line SL to the ground node when the output signal of inverter circuit IVK4 is at the H level are included.

  Inverter circuit IVK3 receives the power supply voltage as a high-side power supply voltage. Inverter circuit IVK4 receives reference voltage Vref as a high-side power supply voltage. Therefore, when N channel MOS transistor NQ4 conducts, the amount of current flowing to the ground node via source line SL is controlled by reference voltage Vref.

  In the source line decoder 100 and the source line driver 102, the following operations are performed at the time of data writing. First, when verify result instruction signal P / F is at the L level and normal writing is indicated, the output signal of AND gate G8 is at the L level, and the output signal of AND gate G9 is accordingly at the L level. At the time of data writing, read instruction signal Read and verify read activation signal VFREN are both at L level. In this state, the output signal of OR gate OG4 is at L level, and the output signal of NAND gate NG4 is at H level. Therefore, in source line drive circuit 124, MOS transistor PQ4 is turned on and MOS transistor NQ4 is turned off. Thereby, source line SL is coupled to the power supply node.

  At this time, also in the bit line decoder, the output signal of AND gate G7 is at L level, and accordingly, the output signal of NAND gate NG2 is at H level. The output signal of the OR gate OG1 is at L level. Therefore, the output signal of the NAND circuit NK1 becomes L level and the output signal of the NOR circuit NRK1 becomes L level. Thereby, the bit line BL is maintained at the power supply voltage level.

  In a standby state or a non-selected state, Y address signal YADD does not specify corresponding bit line BL and source line SL. Therefore, in bit line decode circuit 74, the output signal of NAND gate NG2 becomes H level, and MOS transistor NQ2 is turned off. Further, the output signal of OR gate OG1 is at L level, and therefore the output signal of inverter circuit IV3 is at H level. Accordingly, the output signal of NAND circuit NK1 becomes L level, MOS transistor PQ2 is rendered conductive, and bit line BL is maintained at the power supply voltage level. Similarly for the source line, the output signal of NAND gate NG4 becomes H level, MOS transistor PQ4 is turned on, and MOS transistor NQ4 is turned off. Therefore, source line SL is also maintained at the power supply voltage level.

  The configuration of the word line selection decoding circuit and the word line drive circuit is the same as that shown in FIG. 13 except that the word line decoding circuit 80 performs an X address decoding operation during writing and reading. That is, the OR gate OG1 is not used in the configuration shown in FIG.

  At the time of data writing, verify result instruction signal P / F is at the H level. In this case, the potentials of bit line BL and source line SL differ depending on the logic level of the write data from input data latch 65.

(1) Writing H data:
In this case, first, for the bit line, the output signal of the AND gate G7 becomes H level. At the time of writing, the output signal of AND gate G3 becomes H level according to write pulse signal W_PULSE, and accordingly, the output signal of NAND gate NG2 becomes L level. Here, it is assumed that the corresponding bit line is selected. Accordingly, the output signal of NAND circuit NK1 attains H level, and MOS transistor PQ2 is turned off. The output signal of OR gate OG1 is at L level during data writing, and the output signal of NOR circuit NRK1 is at H level. Accordingly, MOS transistor NQ2 is rendered conductive, and bit line BL is coupled to the ground node via MOS transistor NQ2.

  On the other hand, for source line SL, the output signal of inverter IV4 is at L level, and the output signal of AND gate G8 is at L level. Therefore, this state is the same as the non-selected state or the standby state, and source line SL is coupled to the power supply node by source line drive circuit 124.

  For the digit line, the output signal of the digit line drive circuit 72 is at L level, and a current flows through the digit line DL from the power supply node to the ground node.

  Further, the corresponding word line is driven to a selected state according to a word line drive circuit (not shown), and access transistor TRS is turned on. Therefore, in this case, a current flows from the source line SL to the bit line BL. The write current for memory cell MC is controlled by the gate voltage of MOS transistor NQ2 included in bit line drive circuit 76, that is, reference voltage Vref.

(2) Writing L data:
In this case, for the bit line, the output signal of AND gate G7 is at L level, and accordingly, the output signal of NAND gate NG1 is at H level. Therefore, as in the standby state, MOS transistor PQ2 is turned on in bit line drive circuit 76, and bit line BL is coupled to the power supply node.

  Also in the case of the L data writing, the word line WL is driven to the H level, the digit line DL is driven to the selected state, and the digit line current flows.

  On the other hand, for the source line, the output signal of inverter IV4 becomes H level, and accordingly, the output signal of AND gate G8 becomes H level. When write pulse instruction signal W_PULSE becomes H level, the output signal of NAND gate NG4 becomes H level. Accordingly, in source line drive circuit 124, MOS transistor NQ4 is turned on and MOS transistor PQ4 is turned off. Therefore, in this state, a current flows from the bit line BL to the source line SL. At this time, the amount of current flowing through the memory cell MC is controlled by the high-side power supply voltage of the inverter IVK4 of the source line drive circuit 124, that is, the reference voltage Vref.

  At the time of data reading, for the bit line, the output signal of OR gate OG1 becomes H level, and accordingly, the output signal of NOR circuit NRK1 becomes L level. The output signal of inverter IV3 becomes L level, and accordingly, the output signal of NAND circuit NK1 becomes H level. As a result, MOS transistor PQ2 is turned off. That is, when reading data, bit line drive circuit 76 is in an output high impedance state.

  On the other hand, for the source line, in the source line decode control circuit 120, the output signal of the OR gate OG3 becomes H level. Accordingly, in source line decode circuit 122, the output signal of OR gate OG4 becomes H level, and the output signal of NAND gate NG4 becomes L level. Accordingly, in source line drive circuit 124, MOS transistor NQ4 is turned on and MOS transistor PQ4 is turned off. Therefore, source line SL is coupled to the ground node.

  At the time of data reading, the bit line of the selected column is coupled to the power supply node using a connection gate (not shown), whereby a current flows from the bit line BL to the source line SL, and the remaining current is applied to the sense amplifier circuit 78. Then, a comparison operation is performed. In this case, the sense amplifier circuit 78 may have a current source, and may be configured to supply the current of the current source to the selected bit line in accordance with the activation of the read activation signal.

  Therefore, also in the spin injection type MRAM as shown in FIG. 16, by using comparator 116, after data writing, a verify operation can be performed as to whether writing has been normally performed.

  In the memory cell in the selected column and non-selected row, access transistor TRS is non-conductive, and the path through which current flows between bit line BL and source line SL is blocked. In the memory cell of the selected row and the non-selected column, the bit line BL and the source line SL are maintained at the same power supply voltage level, and similarly, no current flows.

  FIG. 17 is a timing chart showing an operation at the time of data writing of the spin injection MRAM shown in FIG. Hereinafter, with reference to FIG. 17, an operation at the time of data writing of the spin injection type MRAM shown in FIG. 16 will be briefly described.

  Command decoder 112 drives write instruction signal Write to an active state in accordance with a write instruction command applied via pad PAD. At this time, the command decoder 112 drives the comparison invalidation signal 1st_Write to the active state.

  Timing generator 114 drives write digit line drive signal W_DL and write pulse signal W_PULSE to an active state at a predetermined timing in accordance with a write instruction from command decoder 112. In accordance with the activation of the comparison invalidation signal 1st_Write from the command decoder 112, the verification result instruction signal P / F from the comparator 116 is fixed at the H level.

  Therefore, a current flows through the digit line DL by the output signals of the digit line decoding circuit 70 and the digit line driver 72, and an auxiliary magnetic field is generated. As for the bit lines, the bit line BL corresponding to the selected column is written by the bit line decode circuit 74, the bit line decode control circuit 73, and the bit line driver 76. Depending on the value, it is coupled to a power supply node or a ground node. The bit line BL of the non-selected column is maintained by the bit line drive circuit 76 corresponding to the power supply voltage level.

  Similarly, for the source line SL, the source line of the selected column is connected to the ground node or the power supply node by the source line decode circuit 122, the source line decode control circuit 120, and the source line drive circuit 124 according to the logical value of the write data. Combined with The source line SL in the non-selected column is coupled to the power supply node by the source line drive circuit 124.

  In this state, a current flows between the bit line and the source line SL in a direction corresponding to the logical value of the write data, and data is written to the selected memory cell MC.

  When the predetermined period elapses, write digit line activation signal W_DL and write pulse signal W_PULSE are driven to an inactive state (L level). This write digit line activation signal W_DL only assists in changing the magnetization direction of the variable magnetoresistive element VR of the selected memory cell MC, and is driven to an inactive state at a timing earlier than the write pulse signal W_PULSE. Also good. In FIG. 17, the deactivation timing of write digit line activation signal W_DL indicates a reset period with a double-pointed arrow so that it may have a certain width in time.

  When this writing is completed (when write pulse signal W_PULSE is deactivated), comparison invalidation signal 1st_Write is driven to the L level. Further, after this writing, the timing generator 114 drives the verify activation signal VFREN to the active state for a predetermined period. When the verify activation signal VFREN is activated, in the bit line drive circuit 76, both the P channel MOS transistor and the N channel MOS transistor NQ2 are turned off, and the output high impedance state is obtained. Also in source line drive circuit 124, source line SL of the selected column is coupled to the ground node via N channel MOS transistor NQ4. Note that the word line WL is driven to a selected state by a word line drive circuit (not shown), and the access transistor TRS becomes conductive. Thereby, a path through which a current flows is formed between the bit line BL and the source line SL.

  A current flows through the bit line via a supply current (not shown) from the sense amplifier circuit 78 or a gate circuit connecting the bit line BL to the power supply node at the time of reading. This bit line current changes according to the data stored in the memory cell MC. The sense amplifier circuit 78 senses the voltage change or current change of the bit line BL. Here, sense amplifier circuit 78 is activated by activation of sense activation signal EN (only for the selected column).

  In the case of writing failure, verify result instruction signal P / F from comparator 116 is at the H level. Therefore, when the verify result signal VRFE is deactivated, the timing generator 114 again drives the write digit line activation signal W_DL and the write pulse signal W_PULSE to the active state in a predetermined sequence. Rewrite to the cell MC is executed.

  The verify operation after writing is executed again. When the verify operation is performed by the verify activation signal VRFE, when the write is normally performed, the verify result instruction signal P / F from the comparator 116 is at the L level. Thereby, the timing generator 114 gives a signal for inactivating the write instruction signal Write to the command decoder 112, and the data writing is completed. In this case, the standby state is established, and the bit line BL and the source line SL are maintained at the power supply voltage level by the bit line drive circuit 76 and the source line drive circuit 124. Therefore, the digit line DL is also maintained at the power supply voltage level by the digit line drive circuit 72.

  In this standby state, the verification result instruction signal P / F from the comparator 116 may be set to the initial state.

  Timing generator 114 is formed of, for example, a sequence controller, and in a predetermined sequence according to a write instruction signal or a read instruction signal from command decoder 112, write pulse signal W_PULSE, write digit line activation signal W_DL, and verify activation signal VFREN is generated (in consideration of the logic level of the verify result instruction signal P / F).

  The command decoder 112 generates a pulse signal in accordance with an externally applied command, and generates a write instruction signal Write and a read instruction signal Read by the timing generator 114 defining the inactivation timing of the pulse signal. be able to.

  As described above, according to the first embodiment of the present invention, in the magnetic memory (MRAM), after data writing, a verify operation as to whether writing has been normally performed is executed. Therefore, highly reliable data writing can be realized.

  Further, the MRAM cell returns to the initial state before writing in the case of writing failure. Therefore, even if rewriting is performed under the same writing conditions, the probability of writing failure is reduced by repeating the number of rewriting due to the influence of heat on the electron spin state, and reliable data writing is performed. Can be guaranteed. At this time, as described later in the embodiment, the write condition may be changed for each rewrite.

[Embodiment 2]
FIG. 18 is a timing diagram showing a write sequence of the spin injection MRAM according to the second embodiment of the present invention. Referring to FIG. 18, a description will now be given of the MRAM write sequence according to the second embodiment of the present invention. Here, the same operation is performed in both the toggle MRAM and the spin injection type MRAM as the MRAM (the toggle MRAM will be described later).

  The MRAM takes in the command CMD and the address signal AD from the outside in synchronization with the clock signal CLK. The internal operation cycle is also defined by this clock signal CLK.

  In a cycle starting from time T0, a write command is given as the command CMD, and an address signal AD0 is given as the external address signal AD.

  In accordance with this write command, write mode instruction signal φW is internally generated in the form of a one-shot pulse. In accordance with write mode instruction signal φW, write instruction signal Write is activated for a predetermined period. In accordance with write instruction signal Write, write digit line drive signal W_DL and write pulse signal W_PULSE are activated. In the first writing, the comparison invalidation signal 1st_Write is activated.

  At the time of writing, a busy / ready signal B / RZ is issued to the outside to indicate that writing is in progress.

  Next, in the cycle starting from time T0, when writing is completed, the write instruction signal Write is deactivated, and the comparison invalidation signal 1st_Write is deactivated. In response to the deactivation of write instruction signal Write, write verify activation signal VFREN is activated, and data is read from the memory cell to be written and the write data is compared with the internal read data. It is. In the case of writing failure, verify result instruction signal P / F is at the H level.

  In a cycle starting from time T1, write mode instruction signal φW is again applied in the form of a one-shot pulse in accordance with the H level verify result instruction signal P / F. As a result, writing is performed again for the same address, and then a write verify operation is performed. In the cycle starting from time T1, the busy / ready signal B / RZ is externally at H level, and access from the outside is prohibited during this cycle.

  If the verify result indicates that the writing has been performed normally, verify result instruction signal P / F attains the L level. In response, busy / ready signal B / RZ is set to the L level, and the access is permitted.

  Therefore, in a cycle starting from time T2, the processor (or controller) can access (write or read data) this MRAM.

  As shown in FIG. 18, when operating in synchronization with the clock signal CLK, the external processor (or controller) can issue an MRAM by issuing a busy / ready signal B / RZ to the outside during the internal write period. You can know the internal state of.

  When this write failure occurs, a write mode instruction signal φW is generated internally, and equivalently, an internal write command is issued, so that the same sequence can be written even during rewrite after write verify. Can be executed.

  FIG. 19 schematically shows structures of command decoder 112 and timing generator 114 of the spin injection MRAM according to the second embodiment of the present invention. This command decoder 112 corresponds to the command decoder 112 of the spin injection MRAM shown in FIG.

  In FIG. 19, a command decoder 112 takes in a command CMD from the outside in synchronization with the clock signal CLK and detects whether a write command is given, and an output signal and timing of the write command detection circuit 202 OR circuit 204 that receives rewrite instruction signal φWI from generator 114, and write activation circuit 206 that generates write instruction signal Write according to write mode instruction signal φW output from OR circuit 204 are included.

  The write command detection circuit 202 detects whether the command CMD is a write command at the rising edge of the clock signal CLK. The command CMD may be given as a combination of logic levels of a plurality of signals, or may be given as one decoded signal. When this write command detection circuit 202 detects a write command, it generates a one-shot pulse signal. Therefore, OR circuit 204 activates write instruction signal φW when an external write command is applied or when rewrite instruction signal φWI is applied from timing generator 210. Rewrite instruction signal φWI has the same pulse width as the pulse signal generated by write command detection circuit 202, and this rewrite instruction signal φWI is used as an internal write command.

  Write activation circuit 206 generates a pulse signal having a predetermined time width as write instruction signal Write in response to activation of write mode instruction signal φW.

  Command decoder 112 further includes a pre-read inhibit circuit 208 that generates comparison invalidation signal 1st_Write in accordance with write mode instruction signal φW. This pre-read inhibit circuit 208 generates a one-shot pulse signal having a time width similar to that of the write instruction signal Write in accordance with the activation of the write mode instruction signal φW, and is to be written at the first writing. The reading and comparison operation of data from the memory cells is prohibited, and writing is executed.

  The timing generator 114 corresponds to the timing generator 114 shown in FIG. Timing generator 114 includes a write current drive activation circuit 211 that generates write control signals W_DL and W_PULSE in accordance with write mode instruction signal φW from command decoder 200. The MRAM is a spin injection type MRAM, and the write current drive activation circuit 211 generates a write digit line drive signal W_DL and a write pulse signal W_PULSE at a predetermined timing in accordance with the write mode instruction signal φW.

  The timing generator 114 further responds to the deactivation of the write instruction signal Write from the command decoder 112 in accordance with the verify activation circuit 212 that generates the verify read activation signal VFREN and the verification result instruction signal P / F. A busy signal generation circuit 213 for generating a busy / ready signal B / RZ is included.

  Verify activation circuit 212 is formed of, for example, a circuit that generates a one-shot pulse signal, and activates verify read activation signal VFREN for a predetermined period in response to the transition of write instruction signal Write to inactivation. Maintain state.

  Busy signal generation circuit 213 generates busy / ready signal B / RZ in accordance with verify result instruction signal P / F in the write mode. If the busy / ready signal B / RZ is set to the H level when the busy state is indicated, the busy signal generation circuit 213 is configured by a buffer circuit. On the other hand, when this busy / ready signal B / RZ is set to L level when busy, the busy signal generation circuit 213 is formed of an inverting circuit.

Verify result instruction signal P / F is set to L level in the standby state.
Further, the timing generator 112 enters a through state when the verify read activation signal VFREN is activated, and rewrites according to the latch 214 that passes the verification result instruction signal P / F, the output signal of the latch 214, and the clock signal CLK. Including a pulse generation circuit 215 for generating a load instruction signal φWI.

  The latch 214 enters the latch state when the verify read activation signal VFREN is inactive. If the output signal of latch 214 is at the H level, pulse generation circuit 215 generates rewrite instruction signal φWI as an internal write command in the form of a one-shot pulse in synchronization with the rise of clock signal CLK. Even at the time of verification, writing can be executed with the same operation control as when an external command is applied. When the internal write instruction signal is issued, the pre-read operation is naturally stopped in the toggle MRAM. The verify operation in the previous write cycle corresponds to the pre-read operation at the time of rewriting, and the time of the write cycle is shortened.

  When writing is performed normally, verify result designating signal P / F is at L level, and pulse generation circuit 215 does not generate a pulse. Thus, it is possible to prevent the rewrite instruction signal φWI from being generated as an internal write command in the next cycle in which writing is normally performed.

  As described above, a verify operation is performed at the time of internal writing, and a rewrite instruction signal corresponding to the write command is generated internally at the time of writing failure. As a result, data can be reliably written. In addition, a busy / ready signal is issued to notify the external processor or controller of the internal state of the MRAM. Thereby, it is possible to reliably prevent access from the outside during a period in which data is rewritten in the MRAM.

[Example of change]
FIG. 20 schematically shows structures of command decoder 62 and timing generator 64 of the toggle MRAM according to the modification of the second embodiment of the present invention. In FIG. 20, a command decoder 62 receives an external command CMD in synchronization with a clock signal CLK and generates a write instruction detection signal φWF, and an internal write detection signal from a timing generator 64. (Rewrite instruction signal) includes a write activation circuit 224 that generates a write instruction signal Write according to φWI and a clock signal CLK.

  When the rewrite instruction signal φWI is activated, the write activation circuit 224 generates a write instruction signal Write having a predetermined time width in synchronization with the fall of the clock signal CLK.

  The timing generator 64 includes a write current drive activation circuit 231 that generates a write digit line drive signal W_DL and a write bit line drive signal W_BL in a predetermined sequence in accordance with the activation of the write instruction signal Write, and a command decoder 62. Includes a verify activation circuit 232 for generating a verify activation signal VFREN in accordance with write detection signal φWF and write activation signal Write.

  This verify activation circuit 232 responds to activation of write mode detection signal φWF or deactivation of write instruction signal Write in the form of a one-shot pulse having a predetermined time width. Generate VFREN. The pulse width of verify read activation signal VFREN is a time width required for reading data internally and determining the logic match between internal read data and write data.

  Timing generator 64 further includes a busy signal generation circuit 233 for generating busy / ready signal B / RZ in accordance with verify result instruction signal P / F, and a verify result instruction in response to deactivation of verify read activation signal VFREN. Latch 234 for latching signal P / F, and a pulse generation circuit 235 for generating internal write instruction signal (rewrite instruction signal) φWI in accordance with the output signal of latch 234 and verify read activation signal VFREN are included.

  Busy signal generation circuit 233 generates busy / ready signal B / RZ in accordance with verify result instruction signal P / F in the write mode. If verify result instruction signal P / F is at the L level in the standby state, busy signal generation circuit 233 always generates busy / ready signal B / RZ in accordance with verify result instruction signal P / F.

  Latch 234 is at the H level of verify read activation signal VFREN, and is in a through state when internal data reading is performed. When verify read activation signal VFREN is at L level and internal reading is completed, the latch 234 is in a latched state.

  Pulse generation circuit 235 generates internal write instruction signal (rewrite instruction signal) φWI in a one-shot form when the output signal of latch 234 is at the H level when verify read activation signal VFREN falls. Generate.

  FIG. 21 is a timing chart showing operations of command decoder 62 and timing generator 64 shown in FIG. Hereinafter, operations of the command decoder 62 and the timing generator 64 shown in FIG. 20 will be described with reference to FIG.

  In a cycle starting from time T10, in synchronization with the clock signal CLK, a write command is given as the command CMD, and an address signal AD0 is given as the address signal AD. In accordance with this write command, write command detection circuit 222 generates write instruction detection signal φWF in the form of a one-shot pulse. In accordance with activation of write instruction detection signal φWF, verify activation circuit 232 activates verify read activation signal VFREN. At this time, the write instruction signal Write is inactive. Internally, pre-read is performed, and it is determined whether or not the logical value of the stored data of the memory cell to be written and the write data match. If this determination result does not match, verify result instruction signal P / F is at the H level. Accordingly, the output signal of latch 234 is at the H level, and pulse generation circuit 235 generates rewrite instruction signal φWI in the form of a one-shot pulse signal in synchronization with the fall of verify read activation signal VFREN. Generate.

  At this time, the busy / ready signal B / RZ is at the H level according to the verify result instruction signal P / F and indicates a busy state (by the busy signal generation circuit 233).

  In accordance with this one-shot pulse rewrite instruction signal φWI, write activation circuit 224 drives write instruction signal Write to the active state in synchronization with the fall of clock signal CLK. In FIG. 21, write instruction signal Write is set during a period when clock signal CLK is at an L level. However, the activation period of the write instruction signal Write may be shorter than the L level period of the clock signal CLK.

  When write instruction signal Write is activated, write current drive activation circuit 231 is activated, and write digit line drive signal W_DL and write bit line drive signal W_BL are sequentially activated in a predetermined sequence. Is done.

  In a cycle starting from time T11, in response to the deactivation of write instruction signal Write, verify read activation signal VFREN from verify activation circuit 232 is activated. As a result, verification of the write data is executed internally. When the verify result indicates a write failure, rewrite instruction signal φWI is again activated inside, and then write activation circuit 224 activates write instruction signal Write. Again, write digit line drive signal W_DL and write bit line drive signal W_BL are activated, and data is rewritten.

  In the cycle starting from time T12, when write instruction signal Write is deactivated, read verify activation signal VFREN is activated and a determination operation is performed. At this time, if writing is normally performed, verify result instruction signal P / F falls to L level. When verify read activation signal VFREN falls to L level, the output signal of latch 234 is in the latch state at L level. Therefore, pulse generation circuit 235 does not generate a pulse, and rewrite instruction signal φWI is not generated. In response to the inactivation of verify result instruction signal P / F, busy / ready signal B / RZ is driven to the L level in synchronization with the rise of clock signal CLK.

  The busy / ready signal B / RZ may be set to L level asynchronously with the clock signal CLK in accordance with the verify result instruction signal P / F.

  As shown in FIG. 21, although the cycle starting from time T11 and the cycle starting from time T12 are spent in the verify period, the busy / ready signal B / RZ is used to ensure that the external processor or controller Access can be prohibited. External access is therefore permitted in the second half of the cycle starting from time T12.

  As described above, according to the second embodiment of the present invention, the external processor or controller can reliably know that the internal verify period is in progress during the internal write verify operation. It is possible to prevent contention between the external access and the internal verify operation.

[Embodiment 3]
FIG. 22 schematically shows structures of command decoder 62 and timing generator 64 of the toggle MRAM according to the third embodiment of the present invention. In the configuration shown in FIG. 22, the timing generator 64 is different in configuration from the timing generator 64 shown in FIG. That is, in timing generator 64, switching circuit 240 that switches the transmission path of pulse signal (rewrite instruction signal) φWI from pulse generation circuit 235 every time activation of verify read activation signal VFREN, and switching circuit 240 A rewrite request issue circuit 242 is provided for issuing a rewrite request WREQ in accordance with a given pulse signal.

  In response to the first activation of verify read activation signal VFREN, switching circuit 240 applies pulse signal (rewrite instruction signal φWI) from pulse generation circuit 235 to write activation circuit 224. In response to the second activation of verify read activation signal VFREN, switching circuit 240 provides pulse signal (rewrite instruction signal) φWI from pulse generation circuit 235 to rewrite request issue circuit 242. Rewrite request issue circuit 242 activates (issues) rewrite request WREQ in response to the rise of the pulse signal applied from switching circuit 240.

  Other configurations of the command decoder 62 and the timing generator 64 shown in FIG. 22 are the same as those of the timing generator 64 and the command decoder 62 shown in FIG. 20, and corresponding portions are denoted by the same reference numerals, and details thereof are described. Description is omitted.

  FIG. 23 is a timing chart showing operations of command decoder 62 and timing generator 64 shown in FIG. Hereinafter, operations of the command decoder 62 and the timing generator 64 shown in FIG. 22 will be described with reference to FIG.

  In the clock cycle starting from time T20, the write command is applied together with the address signal AD0. In accordance with this write command, the write command detection circuit 222 generates a write instruction detection signal φWF. In response, verify activation circuit 232 activates verify read activation signal VFREN. In accordance with verify read activation signal VFREN, data of the memory cell to be written is read. When the logic levels of the memory cell data read from the inside and the write data do not match, the pulse generation circuit 235 is in the form of a one-shot pulse signal, similarly to the configuration shown in FIG. A rewrite instruction signal φWI is generated.

  Switching circuit 240 provides pulse activation signal WI from pulse generation circuit 235 to write activation circuit 224 in response to the first activation of verify read activation signal VFREN. As a result, the write instruction signal Write is activated, and then the drive signals W_DL and W_BL are sequentially activated by the write current drive activation circuit 231.

  When writing is completed in the clock cycle starting from time T21, the verify activation circuit 232 activates the verify read activation signal VFREN again. In response to the activation of the second verify read activation signal VFREN, the switching circuit 240 switches the connection path, and uses the rewrite instruction signal φWI output from the pulse generation circuit 235 as the rewrite request issue circuit. To 242.

  When a write failure is detected during write verify during writing, verify result instruction signal P / F is at the H level. Therefore, pulse generation circuit 235 again generates rewrite instruction signal φWI in the form of a one-shot pulse. At this time, switching circuit 240 supplies rewrite instruction signal φWI output from pulse generation circuit 235 to rewrite request issuing circuit 242. Rewrite request issuing circuit 242 issues a rewrite request WREQ in accordance with the applied rewrite instruction signal φWI. With this rewrite request WREQ, the external processor or controller again gives the write command together with the same address AD0. Therefore, in the cycle starting from time T22, the same operation as the cycle starting from time T20 is performed again.

  By issuing a write request to an external processor or controller when a write failure occurs internally, the external processor or controller can reliably detect this write state. This makes it possible to monitor the number of occurrences of write failures and take necessary measures.

  The rewrite request WREQ may be issued in synchronization with the rising edge of the clock signal CLK. Further, the period from time T20 to time T22 may be one clock cycle period of the external clock signal.

[Example of change]
FIG. 24 schematically shows structures of command decoder 112 and timing generator 114 of the spin injection MRAM according to the modification of the third embodiment of the present invention. The command decoder 112 and the timing generator 114 shown in FIG. 24 differ from the command decoder 112 and the timing generator 114 shown in FIG. 19 in the following points. That is, in command decoder 112, output signal φWF of write command detection circuit 202 is directly applied to write activation circuit 206 as write mode instruction signal φW.

  Timing generator 114 is provided with a rewrite request issue circuit 210 that issues a rewrite request WREQ in accordance with a pulse signal (rewrite instruction signal) φWI from pulse generation circuit 215.

  Other configurations of the timing generator 114 and the command decoder 112 are the same as those of the command decoder 112 and the timing generator 114 shown in FIG. 19, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. .

  FIG. 25 is a timing chart showing operations at the time of data writing of command decoder 112 and timing generator 114 shown in FIG. Hereinafter, operations of the command decoder 112 and the timing generator 114 shown in FIG. 24 will be described with reference to FIG.

  In a cycle starting from time T30, in synchronization with the rise of the clock signal CLK, a write command is given as the command CMD, and at the same time, an address signal AD0 is given as the address signal AD. In accordance with this write command, write activation circuit 206 activates write instruction signal Write. In accordance with the activation of write instruction signal Write, write current drive activation circuit 211 activates write digit line drive signal W_DL and write pulse signal W_PLSE. At this time, the comparison invalidation signal 1st_Write that prohibits pre-reading is also activated.

  When this write operation is completed, the verify activation circuit 212 then activates the verify read activation signal VFREN and executes the write verify. In the case of a write failure, rewrite instruction signal (internal write instruction signal) φWI from pulse generation circuit 215 is activated as described in the timing chart shown in FIG. In accordance with the activation of rewrite instruction signal φWI, rewrite request issue circuit 250 issues write request WREQ.

  In accordance with the write request WREQ, the external processor or controller issues the same address signal AD0 together with the write command. As a result, in the cycle starting from time T31, the same writing and write verify as the cycle starting from time T30 are executed.

  In the rewrite cycle starting from time T31, if writing is performed normally, verify result instruction signal P / F is inactivated, indicating that writing has been performed normally. In this case, since the pulse generation circuit 215 does not generate a pulse signal, the rewrite request issue circuit 250 does not issue the rewrite request WREQ. Therefore, the next access can be executed in the cycle from time T32.

  In the timing chart shown in FIG. 25, rewrite request WREQ may be issued in synchronization with the rise of clock signal CLK. In this case, the cycle starting from time T31 is a wait cycle.

  As described above, according to the third embodiment of the present invention, a rewrite request is issued to an external command so as to issue a write command indicating writing at the time of writing failure. Therefore, the external controller or processor can grasp the state of data writing, and can execute necessary processing when writing is defective.

  In the third embodiment, as in the second embodiment, a busy / ready signal may be used together.

[Embodiment 4]
FIG. 26 schematically shows an overall configuration of the MRAM according to the fourth embodiment of the present invention. The MRAM shown in FIG. 26 may be either a toggle MRAM or a spin injection MRAM.

  In FIG. 26, in the MRAM, the memory array 20 is divided into a plurality of memory blocks MB0 to MBn. In each of these memory blocks MB0 to MBn, memory cells are arranged in a matrix. Depending on the configuration of the MRAM, word lines, digit lines, bit lines, and source lines are arranged according to each memory cell row / column.

  Sub-write circuits SBW0-SBWn are provided corresponding to memory blocks MB0-MBn, respectively. Each of sub-writing related circuits SBW0-SBWn includes a digit line driver and a bit line driver. In the case of the spin injection type MRAM, a source line driver and a source line decoder are further provided. Sub write circuits SBW0 to SBWn operate in parallel and write multi-bit data. However, as will be described later in detail, the operations at the time of rewriting of these sub-writing circuits can be individually controlled.

  Memory blocks MB0 to MBn are provided corresponding to external input data DI0 to DIn and sub output data DO0 to DOn, respectively, and transmit / receive data to / from corresponding data input / output pads.

  Corresponding to memory blocks MB0-MBn, read column selection circuits RSK0-RSKn are further provided. Read column select circuits RSK0-RSKn include a read column select gate and a read column select decoder provided for each bit line of the corresponding memory block, as shown in FIG. A bit line corresponding to a column addressed in a corresponding memory block is selected in accordance with an address signal (not shown) activated when data is read (including a verify operation).

  Sense amplifier circuits SAK0-SAKn are provided corresponding to read column selection circuits RSK0-RSKn, respectively. These sense amplifier circuits SAK0-SAKn are activated in response to activation of sense activation signals EN0-ENn from corresponding sense control circuits SCK0-SCKn, and verify reference voltage VREFR and corresponding read column selection circuit The data read from RSK0-RSKn is compared.

  Output signals of these sense amplifier circuits SAK0 to SAKn are applied to corresponding output data latches QDL0 to QDLn.

  Comparators COM0-COMn are provided corresponding to output data latches QDL0-QDLn, respectively. Output data latches QDL0 to QDLn generate external read data DO0 to DOn via pads at the time of normal data read, and supply latch data to corresponding comparators COM0 to COMn at the time of verify operation (internal read). . Comparators COM0-COMn compare the latched data of input data latches DDL0-DDLn provided in correspondence with the data supplied from output data latches QDL0-QDLn, respectively, and show signals P / F0-P / Fn is generated. The configurations of these comparators COM0 to COMn are the same as those described in the first to third embodiments, and the configurations are set according to the toggle MRAM and the spin injection MRAM.

  Verify result instruction signals P / F0-P / Fn from these comparators COM0-COMn are applied to corresponding sense control circuits CK0-CKn, and are also applied to sub-write related circuits SBW0-SBWn. Thereby, rewriting is selectively executed for each memory block selectively according to the verify result.

  The output signal of the comparators COM0-COMn is also supplied to the OR circuit 304. From this OR circuit 304, a main verify result instruction signal MP / F is generated and applied to the timing generator 302.

  Timing generator 302 generates digit line drive signal W_DL, verify read activation signal VFREN, and write bit line drive signal W_BL (or write pulse signal W_PLSE) in accordance with a write instruction from command decoder 300. As the configuration of this timing generator 302, the configuration shown in the previous second or third embodiment is used.

  The command decoder 300 takes in an external command CMD in synchronization with the clock signal CLK, and generates a write instruction signal Write when a write instruction is given. When a read instruction is given, the coder 300 generates a read instruction signal Read with a command. Control signals from command decoder 300 and timing generator 302 are applied to sense control circuits SCK0 to SCKn and sub write circuits SBW0 to SBWn. In addition, verify read activation signal VFREN and read instruction signal Read are applied to read column select circuits RSK0-RSKn in order to activate the read operation.

  Although not shown in FIG. 26, an address latch is provided, and an internal address signal (ADD) for designating an address is generated in each memory block.

  Sense amplifier circuits SAK0-SAKn are provided corresponding to memory blocks MB0-MBn, respectively, and an address signal designating a selected column is not applied to sense control circuits SCK0-SCKn that activate the sense amplifier. That is, sense amplifier circuits SAK0 to SAKn are provided in common for the bit lines of the corresponding memory blocks. Sense control circuits SCK0-SCKn activate corresponding sense amplifier circuits SAK0-SAKn according to verify read activation signal VFREN, respectively, when the results of corresponding verify result instruction signals P / F0-P / Fn indicate mismatch. To do.

  In the configuration of the MRAM shown in FIG. 26, external data input data DI0 to DIn are written in parallel to the selected memory cells of memory blocks MB0 to MBn at the time of data writing. During the verify operation, sense amplifier circuits SAK0-SAKn are activated by sense control circuits SCK0-SCKn, and comparison operations are performed in parallel by comparators COM0-COMn.

  At the time of rewriting, rewriting is performed only on the memory block in which the writing failure has occurred in accordance with verify result instruction signals P / F0-P / Fn. Although the write instruction signal Write is supplied to the remaining memory blocks in which writing has been normally performed, the corresponding sub-write circuit is disabled by the verify result instruction signal, and the data Rewriting is not performed.

  FIG. 27 is a flowchart showing an operation at the time of data writing of the MRAM shown in FIG. Hereinafter, the write sequence of the MRAM shown in FIG. 26 will be described with reference to FIG.

  First, the command decoder 300 determines whether writing has been designated by an external command CMD (step S21). Until a write command is given, the command from the outside is monitored and it waits for a write command to be given.

  When a write command is given and writing is instructed, first, pre-reading is performed by the command decoder 300 and the timing generator 302 (step S22). In each of memory blocks MB0 to MBn, data stored in the memory cell to be written is read in parallel. In response, comparators COM0-COMn determine whether or not the logical values of write data DI0-DIn applied from input data latches DDL0-DDLn and the corresponding internal read data match (step S23).

  According to whether the main verify result instruction signal MP / F from the OR circuit 304 is at the H level or the L level, it is determined whether the stored data and the write data match for all bits of the write data. Done. When main verify result instruction signal MP / F is at the H level and the stored data and the write data are inconsistent with respect to the memory cell of at least 1 bit, again from timing generator 302 and command decoder 300 Data is written according to the control signal (step S24). At this time, data is written only to the memory block that needs to be written in accordance with verify result instruction signals P / F0 to P / Fn from comparators COM0 to COMn. Memory blocks that do not require writing are maintained in a standby state (step S24).

  Next, verify read is executed (S25). Next, sense amplifier circuits SAK0-SAKn are selectively activated in accordance with verify result designating signals P / F0-P / Fn, and only for the memory block in which writing is required and writing is performed. A sense operation is performed, and verify read is performed.

  For memory blocks in the standby state, corresponding output data latches QDL0 to QDLn are in a latched state, and the logic level of verify result instruction signal P / Fi output from corresponding comparator COMi does not change.

  Next, whether all bits have been written is determined according to whether main verify result instruction signal MP / F from OR circuit 304 is at the H level (step S26). When writing of all bits is completed, writing of this data is completed. On the other hand, if there is a write failure for at least one bit memory cell, the operation from step S24 is repeated. Thereby, in memory blocks MB0 to MBn, rewriting is repeatedly performed until writing is normally completed, and the memory block in which writing is completed is maintained in a standby state.

  In the spin injection MRAM, steps S22 and S23 for performing pre-reading may be omitted. In this case, the operation from step S24 to step S26 is executed at the time of writing.

  FIG. 28 schematically shows a configuration of a bit line decode control circuit and a digit line decode circuit included in sub-write related circuits SBW0-SBWn shown in FIG. FIG. 28 representatively shows bit line decode control circuit 376i and bit line decode circuit 370i of sub-write circuit SBWi.

  In FIG. 28, bit line decode control circuit 376i includes AND gate G3i receiving write bit line drive signal W_BL, write instruction signal Write and verify result instruction signal P / Fi, verify read activation signal VFREN and read instruction. Sense control circuit SCKi for generating sense activation signal ENi in accordance with signal Read and verify result instruction signal P / Fi is included.

AND gate G3i corresponds to AND gate G3 shown in FIGS.
The sense control circuit SCKi receives an AND gate 380 that receives a verify result instruction signal P / Fi and a verify read activation signal VFREN, an output signal of the AND gate 380 and a read instruction signal Read, and receives a sense activation signal ENi. An OR gate OG1i to be generated is included. This OR gate OG1i corresponds to the OR gate OG1 shown in FIGS.

  Digit line decode circuit 370 i receives write digit line drive signal W_DL, write instruction signal Write, and X address signal XADD, and provides the output signal to digit line drive circuit 72 at the next stage. The configuration of digit line decode circuit 370i is the same as the configuration of the digit line decode circuit shown in FIGS. 11 and 16, and its detailed configuration is not shown.

  As shown in FIG. 28, verification result instructing signal P / Fi is applied to corresponding bit line decode control circuit 376i and digit line decode circuit 370i, thereby activating / inactivating writing of sub-writing circuit SBWi. Can be set for each memory block according to the verification result.

  In the case of a spin injection type MRAM, a write pulse signal W_PULSE is applied instead of the write bit line drive signal W_BL.

  The configurations of the bit line decode circuit 72 and the digit line drive circuit 72 in the next stage are the same as those shown in FIG. 11 or FIG.

  If at least verify result instruction signal P / Fi is at L level, indicating that writing is not required, the output signals of AND gates G3i and 380 are at L level. Read instruction signal Read is at the L level during data writing. Therefore, the bit line decode circuit 74 at the next stage is maintained in an inactive state (disabled state), and no bit line is selected. Sense activation signal ENi is also inactive, and no sensing operation is performed.

  FIG. 29 is a diagram showing a configuration of the source line decode control circuit 380 when the MRAM of the fourth embodiment is a spin injection type MRAM. The source line decode control circuit 380 shown in FIG. 29 corresponds to the configuration of the source line decode control 120 shown in FIG. FIG. 29 also representatively shows a circuit in sub-writing circuit SBWi.

  29, source line decode control circuit 380 includes an inverter IV4i that inverts input data, and an AND gate G8i that receives an output signal of inverter IV4i and a verification result instruction signal P / Fi. These inverter IV4i and AND gate G8i correspond to inverter IV4 and AND gate G8 of decode control circuit 120 shown in FIG.

  Source line decode control circuit 380 further includes an AND gate 382 receiving verify result instruction signal P / Fi and verify read activation signal VFREN, and OR gate OG3i receiving an output signal of AND gate 382 and read instruction signal Read. . The OR gate OG3i corresponds to the OR gate OG3 included in the source line decode control circuit 120 shown in FIG. AND gate 382 selectively sets verify read activation signal VFREN to a valid / invalid state according to verify result instruction signal P / Fi.

  Source line decode control circuit 380 further includes an AND gate G9i receiving write pulse signal W_PULSE, an output signal from AND gate G8i, and write activation signal Write, an output signal from OR gate G9i, and an output signal from OR gate OG3i. And an OR gate OG4i for supplying the output signal to the next source line decoder. AND gate G9i corresponds to AND gate G9 included in source line decode control circuit 120 shown in FIG. OR gate OG4i corresponds to OR gate OG4 in source line decode control circuit 124 shown in FIG. The configuration of the source line decoder is the same as that of the source line decoder 122 shown in FIG.

  In the configuration of source line decode control circuit 380 shown in FIG. 29, when verify result designating signal P / Fi is at L level, the output signals of AND gates G8i and 382 are at L level. In the write mode, read instruction signal Rend is at an inactive L level. Therefore, an L level signal is supplied from the OR gate OGi to the next source line decoder (122), and the source line decoder is maintained in a disabled state.

  Apply verify result instruction signals P / F0-P / Fn from comparators COM0-COMn provided corresponding to the respective memory blocks to corresponding sub-write circuits SBW0-SBWn and sense control circuits SCK0-SCKn, respectively. Thus, rewriting can be controlled individually for the memory blocks MB0 to MBn.

  At the time of this rewriting, all data may be rewritten under the same writing condition, and the writing condition may be changed as will be described later. When writing multi-bit data, only writing to a memory cell that requires writing is performed, and writing to an unnecessary memory cell is performed for a bit (memory cell) in which writing is normally performed. Can be stopped and current consumption can be reduced.

  As described above, according to the fourth embodiment of the present invention, rewriting is performed in units of memory blocks, so that tabbit data can be reliably written. In addition, since the writing operation is not performed in the memory block in which writing has been completed and the standby state is maintained, unnecessary writing is not performed, and power consumption can be reduced.

[Embodiment 5]
FIG. 30 schematically shows a structure of an MRAM command decoder 400 according to the fifth embodiment of the present invention. In FIG. 30, a command decoder 400 detects a write command detection circuit 402 that detects whether a write command is given in accordance with an external command CMD in synchronization with a clock signal CLK, and a write command detection from the write command detection circuit 402. It includes a count circuit 404 set to an initial value in accordance with signal φWF and performing a count operation in synchronization with internal clock signal CLKi. When the count value is set to an initial value in accordance with write command detection signal φWF, count circuit 404 performs a count operation in synchronization with the rise or fall of clock signal CLKi and stops the count operation when it reaches a predetermined value. .

  Command decoder 400 further includes a pulse generation circuit 406 that generates a one-shot pulse signal in synchronization with internal clock signal CLKi, and a write command detection signal φWF, when the count-up instruction signal from count circuit 404 is inactive. An OR circuit 408 for generating a write instruction signal φW in accordance with the pulse signal from pulse generation circuit 406 is included.

  Pulse generation circuit 406 stops its pulse generation operation when count circuit 404 reaches a predetermined value and count-up signal φEUP is activated. Therefore, the pulse generation circuit 406 generates a pulse signal for a predetermined count value preset in the count circuit 404.

  Write instruction signal φW from OR circuit 408 is applied to the write activation circuit in the next stage or to the timing generator depending on the configuration of the MRAM in which command decoder 400 is used. Therefore, this command decoder 400 can be applied to an MRAM other than the configuration for issuing a rewrite request to the outside shown in FIG.

  FIG. 31 is a flowchart showing the operation of the command decoder 400 shown in FIG. The operation of command decoder 400 shown in FIG. 30 will be described below with reference to FIG.

  The write command detection circuit 402 monitors the command CMD from the outside in synchronization with the clock signal CLK, and waits for a write instruction (step S40). When the external command CMD is a write command, the write command detection circuit 402 activates the write detection signal φWR. Subsequently, the count circuit 404 is initialized and starts the count operation. At this time, the pulse generation circuit 406 does not generate a pulse signal yet. On the other hand, write instruction signal φW is issued by OR circuit 408 in accordance with write command detection signal φWF (step S41). In accordance with write instruction signal φW, data write and a verify operation after writing are executed internally, and according to the verify result, verify result instruction signal P / F (or P / Fi) corresponds to the verify result. The logical level is set (step S42). In this step S42, in the case of the toggle MRAM, pre-read is executed at the time of the first writing. At the time of rewriting for the second transition, pre-reading is not executed (see FIG. 19).

  Next, since the count value of the count circuit 404 has not yet reached the predetermined value, the count-up signal φEUP is inactive (step S43). Therefore, in this case, pulse generation circuit 406 generates a one-shot pulse signal in synchronization with internal clock signal CLKi, and write instruction signal φW is issued again. On the other hand, when the count value of count circuit 404 reaches a predetermined value in step S43, count-up instruction signal φEUP is activated, and pulse generation circuit 406 stops the subsequent pulse generation operation.

  Therefore, when command decoder 400 shown in FIG. 30 is used, a write instruction is issued and a write sequence is executed even if writing is normally performed internally. In this case, when the verify result instruction signal P / F or P / Fi indicates normal writing, actual data writing to the memory cell to be written is not executed. Only a so-called empty write sequence is executed.

  In the case of the command decoder shown in FIG. 30, when a write command is given from the outside, write and write verify are executed internally a predetermined number of times. Thereby, it is expected that data in the memory cell is reliably written within a predetermined period indicated by a predetermined value set by count circuit 404. Further, the external processor or controller is guaranteed to complete the writing within a predetermined period after the write command is issued, and the system design becomes easy (the write access time can be set to a predetermined value). For).

  As described above, according to the fifth embodiment of the present invention, when a write command is given, writing and verifying are executed a predetermined number of times internally, and accurate data can be written. The write access time can be set to a predetermined value.

  The internal clock signal CLKi may be the same clock signal as the external clock signal CLK, or may be an internal clock signal generated by dividing the external clock signal CLK. Any internal clock signal having a period for guaranteeing a period for defining internal data write and verify cycles may be used.

[Embodiment 6]
FIG. 32 schematically shows a structure of a main portion of time generator 302 of the MRAM according to the sixth embodiment of the present invention. In the configuration shown in FIG. 32, in timing generator 302, busy signal generation circuit 410 for generating busy / ready signal B / RZ in accordance with main verify result instruction signal MP / F from OR circuit 304 is provided.

  In the configuration shown in FIG. 32, busy / ready signal B / RZ is set in a busy state until all bits of multi-bit data are internally written. Therefore, the external processor or controller can detect the period during which all the bits of the multi-bit data are written reliably. During this writing period, the external processor or controller is put in a wait state in accordance with the busy / ready signal B / RZ.

  The configuration of the timing generator shown in FIG. 32 is the same as that of the timing generator including busy signal generation circuit 233 shown in FIG. Instead of the 1-bit verification result instruction signal P / F, a main verification result instruction signal MP / F is used.

  As described above, according to the fifth embodiment of the present invention, a busy / ready signal is issued externally while writing is repeatedly executed internally. Therefore, it is possible to reliably detect the completion point of data writing, avoiding access conflict, and realizing accurate data writing.

[Embodiment 7]
FIG. 33 schematically shows a structure of a main portion of timing generator 302 according to the seventh embodiment of the present invention. In timing generator 302 shown in FIG. 33, rewrite request WREQ is issued to the outside in accordance with main verify result instruction signal MP / F and clock signal CLK. Therefore, the rewrite request WREQ is issued repeatedly during a period in which there is a bit having an internal write failure. Internally, for the bit for which writing has been completed, subsequent writing is stopped in accordance with the corresponding verify result instruction signal P / Fi.

  In the case of the configuration shown in FIG. 33, it is possible to reliably issue a write command externally until data writing is completed, and to realize accurate data writing. Also, the processor or controller can monitor the write status by this rewrite request WREQ, and if the rewrite request WREQ is received a predetermined number of times, it determines that the corresponding bit is defective. May be configured to perform necessary error handling.

  The rewrite request issuing circuit 412 generates a rewrite request WREQ in synchronization with the clock signal CLK (which may be an internal clock signal). However, as shown in FIG. 22, the rewrite request WREQ may be issued asynchronously with the clock signal CLK in accordance with the verify read activation signal VFREN and the main verify result instruction signal MP / F.

  As described above, according to the seventh embodiment of the present invention, even when multi-bit data is written, it is ensured that multiple bits are issued by repeatedly issuing rewrite requests until all bits are written reliably. Bit data can be written. An external processor or controller can monitor the writing status by this rewriting request, and writing control becomes easy.

[Embodiment 8]
FIG. 34 shows an exemplary configuration of a reference voltage generation circuit (Vref generation circuit) 420 according to the eighth embodiment of the present invention. The reference voltage generation circuit 420 shown in FIG. 34 corresponds to the configuration of the Vref generation circuit shown in FIG. 2 or 15 or the Vref generation circuit 306 shown in FIG.

  34, reference voltage generation circuit 420 includes resistance elements Z1-Z4 connected in series between a power supply node and node NDa, and a constant current source CIS connected between node NDa and the ground node. A reference voltage Vref is generated from node NDa. This reference voltage Vref is applied to the bit line drive circuit and the digit line drive circuit in the case of a toggle RAM. Each of the bit line drive circuit and the digit line drive circuit may be provided with a reference voltage generation circuit 420, and a reference voltage Vref adjusted according to each may be applied.

  In the case of a spin injection type MRAM, the reference voltage Vref is also applied to the source line drive circuit. In this case, a reference voltage from a reference voltage generation circuit provided separately from the bit line drive circuit and the digit line drive circuit may be applied to the source line drive circuit.

  The reference voltage Vref has its voltage level set according to the characteristics of the given circuit. Although reference voltages are individually generated for these digit line drive circuit, bit line drive circuit and source line drive circuit, their voltage levels may be the same or different.

  Reference voltage generation circuit 420 further includes switching elements TX1-TX3 connected in parallel with resistance elements Z2-Z4, selector 422 that generates a selection signal according to write mode instruction signal φW, and an output signal of selector 422 AND gates G10 and G11 are included for driving switching elements TX1 and TX2 to a conductive state, respectively.

  The output signal of the selector 422 is also supplied to the gate of the switching element TX3. As an example, the switching elements TX1 to TX3 are configured by N-channel MOS transistors. However, any switching element that is selectively turned on / off in accordance with a signal applied to the control electrode may be used. These switching elements TX1-TX3 each short-circuit corresponding resistance elements Z2-Z4 when conducting.

Selector 422 is formed of a shift register, for example, and internally shifts a power supply voltage level signal (H level signal) in accordance with write mode instruction signal φW. Therefore, each time write mode instructing signal φW is generated, the number of signals that become H level in the output signal of selector 422 is increased. In this case, the following sequence is considered as an example. When write mode instruction signal φW is generated for the first time, selector 422 is set to the initial state, and all switching elements TX1-TX3 are set to the non-conductive state. Next, every time this write mode instruction signal φW is issued, switching elements TX3, TX2, and TX1 are sequentially turned on. In this case, the reference voltage Vref changes sequentially between the following voltage levels, where I is the current that the constant current source CIS flows:
Initial value: VDD-I · (Z1 + Z2 + Z3 + Z4),
Maximum value VDD-I · Z1.

  If the resistance values of the resistance elements Z1 to Z4 are all equal to R, the voltage level of the reference voltage Vref is adjusted in step IR.

  FIG. 35 is a diagram showing an example of a change sequence of the reference voltage Vref. The reference voltage Vref is sequentially increased from the minimum value Vref (min) to reach the maximum value Vref (max). Voltages V1 and V2 are taken at intermediate values. Between the maximum value and the minimum value, an intermediate state reference voltage is generated in step IR.

  In the MRAM, when a writing failure occurs, the state before writing is restored. Therefore, in the case of a write failure, a large write current is sequentially supplied to increase the induced magnetic field or the write current, thereby reliably changing the magnetization state of the memory cell. For example, when the state changes after writing, such as a flash memory, there is a possibility that problems such as overwriting may occur. However, such an overwriting problem does not occur in the MRAM. Can be written to. However, in the case of the toggle MRAM, if this applied magnetic field is too large, the exchange coupling of the free layer is broken, so that the maximum value is limited. Therefore, it is necessary to set the reference voltage Vref at the time of writing to a value equal to or lower than the write allowable maximum value Vref (max).

  This reference voltage Vref is applied to the gate of the driving transistor in the bit line drive circuit, digit line drive circuit and / or source line drive circuit as shown in the previous embodiment. Therefore, by sequentially increasing the voltage level of the reference voltage Vref, the drive current amount of the drive transistor can be increased and the write current can be increased.

  In the configuration shown in FIG. 34, write mode instruction signal φW is applied to selector 422, and selector 422 sequentially shifts to selectively drive switching elements TX1-TX3 to the conductive state. . Write mode instruction signal φW applied to selector 422 may be any signal indicating internally generated write. Rewrite instruction signal φWI may be used. A signal indicating the number of internal writes may be used as a selector shift signal in accordance with the configuration of the corresponding MRAM.

  The selector 422 adjusts the level of the generated reference voltage Vref in three stages. However, the voltage change amount at the time of rewriting the reference voltage Vref generated by the reference voltage generation circuit 420 may be further divided into multiple stages. It is only necessary to sequentially adjust the voltage level of the reference voltage Vref between the minimum writing reference voltage Vref (min) and the maximum reference voltage Vref (max) in steps with small actions. Further, the number of steps may be changed according to the number of times of rewriting.

[Modification 1]
FIG. 36 schematically shows a structure of drive circuit 430 according to the first modification of the seventh embodiment of the present invention. In FIG. 36, this drive circuit 430 is a bit line drive circuit or a source line drive circuit of a spin injection type MRAM. Therefore, the signal line SGL is the bit line BL or the source line SL in the spin injection MRAM.

  Drive circuit 430 includes pre-stage circuits 432 and 434 for internal signals, and drive stage 436 for driving signal line SGL according to the output signals of pre-stage circuits 432 and 434. Pre-stage circuits 432 and 434 receive the power supply voltage as their high-side operation power supply voltage. When drive circuit 430 is a bit line drive circuit, pre-stage circuits 432 and 434 are a NAND circuit and a NOR circuit, respectively, shown in FIG. When drive circuit 430 is a source line drive circuit, pre-stage circuits 432 and 434 are inverter circuits shown in FIG.

  Drive stage 436 has a P-channel MOS transistor PQ10 for driving signal line SGL to the reference voltage Vref level in accordance with the output signal of pre-stage circuit 432, and an N-channel MOS transistor for coupling signal line SGL to the ground node in accordance with the output signal of pre-stage circuit 430. Includes NQ10.

  By drive circuit 430, signal line SGL is driven to reference voltage Vref, and the other end is coupled to the ground node. The write current flowing through the signal line SGL can be adjusted by the voltage level of the reference voltage Vref (the wiring resistance is the same, and the amount of current is given by the ratio between the reference voltage Vref and the wiring resistance).

  It should be noted that the digit line drive circuit normally causes the digit line current to flow by coupling the digit line DL to the ground node. When the digit line has one end coupled to the ground node and the digit line of the selected row passes current according to the output voltage of the digit line drive circuit, drive circuit 430 shown in FIG. 36 is used as the digit line drive circuit. can do. The amount of digit line current can be adjusted by the reference voltage Vref.

[Modification 2]
FIG. 37 schematically shows a structure of a second modification of the eighth embodiment of the present invention. In FIG. 37, in the toggle MRAM, a voltage follower 439 is provided for the bit line BL. This voltage follower 439 receives the reference voltage Vref at the positive input, and the negative input is coupled to the corresponding bit line BL.

  A bit line drive circuit 437 is provided at the other end of the bit line BL. In the bit line drive circuit 437, the high-side power supply voltage is the power supply voltage. The configuration of bit line drive circuit 437 is the same as that shown in FIG. 11 (power supply voltage VDD is applied instead of reference voltage Vref).

  In the configuration shown in FIG. 37, the voltage level of reference voltage Vref is adjusted according to the number of times of rewriting. When selected, bit line drive circuit 437 couples corresponding bit line BL to the power supply node. Therefore, by adjusting the voltage level of the reference voltage Vref, the voltage difference between both ends of the bit line BL is different, and the amount of current flowing through the bit line BL can be adjusted.

  In this case, the voltage level of the reference voltage Vref is lowered as the number of rewrites increases. As a result, as the number of rewrites increases, the amount of bit line write current can be increased, and the bit line current induced magnetic field can be increased accordingly.

  Therefore, in this case, in the reference voltage generating circuit, the selector 422 shown in FIG. 34 is sequentially increased in the number of switching elements TX1-TX3 that are turned on.

[Modification 3]
FIG. 38 schematically shows a structure of write current drive activation circuit 211 according to the structure of modification 3 of the eighth embodiment of the present invention. The write current drive activation circuit 211 generates a write pulse signal W_PULSE in the spin injection MRAM (see FIG. 24).

  In FIG. 38, write current drive activation circuit 211 is set to an initial value by timing adjustment circuit 442 for delaying write instruction detection signal φWF for a fixed time and write instruction detection signal φWF. A count circuit 444 is included that performs a count operation every time the read activation signal VFREN is inactivated. The timing adjustment circuit 442 adjusts the activation timing of the internal write pulse signal W_PULSE by delaying the write instruction detection signal φWF for a fixed time.

  The write current drive activation circuit 211 is further set according to the output signal of the variable delay circuit 446 and reset according to the output signal of the variable delay circuit 446 and the variable delay circuit 446 that delays the timing adjustment circuit 442. Includes a set / reset flip-flop 448 for generating a write pulse signal W_PULSE from the.

  The delay amount of the variable delay circuit 446 is adjusted by the count value of the count circuit 444. In this case, variable delay circuit 446 may include a plurality of cascade-connected delay stages, and a delay stage that outputs a signal may be set in accordance with the output signal of count circuit 444. Instead, the variable delay circuit 446 includes a plurality of delay stages, and the driving operation current of each delay stage is set according to the count value of the count circuit 444, and the delay amount of each delay stage is changed. May be. Any configuration may be used.

  FIG. 39 is a signal waveform diagram representing an operation of write current drive activation circuit 211 shown in FIG. The operation of write current drive activation circuit 211 shown in FIG. 38 will be described below with reference to FIG.

  At the time of data writing, write instruction detection signal φWF is activated in accordance with an external write command (by a write command detection circuit in the command decoder). The count value of the count circuit 444 is set to an initial value. Accordingly, the delay amount of variable delay circuit 446 is set to the initial value. In the first writing, bit line write pulse signal W_PULSE is generated according to the initial value.

  Count circuit 444 updates the count value in response to transition of verify read activation signal VFREN to inactivation. Accordingly, the delay amount of the initial value of the variable delay circuit 446 is updated, and the output signal of the timing adjustment circuit 442 is delayed by a predetermined value. In accordance with the output signal of timing adjustment circuit 442, set / reset flip-flop 448 is set and write pulse signal W_PULSE is activated. Next, after the delay time required for the variable delay circuit 446 has elapsed, the flip-flop 448 is reset and the write pulse signal W_PULSE is deactivated. Therefore, after the second writing, the pulse width of the write pulse signal W_PULSE is sequentially updated.

  As described above, in the MRAM, when a write failure occurs, the memory cell to be written returns to the state before writing. Therefore, in this case, the write data can be surely written into the memory cell in which writing is defective by sequentially increasing the write time. Unlike flash memory cells, the initial state of this writing is always the same, so even if the writing time is extended, the problem of overwriting does not occur.

  As described above, according to the eighth embodiment of the present invention, the write condition is changed according to the number of rewrites, and data can be reliably written to the write target memory cell. .

[Embodiment 9]
FIG. 40 schematically shows a structure of write current drive activation circuit 450 of the toggle MRAM according to the ninth embodiment of the present invention. From write current drive activation circuit 450, digit line write current activation signal W_DL and bit line write current activation signal W_BL are generated. Write circuit 450 corresponds to circuits 211 or 231 shown in FIGS.

  Write current drive activation circuit 450 includes delay elements DLY1-DLY6 connected in cascade and selection circuits SLT1-SKT5 for selecting output signals D2-D6 of delay elements DLY2-DLY6, respectively. Outputs of selection circuits SLT1-SLT5 are coupled in common to generate write bit line drive signal W_BL.

  A selector 452 is provided for write current drive activation circuit 450. For example, selector 452 is provided in the timing generator and sequentially drives selection circuits SLT1-SLT5 to the selected state in accordance with write mode instruction signal φW. Therefore, selector 452 may be formed of a shift register which is set to an initial value in accordance with write mode instruction signal φW and sequentially performs a shift operation in accordance with a clock signal or verify read activation signal VFREN. Instead, selector 452 may be configured by a counter / decode circuit that counts write mode instruction signal φW and decodes the count value. The selection circuits SLT1 to SLT5 may be alternatively driven to the selected state.

  Selection circuits SLT1-SLT5 pass the output signal of the corresponding delay element when selected, and enter an output high impedance state when not selected. Therefore, one of output signals D2-D6 of delay elements DLY2-DLY6 is selected as write bit line drive signal W_BL.

  These delay elements DLY1-DLY6 have a fixed delay time. Write clock signal CLKw is generated as a pulse signal having a predetermined time width in the write mode. Alternatively, the write clock signal CLKw may be an internal clock signal CLKi that is always generated. In this case, although the write digit line drive signal W_DL changes according to the internal clock signal CLKi, the corresponding digit line drive circuit is in a standby state except during data writing, and no particular problem occurs.

  FIG. 41 is a timing diagram representing an operation of write current drive activation circuit 450 shown in FIG. The operation of write current drive activation circuit 450 shown in FIG. 40 will be described below with reference to FIG.

  At the time of data writing, write clock signal CLKw is generated as a pulse signal having a predetermined time width (or is always given as clock signal CLKi). The delay elements DLY1 to DLY6AH each have a delay time Δt, and sequentially delay the given signals to output them. First, the output signal D1 from the first-stage delay element DLY1 is generated as the write digit line drive signal W_DL.

  The selector 452 is set to the initial state at the first writing. Therefore, one of the output signals of the delay elements DLY2 to DLY6 is selected. As shown in FIG. 41, when output signal D2 of delay element DLY2 is selected, write bit line drive signal W_BL is at the H level from time ta to time tc. On the other hand, when the output signal DL6 of the final-stage delay element DLY6 is selected, the write bit line drive signal W_BL is at the H level from time tb to time td.

  In this period, the write bit line drive signal W_BL is sequentially delayed according to the number of rewrites. Writing to the memory cell is performed during a period in which the write digit line current activation signal W_DL and the write bit line drive signal W_BL overlap (magnetic field rotation). Therefore, by increasing the period during which this combined magnetic field is generated, the magnetization of the variable magnetoresistive element (MTJ element) of the memory cell is reliably made in the direction of the combined magnetic field induced by the digit line current and the bit line current. The direction can be set, and writing can be executed reliably.

  By adjusting the relative timing relationship between W_DL and W_BL for each writing, it is possible to reliably write data. When the cause of the writing failure is a magnetic field separation failure (a state where the spin-flop state is not generated), the time during which the digit line current flows is lengthened. When the magnetic field rotation failure is the cause of the writing failure, the time for which both the bit line current and the digit line current flow is lengthened. When the cause of the write failure is a rotation failure of the easy axis due to the bit line current, the time during which the bit line current flows is lengthened. A delay time change sequence is set in accordance with the cause of these write failures. A failure cause with a high probability of occurrence is identified during testing, and a delay change sequence is set.

[Example of change]
FIG. 42 schematically shows a structure of a modification of write current drive activation circuit 450 according to the ninth embodiment of the present invention. In write current drive activation circuit 450 shown in FIG. 42, selection circuits SLT10-SLT12 are provided corresponding to the outputs of delay elements DLY1-DLY3, respectively. Selection circuits SLT10-SLT12 are selectively turned on in accordance with an output signal from selector 452, and are in an output high impedance state when not selected.

  As in the configuration shown in FIG. 40, selector 452 has an initial value set in accordance with write mode instruction signal φW and performs a count operation. Instead of write mode instruction signal φW, selector 452 may perform a count operation in accordance with, for example, a verify read activation signal (VFREN). A signal indicating the number of times of internal writing is used as a selector shift control signal, and the selector counts the number of times of rewriting according to this shift control signal, and a selection signal corresponding to the count value is generated. Any configuration may be used.

  Write current drive activation circuit 450 further includes two stages of cascade-connected delay elements DLY10 and DLY11 that receive the output signals of selection circuits SLT10 to SLT12, and output signals and delay elements of any of selection circuits SLT10 to SLT12. An OR circuit 454 that receives the output signal D1 of DLY1 is included. Write bit line drive signal W_BL is generated from delay element DLY11, and write digit line drive signal W_DL is generated from OR circuit 454.

  FIG. 43 is a timing chart representing an operation of write current drive activation circuit 450 shown in FIG. The operation of write current drive activation circuit 450 shown in FIG. 42 will be described below with reference to FIG.

  Consider a state where the selector 452 selects the selection circuit SLT12. In this case, write digit line drive signal W_DL rises in synchronization with the rise of output signal D1 of delay element DLY1, and then falls in response to the fall of output signal D3 of delay element DLY3.

  On the other hand, write bit line drive signal W_BL changes with a delay time delay of delay elements DLY10 and DLY11 with respect to output signal D3 of delay element DLY3.

  Therefore, when write digit line drive signal W_DL is at H level and write bit line drive signal W_BL is in an inactive state, a spin flop state is established in the variable magnetoresistive element (MTJ element). Next, when both the write digit line drive signal W_DL and the write bit line drive signal W_BL are at H level, the magnetization direction of the variable magnetoresistive element of the memory cell by the combined magnetic field rotates.

  Further, after the digit line current is stopped, the magnetization direction of the variable magnetoresistive element of the memory cell is rotated during the period when the write bit line drive signal W_BL is in the active state, and the easy axis direction is the bit line current induced magnetic field. The magnetization direction is set in a direction of 45 degrees.

  Therefore, also in this case, the selector 452 can alternatively select the selection circuits SLT10 to SLT12 so that the write time can be adjusted and data can be written reliably.

  When the writing failure is a failure in which the spin-flop state is not formed, the writing time is sequentially increased for each number of writings so as to increase the writing time. On the other hand, when this synthetic magnetic field is weak, the selection sequence of the selection circuits SLT10 to SLT12 is set so as to lengthen the writing time. Therefore, write bit line current activation signal W_BL can be moved in the range indicated by the arrow in FIG.

  Note that delay elements DLY4-DLY6 are not used in write current drive activation circuit 410 shown in FIG. The output signals D4-D6 of these delay elements DLY4-DLY6 may be used to generate a file signal of a part related to other writing. For example, output signals D5 and D6 of delay elements DLY5 and DLY6 may be used when setting activation of read verify read activation signal VFREN.

  As described above, according to the ninth embodiment of the present invention, in the toggle MRAM, the period during which the digit line current and the bit line current flow is adjusted at the time of internal rewriting. Can be executed.

  Further, the ninth embodiment may be used in combination with the configuration of the toggle MRAM shown in the other first to seventh embodiments.

  The present invention can be applied to a magnetic memory (MRAM) that uses variable magnetoresistive elements such as MTJ elements and MJT elements as memory elements. The MRAM may be a single memory or a memory integrated on the same chip as the processor, such as a microcomputer.

It is a figure which shows roughly the cross-section of a toggle MRAM cell. It is a figure which shows roughly the arrangement | positioning in a memory cell array of a toggle MRAM cell. FIG. 3 schematically shows a write sequence of the toggle MRAM cell shown in FIG. 2. It is a figure which shows roughly the cross-section of a spin injection type RAM cell. (A) And (B) is a figure which shows the magnetization direction at the time of data writing of a spin injection type MRAM cell with the direction of a write current. 1 schematically shows an entire configuration of an MRAM according to the present invention. FIG. It is a flowchart which shows the write-in sequence of MRAM according to this invention. FIG. 12 is a flowchart showing another write sequence of the MRAM according to the present invention. (A)-(C) is a figure which shows roughly the relationship between the writing conditions at the time of data writing, and a generation | occurrence | production defect rate. It is a figure which shows roughly the whole structure of toggle MRAM according to Embodiment 1 of this invention. It is a figure which shows more specifically the structure of the principal part of toggle MRAM shown in FIG. FIG. 12 is a signal waveform diagram showing a write operation of the toggle MRAM shown in FIG. 11. FIG. 11 is a diagram illustrating an example of a configuration of a word line driver circuit included in the WL driver illustrated in FIG. 10. It is a figure which shows the structure of the column selection part of the example of a change of Embodiment 1 of this invention. It is a figure which shows roughly the whole structure of the spin injection type MRAM according to the modification of Embodiment 1 of this invention. FIG. 16 is a diagram specifically showing a configuration of a main part of the spin injection MRAM shown in FIG. 15. FIG. 17 is a signal waveform diagram showing a data write sequence of the MRAM shown in FIG. 16. FIG. 12 is a timing diagram showing a write sequence of the MRAM according to the second embodiment of the present invention. It is a figure which shows schematically the structure of the command decoder and timing generator of MRAM according to Embodiment 2 of this invention. It is a figure which shows roughly the example of a change of the command decoder and timing generator of MRAM according to Embodiment 2 of this invention. FIG. 21 is a timing chart showing operations at the time of data writing of the command decoder and the timing generator shown in FIG. 20. It is a figure which shows roughly the structure of the principal part of MRAM according to Embodiment 3 of this invention. FIG. 23 is a timing chart showing an operation at the time of data writing of the configuration shown in FIG. It is a figure which shows schematically the structure of the command decoder and timing generator of MRAM according to the modification of Embodiment 3 of this invention. FIG. 25 is a timing chart showing operations at the time of data writing of the command decoder and the timing generator shown in FIG. 24. It is a figure which shows roughly the whole structure of MRAM according to Embodiment 4 of this invention. FIG. 27 is a flowchart showing a data write sequence of the MRAM shown in FIG. 26. FIG. 27 schematically shows a configuration of a main part of the sub-write circuit shown in FIG. 26. FIG. 27 schematically shows a configuration of a source line decode control circuit of the sub-write circuit shown in FIG. 26. It is a figure which shows roughly the structure of the principal part of MRAM according to Embodiment 5 of this invention. It is a flowchart which shows the operation | movement at the time of the data writing of a command decoder. It is a figure which shows roughly the structure of the principal part of MRAM according to Embodiment 6 of this invention. It is a figure which shows roughly the structure of the principal part of MRAM according to Embodiment 7 of this invention. It is a figure which shows an example of a structure of the reference voltage generation circuit of MRAM according to Embodiment 8 of this invention. FIG. 35 is a diagram showing steps of a reference voltage of the reference voltage generation circuit shown in FIG. 34. It is a figure which shows roughly the structure of the example of a change of the principal part of MRAM according to Embodiment 8 of this invention. It is a figure which shows schematically the structure of the 2nd modification of the principal part of MRAM of Embodiment 8 of this invention. It is a figure which shows schematically the structure of the 3rd modification of the principal part of MRAM according to Embodiment 8 of this invention. FIG. 39 is a signal waveform diagram representing an operation of the circuit shown in FIG. 38. It is a figure which shows schematically the structure of the write-current drive activation circuit according to Embodiment 9 of this invention. FIG. 41 is a timing chart representing an operation of the write current drive activation circuit shown in FIG. 40. It is a figure which shows the example of a change of the write-current drive activation circuit according to Embodiment 9 of this invention. FIG. 43 is a timing chart showing an operation of the circuit shown in FIG. 42.

Explanation of symbols

  1 free layer, 2 pin layer, 3 barrier layer, 11 free layer, 12 pin layer, 13 barrier layer, 20 memory cell array, 22 write system circuit, 23 read system circuit, 24 write control circuit, 50 X decoder, 52 DL driver / WL driver, 54 Y decoder, 56 bit line driver, 58 read amplifier, 60 Vref generation circuit, 62 command decoder, 64 timing generator, 65 input data latch, 66 comparator, 67 output data latch, 70 digit line decode Circuit, 72 digit line driver circuit, 73 bit line decode control circuit, 74 bit line decode circuit, 76 bit line drive circuit, 78 sense amplifier circuit, EG EXNOR circuit, 80 word line decode circuit, 82 word line driver circuit, 90 read Amplifier, 92 write driver, 100 source line decoder, 102 source line driver, 112 command decoder, 114 timing generator, 120 source line decode control circuit, 122 source line decode circuit, 124 source line drive circuit, 206 write activation circuit, 208 Pre-read inhibit circuit, 211 Write current drive activation circuit, 212 Verify activation circuit, 213 Busy signal generation circuit, 214 Latch, 215 Pulse generation circuit, 202 Write command detection circuit, 222 Write command detection circuit, 224 Write activation Circuit, 231 write current drive activation circuit, 232 verify activation circuit, 233 busy signal generation circuit, 234 latch, 235 pulse generation circuit, 240 switching circuit, 242 rewrite request issue circuit, 25 Rewrite request issue circuit, DDL0-DDLn input data latch, QDL0-QDLn output data latch, COM0-COMn comparator, MB0-MBn memory block, SBW0-SBWn sub-write system circuit, SAK0-SAKn sense amplifier circuit, SCK0 -SCKn sense control circuit, 300 command decoder, 302 timing generator, 306 Vref generation circuit, 304 OR circuit, 370i digit line decode control circuit, 376i bit line decode control circuit, 380 source line decode control circuit, 400 command decoder, 410 busy Signal generation circuit, 412 rewrite request issue circuit, 420 reference voltage generation circuit, 437 bit line drive circuit, 439 voltage follower, 444 count circuit, 446 variable Extension circuit, 448 set / reset flip-flop, 450 write current drive activation circuit, DLY1-DLY6 delay element, SLT1-SLT5 selection circuit, 452,453 selector, SLT10-SLT12 selection circuit, DLY10, DLY11 delay element, 454 OR circuit.

Claims (9)

A plurality of memory cells arranged in a matrix, each including a variable magnetoresistive element, and storing data according to a resistance value of the variable magnetoresistive element;
A write circuit for writing the write data to a write target memory cell of the plurality of memory cells according to the write data; and storage of the write target memory cell after the write data is written A write control circuit that compares data and the write data, and causes the write circuit to selectively write to the write target memory cell according to the comparison result; When the memory cell is rewritten, the memory cell is rewritten from the same initial state as before writing. The magnetic memory further includes a plurality of bit lines that are arranged corresponding to the memory cell columns and to which the memory cells of the corresponding column are connected,
The write circuit causes a current to flow in the same direction to the bit line to which the memory cell to be written is connected during data writing regardless of the logical value of the write data,
Further, the write control circuit further determines that the storage data of the write target memory cell and the logical value of the write data are equal before the first write of the write data to the write target memory cell. The magnetic memory according to claim 1, wherein it is determined whether or not a match is made, and writing to the memory cell to be written by the write circuit is stopped when coincidence is determined. A plurality of bit lines arranged corresponding to each memory cell column, each applying a magnetic field corresponding to a first write current from the write circuit to the memory cells in the corresponding column during writing;
A plurality of digit lines arranged corresponding to each memory cell row and each applying a magnetic field corresponding to a second write current supplied from the write circuit to the memory cells in the corresponding row during writing And further comprising
3. The write circuit according to claim 2, wherein when the mismatch of the write control circuit is determined, the relative relationship between the supply timings of the first and second write currents is different from the timing relationship during the writing. Magnetic memory. At least one of the number of determinations and the writing time of the write control circuit has a predetermined specified value,
2. The magnetic circuit according to claim 1, wherein the write-related circuit repeats a write sequence of the write data to the write target memory cell regardless of a match determination result of the write control circuit until the specified value is reached. Body memory. The plurality of memory cells are divided into a plurality of memory cell blocks, and the memory cells to be written are selected as write targets for different write data bits in each memory block,
The write control circuit performs the match determination operation for each memory block,
The write circuit is provided corresponding to each memory block, and writes a corresponding write data bit into a corresponding write target memory cell;
5. A magnetic memory according to claim 4, further comprising: a circuit that stops writing to a memory cell to be written in a corresponding memory block in accordance with a match determination output of the write control circuit.   The magnetic memory according to claim 1, further comprising a circuit that issues a write request to the outside of the magnetic memory when a mismatch of the write control circuit is detected.   2. The magnetic memory according to claim 1, further comprising a circuit that generates a write instruction internally and supplies it to the write system circuit in place of an external write instruction in accordance with the mismatch detection of the write control circuit.   The write control circuit determines whether the stored data of the memory cell to be written and the write data match when the write instruction is supplied from the outside of the magnetic memory, and the write data is determined according to the determination result. The write system circuit executes the write operation and omits the operation of comparing the stored data of the memory cell to be written with the write data when the write instruction is generated internally. 8. The magnetic memory according to claim 7, wherein writing is executed. In the memory cell, data is written by a current flowing through the variable resistance element,
The magnetic memory according to claim 1, wherein the write control circuit forcibly sets a signal indicating a comparison result of the previous period to a state indicating a write failure at the time of the first data write.

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