JP2010026294A - Fail-safe circuit and control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit that safely controls an image display device even if input of a pixel clock stops, and generates determination signals uniquely corresponding to a normal state and an abnormal state of an input signal. <P>SOLUTION: The fail-safe circuit is constituted having a determination unit 40 and a protection gate unit 90. The determination unit has a clock determination circuit 200 which determines whether the pixel clock is normal by using a count result of the pixel clock within a period determined with a reference clock, and generates a clock determination signal showing a result of the determination. The determination unit outputs the clock determination signal as a determination signal. Further, the protection gate unit passes a timing signal when the determination signal indicates a normal state. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a circuit that outputs a timing signal for controlling an image display device, and more particularly to a fail-safe circuit that controls output of a timing signal in order to operate the image display device safely and a control circuit including the fail-safe circuit. About.

  A conventional example of a control circuit for driving a liquid crystal display device as an image display device will be described with reference to FIG. 20 (see, for example, Patent Document 1). FIG. 20 is a schematic configuration diagram of a conventional control circuit.

  An image signal including a horizontal / vertical synchronizing signal and a pixel clock are input to the control circuit 18. The pixel clock is included in the image signal and is extracted by another circuit (not shown) provided in the previous stage.

  The control circuit 18 includes a timing signal generation circuit 21 and a fail safe circuit 38. The fail safe circuit 38 includes a determination unit 48 and a protection gate unit 90.

  The image signal input to the control circuit 18 is sent to the timing signal generation circuit 21. Further, the pixel clock input to the control circuit 18 is branched into two. One of the two branched pixel clocks is sent to the timing signal generation circuit 21, and the other is sent to the determination unit 48 of the fail safe circuit 38.

  The timing signal generation circuit 21 generates a timing signal including a start pulse using a horizontal / vertical synchronization signal included in the image signal. At this time, the timing signal generation circuit 21 performs signal processing using the pixel clock input to the clock input terminal CK.

  The timing signal generated by the timing signal generation circuit 21 is sent to the protection gate unit 90 of the fail safe circuit 38. Further, the timing signal generation circuit 21 outputs the signal used as the start pulse rising trigger as it is as a trigger signal. This trigger signal is sent to the determination unit 48 of the fail safe circuit 38.

  The determination unit 48 starts counting the pixel clock in response to the input of the trigger signal. The determination unit 48 outputs an H level signal as a determination signal while counting the clock pulses included in the pixel clock. As a result of counting the pixel clock, the determination unit 48 resets the count value to 0 and sets the output level of the determination signal to L level when the count value reaches a predetermined value 'N' set in advance. To do.

  This determination signal is sent to the protection gate unit 90 and used as a so-called gate signal. When the determination signal is at the H level, the protection gate unit 90 passes the timing signal and outputs it as an output signal. On the other hand, when the determination signal is at the L level, the protection gate unit 90 blocks the timing signal.

According to the conventional example of this control circuit, even if a malfunction occurs such that the start pulse included in the timing signal remains at the H level, the determination signal becomes the L level for a certain period and the timing signal is cut off. Therefore, the runaway of the image display device provided in the subsequent stage can be suppressed.
JP 2004-133124 A

  However, in the above-described conventional example of the control circuit, each time a trigger signal is input, the determination signal generated by the determination unit changes from L level to H level, and after a certain period determined by the count value of the pixel clock, Become a level. Therefore, the logical level of the determination signal does not uniquely correspond to the normal state or abnormal state of the image signal or pixel clock input to the control circuit. For this reason, the conventional fail-safe circuit can only be expected to prevent the start pulse from becoming too long. That is, it is difficult to use the determination signal for the purpose of resetting each internal circuit included in the control circuit in an abnormal state.

  Further, when the input of the pixel clock is stopped for some reason, the determination unit may remain at the H level because the count value does not reach the predetermined value N in the determination unit. In this case, it is impossible to prevent the start pulse from becoming long, and there is a risk of destroying the subsequent image display device.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to control the image display device safely even when the input of the pixel clock is stopped, as well as the normal state of the input signal and An object of the present invention is to provide a fail-safe circuit capable of generating a determination signal uniquely corresponding to an abnormal state and a control circuit including the fail-safe circuit.

  In order to achieve the above-described object, the fail-safe circuit of the present invention includes a determination unit and a protection gate unit. The determination unit determines whether or not the input of the pixel clock is normal using the count value of the pixel clock within the period determined by the count value of the reference clock, and generates a clock determination signal indicating the result of the determination A clock determination circuit is included. The determination unit outputs a clock determination signal as a determination signal. Further, the protection gate unit passes the timing signal when the determination signal indicates normal.

  The control circuit according to the present invention includes a synchronization signal extraction circuit that extracts a synchronization signal from an image signal, a timing signal generation circuit that generates a timing signal from the synchronization signal, and the fail-safe circuit described above.

  According to the fail-safe circuit of the present invention and the control circuit including the fail-safe circuit, it is determined whether or not the input of the pixel clock is normal using the reference clock independent of the pixel clock. . For this reason, when the pixel clock stops, this stop can be detected and the timing signal can be cut off. As a result, it is possible to prevent the subsequent image display device from being destroyed due to the long start pulse included in the timing signal.

  Further, according to the fail-safe circuit of the present invention and the control circuit including the fail-safe circuit, it is determined whether the pixel clock input is normal every period determined by the reference clock. Alternatively, a clock determination signal uniquely corresponding to the abnormal state is obtained. As a result, an internal circuit such as a timing signal generation circuit can be reset when the pixel clock input becomes abnormal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described, but it is merely a preferred example. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention.

(First embodiment)
A fail-safe circuit and a control circuit according to the first embodiment will be described with reference to FIG. FIG. 1 is a schematic configuration diagram of a control circuit according to the first embodiment.

  The control circuit 10 includes a synchronization signal extraction circuit 20, a timing signal generation circuit 22, and a fail safe circuit 30. An image signal, a pixel clock, and a reference clock are input to the control circuit 10, and the control circuit 10 outputs a timing signal as an output signal. The timing signal output as the output signal is used, for example, in a scanning line driving circuit of an image display device (not shown) provided in the subsequent stage of the control circuit 10.

  The pixel clock input to the control circuit 10 is branched into three pixel clocks and sent to the synchronization signal extraction circuit 20, the timing signal generation circuit 22, and the fail safe circuit 30, respectively.

  The synchronization signal extraction circuit 20 performs signal processing using the pixel clock input to the clock input terminal CK, and extracts the synchronization signal from the image signal. The extracted synchronization signal is sent to the timing signal generation circuit 22.

  The synchronization signal is a signal used to determine the timing for scanning the screen with an image display device such as a television receiver. The synchronization signal includes a horizontal synchronization signal and a vertical synchronization signal. The horizontal synchronization signal generates a pulse for each horizontal scan by one scan line. The vertical synchronizing signal generates a pulse every time one screen is scanned by a plurality of horizontal scanning lines.

  Although FIG. 1 shows an example in which the output of the synchronization signal is one system, the present invention is not limited to this example. For example, the output may be two or more, and the horizontal synchronization signal and the vertical synchronization signal may be output separately, or a plurality of the same type of synchronization signals may be output.

  The timing signal generation circuit 22 generates a timing signal from the synchronization signal in accordance with the specification of the scanning line driving circuit provided in the subsequent stage. At this time, the timing signal generation circuit 22 performs signal processing using the pixel clock input to the clock input terminal CK. The timing signal generated by the timing signal generation circuit 22 is sent to the fail safe circuit 30.

  The fail safe circuit 30 includes a determination unit 40 and a protection gate unit 90. The timing signal sent to the fail safe circuit 30 is sent to the protection gate unit 90.

  The protection gate unit 90 uses the determination signal generated by the determination unit 40 as a gate signal. When the determination signal indicates that the input of the pixel clock is normal, the protection gate unit 90 passes the timing signal and outputs it as an output signal. On the other hand, when the determination signal indicates that the pixel clock input is abnormal, the protection gate unit 90 blocks the timing signal. In the following description, it is assumed that when the logic level of the determination signal is the first level (L level), the input is abnormal, and when the logic level is the second level (H level), the input is normal. To do.

  The protection gate unit 90 can be configured by a circuit that controls the presence or absence of output according to the logic level of the determination signal, for example, an AND circuit that outputs a logical product of the timing signal and the determination signal.

  The determination unit 40 includes a clock determination circuit 200. A pixel clock and a reference clock are input to the determination unit 40.

  The pixel clock input to the determination unit 40 is a clock included in the image signal, similar to that used for signal processing in the synchronization signal extraction circuit 20 and the timing signal generation circuit 22. On the other hand, the reference clock is an independent clock from the pixel clock, and the reference clock and the pixel clock are asynchronous.

  The reference clock has clock pulses at a constant time interval, and can be generated by the reference clock generating means 24 configured by any suitable known crystal oscillation circuit. This reference clock is used as a determination reference in the determination unit 40. Therefore, it is preferable to provide the reference clock generating means 24 at a position physically close to the control circuit 10 in order to prevent an input abnormality of the reference clock due to cable disconnection or the like. Further, the reference clock generating means 24 may be provided inside the control circuit 10.

  The clock determination circuit 200 determines whether or not the input of the pixel clock is normal using the count value of the pixel clock within the period determined by the count value of the reference clock. The clock determination circuit 200 generates a clock determination signal indicating the result of this determination. This clock determination signal is output from the determination unit 40 as a determination signal.

(First configuration example of clock determination circuit)
A first configuration example of the clock determination circuit will be described with reference to FIG. FIG. 2 is a schematic configuration diagram of a first configuration example of the clock determination circuit.

  The clock determination circuit 200 includes a reference clock counting unit 220, a pixel clock counting unit 230, and a flip-flop circuit 240.

  The reference clock input to the clock determination circuit 200 is branched into two. One of the two branches is sent to the reference clock counter 220, and the other is sent to the flip-flop circuit 240.

  The reference clock counting unit 220 counts the reference clock. The reference clock counting unit 220 changes the logic level of the clear signal (CLEAR) from the L level to the H level when the reference clock count value AQ, which is the counting result, is equal to the preset clear value M. And the reference clock count value AQ is reset to zero. Further, the reference clock counting unit 220 changes the logic level of the check signal (CHECK) from the L level to the H level when the reference clock count value AQ is equal to a predetermined check value M−1. Output.

  The reference clock counting unit 220 includes, for example, any suitable and conventionally known clock counter (hereinafter referred to as a reference clock counter) 222 and a decoder 224.

  The reference clock counter 222 increases the reference clock count value AQ by one for each rising edge of each clock pulse of the reference clock, and outputs a reference clock count signal indicating the reference clock count value AQ. When the reference clock count value AQ becomes equal to the clear value M, the reference clock counter 222 resets the reference clock count value AQ to 0.

  The decoder 224 generates a check signal and a clear signal corresponding to the reference clock count value AQ indicated by the reference clock count signal. The check signal is H level when the reference clock count value AQ is equal to the check value M-1, and is L level otherwise. The clear signal is at the H level when the reference clock count value AQ is equal to the clear value M, and is at the L level otherwise.

  A pixel clock is input to the pixel clock counting unit 230, and the pixel clock counting unit 230 counts the pixel clock. When the pixel clock count value BQ, which is the count result, is equal to a predetermined stop value N, which is a preset value, the comparator signal is changed from the L level to the H level and output, and the count operation is stopped. Further, when the pixel clock count value BQ takes a value less than the stop value N, the pixel clock count unit 230 sets the comparator signal to the L level and performs a count operation. Further, when the clear signal input to the pixel clock counter 230 becomes H level, the pixel clock count value BQ is reset to zero.

  The pixel clock counting unit 230 includes, for example, a pixel counter 232, a pixel comparator 234, a first pixel constant unit 236, and a second pixel constant unit 238. The pixel counter 232 can be configured by a conventionally known clock counter having an enable terminal E and a load terminal LD. In addition, the pixel comparator 234 compares any two input signals and outputs an H level signal when they coincide with each other, and an arbitrary suitable circuit having a function of outputting an L level signal when they do not coincide with each other. it can. The first pixel constant unit 236 and the second pixel constant unit 238 hold a predetermined value set in advance, and send a signal indicating the held value to the pixel counter 232 or the pixel comparator 234. Yes.

  The clear signal generated by the reference clock counter 220 is input to the load terminal LD of the pixel counter 232. When the logic level of the signal input to the load terminal LD of the pixel counter 232 becomes H level, the value '0' held in the first pixel constant unit 236 is sent to the pixel counter 232 and the pixel clock count value BQ Is reset to zero.

  After the pixel clock count value BQ is reset to 0, the pixel counter 232 starts counting the pixel clock when the logic level of the clear signal input to the load terminal LD becomes L level. The pixel counter 232 increments the pixel clock count value BQ by one for each rising edge of the clock pulse included in the pixel clock, and outputs a pixel clock count signal indicating the pixel clock count value BQ, to the pixel comparator 234. send.

  The pixel comparator 234 compares the stop value N held in the second pixel constant unit 238 with the pixel clock count value BQ. The pixel comparator 234 outputs the logic level of the comparator signal as an H level when the pixel clock count value BQ is equal to or greater than the stop value N, and outputs the logic level of the comparator signal when the pixel clock count value BQ is less than the stop value N. Set to L level.

  The output of the pixel comparator 234 is inverted and input to the enable terminal E of the pixel counter 232. That is, when the logic level of the comparator signal is H level, the logic level of the signal input from the enable terminal E becomes L level, and the pixel counter 232 stops counting the pixel clock. On the other hand, when the logic level of the comparator signal is L level, the logic level of the signal input from the enable terminal E becomes H level, and the pixel counter 232 counts the pixel clock.

  As a result of the pixel counter 232 counting the pixel clock, when the pixel clock count value BQ becomes equal to the stop value N, the logical level of the comparator signal becomes H level and the pixel clock count is stopped. Accordingly, the pixel clock count value BQ is maintained at the stop value N, and the comparator signal is also maintained at the H level.

  In the flip-flop circuit 240, a comparator signal is input to the input terminal D, and a check signal is input to the enable terminal E. A reference clock is input to the clock terminal CK of the flip-flop circuit 240.

  When the logic level of the check signal input to the enable terminal E of the flip-flop circuit 240 becomes H level, the flip-flop circuit 240 takes in the comparator signal as data at the rising edge of the clock pulse of the reference clock. The flip-flop circuit 240 outputs the captured comparator signal as a clock determination signal.

(Operation of the first configuration example of the clock determination circuit)
The operation of the first configuration example of the clock determination circuit will be described with reference to FIGS. FIGS. 3A to 3H and FIGS. 4A to 4H are timing charts for explaining the operation of the first configuration example of the clock determination circuit. 3A to 3H show the case where the pixel clock input continues normally, and FIGS. 4A to 4H show the case where the pixel clock input stops.

  3A and 4A show the reference clock. 3B and 4B show the reference clock count signal. FIG. 3C and FIG. 4C show check signals. 3D and 4D show the clear signal. 3E and 4E show the pixel clock. 3 (F) and 4 (F) show the pixel clock count signal. 3 (G) and 4 (G) show the comparator signal. FIG. 3H and FIG. 4H show clock determination signals.

  In FIGS. 3A to 3H and FIGS. 4A to 4H, the horizontal axis indicates the time axis, and the vertical axis indicates the signal intensity as a logical level.

  First, the case where the pixel clock input is normal will be described with reference to FIG.

  The synchronization signal extraction circuit 20, the timing signal generation circuit 22, the reference clock counter 222, the pixel counter 232, and the flip-flop circuit 240 have a reset terminal R and are reset when the power is turned on. As a result, the logic levels of the check signal, the clear signal, the comparator signal, and the clock determination signal are all at the L level when the power is turned on. Further, it is assumed that the reference clock and the pixel clock are continuously input to the clock determination circuit 200 after the power is turned on.

  At time t0, power is turned on to each circuit included in the control circuit 10. After the power is turned on, the reference clock and the pixel clock are continuously input to the clock determination circuit 200. At this time, since the reference clock counter 222 counts the clock pulses of the reference clock, the reference clock count value AQ indicated by the reference clock count signal increases by one for each rising edge of the clock pulse of the reference clock.

  On the other hand, the pixel clock counter 232 does not perform counting, and the pixel clock count value BQ indicated by the pixel clock count signal remains 0.

  When the reference clock count value AQ becomes equal to the check value M-1 at time t1, the logic level of the check signal changes from the L level to the H level. When the logic level of the check signal becomes H level, the flip-flop circuit 240 fetches the comparator signal from the data terminal D at the rising edge of the clock pulse of the next reference clock (time t2). At time t2, since the comparator signal is at the L level, the logic level of the clock determination signal that is the output signal of the flip-flop circuit 240 is at the L level.

  Subsequently, when the reference clock count value AQ becomes equal to the clear value M at time t2, the logic level of the clear signal changes from the L level to the H level. When the logic level of the clear signal becomes H level, the pixel counter 232 loads the numerical value “0” from the first pixel constant unit 236. At this time, the logic level of the check signal changes from H level to L level.

  Thereafter, at time t3, after the logic level of the clear signal has changed from the H level to the L level, the pixel counter 232 starts counting the pixel clock. Further, since the reference clock count value AQ becomes equal to the clear value M at time t2, the reference clock count value AQ is reset to 0 at time t3.

  When the pixel clock count value BQ becomes equal to the stop value N at time t4, the pixel counter 230 changes the logical level of the comparator signal from the L level to the H level and stops counting the pixel clock. Accordingly, the pixel clock count value BQ continues to be equal to the stop value 'N', and during that time, the logic level of the comparator signal is maintained at the H level.

  It should be noted that the reference clock is counted independently while the pixel clock counting is stopped.

  When the reference clock count value AQ becomes equal to the check value M-1 at time t5, the logical level of the check signal changes from L level to H level. When the logic level of the check signal becomes H level, the flip-flop circuit 240 fetches the comparator signal from the data terminal D at the rising edge of the next reference clock pulse (time t6). At time t6, since the comparator signal is at the H level, the logic level of the clock determination signal that is the output signal of the flip-flop circuit 240 is at the H level.

  Subsequently, when the reference clock count value AQ becomes equal to the clear value M at time t6, the logic level of the clear signal changes from the L level to the H level. When the logic level of the clear signal becomes H level, the pixel counter 232 loads the numerical value “0” from the first pixel constant unit 236. At time t7, after the logic level of the clear signal changes from the H level to the L level, the pixel clock counter 232 resumes counting the pixel clock.

  Since the reference clock count value AQ becomes equal to the clear value M at time t6, the reference clock count value AQ is reset to 0 at time t7.

  Thereafter, the same operation is repeated from time t3 to time t7. However, while the clock pulse of the pixel clock is continuously input to the clock determination circuit 200, that is, when the input of the pixel clock is in a normal state, At the time when the flip-flop circuit 240 fetches data, the comparator signal becomes H level, so that the logic level of the clock determination signal is maintained at H level.

  Next, a case where the input of the pixel clock is stopped will be described with reference to FIG.

  It is assumed that the input of the pixel clock is stopped at time t8. In this case, the counting of the pixel clock is interrupted, but the counting of the reference clock continues because the reference clock is independent of the pixel clock.

  When the reference clock count value AQ becomes equal to the check value M-1 at time t10 as a result of continuing the reference clock counting, the logical level of the check signal changes from the L level to the H level. When the logic level of the check signal becomes H level, the flip-flop circuit 240 fetches the comparator signal from the data terminal D at the next rising edge (time t11) of the clock pulse included in the reference clock.

  Even when the input of the pixel clock is resumed at time t9, the input of the pixel clock is temporarily stopped, so that at the time t11, the pixel clock count value BQ becomes smaller corresponding to the stopped time. The stop value is less than N. Accordingly, when the flip-flop circuit 240 captures the comparator signal at time t11, the logical level of the comparator signal is L level. As a result, the logic level of the clock determination signal that is the output signal of the flip-flop circuit 240 becomes L level.

  In this way, when the pixel clock input is in an abnormal state that stops, the clock determination signal becomes L level.

  Further, when the logic level of the clear signal becomes H level at time t11, the pixel clock count value BQ of the pixel counter 232 is reset to 0, and then the pixel counter 232 is reset in the same manner as described with reference to FIG. Counting is done normally.

  As described above, according to this configuration, while the input of the pixel clock is continued, that is, when the input of the pixel clock is normal, the logic level of the clock determination signal becomes the H level, and the pixel clock When an abnormality occurs in the input of the clock, the logic level of the clock determination signal becomes L level.

  According to the fail-safe circuit of the present invention and the control circuit including the fail-safe circuit, it is determined whether or not the input of the pixel clock is normal using the reference clock independent of the pixel clock. . For this reason, even when the pixel clock is stopped, this can be detected and the output of the timing signal can be stopped.

  Further, according to the fail-safe circuit of the present invention and the control circuit including the fail-safe circuit, the normality and abnormality of the pixel clock are determined every period determined by the reference clock, so that the clock uniquely corresponding to the normality or abnormality of the input A determination signal is obtained.

  Therefore, the clock determination signal can be sent to the enable terminal E of the timing signal generation circuit 22 as a determination signal. With this configuration, the timing signal generation circuit 22 is operated only when the determination signal indicates that the pixel clock input is normal, and when the determination signal indicates that the pixel clock input is abnormal, the timing signal generation circuit 22 is operated. Can be reset.

  As a result, even when the inside of the timing signal generation circuit 22 becomes unstable due to an abnormality in the input of the pixel clock, the stable operation can be resumed by resetting the timing signal generation circuit 22. it can.

(Second configuration example of clock determination circuit)
A second configuration example of the clock determination circuit will be described with reference to FIG. FIG. 5 is a schematic configuration diagram of a second configuration example of the clock determination circuit.

  The clock determination circuit 201 is different in that it includes a clear signal delay 242 and a comparator signal delay 244 in addition to the first configuration example of the clock determination circuit described with reference to FIG. Since the other configuration is the same as that of the first configuration example, a duplicate description may be omitted.

  The pixel clock input to the clock determination circuit 201 is branched into two. One of the two branches is sent to the pixel clock counter 230, and the other is sent to the clear signal delay 242.

  The reference clock input to the clock determination circuit 201 is branched into three systems of reference clocks and sent to the reference clock counter 220, the flip-flop circuit 240, and the comparator signal delay 244, respectively.

  The clear signal delay unit 242 is provided between the reference clock counting unit 220 and the pixel clock counting unit 230. The clear signal delay unit 242 delays the clear signal generated by the reference clock counting unit 220 and sends it to the pixel clock counting unit 230 as a delayed clear signal. The clear signal delay 242 can be configured as a D flip-flop circuit. A pixel clock is input to the clock terminal CK of the clear signal delay 242. When the clear signal becomes H level, the delayed clear signal becomes H level at the next rising edge of the clock pulse included in the pixel clock, and when the clear signal becomes L level, the next of the clock pulse included in the pixel clock. At the rising edge, the delayed clear signal becomes L level.

  The comparator signal delay unit 244 is provided between the pixel clock counter 230 and the flip-flop circuit 240. The comparator signal delay unit 244 delays the comparator signal generated by the pixel clock counter 230 and sends it to the flip-flop circuit 240 as a delayed comparator signal. The comparator signal delay 244 can be configured as a D flip-flop circuit. The reference clock is input to the clock terminal CK of the comparator signal delay 244. When the comparator signal becomes H level, the delayed comparator signal becomes H level at the next rising edge of the clock pulse included in the reference clock, and when the comparator signal becomes L level, the next of the clock pulse included in the reference clock. At the rising edge, the delay comparator signal becomes L level.

  The clear signal delay unit 242 and the comparator signal delay unit 244 have a reset terminal and are reset when the power is turned on. The logic levels of the clear signal delay unit 242 and the comparator signal delay unit 244 are both set to L level when the power is turned on.

(Operation of Second Configuration Example of Clock Determination Circuit)
The operation of the second configuration example of the clock determination circuit will be described with reference to FIGS. 6A to 6J and FIGS. 7A to 7J are timing charts for explaining the operation of the second configuration example of the clock determination circuit. 6A to 6J show a case where the pixel clock input continues normally, and FIGS. 7A to 7J show a case where the pixel clock input stops.

  6A and 7A show the reference clock. FIG. 6B and FIG. 7B show the reference clock count signal. FIG. 6C and FIG. 7C show check signals. 6D and 7D show the clear signal. 6E and 7E show the pixel clock. FIGS. 6F and 7F show delayed clear signals. FIG. 6G and FIG. 7G show pixel clock count signals. FIGS. 6H and 7H show the comparator signals. 6 (I) and 7 (I) show the delayed comparator signal. FIG. 6J and FIG. 7J show clock determination signals.

  In FIGS. 6A to 6J and FIGS. 7A to 7J, the horizontal axis indicates the time axis, and the vertical axis indicates the signal intensity at a logical level.

  The reference clock, the reference clock count signal, the check signal, the clear signal, and the pixel clock are the same as those in the first configuration example of the clock determination circuit, and thus redundant description may be omitted.

  First, the case where the pixel clock input is normal will be described with reference to FIG.

  At time t0, power is turned on to each circuit included in the control circuit 10. After the power is turned on, the reference clock and the pixel clock are continuously input to the clock determination circuit 201. At this time, since the reference clock counter 222 counts the clock pulses of the reference clock, the reference clock count value AQ indicated by the reference clock count signal increases by one for each rising edge of the clock pulse of the reference clock.

  On the other hand, the pixel clock counter 232 does not perform counting, and the pixel clock count value BQ indicated by the pixel clock count signal remains 0.

  When the reference clock count value AQ becomes equal to the check value M-1 at time t1, the logic level of the check signal changes from the L level to the H level. When the logic level of the check signal becomes H level, the flip-flop circuit 240 fetches the delay comparator signal from the data terminal D at the next rising edge (time t2) of the clock pulse included in the reference clock. At time t2, since the delay comparator signal is at the L level, the logic level of the clock determination signal that is the output signal of the flip-flop circuit 240 is at the L level.

  Subsequently, when the reference clock count value AQ becomes equal to the clear value M at time t2, the logic level of the clear signal changes from the L level to the H level. When the logic level of the clear signal becomes H level, the clear signal delay unit 242 delays the input clear signal and outputs it as a delayed clear signal at the next rising edge of the clock pulse of the pixel clock (time t21). . At this time, the logic level of the check signal changes from H level to L level. Further, since the reference clock count value AQ becomes equal to the clear value M at time t2, the reference clock count value AQ is reset to 0 at time t3.

  When the logic level of the delayed clear signal becomes H level at time t 21, the pixel counter 232 loads the numerical value “0” from the first pixel constant unit 236.

  At time t22, after the logic level of the delayed clear signal becomes L level, the pixel counter 232 starts counting the pixel clock.

  When the pixel clock count value BQ becomes equal to the stop value N at time t4, the pixel clock count unit 230 changes the logical level of the comparator signal from L level to H level and stops counting the pixel clock. Accordingly, the pixel clock count value BQ continues to be equal to the stop value 'N', and during that time, the logic level of the comparator signal is maintained at the H level.

  When the logic level of the comparator signal becomes H level at time t4, the comparator signal delay unit 244 changes the comparator delay signal from L level to H level at the next rising edge of the clock pulse included in the reference clock (time t23). Change the output.

  It should be noted that the reference clock is counted independently while the pixel clock counting is stopped.

  When the reference clock count value AQ becomes equal to the check value M-1 at time t5, the logical level of the check signal changes from the L level to the H level. When the logic level of the check signal becomes H level, the flip-flop circuit 240 takes in the delayed comparator signal from the data terminal D at the rising edge of the clock pulse of the next reference clock (time t6). At time t6, since the delay comparator signal is at the H level, the logic level of the clock determination signal that is the output signal of the flip-flop circuit 240 is at the H level.

  At time t24, when the logic level of the delayed clear signal becomes H level, the pixel counter 232 loads the numerical value “0” from the first pixel constant unit 236. At time t25, after the logic level of the delayed clear signal has changed from the H level to the L level, the pixel clock counter 232 starts counting the pixel clock.

  Further, since the reference clock count value AQ becomes equal to the clear value M at time t6, the reference clock count value AQ is reset to 0 at time t7.

  Thereafter, the operation from time t3 to time t7 is repeated. While the clock pulse of the pixel clock is continuously input to the clock determination circuit, that is, when the pixel clock is in a normal state, the data in the flip-flop circuit 240 Since the delay comparator signal is at the H level at the time when the signal is taken in, the logic level of the clock determination signal is maintained at the H level.

  Next, a case where the input of the pixel clock is stopped will be described with reference to FIG.

  It is assumed that the input of the pixel clock is stopped at time t8. In this case, the counting of the pixel clock is interrupted, but the counting of the reference clock continues because the reference clock is independent of the pixel clock.

  When the reference clock count continues and the reference clock count value AQ becomes equal to the check value M-1 at time t10, the logic level of the check signal changes from the L level to the H level. When the logic level of the check signal becomes H level, the flip-flop circuit 240 fetches the delayed comparator signal from the data terminal D at the next rising edge (time t11) of the clock pulse included in the reference clock.

  Even when the input of the pixel clock is resumed at time t9, the pixel clock count value BQ becomes small corresponding to the stopped time at the time t11 because the input of the pixel clock is temporarily stopped. Therefore, the stop value is less than N. Therefore, when the flip-flop circuit 240 takes in the delay comparator signal at time t11, the logic level of the delay comparator signal becomes L level. As a result, the logic level of the clock determination signal that is the output signal of the flip-flop circuit 240 becomes L level.

  In this way, when the pixel clock input is in an abnormal state that stops, the clock determination signal becomes L level.

  Further, when the logic level of the delayed clear signal becomes H level at time t26, the pixel counter 232 is reset to 0, and thereafter the pixel counter 232 performs normal counting as described with reference to FIG. Is called.

  According to the second configuration example of the clock determination circuit described above, in addition to the effects obtained in the first configuration example of the clock determination circuit, the following effects can be obtained. That is, the second configuration example of the clock determination circuit delays the pixel signal by one cycle of the pixel clock with respect to the clear signal, resets the pixel clock counter, and delays the comparator output signal by one cycle of the pixel clock. . As a result, the time at which the comparator output signal changes increases the difference between the time at which the comparator output signal changes and the time of the rising edge included in the reference clock, ensuring that the flip-flop circuit enters the metastable state. Can be prevented.

(Another configuration example of the control circuit of the first embodiment)
Although FIG. 1 shows a configuration example in which the clock determination circuit outputs a determination signal of one system and then branches and sends it to the timing signal generation circuit 20 and the protection gate unit 90, it is not limited to this. .

  FIG. 8 is a schematic configuration diagram of a control circuit of a first modification. In the control circuit 11, the determination unit 41 of the fail safe circuit 31 includes an output gate unit 300. In the output gate unit 300, after branching the clock determination signal in two, one is sent to the timing signal generation circuit 22 and the other is sent to the protection gate unit 90. At this time, the determination signal may be appropriately amplified by the amplifier circuits 302 and 304.

  FIG. 9 is a schematic configuration diagram of a control circuit of a second modification. In the control circuit 12, the determination unit 42 of the fail safe circuit 32 includes an output gate unit 310. In the output gate unit 310, the clock determination signal is branched into two. The output gate unit 310 includes a test terminal 316 and an OR circuit 312.

  The OR circuit 312 is supplied with one of the two clock determination signals and the test signal input via the test terminal 316 after being appropriately amplified by the amplifier circuit 318. The OR signal that is the output of the OR circuit 312 is sent to the timing signal generation circuit 22 as a determination signal. Further, the other of the two branched clock determination signals is appropriately amplified by an amplifier 314 as necessary, and sent to the protection gate unit 90 as a determination signal.

  According to this configuration, for example, when an H level signal is input to the test terminal 316, the output of the OR circuit 312 becomes H level regardless of the logic level of the clock determination signal. As a result, since the logical level of the determination signal input to the enable terminal E of the timing signal generation circuit 22 is always H level, even when an abnormality occurs in the input of the pixel clock, the timing signal generation circuit 22 Is not reset. By utilizing this fact, it is possible to easily confirm the behavior of the timing signal generation circuit 22 when the pixel clock input is abnormal.

  FIG. 10 is a diagram illustrating a control circuit of a third modification. In the control circuit 13, the determination unit 43 of the failsafe circuit 33 includes an output gate unit 320. In the output gate unit 320, the clock determination signal is branched into three to the first to third clock determination signals. The protection gate unit 91 includes an AND gate 94 as a first gate circuit, and an OR gate 96 as a second gate circuit.

  The timing signal generation circuit 22 generates two systems of timing signals. One timing signal is sent to the AND gate 94 and the other timing signal is sent to the OR gate 96.

  The first clock determination signal is appropriately amplified by the amplifier circuit 322 as necessary, and is sent to the timing signal generation circuit 22 as the first determination signal while maintaining the positive logic.

  The second clock determination signal is appropriately amplified by the amplifier circuit 324 as necessary, and sent to the AND gate 94 of the protection gate unit 91 as the second determination signal while maintaining the positive logic. The processing using the second determination signal in the AND gate 94 is the same as in the first embodiment.

  The third clock determination signal is inverted to negative logic by the inverting circuit 326 and then sent to the OR gate 96 of the protection gate unit 91 as the third determination signal. That is, the logic level of the third determination signal sent to the OR gate 96 of the protection gate unit 91 is L level when the pixel clock input is normal, and H level when the pixel clock input is abnormal. Become.

  The output signal from the OR gate 96 outputs a timing signal as it is when the pixel clock is normal, and outputs a signal whose logic level is H level when the pixel clock is abnormal.

  Therefore, by using a timing signal that is an output signal from the OR gate 96 in the scanning line driver circuit provided in the subsequent stage, malfunction in the scanning line driver circuit can be effectively prevented.

(Second Embodiment)
A fail-safe circuit and a control circuit according to the second embodiment will be described with reference to FIG. FIG. 11 is a schematic configuration diagram of a control circuit according to the second embodiment.

  The control circuit 14 is different from the first embodiment in that the determination unit 44 of the fail-safe circuit 34 includes an operation determination circuit 400, and is otherwise the same as the first embodiment. In some cases, duplicate descriptions are omitted.

  The control circuit 14 includes a synchronization signal extraction circuit 20, a timing signal generation circuit 22, and a fail safe circuit 34. An image signal, a pixel clock, and a reference clock are input to the control circuit 14, and the control circuit 14 outputs a timing signal as an output signal. The timing signal output as the output signal is used, for example, in a scanning line driving circuit of an image display device (not shown) provided in the subsequent stage of the control circuit 14.

  The pixel clock input to the control circuit 14 is branched into three pixel clocks and sent to the synchronization signal extraction circuit 20, the timing signal generation circuit 22, and the fail safe circuit 34, respectively.

  The synchronization signal extraction circuit 20 performs signal processing using the pixel clock input to the clock input terminal CK, and extracts the synchronization signal from the image signal. The extracted synchronization signal is sent to the timing signal generation circuit 22.

  The timing signal generation circuit 22 generates a timing signal from the synchronization signal in accordance with the specification of the scanning line driving circuit provided in the subsequent stage. At this time, the timing signal generation circuit 22 performs signal processing using the pixel clock input to the clock input terminal CK. The timing signal generated by the timing signal generation circuit 22 is sent to the fail safe circuit 34.

  The fail safe circuit 34 includes a determination unit 44 and a protection gate unit 90. The timing signal sent to the fail safe circuit 34 is branched into two. One of the two branched timing signals is sent to the protection gate unit 90, and the other is sent to the determination unit 44.

  The protection gate unit 90 uses the determination signal generated by the determination unit 44 as a gate signal. When the determination signal indicates that the input of the pixel clock is normal, the protection gate unit 90 passes the timing signal and outputs it as an output signal. On the other hand, when the determination signal indicates that the pixel clock input is abnormal, the protection gate unit 90 blocks the timing signal.

  The determination unit 44 includes a clock determination circuit 200 and an operation determination circuit 400. The determination unit 44 receives a timing signal, a pixel clock, and a reference clock. The pixel clock input to the determination unit 44 is branched into two, one being sent to the clock determination circuit 200 and the other being sent to the operation determination circuit 400.

  As described with reference to FIG. 1, the clock determination circuit 200 uses the pixel clock count value within the period determined by the reference clock count value to determine whether or not the pixel clock input is normal. judge. The clock determination circuit 200 generates a clock determination signal indicating the result of this determination.

  The operation determination circuit 400 includes, for example, a counter 404, a decoder 406, and an AND gate 408. While the output of the counter 404 is from 0 to a predetermined value T, the decoder 406 outputs a signal whose logic level is H level, and outputs a signal of L level during the rest.

  A timing signal and a decoder output signal that is an output of the decoder 406 are input to the AND gate 408. The AND gate 408 generates an operation determination signal indicating that the timing signal is normal when both the timing signal and the decoder output signal are at the H level.

  That is, the operation determination circuit 400 outputs an operation determination signal indicating that the timing signal is normal within a period determined by the pixel clock and within a period in which the start pulse included in the timing signal is sustained. .

  The operation determination signal and the clock determination signal generated by the clock determination unit 200 are input to the AND gate 402, and the logical product (AND) of the operation determination signal and the clock determination signal is output as the determination signal.

  For example, the protection gate 90 is configured as a three-input AND gate to which a timing signal, an operation determination signal, and a clock determination signal are input, and the enable terminal E of the timing signal generation circuit 22 is It may be configured as a 2-input AND gate to which a clock determination signal is input, and the determination unit 44 may output an operation determination signal and a clock determination signal.

(Third embodiment)
The control circuit of the third embodiment will be described with reference to FIG. FIG. 12 is a schematic configuration diagram for explaining a control circuit of the third embodiment.

  The control circuit 15 of the third embodiment differs from the control circuit of the first embodiment in that the determination unit 45 of the fail-safe circuit 35 further includes a first synchronization determination circuit 410 and a second synchronization determination circuit 420. Since the other points are the same as those in the first embodiment, a duplicate description may be omitted.

  The control circuit 15 includes a synchronization signal extraction circuit 20, a timing signal generation circuit 22, and a fail safe circuit 35. The control circuit 15 receives two systems of image signals, a pixel clock, and a reference clock, and the control circuit 15 outputs a timing signal as two systems of output signals. The timing signal output as the output signal is used, for example, in the scanning line driving circuit of the image display device provided in the subsequent stage of the control circuit 15.

  The pixel clock input to the control circuit 15 is branched into three pixel clocks and sent to the synchronization signal extraction circuit 20, the timing signal generation circuit 22, and the fail safe circuit 35, respectively.

  The synchronization signal extraction circuit 20 performs signal processing using the pixel clock input to the clock input terminal CK, and extracts synchronization signals from the two systems of image signals. Here, for example, one is a horizontal synchronizing signal (sometimes referred to as a first synchronizing signal), and the other is a vertical synchronizing signal (sometimes referred to as a second synchronizing signal).

  Each of the first synchronization signal and the second synchronization signal is branched into two. One of the two branches is sent to the timing signal generation circuit 22, and the other is sent to the fail safe circuit 35.

  The timing signal generation circuit 22 generates a first timing signal and a second timing signal from the first synchronization signal and the second synchronization signal in accordance with the specifications of the scanning line driving circuit provided in the subsequent stage. At this time, the timing signal generation circuit 22 performs signal processing using the pixel clock input to the clock input terminal CK. The first timing signal and the second timing signal generated by the timing signal generation circuit 22 are sent to the fail safe circuit 35.

  The fail safe circuit 35 includes a determination unit 45 and a protection gate unit 92. The first timing signal and the second timing signal sent to the fail safe circuit 35 are sent to the protection gate unit 92.

  The protection gate unit 92 includes a first protection gate circuit 97 and a second protection gate circuit 98. The first protection gate circuit 97 and the second protection gate circuit 98 each use the determination signal generated by the determination unit 45 as a gate signal. The first protection gate circuit 97 and the second protection gate circuit 98 can be configured by AND circuits that control the presence or absence of output in accordance with the logic level of the determination signal.

  When the determination signal indicates that the input of the pixel clock is normal, the first protection gate circuit 97 passes the first timing signal and outputs it as an output signal. On the other hand, when the determination signal indicates that the input of the pixel clock is abnormal, the first protection gate circuit 97 blocks the first timing signal.

  Similarly, when the determination signal indicates that the input of the pixel clock is normal, the second protection gate circuit 98 passes the second timing signal and outputs it as an output signal. On the other hand, when the determination signal indicates that the pixel clock input is abnormal, the second protection gate circuit 98 blocks the first timing signal.

  The determination unit 45 includes a clock determination circuit 200, a first synchronization determination circuit 410, and a second synchronization determination circuit 420.

  The first synchronization signal input to the determination unit 45 is sent to the first synchronization determination circuit 410.

  The second synchronization signal input to the determination unit 45 is branched into two. One of the two branches is sent to the first synchronization determination circuit 410 and the other is sent to the second synchronization determination circuit 420.

  The reference clock input to the determination unit 45 is branched into two. One of the two branches is sent to the clock determination circuit 200, and the other is sent to the second synchronization determination circuit 420.

  The clock determination circuit 200 determines whether or not the input of the pixel clock is normal using the count value of the pixel clock within the period determined by the count value of the reference clock. The clock determination circuit 200 generates a clock determination signal indicating the result of this determination.

  The first synchronization determination circuit 410 determines whether or not the first synchronization signal is normal using the count value of the first synchronization signal within the period determined by the count value of the second synchronization signal. The first synchronization determination circuit 410 generates a first synchronization determination signal indicating the result of this determination.

  The second synchronization determination circuit 420 determines whether or not the second synchronization signal is normal using the count value of the second synchronization signal within the period determined by the count value of the reference clock. The second synchronization determination circuit 420 generates a second synchronization determination signal indicating the result of this determination.

  The clock determination signal, the first synchronization determination signal, and the second synchronization determination signal are input to the AND gate 430, and the logical product (AND) thereof is output as the determination signal.

  The clock determination circuit 200, the first synchronization determination circuit 410, and the second synchronization determination circuit 420 can be configured as similar determination circuits.

  These determination circuits include a first clock counting unit, a second clock counting unit, and a flip-flop circuit.

  The first clock counting unit counts the first clock input, and when the first clock count value, which is the counting result, becomes equal to the preset clear value M, the clear signal is changed from the L level to the H level. And the first clock count value is reset to zero. Further, the first clock counting unit changes the check signal from the L level to the H level when the first clock count value is equal to the preset check value M-1.

  The second clock counting unit counts the second clock, and when the second clock count value as a count result becomes equal to the preset stop value N, the comparator signal is changed from L level to H level, Stop counting operation. The second clock counter resets the second clock count value to 0 when the clear signal output from the first clock counter becomes H level.

  When the check signal is at the H level from the first clock counter, the flip-flop circuit takes in the comparator signal generated by the second clock counter and outputs it as a synchronization determination signal.

  Here, if the reference clock and the pixel clock are input as the first clock and the second clock, the first configuration example of the clock determination circuit described with reference to FIG. 2 is obtained. At this time, the clock determination circuit 200 outputs a clock determination signal as a synchronization determination signal.

  The first synchronization determination circuit 410 receives the second synchronization signal and the first synchronization signal as the first clock and the second clock, respectively. At this time, the first synchronization determination circuit 410 outputs a first synchronization determination signal as a synchronization determination signal.

  The second synchronization determination circuit 420 receives the reference clock and the second synchronization signal as the first clock and the second clock, respectively. At this time, the second synchronization determination circuit 420 outputs a second synchronization determination signal as a synchronization determination signal.

  Here, the clock determination circuit 200, the first synchronization determination circuit 410, and the second synchronization determination circuit 420 may have the same configuration as the second configuration example of the clock determination circuit described with reference to FIG.

  Note that the second synchronization signal and the reference clock are input to the second synchronization determination circuit 420. However, when the frequency of the second synchronization signal is significantly different from the frequency of the reference clock, the frequency is passed through the frequency divider 440. It is preferable to input the second synchronization determination circuit 420 after reducing the frequency of the reference clock.

  According to this configuration, since not only the pixel clock but also the input state of the synchronization signal is determined, the output of the timing signal can be stopped even when an abnormality occurs in the image signal or the synchronization signal. Further, by using a signal input to the timing signal generation circuit for determination, it is possible to detect an abnormality at an earlier stage in time series than the configuration described in Patent Document 1. As a result, control when an abnormality occurs becomes easier.

  For example, the protection gate unit is configured as a 4-input AND gate to which the timing signal, the clock determination signal, the first synchronization determination signal, and the second synchronization determination signal are input, and the enable terminal E of the timing signal generation circuit. Is configured as a three-input AND gate to which the clock determination signal, the first synchronization determination signal, and the second synchronization determination signal are input, and the determination unit receives the clock determination signal, the first synchronization determination signal, and the second synchronization determination signal. Each may be configured to output.

(Fourth embodiment)
A fail-safe circuit and a control circuit according to the fourth embodiment will be described with reference to FIGS. FIG. 13 is a schematic configuration diagram of a control circuit according to the fourth embodiment. FIG. 14 is a schematic configuration diagram of a clock determination circuit and a PLL determination circuit included in the fail-safe circuit according to the fourth embodiment.

  The control circuit 16 according to the fourth embodiment is different from the first embodiment in that the control circuit 16 includes a PLL (Phase Locked Loop) 26 and the determination unit 46 of the fail-safe circuit 36 includes a PLL determination circuit 600. The other points are the same as those in the first embodiment, and therefore, redundant description may be omitted.

  The control circuit 16 includes a synchronization signal extraction circuit 20, a timing signal generation circuit 22, a PLL 26, and a fail safe circuit 36. An image signal, a pixel clock, and a reference clock are input to the control circuit 16, and the control circuit 16 outputs a timing signal as an output signal. The timing signal output as the output signal is used, for example, in a scanning line driving circuit of an image display device (not shown) provided in the subsequent stage of the control circuit 16.

  The pixel clock input to the control circuit 16 is branched into three pixel clocks and sent to the synchronization signal extraction circuit 20, the PLL 26, and the fail safe circuit 36, respectively.

  The synchronization signal extraction circuit 20 performs signal processing using the pixel clock input to the clock input terminal CK, and extracts the synchronization signal from the image signal. The extracted synchronization signal is sent to the timing signal generation circuit 22.

  The PLL 26 converts the input pixel clock into a PLL clock and outputs it. The PLL clock is branched into two branches, one being sent to the timing signal generation circuit 22 and the other being sent to the failsafe circuit 36. The configuration of the PLL 26 is well known in the art and will not be described here.

  The timing signal generation circuit 22 generates a timing signal from the synchronization signal in accordance with the specification of the scanning line driving circuit provided in the subsequent stage. At this time, the timing signal generation circuit 22 performs signal processing using the PLL clock input to the clock input terminal CK. The timing signal generated by the timing signal generation circuit 22 is sent to the fail safe circuit 36.

  The determination unit 46 of the fail safe circuit 36 includes a clock determination circuit 202, a PLL determination circuit 600, and an AND gate 602.

  The reference clock input to the determination unit is branched into two, one is sent to the clock determination circuit 202 and the other is sent to the PLL determination circuit 600.

  The clock determination circuit 202 determines whether or not the input of the pixel clock is normal using the count value of the pixel clock within the period determined by the input count value of the reference clock. The clock determination circuit 202 generates a clock determination signal indicating the result of this determination.

  The PLL determination circuit 600 determines whether or not the input of the PLL clock is normal by comparing the count values of the pixel clock and the PLL clock within a period determined by the reference clock count value input to the determination unit 46. . The PLL determination circuit 600 generates a PLL determination signal indicating the result of this determination.

  The clock determination signal and the PLL determination signal are input to the AND gate 602. A logical product (AND) of the clock determination signal and the PLL determination signal is output from the determination unit 46 as a determination signal.

  The clock determination circuit 202 shown in FIG. 14 is different from the clock determination circuit 200 described with reference to FIG. 2 in that a comparator delay 244 is provided. Sometimes. Further, the comparator delay unit 244 may be configured in the same manner as that included in the clock determination circuit 201 described with reference to FIG. The clock determination circuit 202 also sends a pixel clock count signal to the PLL determination circuit 600.

  The PLL determination circuit 600 includes a PLL clock counting unit 630, a PLL determination unit 660, a PLL comparator delay unit 644, and a flip-flop circuit 640.

  A PLL clock is input to the PLL clock counter 630. The PLL clock counting unit 630 counts the PLL clock, and sends a PLL clock count signal indicating the PLL clock count value CQ that is the counting result to the PLL determination unit 660. Further, the clear signal generated by the clock determination circuit 202 is input to the PLL clock counting unit 630, and when the clear signal becomes H level, the PLL clock count value CQ is reset to zero.

  The PLL clock counting unit 630 includes, for example, a PLL counter 632, a PLL comparator 634, a first PLL constant unit 636, and a second PLL constant unit 638. The PLL counter 632 can be configured by a conventionally known clock counter having an enable terminal E and a load terminal LD. Further, the PLL comparator 634 is configured by any suitable circuit having a function of outputting an H level signal when two input signals are compared and matching, and outputting an L level signal when they do not match. it can. The first PLL constant unit 636 and the second PLL constant unit 638 hold a predetermined value set in advance, and send a signal indicating the held value to the PLL counter 632 or the PLL comparator 634.

  The clear signal generated by the reference clock counter 220 is input to the load terminal LD of the PLL counter 632. When the logic level of the signal input to the load terminal LD of the PLL counter 632 becomes H level, the value “0” held in the first PLL constant unit 636 is sent to the PLL counter 632, and the PLL clock count value CQ is Reset to zero.

  The PLL counter 632 starts counting the PLL clock when the logic level of the clear signal input to the load terminal LD becomes L level after the PLL clock count value CQ is reset. The PLL counter 632 increments the PLL clock count value CQ by one for each rising edge of the clock pulse included in the PLL clock, outputs two PLL clock count signals indicating the PLL clock count value CQ, and outputs one of them as the PLL. While sending to the comparator 634, the other is sent to the PLL determination unit 660.

  The PLL comparator 634 compares the stop value N held in the second PLL constant unit 638 with the PLL clock count value CQ. The PLL comparator 634 outputs the logic level of the comparator signal as an H level when the PLL clock count value CQ is equal to or greater than the stop value N, and outputs the logic level of the comparator signal when the PLL clock count value CQ is less than the stop value N. Set to L level. The output of the PLL comparator 634 is inverted and input to the enable terminal E of the PLL counter 632. That is, when the logic level of the comparator signal is H level, the logic level of the signal input from the enable terminal E becomes L level, and the PLL counter 632 stops counting the PLL clock. On the other hand, when the logic level of the comparator signal is L level, the logic level of the signal input from the enable terminal E becomes H level, and the PLL counter 632 counts the PLL clock.

  As a result of the PLL counter 632 counting the PLL clock, when the PLL clock count value CQ becomes equal to the stop value N, the logic level of the comparator signal becomes H level and the PLL clock count is stopped. Therefore, the PLL clock count value CQ is maintained at the stop value N, and the comparator signal is also maintained at the H level.

  The PLL determination unit 660 includes a comparator 662, a PLL comparison reference constant unit 664, a comparator delay unit 666, a register 668, a PLL comparator 670, a lower limit constant unit 672, and an upper limit constant unit 674.

  The comparator 662 compares the pixel clock count value BQ indicated by the pixel clock count signal with a predetermined PLL comparison reference L. The PLL comparison reference L is held in the PLL comparison reference constant unit 664.

  The comparator 662 outputs the pixel comparator signal as an H level when the PLL comparison reference L and the pixel clock count value BQ are equal. This pixel comparator signal is subjected to a predetermined delay by the comparator delay unit 666 and sent to the enable terminal E of the register 668 as a delayed pixel comparator signal.

  The register 668 takes in a PLL clock count signal indicating the PLL clock count value CQ output from the PLL clock counter 630 when the delayed pixel comparator signal is at the H level. The register 668 sends the PLL clock count value CQ to the PLL comparator 670 as a register signal.

  The PLL comparator 670 compares the PLL clock count value CQ indicated by the register signal sent from the register 668 with a preset lower limit value P and upper limit value Q. The lower limit value P and the upper limit value Q are held in the lower limit constant unit 672 and the upper limit constant unit 674, respectively.

  When the PLL clock count value CQ is larger than the lower limit value P and smaller than the upper limit value Q, the PLL comparator 670 outputs the PLL comparator signal as H level.

  The PLL comparator signal is delayed by a PLL comparator delay 644 and output as a delayed PLL comparator signal.

  In the flip-flop circuit 640, the delayed PLL comparator signal is input to the input terminal D, and the check signal is input to the enable terminal E. The reference clock is input to the clock terminal CK of the flip-flop circuit 640.

  When the logic level of the check signal input to the enable terminal E of the flip-flop circuit 640 becomes H level, the flip-flop circuit 640 takes in the delayed PLL comparator signal as data at the rising edge of the clock pulse of the reference clock. The flip-flop circuit 640 outputs the delayed PLL comparator signal that has been taken in as a PLL determination signal.

  Here, if the lower limit value P and the upper limit value Q are set before and after the PLL comparison reference L, that is, P ≦ L ≦ Q, the count values of the PLL clock and the pixel clock within the period determined by the reference clock are equal. Sometimes, the PLL comparator signal becomes H level. That is, in the PLL 26, after the pixel clock and the PLL clock are synchronized, that is, when the lock-in is completed, the PLL determination circuit 600 outputs the PLL determination signal as an H level. On the other hand, when the pixel clock and the PLL clock are asynchronous, that is, during the lock-in process, the PLL determination signal is set to the L level.

(Operation of Clock Determination Circuit and PLL Determination Circuit of Fourth Embodiment)
With reference to FIGS. 15 and 16, operations of the clock determination circuit and the PLL determination circuit of the fourth embodiment will be described. FIGS. 15A to 15Q and FIGS. 16A to 16Q are timing charts for explaining the operation of the clock determination circuit of the fourth embodiment. FIGS. 15A to 15Q show the case where the pixel clock input continues normally. FIGS. 16A to 16Q show that the pixel clock input is normal but the lock in the PLL is performed. It shows the case where is off.

  FIG. 15A and FIG. 16A show the reference clock. FIG. 15B and FIG. 15B show the reference clock count signal. FIG. 15C and FIG. 16C show check signals. FIG. 15D and FIG. 16D show a clear signal. FIG. 15E and FIG. 16E show pixel clocks. FIG. 15F and FIG. 16F show pixel clock count signals. FIG. 15G and FIG. 16G show the comparator signal. FIG. 15H and FIG. 16H show delayed comparator signals. FIG. 15I and FIG. 16I show clock determination signals. FIG. 15 (J) and FIG. 16 (J) show pixel comparator signals. FIGS. 15K and 16K show delayed pixel comparator signals. FIG. 15L and FIG. 16L show the PLL clock. FIG. 15 (M) and FIG. 16 (M) show the PLL clock count signal. FIG. 15N and FIG. 16N show register signals. FIG. 15 (O) and FIG. 16 (O) show PLL comparator signals. 15 (P) and 16 (P) show the delayed PLL comparator signal. FIG. 15 (Q) and FIG. 16 (Q) show the PLL determination signal.

  Further, in FIGS. 15A to 15Q and FIGS. 16A to 16Q, the horizontal axis indicates the time axis, and the vertical axis indicates the signal intensity at a logical level.

  The synchronization signal extraction circuit 20, the timing signal generation circuit 22, the reference clock counter 222, the pixel counter 232, and the flip-flop circuit 240 have a reset terminal and are reset when the power is turned on. As a result, the logic levels of the check signal, the clear signal, the comparator signal, and the clock determination signal are all at the L level when the power is turned on. Further, it is assumed that the reference clock and the pixel clock are continuously input after the power is turned on.

  First, the case where the pixel clock input is normal will be described with reference to FIG.

  At time t0, power is turned on to each circuit included in the control circuit 16. After the power is turned on, the reference clock and the pixel clock are continuously input to the determination unit. Further, the PLL clock that is the output of the PLL 26 is also input to the determination unit. At this time, since the reference clock counter 222 counts the clock pulses of the reference clock, the reference clock count value AQ indicated by the reference clock count signal increases by one for each rising edge of the clock pulse of the reference clock. On the other hand, the pixel clock counter 232 and the PLL counter 632 do not count, and the pixel clock count value BQ indicated by the pixel clock count signal and the PLL clock count value CQ indicated by the PLL clock count signal remain 0.

  When the reference clock count value AQ becomes equal to the check value M-1 at time t1, the logic level of the check signal changes from the L level to the H level.

  Subsequently, when the reference clock count value AQ becomes equal to the clear value M at time t2, the logic level of the clear signal changes from the L level to the H level. At this time, the logic level of the check signal changes from H level to L level.

  When the logic level of the check signal becomes H level at time t1, the flip-flop circuit 240 takes in the delay comparator signal from the data terminal D at the rising edge of the clock pulse of the next reference clock (time t2). At time t2, since the delay comparator signal is at the L level, the logic level of the clock determination signal that is the output signal of the flip-flop circuit 240 is at the L level.

  At time t2, when the logic level of the clear signal becomes H level, the pixel counter 232 loads the numerical value “0” from the first pixel constant unit 236. At time t3, after the logic level of the clear signal changes from H level to L level, the pixel counter 232 starts counting the pixel clock.

  This clear signal is also input to the LD terminal of the PLL counter 632. When the logic level of the clear signal becomes H level at time t 2, the PLL counter 632 loads the numerical value “0” from the first PLL constant unit 636. At time t3, after the logic level of the clear signal is changed from H level to L level, the pixel counter 232 starts counting the pixel clock, and the PLL counter 632 starts counting the PLL clock.

  When the pixel clock count value BQ becomes equal to the stop value N at time t4, the logical level of the comparator signal changes from the L level to the H level, and the pixel clock count stops. Accordingly, the pixel clock count value BQ continues to be equal to the stop value 'N', and during that time, the logic level of the comparator signal is maintained at the H level.

  It should be noted that the reference clock is counted independently while the pixel clock counting is stopped.

  When the reference clock count value AQ becomes equal to the check value M-1 at time t5, the logical level of the check signal becomes H level. When the logic level of the check signal becomes H level, the flip-flop circuit 240 takes in the delayed comparator signal from the data terminal D at the rising edge of the clock pulse of the next reference clock (time t6). At time t6, since the delay comparator signal is at the H level, the logic level of the clock determination signal that is the output signal of the flip-flop circuit 240 is at the H level.

  Further, when the logic level of the clear signal becomes H level at time t <b> 6, the pixel counter 232 loads the numerical value “0” from the first pixel constant unit 236. At time t7, after the logic level of the clear signal changes from H level to L level, the pixel clock counter 232 starts counting the pixel clock.

  Further, since the reference clock count value AQ becomes equal to the clear value M at time t6, the reference clock count value AQ is reset to 0 at time t7.

  When the pixel clock count value BQ becomes equal to the constant value L at time t41, the pixel comparator signal becomes H level. When the pixel comparator signal becomes H level, the pixel comparator delay unit 666 delays the pixel comparator signal and sends it to the register 668 as a delayed pixel comparator signal at the rising edge of the clock pulse of the PLL clock (time t42).

  The delayed pixel comparator signal is input to the enable terminal E of the register 668. When the delayed pixel comparator signal becomes H level, the register 668 takes in the PLL clock count signal. The captured PLL clock count signal is output as a register signal at the rising edge of the PLL clock (t43) and sent to the PLL comparator 670.

  The PLL comparator 670 compares the register value indicated by the register signal with the lower limit value P and the upper limit value Q. For example, when the register value R fetched at time t43 does not satisfy P ≦ R ≦ Q, the PLL comparator signal is at the L level.

  When the pixel clock count value BQ becomes equal to the constant value L at time t44, the pixel comparator signal becomes H level. When the pixel comparator signal becomes H level, the pixel comparator delay unit 666 delays the pixel comparator signal and sends it to the register 668 as the delayed pixel comparator signal at the next rising edge (time t45) of the clock pulse of the PLL clock.

  The delayed pixel comparator signal is input to the enable terminal E of the register 668. When the delayed pixel comparator signal becomes H level, the register 668 takes in the PLL clock count signal. The captured PLL clock count signal is output as a register signal at the rising edge of the PLL clock (t46) and sent to the PLL comparator 670.

  The PLL comparator 670 compares the register value indicating the PLL clock count value CQ captured in the register 668 with the lower limit value P and the upper limit value Q. For example, when the register value S fetched at time t46 satisfies P ≦ S ≦ Q, the PLL comparator signal becomes H level.

  This PLL comparator signal is delayed by a PLL comparator delay 644 and sent to the flip-flop circuit 640 as a delayed PLL comparator signal.

  At time t47, when the reference clock count value AQ becomes equal to the check value M-1, the logical level of the check signal becomes H level. When the logic level of the check signal becomes H level, the flip-flop circuit 640 takes in the delayed PLL comparator signal from the data terminal D at the rising edge of the clock pulse of the next reference clock (time t48). At time t48, since the delayed PLL comparator signal is at the H level, the logic level of the PLL determination signal that is the output signal of the flip-flop circuit 640 is at the H level.

  Next, a case where the pixel clock input is normal but the PLL is unlocked will be described with reference to FIG.

  Assume that the lock is released at time t50.

  When the pixel clock count value BQ becomes equal to the constant value L at time t51, the pixel comparator signal becomes H level. When the pixel comparator signal becomes H level, the pixel comparator delay unit 666 delays the pixel comparator signal and sends it to the register 668 as a delayed pixel comparator signal at the next rising edge (time t52) of the clock pulse of the PLL clock.

  The delayed pixel comparator signal is input to the enable terminal E of the register 668. When the delayed pixel comparator signal becomes H level, the register 668 captures the PLL clock count signal at the rising edge of the PLL clock (t53). The captured PLL clock count signal is output as a register signal and sent to the PLL comparator 670.

  The PLL comparator 670 compares the register value with the lower limit value P and the upper limit value Q. If the PLL is unlocked at time t50, the register value V fetched at time t53 does not satisfy P ≦ V ≦ Q. Therefore, the PLL comparator signal becomes L level.

  When the reference clock count value AQ becomes equal to the check value M-1 at time t55, the logic level of the check signal becomes H level. When the logic level of the check signal becomes H level, the flip-flop circuit 640 takes in the delayed PLL comparator signal from the data terminal D at the rising edge of the clock pulse of the next reference clock (time t56). At time t56, since the delayed PLL comparator signal is at L level, the logic level of the PLL determination signal that is the output signal of the flip-flop circuit 640 becomes L level.

  After the lock is released at t50, the lock-in process is performed again. When the lock-in process is performed, the PLL determination signal becomes H level at time t57 through the same process as described with reference to FIG.

  In the control circuit of the fourth embodiment, the synchronization signal extraction circuit operates with a pixel clock, and the timing signal generation circuit operates with a PLL clock. With this configuration, the image processing apparatus can be driven at a frequency different from the clock frequency of the input image signal.

  The PLL determination signal generated by the PLL determination circuit outputs a signal indicating normality when the PLL is locked, and outputs a signal indicating abnormality when the PLL is unlocked. For this reason, a timing signal can be generated according to the lock-in state in the PLL.

  In addition, about the control circuit of 4th Embodiment, you may make it a structure in which a fail safe circuit is further provided with the 1st synchronization determination circuit and the 2nd synchronization determination circuit similarly to the control circuit of 3rd Embodiment.

  With this configuration, since not only the pixel clock but also the input state of the synchronization signal is determined, the output of the timing signal can be stopped even when an abnormality occurs in the image signal or the synchronization signal. Further, by using a signal input to the timing signal generation circuit for determination, it is possible to detect an abnormality at an earlier stage in time series than the configuration described in Patent Document 1. As a result, control when an abnormality occurs becomes easier.

  In the control circuit of the fourth embodiment described above, an example in which the PLL clock and the pixel clock have the same frequency has been described. However, the PLL 26 may be configured such that the PLL clock frequency is different from the pixel clock frequency. In this case, the lower limit value P, the upper limit value Q, and the PLL comparison reference value L may be set as appropriate.

(Modification of Control Circuit of Fourth Embodiment)
A modification of the control circuit of the fourth embodiment will be described with reference to FIGS. 17 and 18. FIG. 17 is a schematic configuration diagram of a modified example of the control circuit. FIG. 18 is a schematic configuration diagram of a PLL.

  The control circuit 17 of this modification is different from the configuration of the fourth embodiment described with reference to FIG. 13 in that it includes an initialization signal generation circuit 604.

  The initialization signal generation circuit 604 can be configured by any suitable conventionally known logical differentiation circuit. The initialization signal generation circuit 604 receives the determination signal generated by the determination unit 46, and the initialization signal generation circuit 604 outputs an initialization signal. When the determination signal changes from the H level to the L level, the initialization signal becomes the H level for a predetermined time, and at other times, the initialization signal is constantly at the L level.

  The PLL 28 includes a first frequency divider 702, a second frequency divider 704, a phase comparator (PC) 706, a low pass filter (LPF) 708, and a voltage controlled oscillator (VCO) 710.

  The pixel clock is input to the first frequency divider 702. The output of the first frequency divider 702 and the output of the second frequency divider 704 are input to the phase comparator 706. A voltage signal corresponding to the phase difference between the output of the first frequency divider 702 and the output of the second frequency divider 704 is output from the phase comparator 706 as a phase difference signal. This phase difference signal passes through the low pass filter 708 and is then sent to the voltage controlled oscillator 710. The voltage controlled oscillator 710 outputs a signal having a frequency determined according to the voltage of the phase difference signal. The output signal of the voltage controlled oscillator 710 is branched into two, one being sent to the second frequency divider 704 and the other being outputted from the PLL 28 as a PLL clock.

  By operating the PLL 28, the outputs of the first frequency divider 702 and the second frequency divider 704 are synchronized. That is, the pixel clock input to the PLL 28 and the PLL clock output from the PLL 28 are synchronized. Note that the frequency of the PLL clock output from the PLL 28 can be determined by the reference frequency of the voltage controlled oscillator 710 and the size of the frequency division in the first frequency divider 702 and the second frequency divider 704.

  Here, a first switch 712 is provided between the phase comparator 706 and the low-pass filter 708. A second switch 714 is provided between the voltage supply terminal 716 and the input terminal of the voltage controlled oscillator 710.

  The first switch 712 and the second switch 714 are turned ON / OFF depending on the level of the initialization signal. The first switch 712 is turned on when the initialization signal is at the L level, and is turned off when the initialization signal is at the H level. On the other hand, the second switch 714 is turned on when the initialization signal is at the H level, and turned off when the initialization signal is at the L level.

  The voltage supply terminal 716 has a predetermined potential determined according to the characteristics of the voltage controlled oscillator 710. For example, when the input voltage of the voltage controlled oscillator 710 decreases and the frequency of the output signal decreases, the potential of the voltage supply terminal 716 is set to the ground potential GND. On the other hand, when the input voltage of the voltage controlled oscillator increases, the frequency of the output signal decreases, and the potential of the voltage supply terminal 716 is set to a high potential, for example, the potential VDD of the power supply voltage.

  FIG. 19 is a timing chart showing the operation of the PLL of this configuration example.

  FIG. 19A shows a clock determination signal. FIG. 19B shows a PLL determination signal. FIG. 19C shows a determination signal. FIG. 19D shows an initialization signal. FIG. 19E shows the frequency in the voltage controlled oscillator (VCO).

  When the control circuit 17 is powered on at time t0, each signal becomes L level. At this time, the output frequency of the voltage controlled oscillator 710 is the lowest in the operating range.

  Thereafter, the clock determination signal becomes H level at t80. At this stage, the PLL 28 is in the lock-in process, and the PLL determination signal is at the L level. Therefore, at time t80, the determination signal that is the logical product of the clock determination signal and the PLL determination signal is at the L level.

  Thereafter, when the lock-in is completed and becomes stable at time t81, the PLL determination signal becomes H level. At this time, the determination signal becomes H level.

  Next, it is assumed that the PLL 28 is unlocked at time t82. When the PLL 28 is unlocked, the PLL determination signal and the determination signal become L level.

  When the determination signal changes from H level to L level, the initialization signal becomes H level for a predetermined period. When the initialization signal becomes H level, the PLL is initialized and the PLL lock-in process is performed again. Then, it stabilizes at time t83.

  Next, it is assumed that the clock determination signal becomes L level at time t84. In this case, even if the PLL determination signal remains at the H level, the determination signal becomes the L level, so that the PLL is initialized.

  When the PLL 28 is unlocked, the PLL 28 starts oscillating at a frequency different from the target. However, if the oscillation frequency becomes higher than the target, the operation of each internal circuit may be abnormal. As a result, even when the frequency of the voltage controlled oscillator is higher than the target value, it is possible that the phase comparator 706 erroneously makes a determination and outputs the frequency controlled oscillator in a direction of increasing the frequency. When such an event occurs, the PLL does not operate normally unless the power is turned off.

  On the other hand, according to the configuration of this embodiment, the PLL is initialized every time the determination signal becomes L level. In this initialization, since the operation of the voltage controlled oscillator is always restarted from a low frequency, it is possible to prevent the PLL internal circuit from malfunctioning due to an input of a frequency higher than expected.

It is a schematic block diagram of the control circuit of 1st Embodiment. It is a schematic block diagram which shows the 1st structural example of a clock determination circuit. It is a time chart (1) for demonstrating operation | movement of a clock determination circuit. It is a time chart (2) for demonstrating operation | movement of a clock determination circuit. It is a schematic block diagram which shows the 2nd structural example of a clock determination circuit. It is a time chart (3) for demonstrating operation | movement of a clock determination circuit. It is a time chart (4) for demonstrating operation | movement of a clock determination circuit. It is a schematic block diagram of the 1st modification of the control circuit of 1st Embodiment. It is a schematic block diagram of the 2nd modification of the control circuit of 1st Embodiment. It is a schematic block diagram of the 3rd modification of the control circuit of 1st Embodiment. It is a schematic block diagram of the control circuit of 2nd Embodiment. It is a schematic block diagram of the control circuit of 3rd Embodiment. It is a schematic block diagram of the control circuit of 4th Embodiment. It is a schematic block diagram which shows the determination part of 4th Embodiment. It is a time chart (1) for demonstrating operation | movement of the determination part of 4th Embodiment. It is a time chart (2) for demonstrating operation | movement of the determination part of 4th Embodiment. It is a schematic block diagram of the modification of the control circuit of 4th Embodiment. It is a schematic block diagram of PLL used with the modification of the control circuit of 4th Embodiment. It is a schematic diagram for demonstrating the initialization process of PLL. It is a schematic block diagram which shows the prior art example of a control circuit.

Explanation of symbols

10, 11, 12, 13, 14, 15, 16, 17 Control circuit 20 Synchronization signal extraction circuit 22 Timing signal generation circuit 24 Reference clock generation means 26, 28 PLL
30, 31, 32, 33, 34, 35, 36, 37 Fail safe circuit 40, 41, 42, 43, 44, 45, 46 Judgment unit 90, 91, 92 Protection gate unit 94 AND gate 96 OR gate 97 1st Protection gate circuit 98 Second protection gate circuit 200, 201, 202 Clock determination circuit 220 Reference clock counter 222 Reference clock counter 224, 406 Decoder 230 Pixel clock counter 232 Pixel counter 234 Pixel comparator 236 First pixel constant unit 238 Second Pixel constant unit 240, 640 Flip-flop circuit 242 Clear signal delay unit 244 Comparator signal delay unit 300, 310, 320 Output gate unit 302, 304, 314, 318, 322, 324 Amplifier circuit 312 OR circuit 31 Test terminal 326 Inversion circuit 400 Operation determination circuit 402, 408, 430, 602 AND gate 404 Counter 410 First synchronization determination circuit 420 Second synchronization determination circuit 440 Frequency divider 600 PLL determination circuit 604 Initialization signal generation circuit 630 PLL clock count Unit 632 PLL counter 634, 670 PLL comparator 636 First PLL constant unit 638 Second PLL constant unit 644 PLL comparator delay unit 660 PLL determination unit 662 Comparator 664 PLL comparison reference constant unit 666 Comparator delay unit 668 Register 672 Lower limit constant unit 674 Upper limit Number 702 First frequency divider 704 Second frequency division 706 Phase comparator (PC)
708 Low pass filter (LPF)
710 Voltage controlled oscillator (VCO)
712 First switch 714 Second switch 716 Voltage supply terminal

Claims (21)

A clock determination circuit that determines whether or not the input of the pixel clock is normal using a count value of a pixel clock within a period determined by a count value of a reference clock, and generates a clock determination signal indicating the result of the determination A determination unit that outputs the clock determination signal as a determination signal;
A fail-safe circuit comprising: a protection gate section that allows a timing signal to pass when the clock determination signal indicates normality. A clock determination circuit that determines whether or not the input of the pixel clock is normal using a count value of a pixel clock within a period determined by a count value of a reference clock, and generates a clock determination signal indicating the result of the determination And an operation determination indicating that the timing signal is normal within a period determined by a count value of the pixel clock and within a period in which a start pulse included in one of the two branched timing signals is continued. A determination unit that includes an operation determination circuit that generates a signal, and outputs a logical product of the clock determination signal and the operation determination signal as a determination signal;
A fail-safe circuit comprising: a protection gate section that allows the timing signal to pass through the other branched into two when the clock determination signal and the operation determination signal indicate normality. The clock determination circuit includes:
The reference clock is counted, and when a reference clock count value as a counting result is equal to a preset clear value M, a clear signal is changed from the first level to the second level and output, and the reference clock is output. A reference clock counter for resetting the count value to 0 and changing the check signal from the first level to the second level when the reference clock count value is equal to a preset check value M−1;
The pixel clock is counted, and when the pixel clock count value as a count result is equal to a preset stop value N, the comparator signal is changed from the first level to the second level and output, and the counting operation is performed. A pixel clock counter that stops and resets the pixel clock count value to 0 when the clear signal is at a second level;
3. The fail-safe circuit according to claim 1, further comprising: a flip-flop circuit that takes in the comparator signal and outputs it as the clock determination signal when the check signal is at a second level. A clear signal delay device that delays the clear signal and sends it to the pixel clock counter;
The fail-safe circuit according to claim 3, further comprising a pixel determination signal delay device that delays the comparator signal and sends the delayed signal to the flip-flop circuit. A clock determination circuit that determines whether or not the input of the pixel clock is normal using a count value of a pixel clock within a period determined by a count value of a reference clock, and generates a clock determination signal indicating the result of the determination ,
A first synchronization determination signal indicating whether or not the first synchronization signal is normal using a count value of the first synchronization signal within a period determined by a count value of the second synchronization signal and indicating a result of the determination A first synchronization determination circuit for generating the first synchronization signal, and using the count value of the second synchronization signal within a period determined by the count value of the reference clock to determine whether the second synchronization signal is normal, A second synchronization determination circuit that generates a second synchronization determination signal indicating a determination result, and that outputs a logical product of the clock determination signal, the first synchronization determination signal, and the second synchronization determination signal as a determination signal And
A fail-safe circuit comprising: a protection gate section that allows a timing signal to pass when the clock determination signal, the first synchronization determination signal, and the second synchronization determination signal indicate normality. The clock determination circuit, the first synchronization determination circuit, and the second synchronization determination circuit each count the first clock, and when the first clock count value that is a count result is equal to a preset clear value M The clear signal is changed from the first level to the second level and output, the first clock count value is reset to 0, and the first clock count value is equal to the preset check value M-1. A first clock counting unit that sometimes changes the check signal from the first level to the second level and outputs it;
The second clock is counted, and when the second clock count value as a count result is equal to a preset stop value N, the comparator signal is changed from the first level to the second level and output, and the count is performed. A second clock counter that stops operation and resets the second clock count value to 0 when the clear signal is at a second level;
A flip-flop circuit that takes in the comparator signal and outputs it as the synchronization determination signal when the check signal is at the second level;
The clock determination circuit receives the reference clock and the pixel clock as a first clock and a second clock, respectively.
From the clock determination circuit, the clock determination signal is output as a synchronization determination signal,
The first synchronization determination circuit receives the second synchronization signal and the first synchronization signal as a first clock and a second clock, respectively.
The first synchronization determination circuit outputs the first synchronization determination signal as a synchronization determination signal.
The second synchronization determination circuit receives the reference clock and the second synchronization signal as a first clock and a second clock, respectively.
6. The failsafe circuit according to claim 5, wherein the second synchronization determination circuit outputs the second synchronization determination signal as a synchronization determination signal. The clock determination circuit, the first synchronization determination circuit, and the second synchronization determination circuit are:
A clear signal delay unit that delays the clear signal output from the first clock counting unit and sends the delayed signal to the second clock counting unit;
The fail-safe circuit according to claim 6, further comprising a comparator signal delay device that delays the comparator signal output from the second clock counting unit and sends the delayed signal to the flip-flop circuit. A clock determination circuit that determines whether or not the pixel clock is normal using a count value of a pixel clock within a period determined by a count value of a reference clock, and generates a clock determination signal indicating a result of the determination;
Compares the count values of the pixel clock and PLL clock within a period determined by the reference clock count value to determine whether or not the PLL clock is normal, and generates a PLL determination signal indicating the result of the determination A PLL decision circuit to perform,
A determination unit that outputs a logical product of the clock determination signal and the PLL determination signal as a determination signal;
A fail-safe circuit comprising: a protection gate section that allows a timing signal to pass when the clock determination signal and the PLL determination signal indicate normality. The clock determination circuit includes:
The reference clock is counted, and when a reference clock count value as a counting result is equal to a preset clear value M, a clear signal is changed from the first level to the second level and output, and the reference clock is output. A reference clock counter for resetting the count value to 0 and changing the check signal from the first level to the second level when the reference clock count value is equal to a preset check value M−1;
The pixel clock is counted, and when the pixel clock count value as a count result is equal to a preset stop value N, the pixel clock count signal is changed from the first level to the second level and is output, A pixel clock counter that stops the counting operation and resets the pixel clock count value to 0 when the clear signal is at the second level;
A flip-flop circuit that captures the pixel clock count signal and outputs it as a clock determination signal when the check signal is at the second level;
The PLL determination circuit includes:
A PLL counter that counts the PLL clock and outputs a PLL clock count signal indicating a PLL clock count value as a counting result;
A register that captures the PLL clock count signal when the pixel clock count value is equal to a preset pixel comparison reference value L;
The PLL clock count value indicated by the PLL clock count signal fetched by the register is compared with a preset lower limit value P and upper limit value Q, and the PLL clock count value is greater than or equal to the lower limit value P and the upper limit value Q. 9. The fail-safe circuit according to claim 8, further comprising: a PLL comparator that outputs a PLL determination signal by changing the PLL determination signal from the first level to the second level when: A clock determination circuit that determines whether or not the pixel clock is normal using a count value of a pixel clock within a period determined by a count value of a reference clock, and generates a clock determination signal indicating a result of the determination;
Compares the count values of the pixel clock and PLL clock within a period determined by the reference clock count value to determine whether or not the PLL clock is normal, and generates a PLL determination signal indicating the result of the determination A PLL determination circuit to perform,
A first synchronization determination signal indicating whether or not the first synchronization signal is normal using a count value of the first synchronization signal within a period determined by a count value of the second synchronization signal and indicating a result of the determination A first synchronization determination circuit for generating the second synchronization signal using a count value of the second synchronization signal within a period determined by the count value of the reference clock, and the determination A second synchronization determination circuit that generates a second synchronization determination signal indicating the result of the determination, and a logical product of the clock determination signal, the PLL determination signal, the first synchronization determination signal, and the second synchronization determination signal is a determination signal A determination unit that outputs as
A fail-safe circuit comprising: a protection gate section that allows a timing signal to pass when the clock determination signal, the PLL determination signal, the first synchronization determination signal, and the second synchronization determination signal indicate normality. The clock determination circuit, the first synchronization determination circuit, and the second synchronization determination circuit each count the first clock, and when the first clock count value that is a count result is equal to a preset clear value M The clear signal is changed from the first level to the second level and output, the first clock count value is reset to 0, and the first clock count value is equal to the preset check value M-1. A first clock counting unit that sometimes changes the check signal from the first level to the second level and outputs it;
The second clock is counted, and when the second clock count value as a count result is equal to a preset stop value N, the comparator signal is changed from the first level to the second level and output, and the count is performed. A second clock counter that stops operation and resets the second clock count value to 0 when the clear signal is at a second level;
A flip-flop circuit that takes in the comparator signal and outputs it as the synchronization determination signal when the check signal is at the second level;
The clock determination circuit receives the reference clock and the pixel clock as a first clock and a second clock, respectively.
From the clock determination circuit, the clock determination signal is output as a synchronization determination signal,
The first synchronization determination circuit receives the second synchronization signal and the first synchronization signal as a first clock and a second clock, respectively.
The first synchronization determination circuit outputs the first synchronization determination signal as a synchronization determination signal.
The second synchronization determination circuit receives the reference clock and the second synchronization signal as a first clock and a second clock, respectively.
From the second synchronization determination circuit, the second synchronization determination signal is output as a synchronization determination signal,
The PLL determination circuit includes:
A PLL counter that counts the PLL clock and outputs a PLL clock count signal indicating a PLL clock count value that is a count result;
A register that captures the PLL clock count signal when the pixel clock count value is equal to a preset pixel comparison reference value L;
The PLL clock count value indicated by the PLL clock count signal taken in by the register is compared with a preset lower limit value P and upper limit value Q, and the PLL clock count value is not less than the lower limit value P and not more than the upper limit value Q. 11. A fail-safe circuit according to claim 10, further comprising a PLL comparator that outputs the PLL determination signal by changing the PLL determination signal from the first level to the second level. A synchronization signal extraction circuit for extracting the synchronization signal from the image signal;
A timing signal generation circuit that generates a timing signal from the synchronization signal;
A control circuit comprising the fail-safe circuit according to claim 1. A synchronization signal extraction circuit for extracting the first synchronization signal and the second synchronization signal from the image signal;
A timing signal generation circuit for generating a timing signal from the first synchronization signal and the second synchronization signal;
A control circuit comprising the fail-safe circuit according to claim 5. A synchronization signal extraction circuit for extracting the synchronization signal from the image signal;
A timing signal generation circuit that generates a timing signal from the synchronization signal;
A PLL circuit for generating a PLL clock synchronized with the pixel clock;
A control circuit comprising the fail-safe circuit according to claim 8. A synchronization signal extraction circuit for extracting the first synchronization signal and the second synchronization signal from the image signal;
A timing signal generation circuit for generating a timing signal from the first synchronization signal and the second synchronization signal;
A PLL circuit for generating a PLL clock synchronized with the pixel clock;
A control circuit comprising the fail-safe circuit according to claim 10. The fail safe circuit includes an initialization signal generation circuit that generates an initialization signal when the determination signal changes from a normal state to an abnormal state;
16. The control circuit according to claim 14, wherein the PLL circuit is initialized in response to an input of the initialization signal. 17. The control circuit according to claim 16, wherein the voltage controlled oscillator provided in the PLL circuit has an oscillation frequency that falls within an operating range in response to the input of the initialization signal. The control circuit according to any one of claims 12 to 17, wherein the timing signal generation circuit is reset when the determination signal indicates an abnormality. The control according to claim 12, wherein the determination unit branches the determination signal into two, sends one to the timing signal generation circuit, and sends the other to the protection gate unit. circuit. The determination unit bifurcates the determination signal, sends a logical sum signal of one of the two branched and the test signal input via the test input terminal to the timing signal generation circuit, and the other of the two branched The control circuit according to any one of claims 12 to 18, wherein the control circuit sends the protection gate unit. The timing signal generation circuit generates a first timing signal and a second timing signal;
The protection gate unit includes an AND gate to which the first timing signal is input and an OR gate to which the second timing signal is input.
The determination unit
The determination signal is branched into three first to third determination signals,
Sending the first determination signal to the timing signal generation circuit;
Sending the second decision signal to the AND gate;
The control circuit according to claim 12, wherein the control circuit is inverted and then sent to the OR gate.

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