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JP2010021353A - Method of manufacturing semiconductor apparatus - Google Patents

Method of manufacturing semiconductor apparatus Download PDF

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JP2010021353A
JP2010021353A JP2008180292A JP2008180292A JP2010021353A JP 2010021353 A JP2010021353 A JP 2010021353A JP 2008180292 A JP2008180292 A JP 2008180292A JP 2008180292 A JP2008180292 A JP 2008180292A JP 2010021353 A JP2010021353 A JP 2010021353A
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semiconductor wafer
polishing
polishing pad
polished
cmp
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Shunsuke Doi
俊介 土肥
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Toshiba Corp
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To reduce the occurrence of defects in a semiconductor wafer transfer after a polishing processing. <P>SOLUTION: In a CMP method of a semiconductor wafer using a polishing apparatus, supply of polishing liquid is stopped after completion of CMP polishing of the semiconductor wafer, and pure water containing a surfactant agent is supplied on an interface between a semiconductor wafer 5 and a polishing pad 3, and a hydrophile processing of the interface between the polished semiconductor wafer 5 and the polishing pad 3 is carried out while rotating a semiconductor wafer holding head 4 and a polishing table 1 in the same rotation direction. After completion of the hydrophile processing, the semiconductor wafer 5 held by the semiconductor wafer holding head 4 at a position immediately after the hydrophile processing is separated from the polishing pad 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

近年、微細加工の進展に伴い、半導体集積回路(LSI)の高集積度化、低消費電力化、高機能化などが進行している。高集積度化された半導体集積回路(LSI)の微細加工では、半導体集積回路(LSI)が形成される半導体ウェハ表面の層或いは膜を平坦化することが大変重要となる。半導体ウェハ表面に設けられる配線材料(銅(Cu)、アルミニウム(AL)など)、層間絶縁膜(TEOS膜、Low−K膜など)、或いはレジスト膜等を平坦化する手法として半導体ウェハ研磨装置を用いたCMP(Chemical Mechanical Polishing 化学機械研磨)法が多用される。研磨液を用いて被処理面である半導体ウェハ表面を研磨した後、研磨パッドと半導体ウェハの界面が疎水性となり、半導体ウェハの離脱が困難になるので、半導体ウェハを研磨位置から研磨パッド外周端に移動させ、半導体ウェハの一部が研磨パッドから離れた位置で半導体ウェハの離脱を行っている。この動作は、例えばオーバーハング動作と呼称される(例えば、特許文献1参照。)。   In recent years, with the progress of microfabrication, higher integration, lower power consumption, higher functionality, and the like of semiconductor integrated circuits (LSIs) have progressed. In microfabrication of a highly integrated semiconductor integrated circuit (LSI), it is very important to flatten the layer or film on the surface of the semiconductor wafer on which the semiconductor integrated circuit (LSI) is formed. A semiconductor wafer polishing apparatus is used as a method for flattening a wiring material (copper (Cu), aluminum (AL), etc.), an interlayer insulating film (TEOS film, Low-K film, etc.) or a resist film provided on the surface of a semiconductor wafer. The CMP (Chemical Mechanical Polishing) method used is often used. After polishing the surface of the semiconductor wafer, which is the surface to be processed, using a polishing liquid, the interface between the polishing pad and the semiconductor wafer becomes hydrophobic, making it difficult to separate the semiconductor wafer. The semiconductor wafer is detached at a position where a part of the semiconductor wafer is separated from the polishing pad. This operation is called, for example, an overhang operation (see, for example, Patent Document 1).

特許文献1などに記載される研磨装置を用いた研磨処理後の半導体ウェハ移動では、研磨パッド外周端が半導体ウェハに接触することにより研磨された半導体ウェハ表面にダストなどのディフェクトが増加するという問題点がある。
特開平7−135192号公報
In the semiconductor wafer movement after the polishing process using the polishing apparatus described in Patent Document 1 or the like, a defect such as dust increases on the polished semiconductor wafer surface when the outer peripheral edge of the polishing pad contacts the semiconductor wafer. There is a point.
JP 7-135192 A

本発明は、研磨処理後の半導体ウェハ移動でのディフェクトの発生を低減できる半導体装置の製造方法を提供する。   The present invention provides a method of manufacturing a semiconductor device that can reduce the occurrence of defects due to movement of a semiconductor wafer after polishing.

本発明の一態様の半導体装置の製造方法は、研磨パッドに当接する半導体ウェハの被研磨面に研磨液を供給して前記半導体ウェハを研磨処理するステップと、研磨処理終了後、研磨液の供給を停止し、前記研磨パッドに当接する前記半導体ウェハの研磨された面に界面活性剤を含有する純水を供給し、前記研磨パッドと前記半導体ウェハの界面を親水化するステップと、親水化処理後、前記パッドから前記ウェハを離脱させ、前記ウェハを移動させるステップとを具備することを特徴とする。   In one embodiment of the present invention, a method of manufacturing a semiconductor device includes a step of supplying a polishing liquid to a surface to be polished of a semiconductor wafer in contact with a polishing pad to polish the semiconductor wafer, and supplying the polishing liquid after the polishing process is completed. A step of supplying a pure water containing a surfactant to the polished surface of the semiconductor wafer that comes into contact with the polishing pad, and hydrophilizing the interface between the polishing pad and the semiconductor wafer; And removing the wafer from the pad and moving the wafer.

本発明によれば研磨処理後の半導体ウェハ移動でのディフェクトの発生を低減できる半導体装置の製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can reduce generation | occurrence | production of the defect by the semiconductor wafer movement after a grinding | polishing process can be provided.

以下本発明の実施例について図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

まず、本発明の実施例1に係る半導体装置の製造方法について、図面を参照して説明する。図1は半導体ウェハの研磨工程を示すフローチャート、図2は研磨装置の構成図、図2(a)はその平面図、図2(b)は図2(a)のA−A線に沿う断面図、図3は半導体ウェハと研磨パッドの界面の親水化及び半導体ウェハ離脱を示す断面図、図4は比較例の研磨工程を示すフローチャート、図5は比較例の半導体ウェハ離脱を示す断面図である。   First, a method for manufacturing a semiconductor device according to Example 1 of the present invention will be described with reference to the drawings. 1 is a flowchart showing a polishing process of a semiconductor wafer, FIG. 2 is a configuration diagram of a polishing apparatus, FIG. 2A is a plan view thereof, and FIG. 2B is a cross section taken along line AA in FIG. FIG. 3, FIG. 3 is a sectional view showing the hydrophilization of the interface between the semiconductor wafer and the polishing pad and the separation of the semiconductor wafer, FIG. 4 is a flowchart showing the polishing process of the comparative example, and FIG. 5 is a sectional view showing the separation of the semiconductor wafer of the comparative example. is there.

図1に示すように、研磨装置を用いた半導体ウェハのCMP(Chemical Mechanical Polishing 化学機械研磨)法では、研磨パッドコンディショニング(S1)、半導体ウェハ研磨(S2)、界面親水化(S3)、半導体ウェハ離脱(S4)、及びCMP後処理(S5)という一連の工程が行われる。   As shown in FIG. 1, in a CMP (Chemical Mechanical Polishing) method of a semiconductor wafer using a polishing apparatus, polishing pad conditioning (S1), semiconductor wafer polishing (S2), interfacial hydrophilization (S3), semiconductor wafer A series of steps of separation (S4) and post-CMP processing (S5) are performed.

CMP法に使用される研磨装置には、図2(a)に示すように、研磨パッド3が表面に設けられる研磨テーブル1と、半導体ウェハの裏面を保持して半導体ウェハの研磨すべき表面を研磨パッドに当接させる半導体ウェハ保持ヘッド4と、研磨工程中に研磨液を供給する供給ノズル6と、純水或いは界面活性剤などを含む純水などを供給する供給ノズル7と、半導体ウェハ保持ヘッド4を研磨テーブル1に対して相対回転させ、左右方向に半導体ウェハ保持ヘッド4を移動させる図示しない半導体ウェハ保持ヘッド駆動機構とが設けられる。   As shown in FIG. 2A, the polishing apparatus used in the CMP method includes a polishing table 1 provided with a polishing pad 3 on the surface, and a surface to be polished of the semiconductor wafer while holding the back surface of the semiconductor wafer. Semiconductor wafer holding head 4 to be brought into contact with the polishing pad, supply nozzle 6 for supplying a polishing liquid during the polishing process, supply nozzle 7 for supplying pure water or pure water containing a surfactant, etc., and semiconductor wafer holding A semiconductor wafer holding head drive mechanism (not shown) that rotates the head 4 relative to the polishing table 1 and moves the semiconductor wafer holding head 4 in the left-right direction is provided.

研磨装置は、半導体集積回路(LSI)が形成される半導体ウェハ(例えば、12インチ半導体ウェハ)表面の配線材料(銅(Cu)、アルミニウム(AL)など)、層間絶縁膜(TEOS膜、Low−K膜など)、絶縁膜、ベア半導体ウェハ、或いはレジスト膜等の平坦化処理用として使用される。   The polishing apparatus includes a wiring material (copper (Cu), aluminum (AL), etc.) on the surface of a semiconductor wafer (for example, a 12-inch semiconductor wafer) on which a semiconductor integrated circuit (LSI) is formed, an interlayer insulating film (TEOS film, Low− K film, etc.), insulating film, bare semiconductor wafer, resist film, etc. are used for planarization treatment.

図2(b)に示すように、研磨テーブル1の下部には、研磨テーブル1を支持し、研磨テーブル1を回転させるスピンドル2が設けられる。半導体ウェハ保持ヘッド4は、研磨パッド3上の研磨される半導体ウェハ5を保持し、リテーナリング11、メンブレン12、上板13、及びスピンドル14が設けられる。ここでは、図示していないが、研磨パッド3の表面を処理して表面状態を調整するドレッサが研磨パッド3上に設けられる。   As shown in FIG. 2B, a spindle 2 that supports the polishing table 1 and rotates the polishing table 1 is provided below the polishing table 1. The semiconductor wafer holding head 4 holds the semiconductor wafer 5 to be polished on the polishing pad 3, and is provided with a retainer ring 11, a membrane 12, an upper plate 13, and a spindle 14. Although not shown here, a dresser for treating the surface of the polishing pad 3 to adjust the surface state is provided on the polishing pad 3.

リテーナリング11は、半導体ウェハ保持ヘッド4の端部に設けられ、半導体ウェハ5の側面に接し、研磨中に半導体ウェハ5が半導体ウェハ保持ヘッド4から飛び出さないように半導体ウェハ5を保持する。メンブレン12は、半導体ウェハ5と上板13の間に設けられ、半導体ウェハ5の研磨されるべき表面(第1主面)と相対向する裏面(第2主面)に当接し、半導体ウェハ5を保持する。上板13は、リテーナリング11及びメンブレン12を保持する。スピンドル14は、上板13上に設けられ、半導体ウェハ保持ヘッド4を回転させ、図示しない半導体ウェハ保持ヘッド駆動機構により回転制御される。   The retainer ring 11 is provided at an end portion of the semiconductor wafer holding head 4, is in contact with the side surface of the semiconductor wafer 5, and holds the semiconductor wafer 5 so that the semiconductor wafer 5 does not jump out of the semiconductor wafer holding head 4 during polishing. The membrane 12 is provided between the semiconductor wafer 5 and the upper plate 13, abuts against the back surface (second main surface) opposite to the surface (first main surface) to be polished of the semiconductor wafer 5, and the semiconductor wafer 5 Hold. The upper plate 13 holds the retainer ring 11 and the membrane 12. The spindle 14 is provided on the upper plate 13, rotates the semiconductor wafer holding head 4, and is rotationally controlled by a semiconductor wafer holding head driving mechanism (not shown).

研磨装置を用いた半導体ウェハのCMP法では、例えば研磨パッド5の交換直後であれば、半導体ウェハ5の研磨前に研磨パッド3のドレッシングを行う。具体的には純水等を供給させながらドレッサを回転させ、半導体ウェハのCMP研磨が可能になるように研磨パッド3の表面を改質する(ステップS1)。   In the CMP method of a semiconductor wafer using a polishing apparatus, for example, immediately after the polishing pad 5 is replaced, the polishing pad 3 is dressed before the semiconductor wafer 5 is polished. Specifically, the surface of the polishing pad 3 is modified so as to enable CMP polishing of the semiconductor wafer by rotating the dresser while supplying pure water or the like (step S1).

次に、研磨する半導体ウェハ5表面を研磨パッド3に当接させ、半導体ウェハ5裏面をメンブレン12で保持し、半導体ウェハ5の側面をリテーナリング11で保持しながら、供給ノズル6及び7から研磨液、純水などを半導体ウェハ5と研磨パッド3の界面に供給し、半導体ウェハ保持ヘッド4及び研磨テーブル1を同じ回転方向に回転させながら半導体ウェハのCMP研磨を行う。   Next, the surface of the semiconductor wafer 5 to be polished is brought into contact with the polishing pad 3, the back surface of the semiconductor wafer 5 is held by the membrane 12, and the side surface of the semiconductor wafer 5 is held by the retainer ring 11 and polished from the supply nozzles 6 and 7. Liquid, pure water or the like is supplied to the interface between the semiconductor wafer 5 and the polishing pad 3, and the semiconductor wafer is subjected to CMP polishing while the semiconductor wafer holding head 4 and the polishing table 1 are rotated in the same rotational direction.

CMP研磨処理により半導体ウェハ5と研磨パッド3の界面が、CMP研磨前と比較して疎水性が増す。この理由は、CMP研磨により研磨される材料の内部が露出し、材料本来の性質が出現するからである。例えば、研磨される材料が銅(Cu)やSiOCなど水に対して疎水性のものではより顕著となる。また、研磨された材料が半導体ウェハ5と研磨パッド3の界面に多く残存するほど疎水性が増す。疎水性が増すことにより、半導体ウェハ5と研磨パッド3の密着性が増加して半導体ウェハ5の離脱が困難となる(ステップS2)。   Due to the CMP polishing process, the interface between the semiconductor wafer 5 and the polishing pad 3 becomes more hydrophobic than before the CMP polishing. This is because the interior of the material to be polished by CMP polishing is exposed and the original properties of the material appear. For example, if the material to be polished is hydrophobic with respect to water, such as copper (Cu) or SiOC, it becomes more prominent. In addition, the more polished material remains at the interface between the semiconductor wafer 5 and the polishing pad 3, the more hydrophobic the material becomes. As the hydrophobicity increases, the adhesion between the semiconductor wafer 5 and the polishing pad 3 increases, and the separation of the semiconductor wafer 5 becomes difficult (step S2).

続いて、図3に示すように、半導体ウェハのCMP研磨終了後、研磨液の供給を停止し、界面活性剤を含む純水を半導体ウェハ5と研磨パッド3の界面に供給し、半導体ウェハ保持ヘッド4及び研磨テーブル1を同じ回転方向に回転させながら研磨された半導体ウェハ5と研磨パッド3の界面の親水化処理を行う。   Subsequently, as shown in FIG. 3, after the CMP of the semiconductor wafer is completed, the supply of the polishing liquid is stopped, and pure water containing a surfactant is supplied to the interface between the semiconductor wafer 5 and the polishing pad 3 to hold the semiconductor wafer. A hydrophilic treatment is performed on the interface between the polished semiconductor wafer 5 and the polishing pad 3 while rotating the head 4 and the polishing table 1 in the same rotation direction.

親水化処理では、疎水化された半導体ウェハ5の表面に界面活性剤が供給され、半導体ウェハ5の表面が親水化される。また、研磨パッド3の表面も親水化される。界面活性剤を含む水は、水単独よりも半導体ウェハ5と研磨パッド3の界面に充分供給されるので、研磨された半導体ウェハ5の表面に付着したダスト等が十分除去され、ウオーターマークなどの発生も抑制することができる。このため、半導体ウェハ5と研磨パッド3の界面の親水性が向上して研磨パッド3と半導体ウェハ5の密着性が低下し、半導体ウェハ5を研磨パッド3から容易に離脱させることが可能となる。   In the hydrophilization treatment, a surfactant is supplied to the surface of the semiconductor wafer 5 that has been hydrophobized, and the surface of the semiconductor wafer 5 is hydrophilized. Further, the surface of the polishing pad 3 is also made hydrophilic. Since the water containing the surfactant is sufficiently supplied to the interface between the semiconductor wafer 5 and the polishing pad 3 rather than the water alone, dust adhering to the surface of the polished semiconductor wafer 5 is sufficiently removed, and a water mark or the like is removed. Occurrence can also be suppressed. For this reason, the hydrophilicity of the interface between the semiconductor wafer 5 and the polishing pad 3 is improved, the adhesion between the polishing pad 3 and the semiconductor wafer 5 is lowered, and the semiconductor wafer 5 can be easily detached from the polishing pad 3. .

ここで、使用する界面活性剤には、室温でHLB(Hydrophile Lipophile Balance)が3〜12の値を有し、親水親油バランスのとれたもので、水に溶けたときに陽イオンや陰イオンを発生しない親水基を有する非イオン系の界面活性剤を用いるのが好ましい。HLBが3よりも小さい場合、親油性が増大し、HLBが12よりも大きく場合、親水性が増大する。非イオン系界面活性剤は、CMP研磨された半導体ウェハ5の表面を親水化させるが、陽イオンや陰イオンなどによる半導体ウェハ5の表面の改質を行わない。   Here, the surfactant used has a value of 3-12 HLB (Hydrophile Lipophile Balance) at room temperature and has a hydrophilic / lipophilic balance. When dissolved in water, a cation or an anion is used. It is preferable to use a nonionic surfactant having a hydrophilic group that does not generate water. When HLB is less than 3, lipophilicity increases, and when HLB is greater than 12, hydrophilicity increases. The nonionic surfactant makes the surface of the semiconductor wafer 5 subjected to CMP polishing hydrophilic, but does not modify the surface of the semiconductor wafer 5 with cations or anions.

非イオン系の界面活性剤の中で、耐薬品性が大で、消泡性を有するポリエーテル型非イオン系界面活性剤、例えば、ポリオキシエチレンアルキルエーテル(AE)やポリオキシエチレンアルキルフェニルエーテル(APA)などを用いるのが好ましい。発泡性を有する界面活性剤では、泡の発生により半導体ウェハ5と研磨パッド3の界面の親水化が阻害される。   Among nonionic surfactants, polyether-type nonionic surfactants having high chemical resistance and defoaming properties, such as polyoxyethylene alkyl ether (AE) and polyoxyethylene alkylphenyl ether (APA) or the like is preferably used. In the foaming surfactant, the generation of bubbles inhibits the hydrophilicity of the interface between the semiconductor wafer 5 and the polishing pad 3.

また、純水中の界面活性剤の濃度は0.1重量%以上、50重量%未満が好ましい。濃度が0.1重量%よりも小さな場合、界面活性剤の効果が出現せず、濃度が50重量%よりも大きな場合、界面活性剤の純水に対する可溶性が低下する。なお、HLBの算出にはアトラス法を用いているが、代わりにグリフィン法、デイビス法、川上法などを用いてもよい(ステップS3)。   The concentration of the surfactant in pure water is preferably 0.1% by weight or more and less than 50% by weight. When the concentration is less than 0.1% by weight, the effect of the surfactant does not appear, and when the concentration is more than 50% by weight, the solubility of the surfactant in pure water decreases. The Atlas method is used for calculating the HLB, but the Griffin method, the Davis method, the Kawakami method, etc. may be used instead (step S3).

そして、親水化処理終了後、半導体ウェハ保持ヘッド4を研磨テーブル1端まで移動させずに、親水化処理直後の位置で半導体ウェハ保持ヘッド4に保持されている半導体ウェハ5を研磨パッド3から離脱させる(ステップS4)。   After the hydrophilic treatment, the semiconductor wafer 5 held by the semiconductor wafer holding head 4 is detached from the polishing pad 3 at a position immediately after the hydrophilic treatment without moving the semiconductor wafer holding head 4 to the end of the polishing table 1. (Step S4).

次に、研磨され表面が親水性化された半導体ウェハ5を図示しない研磨装置の半導体ウェハ洗浄部に移動し、半導体ウェハ洗浄部でCMP後処理が行われる。   Next, the polished semiconductor wafer 5 whose surface is made hydrophilic is moved to a semiconductor wafer cleaning section of a polishing apparatus (not shown), and post-CMP processing is performed in the semiconductor wafer cleaning section.

この場合、半導体ウェハ5の表面が親水性を保持している間にCMP後処理を実行するのが好ましい。半導体ウェハ5の移動途中で半導体ウェハ5の表面が親水性から疎水性へと変化した場合、周囲のダスト等が半導体ウェハ5の表面に物理吸着しやすいので、例えば界面活性剤を含有する純水を半導体ウェハ5の表面に噴霧して半導体ウェハ5の表面の親水性を保持させるのが好ましい。   In this case, it is preferable to perform post-CMP treatment while the surface of the semiconductor wafer 5 is hydrophilic. When the surface of the semiconductor wafer 5 changes from hydrophilic to hydrophobic during the movement of the semiconductor wafer 5, the surrounding dust or the like is likely to be physically adsorbed on the surface of the semiconductor wafer 5, so that, for example, pure water containing a surfactant Is preferably sprayed onto the surface of the semiconductor wafer 5 to maintain the hydrophilicity of the surface of the semiconductor wafer 5.

CMP後処理では、CMP残渣や表面部のダメージ除去が行われる。例えば、ダマシン法による銅(Cu)のCMP研磨では、銅(Cu)表面に形成される錯体の除去、銅(Cu)イオンの除去、研磨パッド材料残渣除去、銅(Cu)酸化膜の除去などが行われる(ステップS5)。   In the post-CMP treatment, damage removal on the CMP residue and the surface portion is performed. For example, in CMP polishing of copper (Cu) by the damascene method, removal of complexes formed on the surface of copper (Cu), removal of copper (Cu) ions, removal of polishing pad material residue, removal of copper (Cu) oxide film, etc. Is performed (step S5).

図4に示すように、比較例の研磨装置を用いた半導体ウェハのCMP法では、研磨パッドコンディショニング(S1)、半導体ウェハ研磨(S2)、半導体ウェハ移動(S11)、半導体ウェハ離脱(S4)、及びCMP後処理(S5)という一連の工程が行われる。ここでいう比較例では、研磨された半導体ウェハは、研磨パッド外周端へ移動される。なお、本実施例と同じ工程については説明を省略し、異なる部分のみ説明する。   As shown in FIG. 4, in the CMP method of the semiconductor wafer using the polishing apparatus of the comparative example, polishing pad conditioning (S1), semiconductor wafer polishing (S2), semiconductor wafer movement (S11), semiconductor wafer separation (S4), A series of steps of CMP post-processing (S5) is performed. In the comparative example here, the polished semiconductor wafer is moved to the outer peripheral edge of the polishing pad. In addition, description is abbreviate | omitted about the process same as a present Example, and only a different part is demonstrated.

図5に示すように、半導体ウェハのCMP研磨終了後、研磨液の供給を停止し、純水を半導体ウェハ5と研磨パッド界面に供給し、半導体ウェハ保持ヘッド4及び研磨テーブル1を同じ回転方向に回転させながら研磨された半導体ウェハ5表面部分の研磨液を純水に置換する。なお、純水置換だけでは、研磨された半導体ウェハ5表面に付着したダスト等が十分除去されず、ウオーターマークなどの発生も抑制しにくい。   As shown in FIG. 5, after the CMP of the semiconductor wafer is completed, the supply of the polishing liquid is stopped, pure water is supplied to the interface between the semiconductor wafer 5 and the polishing pad, and the semiconductor wafer holding head 4 and the polishing table 1 are rotated in the same rotational direction. The polishing liquid on the surface portion of the semiconductor wafer 5 polished while rotating is replaced with pure water. Note that pure water replacement alone does not sufficiently remove dust and the like adhering to the polished semiconductor wafer 5 surface, and it is difficult to suppress generation of water marks and the like.

研磨された半導体ウェハ5の表面は、研磨前よりも疎水性が高まるので、この位置では半導体ウェハ5を研磨パッド3から離脱させることが困難となる。純水置換後、研磨パッド3の外周端部へと平行に半導体ウェハ保持ヘッド4に保持されている半導体ウェハ5を移動させる。具体的には、半導体ウェハ表面の一部を露出させ、研磨パッド3と半導体ウェハ5との密着性が低下し、半導体ウェハ5が研磨パッドから離脱させることができるまで移動させる。このとき、研磨パッド3の外周端部が半導体ウェハ5と接触するので半導体ウェハ5のダスト等のディフェクトが増加する(ステップS11)。   Since the surface of the polished semiconductor wafer 5 is more hydrophobic than before polishing, it is difficult to separate the semiconductor wafer 5 from the polishing pad 3 at this position. After the replacement with pure water, the semiconductor wafer 5 held by the semiconductor wafer holding head 4 is moved in parallel to the outer peripheral end of the polishing pad 3. Specifically, a part of the surface of the semiconductor wafer is exposed and moved until the adhesion between the polishing pad 3 and the semiconductor wafer 5 is lowered and the semiconductor wafer 5 can be detached from the polishing pad. At this time, since the outer peripheral edge of the polishing pad 3 is in contact with the semiconductor wafer 5, defects such as dust on the semiconductor wafer 5 increase (step S11).

次に、研磨され、純水置換された半導体ウェハ5を研磨パッド3の外周端部へ移動後、半導体ウェハ保持ヘッド4に保持されている半導体ウェハ5を研磨パッド3から離脱させる(ステップS12)。これ以降は本実施例と同様なので説明を省略する。   Next, after moving the polished and pure water-substituted semiconductor wafer 5 to the outer peripheral end of the polishing pad 3, the semiconductor wafer 5 held by the semiconductor wafer holding head 4 is detached from the polishing pad 3 (step S12). . Since the subsequent steps are the same as in the present embodiment, description thereof is omitted.

次に、研磨された半導体ウェハ表面に発生したディフェクトについて図6を参照して説明する。図6は半導体ウェハのディフェクト数の示す図である。ここでは、対象物にレーザ光を照射してディフェクトの数やディフェクトの分布の観察する欠陥検査装置を使用しているが、レーザ光の代わりにハロゲン光源、ストロボ光源、電子線などを用いてもよい。   Next, the defects generated on the polished semiconductor wafer surface will be described with reference to FIG. FIG. 6 is a diagram showing the number of defects in the semiconductor wafer. Here, a defect inspection apparatus is used to observe the number of defects and the distribution of the defects by irradiating the object with laser light, but a halogen light source, strobe light source, electron beam, etc. may be used instead of the laser light. Good.

図6に示すように、本実施例では、半導体ウェハ5の表面研磨後、界面活性剤を含む純水を用いて研磨された半導体ウェハ5の表面を親水化し、半導体ウェハ5を保持した半導体ウェハ保持ヘッド4の移動を研磨パッド3の外周端部まで行っていないので、ディフェクトの発生を大幅に抑制することができる。   As shown in FIG. 6, in this embodiment, after the surface of the semiconductor wafer 5 is polished, the surface of the semiconductor wafer 5 polished with pure water containing a surfactant is hydrophilized to hold the semiconductor wafer 5. Since the holding head 4 is not moved to the outer peripheral end of the polishing pad 3, the occurrence of defects can be greatly suppressed.

一方、比較例では、半導体ウェハ5を研磨パッド3の外周端部へ移動させるので、半導体ウェハ5が研磨パッド3の外周端部と接触する部分にディフェクトが集中して発生する。このため、ディフェクトの数は多く、ディフェクト分布は一様ではない。   On the other hand, in the comparative example, since the semiconductor wafer 5 is moved to the outer peripheral end portion of the polishing pad 3, defects concentrate on the portion where the semiconductor wafer 5 contacts the outer peripheral end portion of the polishing pad 3. For this reason, the number of defects is large and the defect distribution is not uniform.

上述したように、本実施例の半導体装置の製造方法では、研磨装置を用いた半導体ウェハのCMP法では、半導体ウェハのCMP研磨終了後、研磨液の供給を停止し、界面活性剤を含む純水を半導体ウェハ5と研磨パッド3の界面に供給し、半導体ウェハ保持ヘッド4及び研磨テーブル1を同じ回転方向に回転させながら研磨された半導体ウェハ5と研磨パッド3の界面の親水化処理を行う。親水化処理終了後、親水化処理直後の位置で半導体ウェハ保持ヘッド4に保持されている半導体ウェハ5を研磨パッド3から離脱させてから、半導体ウェハ5を移動させる。   As described above, in the semiconductor device manufacturing method of this embodiment, in the CMP method of the semiconductor wafer using the polishing apparatus, the supply of the polishing liquid is stopped after the CMP polishing of the semiconductor wafer, and Water is supplied to the interface between the semiconductor wafer 5 and the polishing pad 3, and the interface between the polished semiconductor wafer 5 and the polishing pad 3 is hydrophilized while rotating the semiconductor wafer holding head 4 and the polishing table 1 in the same rotation direction. . After the hydrophilic treatment is completed, the semiconductor wafer 5 held by the semiconductor wafer holding head 4 is detached from the polishing pad 3 at a position immediately after the hydrophilic treatment, and then the semiconductor wafer 5 is moved.

このため、研磨パッド3の外周端が半導体ウェハ5に接触するほど半導体ウェハ5を移動させることが不要となり、半導体ウェハ5の離脱動作を最小限度にすることができるので、研磨された半導体ウェハ5の表面にダストなどのディフェクトが付着するのを防止できる。   For this reason, it is not necessary to move the semiconductor wafer 5 as the outer peripheral edge of the polishing pad 3 comes into contact with the semiconductor wafer 5, and the separation operation of the semiconductor wafer 5 can be minimized. It is possible to prevent defects such as dust from adhering to the surface.

本発明は、上記実施例に限定されるものではなく、発明の趣旨を逸脱しない範囲で、種々、変更してもよい。   The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

例えば、実施例の研磨装置では、研磨液を用いてCMP研磨を行っているが、電解液を使用し、研磨テーブルと半導体ウェハの間に電圧を印加して電解研磨を行うECMP研磨装置にも適用することができる。   For example, in the polishing apparatus of the embodiment, the CMP polishing is performed using the polishing liquid, but the ECMP polishing apparatus that uses the electrolytic solution and applies the voltage between the polishing table and the semiconductor wafer to perform the electrolytic polishing. Can be applied.

本発明の実施例1に係る半導体ウェハの研磨工程を示すフローチャート。1 is a flowchart showing a polishing process of a semiconductor wafer according to Embodiment 1 of the present invention. 本発明の実施例1に係る研磨装置を示す概略構成図、図2(a)はその平面図、図2(b)は図2(a)のA−A線に沿う断面図。The schematic block diagram which shows the grinding | polishing apparatus which concerns on Example 1 of this invention, FIG. 2 (a) is the top view, FIG.2 (b) is sectional drawing which follows the AA line of Fig.2 (a). 本発明の実施例1に係る半導体ウェハと研磨パッド界面の親水化及び半導体ウェハ離脱を示す断面図。BRIEF DESCRIPTION OF THE DRAWINGS Sectional drawing which shows the hydrophilization of a semiconductor wafer and polishing pad interface, and semiconductor wafer separation which concern on Example 1 of this invention. 本発明の実施例1に係る比較例の研磨工程を示すフローチャート。The flowchart which shows the grinding | polishing process of the comparative example which concerns on Example 1 of this invention. 本発明の実施例1に係る比較例の半導体ウェハ離脱を示す断面図。Sectional drawing which shows semiconductor wafer separation of the comparative example which concerns on Example 1 of this invention. 本発明の実施例1に係る半導体ウェハのディフェクト数を示す図。The figure which shows the defect number of the semiconductor wafer which concerns on Example 1 of this invention.

符号の説明Explanation of symbols

1 研磨テーブル
2、14 スピンドル
3 研磨パッド
4 半導体ウェハ保持ヘッド
5 半導体ウェハ
6、7 供給ノズル
11 リテーナリング
12 メンブレン
13 上板
DESCRIPTION OF SYMBOLS 1 Polishing table 2 and 14 Spindle 3 Polishing pad 4 Semiconductor wafer holding head 5 Semiconductor wafer 6 and 7 Supply nozzle 11 Retainer ring 12 Membrane 13 Upper plate

Claims (4)

研磨パッドに当接する半導体ウェハの被研磨面に研磨液を供給して前記半導体ウェハを研磨処理するステップと、
研磨処理終了後、研磨液の供給を停止し、前記研磨パッドに当接する前記半導体ウェハの研磨された面に界面活性剤を含有する純水を供給し、前記研磨パッドと前記半導体ウェハの界面を親水化するステップと、
親水化処理後、前記パッドから前記ウェハを離脱させ、前記ウェハを移動させるステップと、
を具備することを特徴とする半導体装置の製造方法。
Polishing the semiconductor wafer by supplying a polishing liquid to the surface to be polished of the semiconductor wafer in contact with the polishing pad;
After completion of the polishing process, the supply of the polishing liquid is stopped, pure water containing a surfactant is supplied to the polished surface of the semiconductor wafer that contacts the polishing pad, and the interface between the polishing pad and the semiconductor wafer is supplied. Hydrophilizing, and
After the hydrophilic treatment, detaching the wafer from the pad and moving the wafer;
A method for manufacturing a semiconductor device, comprising:
前記半導体ウェハの離脱は、前記半導体ウェハの端部が前記研磨パッドの端部に接しない前記研磨パッド表面で行われることを特徴とする請求項1に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the separation of the semiconductor wafer is performed on a surface of the polishing pad where an end portion of the semiconductor wafer does not contact an end portion of the polishing pad. 前記界面活性剤は、ポリエーテル型非イオン系界面活性剤であり、室温でのHLBが3から12の範囲であることを特徴とする請求項1又は2に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the surfactant is a polyether type nonionic surfactant and has an HLB in the range of 3 to 12 at room temperature. 前記界面活性剤の前記純水に対する濃度は、0.1重量%から50重量%の範囲であることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 1, wherein a concentration of the surfactant with respect to the pure water is in a range of 0.1 wt% to 50 wt%. 5.
JP2008180292A 2008-07-10 2008-07-10 Method of manufacturing semiconductor apparatus Pending JP2010021353A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017164842A1 (en) * 2016-03-22 2017-09-28 Intel Corporation Improved optical metrology for chemical mechanical polish
WO2017175465A1 (en) * 2016-04-04 2017-10-12 グローバルウェーハズ・ジャパン株式会社 Protective film forming method for semiconductor substrate
CN113161223A (en) * 2020-01-07 2021-07-23 夏泰鑫半导体(青岛)有限公司 Method and system for processing wafer with polycrystalline silicon layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017164842A1 (en) * 2016-03-22 2017-09-28 Intel Corporation Improved optical metrology for chemical mechanical polish
WO2017175465A1 (en) * 2016-04-04 2017-10-12 グローバルウェーハズ・ジャパン株式会社 Protective film forming method for semiconductor substrate
US10840089B2 (en) 2016-04-04 2020-11-17 Globalwafers Japan Co., Ltd. Protective-film forming method for semiconductor substrate
CN113161223A (en) * 2020-01-07 2021-07-23 夏泰鑫半导体(青岛)有限公司 Method and system for processing wafer with polycrystalline silicon layer

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