JP2010016435A - Power-on reset circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably generate a reset signal even at instantaneous interruption of a power source. <P>SOLUTION: A power-on reset circuit which supplies the reset signal (a POR signal) to circuits to be reset at a time of power-on, is composed of: a voltage level shift circuit 10; a CR oscillation circuit 20; and an oscillation stop detection circuit 30. Power supply voltage VDD is made to be lowered by fixed voltage Vx using the voltage level shift circuit 10 and supplied to the power source of the CR oscillation circuit 20, and it is established that a period (i.e., a time interval) T1 of the CR oscillation operation becomes smaller than a detection time T2 of the oscillation stop detection circuit 30 in a normal operation region that is a normal operation power source voltage condition. Therefore, the POR signal can be stably generated in a suitable condition at a time of the power source interruption even when operation voltage ranges of power source of the circuits to be reset, are wide. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power-on reset circuit that generates a power-on reset signal (hereinafter referred to as “POR signal”) for initializing a reset circuit such as a system when the power is turned on. However, the present invention relates to a power-on reset circuit that can reliably generate a POR signal.

  Conventionally, as a technique related to a power-on reset circuit, for example, there are those described in the following documents.

JP 2007-324963 A

  Paragraph 0023 and FIG. 1 of Patent Document 1 describe a power-on reset circuit that can reliably output a POR signal even when the power supply voltage VDD temporarily falls and then recovers immediately after the power supply is interrupted. Yes. This power-on reset circuit has a latch circuit, and outputs a POR signal to an internal circuit in accordance with the voltage at the output node A of the latch circuit, and is connected between the power supply voltage VDD and the output node A. The first capacitor and an inversion circuit that supplies electric charge to the output node A when the power supply voltage VDD decreases and inverts the output of the latch circuit are provided. The inverting circuit is a circuit that generates a reset signal when the power supply is interrupted, and includes a diode and a P-channel MOS transistor (hereinafter referred to as “PMOS”) connected between the power supply voltage VDD and the output node A, a diode, and the like. The second capacitor is connected between the connection node C to the PMOS and the ground voltage, and the power supply voltage is applied to the gate of the PMOS.

  In the power-on reset circuit having such a configuration, the voltage Vc held by the second capacitor in the inverting circuit is supplied to the output node A when the PMOS is turned on at the time of a momentary interruption. Is raised to forcibly generate a POR signal (logic “L” level).

  The power supply level at the moment of interruption when the inverting circuit starts to operate is a level obtained by subtracting the diode forward voltage (about 0.6 V) and the PMOS threshold voltage (about 0.5 V) from the power supply voltage VDD before the momentary interruption. . For example, when an instantaneous interruption occurs at 3V, when it becomes (3V-about 1.1V) = 1.9V or less, a POR signal generation operation starts. That is, according to this power-on reset circuit, when the difference between the power supply voltage VDD before and after the instantaneous interruption becomes about 1.1 V or more, the POR signal generation operation is started.

  However, in the conventional power-on reset circuit, when the difference between the power supply voltage VDD before and after the instantaneous interruption exceeds a fixed value, the operation of generating the POR signal is started. In such a case, there is a risk that the reset operation may be entered even under conditions where the voltage does not drop to the minimum operating voltage due to a momentary interruption. That is, when the minimum operating voltage VDDmin of the reset target circuit is lower than (maximum operating voltage VDDmax−1.1V), for example, in the reset target circuit having an operation guarantee range of 2.0V to 3.6V, it is 3.6V. There may be a problem that the reset operation is started when the instantaneous interruption occurs (3.6V-1.1V) = 2.5V (> 2.0V), and the reset operation is performed although the operation is normally performed within the operation guarantee range. .

  The present invention solves such a problem and provides a power-on reset circuit capable of stably generating a POR signal under appropriate conditions at the time of instantaneous power interruption.

  The power-on reset circuit according to the present invention includes a voltage level shift circuit that outputs a second power supply voltage by applying a first power supply voltage, lowering the first power supply voltage by a certain voltage, and the second power supply voltage. Is applied, an oscillation circuit that oscillates at a constant period T1 and outputs an oscillation output signal when the level of the second power supply voltage is within a predetermined range, the first power supply voltage is applied, and the oscillation output signal And an oscillation stop detection circuit for outputting a reset signal to the reset target circuit when the oscillation stop state of the oscillation circuit is detected by the detection time T2.

  In a normal operation power supply voltage state when the level of the second power supply voltage is within the predetermined range, the cycle T1 is set to be smaller than the detection time T2, and the cycle T1 is set to the detection time. The reset signal is output when the time is larger than the time T2.

  According to the present invention, even when the operating power supply voltage range of the reset target circuit is wide, a reset signal can be stably generated under appropriate conditions at the time of instantaneous power interruption.

  The best mode for carrying out the invention will become apparent from the following description of the preferred embodiments when read in conjunction with the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Configuration of Example 1)
FIG. 1 is a circuit diagram illustrating a configuration example of a power-on reset circuit according to the first embodiment of the present invention.

  The power-on reset circuit includes a voltage level shift circuit 10 that generates a second power supply voltage (VDD−Vx) by reducing the first power supply voltage VDD by a constant voltage Vx, and the second power supply voltage ( The oscillation circuit of the CR oscillation circuit 20 is connected to the output terminal of the CR oscillation circuit 20 and is connected to the output terminal of the CR oscillation circuit 20. The oscillation stop detection circuit 30 outputs a POR signal by detecting a stop state based on a detection time T2.

  The voltage level shift circuit 10 includes a PMOS 11, and the power supply voltage VDD is applied to the source of the PMOS 11. The gate and drain of the PMOS 11 are connected in common.

  The CR oscillation circuit 20 includes first switch means (for example, a PMOS 21 and an N-channel MOS transistor (hereinafter referred to as “NMOS”) 24), a first resistor 22, a first capacitor 23, and an operational amplifier ( (Hereinafter referred to as “op-amp”) and the like. The PMOS 21, NMOS 24, and Schmitt trigger circuit 25 constitute a first switching circuit. A PMOS 21, a resistor 22, a connection point N22, a capacitor 23, and a ground GND are connected in series to the drain of the PMOS 11. The connection point N22 is connected to the drain of the NMOS 24 and the input terminal of the Schmitt trigger circuit 25, and the source of the NMOS 24 is connected to the ground GND. The output terminal of the Schmitt trigger circuit 25 is connected to the gate of the PMOS 21 and to the gate of the NMOS 24.

  The oscillation stop detection circuit 30 includes a second switch means (for example, a PMOS 31 and an NMOS 33), a second resistor 32, a second capacitor 34, and a second Schmitt trigger circuit 35 composed of an operational amplifier or the like. Have. The PMOS 31, NMOS 33, and Schmitt trigger circuit 35 constitute a second switching circuit. The gate of the PMOS 31 and the gate of the NMOS 33 are connected to the output terminal of the Schmitt trigger circuit 25, and the power supply voltage VDD is applied to the source of the PMOS 31. The drain of the PMOS 31 is connected to a connection point N32 via a resistor 32. The connection point N32 is connected to the ground GND via the drain / source of the NMOS 33 and is connected to the ground GND via a capacitor 34. Yes. An input terminal of the Schmitt trigger circuit 35 is connected to the connection point N32, and a POR signal is output from the output terminal of the Schmitt trigger circuit 35.

(Operation of Example 1)
The operation (a) to (f) of each circuit in the power-on reset circuit according to the first embodiment will be described.

(A) Operation of Voltage Level Shift Circuit 10 The PMOS 11 is in a diode connection state in which the power supply voltage VDD is applied to the source and the gate and the drain are connected in common, so that a substantially constant voltage Vx drop is generated between the source and the drain. As a result, a voltage (VDD−Vx) appears at the drain of the PMOS 11. Since this voltage (VDD-Vx) is supplied as the power supply for the CR oscillation circuit 20, the power supply voltage (VDD-Vx) of the CR oscillation circuit 20 is supplied at a level lower than the original power supply voltage VDD.

(B) Operation of the CR Oscillation Circuit 20 When the PMOS 21 is on and the NMOS 24 is off, it is “charging mode 1”, the capacitor 23 is charged via the resistor 22, the PMOS 21 is off, and the NMOS 24 is When in the on state, it is “discharge mode 1”, and the capacitor 23 is discharged by the NMOS 24. On / off control of the PMOS 21 and the NMOS 24 is performed by the oscillation output signal S25 of the Schmitt trigger circuit 25.

  The Schmitt trigger circuit 25 has a threshold voltage VtH1 on the high level side and a threshold voltage VtL1 on the low level side, receives an input from the connection point N22 of the resistor 22 and the capacitor 23, and oscillates if the voltage at the connection point N22 is equal to or less than VtH1. The output signal S25 becomes “L” level. In response to this, since the PMOS 21 is in the on state and the NMOS 24 is in the off state, the charging mode 1 is entered, so that the voltage at the node N22 increases. When the voltage at the node N22 exceeds the threshold voltage VtH1, the oscillation output signal S25 is inverted to “H” level, the PMOS 21 is turned off, and the NMOS 24 is turned on to switch to the discharge mode 1. This time, the voltage at the node N22 Turns down. When the voltage at the node N22 falls below the threshold voltage VtL1 from this state, the oscillation output signal S25 is inverted to the “L” level and returns to the charging mode 1. The above operation is repeated to realize the CR oscillation operation.

  The “L” level period T1 of the oscillation output signal S25 of the CR oscillation circuit 20 is determined by the first time constant τ1 determined by the resistor 22 and the capacitor 23, and the threshold voltages VtH1 and VtL1.

(C) Operation of Oscillation Stop Detection Circuit 30 The oscillation stop detection circuit 30 receives the oscillation output signal S25 of the CR oscillation circuit 20, and when the oscillation output signal S25 is at "L" level, the PMOS 31 is on and the NMOS 33 is In the “charge mode 2” in the off state, the capacitor 34 is charged via the resistor 32. When the oscillation output signal S25 is at the “H” level, the PMOS 31 is in the off state and the NMOS 33 is in the “discharge mode 2”, and the capacitor 34 is discharged by the NMOS 33. The Schmitt trigger circuit 35 receives the voltage at the connection point N32 of the resistor 32 and the capacitor 34, and when the voltage at the connection point N32 rises from a low level and exceeds the threshold voltage VtH2 on the high level side, the output POR signal is “ When the voltage at the node N32 drops from the high level side and falls below the low level side threshold voltage VtL2, the POR signal is set to the “L” level.

  As described above, the oscillation stop detection circuit 30 detects that the “L” level period T1 of the oscillation output signal S25 is longer than the time T2 determined by the second time constant τ2 by the resistor 32 and the capacitor 34 and the threshold voltage VtH2. Is determined to be in the oscillation stop state, and the POR signal is set to the “H” level, that is, the POR signal is output.

(D) Power Supply Voltage Dependent Characteristics of Period T1 and Time T2 FIG. 2 is a diagram showing characteristics with respect to the power supply voltage VDD of the period T1 and time T2 in the power-on reset circuit of FIG.

  In FIG. 2, the horizontal axis represents the power supply voltage VDD level, and the vertical axis represents time. A curve T1 ′ is a characteristic in the period of “L” level of the oscillation output signal S25 when the power of the CR oscillation circuit 20 is directly supplied from the power supply voltage VDD node. The power supply voltage of the CR oscillation circuit 20 is (VDD− Vx), the period T1 has a characteristic that the curve T1 ′ is shifted by the voltage Vx along the power supply voltage VDD axis.

  When the power supply voltage VDD decreases, both the period T1 and the time T2 increase because of an increase in the on-resistance of the PMOS 21 and the PMOS 31 and a decrease in the response speed of the Schmitt trigger circuits 25 and 35. It reaches a stop state that does not work. Since there is a shift of the voltage Vx, the period T1 reaches the stop state (oscillation stop state) earlier than the time T2 as the power supply voltage VDD decreases. The CR oscillation circuit 20 is in a state in which the PMOS 21 is not sufficiently turned on in that state, so that it cannot be charged while it is in the charged state 1 or is charged slowly. At this time, the oscillation output signal S25 remains at the “L” level. It has become.

  In FIG. 2, at the intersection (cross point) X of the curves of the period T1 and the time T2, the power supply voltage VDD = VDDX level. With this as a boundary, in the region of the normal operation power supply voltage state where the power supply voltage VDD is higher than the VDDX level, Since the period T1 <time T2, the POR signal is held at the “L” level. This state becomes the “normal operation region” of the reset target circuit.

  The relationship of the period T1 <time T2 is realized by setting the relationship between the time constants τ1 and τ2 as τ1 * 2≈τ2 (VtH1≈VtH2) as an example here. On the other hand, when the power supply voltage VDD is lower than the VDDX level, the period T1> time T2, that is, the POR signal is set to the “H” level, and the reset target circuit is reset.

  As described above, the period T1 characteristic is shifted by the voltage Vx, and the cross point X is provided on the characteristics of the period T1 and the time T2, so that the POR signal generates a power supply voltage VDD region lower than the cross point X. Can be an area.

(E) Setting method of voltage Vx When the minimum operation guaranteed power supply voltage of the reset target circuit is VDD1, and the minimum operation power supply voltage of the oscillation stop detection circuit 30 is VDD30 min,
VDD2 = (VDD30min + Vx) <VDDX <VDD1
The voltage Vx is determined so that the above relationship is established within the range of the characteristic variation of all the components of the circuit.

(F) Time chart of the power-on reset circuit of FIG. 1 (FIGS. 3 to 5)
FIG. 3 is a time chart showing the operation of the power-on reset circuit of FIG.
“Section (1)” in FIG. 3 indicates a state in which the power supply voltage VDD rises from 0 V, and “Section (2)” indicates a state in which an instantaneous interruption occurs in the power supply voltage VDD.

  FIG. 4 is a time chart showing an operation in which the time axis of “section (1)” in FIG. 3 is expanded. FIG. 5 shows an operation in which the time axis of “section (2)” in FIG. It is a time chart which shows.

  In FIG. 4, the VDD1 level and VDD2 level of the power supply voltage VDD indicate the voltage levels shown in FIG. When the power supply voltage VDD rises and reaches the VDD2 level, the CR oscillation circuit 20 is in a stopped state, that is, the oscillation output signal S25 remains at the “L” level, while the oscillation stop detection circuit 30 starts operating. When the voltage level of the connection point N32 exceeds the threshold voltage VtH2, the POR signal becomes “H” level and becomes a reset signal when the power is turned on. Thereafter, when the power supply voltage VDD exceeds the VDD1 level, the CR oscillation circuit 20 starts to operate, so that the oscillation stop detection circuit 30 sets the POR signal to the “L” level and releases the reset.

  FIG. 5 showing the operation of instantaneous interruption shows a case where the power supply voltage VDD at the time of instantaneous interruption becomes a level VDDx which is lower than the VDD1 level and slightly higher than the VDD2 level. The circuit 20 is in an oscillation stop state, and the oscillation stop detection circuit 30 performs an operation for detecting it. Therefore, the POR signal becomes “H” level and becomes a reset signal at the time of instantaneous power interruption. Thereafter, when the power supply voltage VDD exceeds the VDD1 level, the CR oscillation circuit 20 starts to operate, so that the oscillation stop detection circuit 30 sets the POR signal to the “L” level and releases the reset.

(Effect of Example 1)
According to the first embodiment, the power-on reset circuit that supplies the POR signal to the reset target circuit when the power is turned on includes the voltage level shift circuit 10, the CR oscillation circuit 20, and the oscillation stop detection circuit 30. The voltage VDD is lowered by the constant voltage Vx by the voltage level shift circuit 10 and supplied to the power supply of the CR oscillation circuit 20. In the normal operation region in the normal operation power supply voltage state, the period of the CR oscillation operation (that is, the period) ) Since T1 is set to be smaller than the detection time T2 of the oscillation stop detection circuit 30, even if the operating power supply voltage range of the reset target circuit is wide, a POR signal is stably generated under appropriate conditions when the power supply is interrupted. Can be made.

(Modification)
The present invention is not limited to the first embodiment, and various usage forms and modifications are possible. For example, the following forms (a) to (d) are used as the usage form and the modified examples.
(A) In the first embodiment, the POR signal is expressed as a signal having a relatively short pulse width, which is the output of the Schmitt trigger circuit 35 itself. However, depending on the application, a POR signal having a wide pulse width may be required. In this case, for example, a logic circuit such as a flip-flop circuit or a counter circuit can be connected to the output side of the Schmitt trigger circuit 35 to easily generate a POR signal having a wide pulse width.
(B) The voltage level shift circuit 10 may be composed of other transistors such as NMOS in addition to the PMOS 11.
(C) In the CR oscillation circuit 20, the PMOS 21 and the NMOS 24 may be configured by switch means such as other transistors. The CR oscillation circuit 20 may be replaced with an oscillation circuit having another configuration that oscillates at a constant period T1.
(D) In the oscillation stop detection circuit 30, the PMOS 31 and the NMOS 33 may be configured by switch means such as other transistors, or the entire circuit may be changed to a circuit configuration other than that illustrated.

It is a circuit diagram which shows the structural example of the power-on reset circuit in Example 1 of this invention. FIG. 2 is a diagram showing characteristics with respect to a power supply voltage VDD in a period T1 and a time T2 in the power-on reset circuit of FIG. 2 is a time chart showing the operation of the power-on reset circuit of FIG. 1. 4 is a time chart showing an operation in which the time axis of “section (1)” in FIG. 3 is enlarged. 4 is a time chart showing an operation in which the time axis of “section (2)” in FIG. 3 is enlarged.

Explanation of symbols

10 Voltage level shift circuit 20 CR oscillation circuit 21, 31 PMOS
22, 32 Resistor 23, 34 Capacitor 24, 33 NMOS
25, 35 Schmitt trigger circuit

Claims (4)

A voltage level shift circuit that is applied with a first power supply voltage, lowers the first power supply voltage by a constant voltage, and outputs a second power supply voltage;
An oscillation circuit that oscillates at a constant period T1 and outputs an oscillation output signal when the second power supply voltage is applied and the level of the second power supply voltage is within a predetermined range;
An oscillation stop detection circuit that outputs a reset signal to a reset target circuit when an oscillation stop state of the oscillation circuit is detected by a detection time T2 based on the oscillation output signal when the first power supply voltage is applied;
In a normal operation power supply voltage state when the level of the second power supply voltage is within the predetermined range, the cycle T1 is set to be smaller than the detection time T2, and the cycle T1 is set to the detection time T2. A power-on reset circuit, wherein the reset signal is output when larger. The oscillation circuit is a CR oscillation circuit having a first capacitor and a first resistor that perform first charging / discharging at a time interval corresponding to the period T1, based on the second power supply voltage.
The oscillation stop detection circuit is a circuit having a second resistor and a second capacitor for performing second charge / discharge at a time interval corresponding to the detection time T2 based on the oscillation output signal. The power-on reset circuit according to claim 1. The CR oscillation circuit is
The first capacitor and the first resistor for performing the first charge / discharge with a first time constant based on the second power supply voltage;
A first switching circuit that switches the first charging / discharging at a time interval corresponding to the period T1 based on the first charging / discharging result and outputs the oscillation output signal;
The oscillation stop detection circuit is
The second capacitor and the second resistor for performing the second charge / discharge with a second time constant based on the first power supply voltage;
3. A second switching circuit that outputs the reset signal by switching the second charge / discharge at a time interval corresponding to the detection time T <b> 2 based on the oscillation output signal. 4. Power-on reset circuit. The first switching circuit includes:
First switch means for switching between the first charge and discharge;
A first Schmitt trigger circuit that switches the first switch means to output the oscillation output signal based on the first charge / discharge result;
The second switching circuit includes:
Second switch means for switching the second charge / discharge based on the oscillation output signal;
The power-on reset circuit according to claim 3, further comprising: a second Schmitt trigger circuit that outputs the reset signal based on the second charge / discharge result.

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