JP2010073889A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents the generation of notch of an insulating layer in a via hole bottom formed in a semiconductor substrate, avoid a damage which may be caused in an interconnect layer under the via hole, and can reduce electric insulating deterioration and poor connection of the interconnect layer, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device includes a first insulating layer 203; a first interconnect layer 204 on the first insulating layer; a via hole 201a penetrating through the semiconductor 201 and being equipped at a bottom with a sectional etching part which is obtained by removing the first insulating layer to a perpendicular direction; a second insulating layer 206 which covers from an inner wall except the sectional etching part of the via hole at the bottom, to the second surface of the semiconductor substrate; an opening 203a which is formed on the first insulating layer so that the first interconnect layer is exposed to the bottom of the via hole; and the second interconnect layer 202 which is in contact with the first interconnect layer at the opening and extends from the second insulating layer of the via hole to the second insulating layer of the second surface of the semiconductor substrate, wherein the first insulating layer in contact with the opening has smaller thickness than the first insulating layer in contact with the semiconductor substrate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having a wiring through hole and a method for manufacturing the same.

  In order to increase the memory capacity of a memory device using a semiconductor integrated circuit, it has been proposed to stack memory chips in multiple stages. A through hole is formed in the memory chip, wiring is provided in the through hole, metal bumps are disposed on the back surface of the chip, and the integrated circuit portion of the upper memory chip and the integrated circuit portion of the lower memory chip are electrically connected. By doing so, stacking is realized. The metal bumps of the upper chip are electrically bonded to metal pads formed on the surface of the lower chip. As a conventional semiconductor device having a through-hole, there is a semiconductor device in which a through-hole is formed by etching from the back surface of a semiconductor substrate and the wirings on the front surface and the back surface of the semiconductor substrate are electrically connected.

  Hereinafter, a conventional semiconductor device (semiconductor chip) will be described with reference to FIG. In the figure, in a semiconductor device 100, a through wiring 102 is formed inside a semiconductor substrate 101 made of silicon. The through wiring 102 is provided in the through hole 101 a of the semiconductor substrate 101. The through wiring 102 electrically connects the wiring layer 104 formed on the front surface of the semiconductor substrate 101 and the external terminal 105 formed on the back surface. On the surface of the semiconductor substrate 101, a semiconductor device such as an image sensor is formed by an integrated circuit. A wiring layer 104 is provided on the first insulating layer 103 on the surface of the semiconductor substrate 101. Furthermore, an external terminal (solder ball) 105 connected to the through wiring 102, a second insulating layer 106, and a protective film 107 are provided on the back surface of the substrate 101. The external terminal 105 protrudes outside the back surface.

  In the semiconductor device 100, the diameters of the through hole 101a and the opening 103a of the first insulating layer 103 are substantially the same. The above-described shape is obtained by etching the semiconductor substrate 101 until the first insulating layer 103 is exposed using, for example, a predetermined mask pattern (not shown) on the back surface of the semiconductor substrate 101, thereby forming the through hole 101a. Form. Next, using the through hole 101a as a mask, the opening 103a is formed by etching the first insulating layer 103 using etching having a high selection ratio with the semiconductor substrate 101.

  In JP 2007-221080 (Patent Document 1), as shown in FIG. 1, the shape of the through hole 5 connected to the first wiring layer 4 has a convex shape toward the first surface. is doing. By having this shape, when the semiconductor substrate 2 is viewed from the second surface, a so-called notch shape in which the opening 3a of the first insulating layer 3 is hidden under the opening of the through hole 5 can be prevented. As a result, the second insulating layer 6 and the second wiring layer 7 are easily formed. In FIG. 1, 1 is a semiconductor device, 8 is a protective film, and 9 is an external terminal.

Furthermore, a technique for increasing the mounting density by stacking a plurality of semiconductor devices has been widely used. As a response to such a demand, attention is paid to a technique for forming a through electrode that penetrates the semiconductor substrate from the electrode pad formed on the surface of the semiconductor device and is connected to the back surface of the semiconductor device.
Examples of this technology include Japanese Patent Application Laid-Open No. 2003-309221 (Patent Document 2) and 2004 International Conference on Solid State Devices and Materials (2004 SSDM). Tokyo, 2004) pages 276-277 (Non-Patent Document 1) is known.

  For example, Patent Document 2 described above discloses a method for manufacturing a BGA (Ball Grid Array) type semiconductor device having a through electrode. In Patent Document 2, a through hole reaching from the back surface of the semiconductor substrate to the electrode formed on the surface of the semiconductor substrate is formed, an oxide film is formed on the inner wall of the through hole and the back surface of the electrode by CVD, and then the electrode is anisotropically etched. Only the oxide film adhering to the back surface is etched to form through electrodes that connect the front and back surfaces of the semiconductor substrate.

Furthermore, in recent years, there is an increasing demand for further reduction in size and thickness in small camera modules typified by mobile phones.
For example, in Non-Patent Document 1 described above, a manufacturing method of a through electrode is announced, and a CCD solid-state imaging device to which the through electrode is applied is assembled into a camera module, incorporated into a mobile phone, and the result of evaluating the function is reported. Yes.

  In order to increase the memory capacity of a memory device using a semiconductor integrated circuit, it has been proposed to stack memory chips in multiple stages. A through hole is formed in the memory chip, wiring is provided in the through hole, metal bumps are arranged on the back surface of the chip, and the integrated circuit portion of the upper memory chip and the integrated circuit portion of the lower memory chip are electrically connected. It is realized by doing. The metal bumps of the upper chip are electrically bonded to metal pads formed on the surface of the lower chip. As a conventional semiconductor device having a through hole, there is a semiconductor device in which a through hole is formed by etching from the back surface of a semiconductor substrate and the semiconductor surface and the back surface are electrically connected.

According to Non-Patent Document 1, an electrode pad on the first surface side on which an element of a semiconductor substrate is mounted, a first insulating film for electrically separating the electrode pad and the semiconductor substrate, and the semiconductor substrate Then, after forming a through hole from the back surface of the wafer to the electrode pad on the front surface of the wafer, the inner wall of the through hole and the bottom of the through hole are covered to electrically separate the conductive wiring made of the conductive member in the through hole and the semiconductor substrate. A second insulating film is formed. Thereafter, in order to form a contact for conducting the conductive wiring in the through hole and the electrode pad, anisotropic dry etching by reactive ion etching (RIE) is used to form the back surface of the wafer, the inner wall of the through hole, Then, the second insulating film covering the back surface of the electrode pad at the bottom of the through hole is removed by etching in the vertical direction as much as possible, leaving the second insulating film on the back surface of the wafer and the inner wall of the through hole, and the bottom of the through hole (= electrode pad) The second insulating film (corresponding to the back side) is removed and only the back side of the electrode pad is exposed to form a contact.
As described above, a semiconductor device having a through electrode and a through electrode forming process are attracting attention in order to realize not only a memory but also a wide range of devices such as a solid-state imaging device in a small size and a thin shape.

JP 2007-221080 JP 2003-309221 A 2004 SSDM; The 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004, pp. 276-277

In FIG. 2 to FIG. 10 shown as the manufacturing method of FIG. 1 in Patent Document 1, the surface of the first wiring layer 4 viewed from the second surface is the through hole 5 and the opening 3a of the first insulating layer. And when the second insulating layer 6 covering the first wiring layer 4 on the through-hole 5 side is removed, it is exposed to plasma twice (particularly, FIGS. 5 and 8). For this reason, the damage area caused by exposure to the plasma by the cleaning process after the plasma process that is generally performed is etched by the subsequent chemical cleaning to become voids, and the plating solution erodes at the connection part during the subsequent plating process. However, Patent Document 1 has a problem that electrical reliability is impaired.
As described above, when forming a through hole in a semiconductor substrate, by suppressing the generation of notches and voids in the insulating layer at the bottom of the through hole, the electrical insulation is deteriorated and the wiring layer of the through hole is poorly connected. It is desired to reduce the above.

In order to solve the above-mentioned problems, the inventors of the present invention include a step of performing the opening of the first insulating layer at the bottom of the through hole simultaneously with the removal of the second insulating layer existing at the bottom of the through hole. Thus, the inventors have found that the above-mentioned problems can be solved and have reached the present invention.
Thus, according to the present invention, the first step of forming the first insulating layer on the first surface of the semiconductor substrate;
A second step of forming a first wiring layer on the first insulating layer;
From the second surface side opposite to the first surface of the semiconductor substrate, the first insulating layer is penetrated through the semiconductor substrate so as to expose the first insulating layer, and the first insulating layer is formed at the bottom. A third step of forming a through hole with a partially etched portion removed in the direction;
A fourth step of forming a second insulating layer covering the inner wall of the through hole and the second surface of the semiconductor substrate;
An opening is formed in the first insulating layer by removing the first insulating layer and the second insulating layer covering the first wiring layer at the bottom of the through hole to expose the first wiring layer. The fifth step,
The first insulating layer is in contact with the first wiring layer at the opening, and from the second insulating layer of the through hole to the second insulating layer on the second surface of the semiconductor substrate. A sixth step of forming a second wiring layer;
A method for manufacturing a semiconductor device is provided.

According to the invention, the first insulating layer on the first surface of the semiconductor substrate;
A first wiring layer on the first insulating layer;
A through hole provided with a partially etched portion that penetrates the semiconductor substrate from the second surface side opposite to the first surface of the semiconductor substrate and has the first insulating layer removed in the thickness direction at the bottom. When,
A second insulating layer covering from the inner wall portion excluding the bottom of the partially etched portion of the through hole to the second surface of the semiconductor substrate;
An opening formed in the first insulating layer so that the first wiring layer in a region defined by the second insulating layer is exposed at the bottom of the through hole;
The second insulating layer is in contact with the first wiring layer at the opening of the first insulating layer and extends from the second insulating layer of the through hole to the second insulating layer of the second surface of the semiconductor substrate. And a wiring layer of
A semiconductor device is provided, wherein the first insulating layer in contact with the opening has a smaller thickness than the first insulating layer in contact with the semiconductor substrate.

  According to the semiconductor device and the manufacturing method thereof of the present invention, when the semiconductor substrate is viewed from the second surface, there is no so-called notch shape in which the opening of the first insulating layer is hidden under the opening of the through hole. The second insulating layer and the second wiring layer can be easily formed, the yield is improved, and the electrical and mechanical reliability is improved.

Hereinafter, the present invention will be described with reference to FIGS.
FIG. 11 is a schematic cross-sectional view of the semiconductor device in the embodiment of the present invention.
In FIG. 11, the semiconductor substrate 201 of the semiconductor device 200 is formed with a through hole 201a having a partially etched portion obtained by removing the first insulating layer in the thickness direction. The surface is covered with a first insulating layer 203 having an opening 203a, and a first wiring layer 204 is formed thereon. The side surface and the second surface of the through hole 201a are covered with a second insulating layer 206. In addition, a second wiring layer 202 is formed in contact with the first wiring layer 204 and extending through the through hole 201a and the second surface. Furthermore, the second wiring layer 202 is provided with an external terminal 205, and a protective layer 207 is covered on the second insulating layer 206 and the second wiring layer 202 except for the external terminal 205.
A method for manufacturing the semiconductor device of FIG. 11 will be described with reference to schematic process cross-sectional views of FIGS. In addition, in FIGS. 11-19, the same code | symbol shows the same or an equivalent part.

In the first step shown in FIG. 12, the first insulating layer 203 is formed on the first surface of the semiconductor substrate 201 by a CVD (Chemical Vapor Deposition) method, a spin coat method, a spray coat method, or the like.
The semiconductor substrate 201 is not particularly limited as long as it is used in a semiconductor device. For example, a bulk of an elemental semiconductor such as silicon or germanium, or a compound semiconductor such as silicon germanium, GaAs, InGaAs, ZnSe, or GaN. A substrate is mentioned. In addition, as a substrate having a semiconductor layer on the surface, various substrates such as an SOI (Silicon on Insulator) substrate, an SOS substrate or a multilayer SOI substrate, or a substrate having a semiconductor layer on a glass or plastic substrate may be used. The semiconductor substrate or semiconductor layer has some amount of current flowing through it, but may be single crystal (for example, by epitaxial growth), polycrystalline, or amorphous.

The first insulating layer 203 is formed of, for example, a silicon oxide film (SiO ₂ ), a silicon nitride film (SiNx), a SiOF (Fluorine-deped SiO ₂ ) film, a porous SiOC (Carbon-deped SiO ₂ ) film, or the like. . The thickness of the semiconductor substrate 201 is usually 10 to 200 μm, and the thickness of the first insulating layer 203 is usually 0.5 to 1 μm.
In the second step shown in FIG. 13, the first wiring layer 204 is formed on the first insulating layer 203 by sputtering, CVD, vapor deposition, plating, or the like. The first wiring layer 204 is made of, for example, a high resistance metal material (Ti, TiN, TiW, Ni, Cr, TaN, CoWP, etc.) or a low resistance metal material (Al, Al-Cu, Al-Si-Cu, Cu, Au). , Ag, etc.) are stacked in a single or multiple layers. The thickness of the first wiring layer 204 is usually 0.2 to 0.5 μm. Subsequently, after an insulating layer (not shown) is formed on the first wiring layer 204, a support (not shown) may be attached thereon.

In the third step shown in FIG. 14, a through-hole 201a is formed on the semiconductor substrate 201 from the second surface side of the semiconductor substrate 201 toward the first surface using a mask having a predetermined pattern (not shown). And the first insulating layer 203 is exposed by plasma etching. Usually, an etching gas (eg, the semiconductor substrate 201 is silicon and the first insulating layer 203 is silicon oxide) is etched in the plasma so that the semiconductor substrate 201 is etched relatively larger than the first insulating layer 203. In the case of a film, a mixed gas of SF ₆ , O ₂ and Ar) is introduced. In this etching, the first insulating layer 203 is also over-etched, and the through-hole 201a includes a partially etched portion in which the first insulating layer is removed in the thickness direction. The overetching is preferably performed less than 100% to more than 0% of the thickness of the first insulating layer 203. Moreover, it is preferable to leave 50% or less. The shape of the through hole 201a is not particularly limited. Further, the width of the through hole 201a is usually 5 to 50 μm.

  In the fourth step shown in FIG. 15, the second insulating layer 206 is formed by the CVD method or the spray coating method so as to cover the second surface of the semiconductor substrate 201 from the inner wall portion of the through hole 201a. The second insulating layer 206 is composed of, for example, a silicon oxide film, a silicon nitride film, a polyimide film, a BCB (benzocyclobutene) film, or the like. The thickness of the second insulating layer 206 is usually 0.2 to 2 μm at the bottom of the through hole 201a, usually 0.1 to 1 μm at the inner wall of the through hole 201a, and usually 0.3 to 3 μm on the second surface.

In the fifth step shown in FIG. 16, the first insulating layer 203 and the second insulating layer 206 covering the first wiring layer 204 at the bottom of the through-hole 201a are removed by plasma etching, and the first wiring layer 204 is removed. Expose. Usually, an etching gas (for example, the second insulating layer) is included in the plasma so that the first insulating layer 203 and the second insulating layer 206 are etched relatively larger than the first wiring layer 204. When 206 is a silicon oxide film and the first wiring layer 204 is composed of TiN and Al, a mixed gas of C ₅ F ₈ , O ₂ , and Ar) is introduced. By this step, an opening 203a in which the first wiring layer 204 is exposed at the bottom is formed in the first insulating layer 203 at the bottom of the through hole 201a. The first insulating layer 203 in contact with the opening 203a has a smaller thickness than the first insulating layer 203 in contact with the semiconductor substrate 201 by the depth of the etched portion (overetched portion). Here, the side walls of the through-hole 201a and the opening 203a are preferably configured from the same plane (that is, flush with each other).

In the sixth step shown in FIGS. 17 and 18, the semiconductor substrate 201 is contacted with the first wiring layer 204 through the opening 203a of the first insulating layer 203 and from above the second insulating layer 206 of the through hole 201a. The second wiring layer 202 is formed on the second insulating layer 206 on the second surface by using a mask having a predetermined pattern (not shown), sputtering, CVD, vapor deposition, plating It is formed by a method or a printing method. The second wiring layer 202 is made of, for example, a high resistance metal material (Ti, TiN, TiW, Ni, Cr, TaN, CoWP, etc.) or a low resistance metal material (Al, Al-Cu, Al-Si-Cu, Cu, Au). , Ag, solder material, etc.) and conductive resin are formed in a single or multiple layers. The thickness of the second wiring layer 202 on the second surface is usually 1 to 10 μm.
The semiconductor device of the present invention is obtained through the above steps.

Thereafter, as shown in FIG. 19, the protective layer 207 is formed on the second insulating layer 206 and the second wiring layer 202.
Furthermore, an opening is formed in a predetermined portion of the protective layer 207 on the second wiring layer 202, and the external terminal 205 connected to the second wiring layer 202 is provided in the opening, whereby the semiconductor device of FIG. 11 is obtained. . The external terminal 205 is formed of, for example, a solder material, and the protective layer 207 is formed of polyimide, an epoxy resin, or a solder resist material.

According to the semiconductor device 200 according to the above embodiment, the through hole 201a and the opening 203a have no so-called notch shape in which the opening of the first insulating layer is hidden under the opening of the through hole. Formation of the second insulating layer and the second wiring layer is facilitated, yield is improved, and electrical and mechanical reliability is improved.
The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented, and the numerical values and the compositions (materials) of the respective configurations. Is just an example. Therefore, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the technical idea of the present invention.

It is a schematic sectional drawing which shows the conventional semiconductor device. It is a general | schematic process sectional drawing of the manufacturing method of the conventional semiconductor device. It is a general | schematic process sectional drawing of the manufacturing method of the conventional semiconductor device. It is a general | schematic process sectional drawing of the manufacturing method of the conventional semiconductor device. It is a general | schematic process sectional drawing of the manufacturing method of the conventional semiconductor device. It is a general | schematic process sectional drawing of the manufacturing method of the conventional semiconductor device. It is a general | schematic process sectional drawing of the manufacturing method of the conventional semiconductor device. It is a general | schematic process sectional drawing of the manufacturing method of the conventional semiconductor device. It is a general | schematic process sectional drawing of the manufacturing method of the conventional semiconductor device.

It is a schematic sectional drawing which shows the conventional semiconductor device. It is a schematic sectional drawing of the semiconductor device of embodiment. It is a schematic process sectional drawing of the manufacturing method of the semiconductor device of embodiment. It is a schematic process sectional drawing of the manufacturing method of the semiconductor device of embodiment. It is a schematic process sectional drawing of the manufacturing method of the semiconductor device of embodiment. It is a schematic process sectional drawing of the manufacturing method of the semiconductor device of embodiment. It is a schematic process sectional drawing of the manufacturing method of the semiconductor device of embodiment. It is a schematic process sectional drawing of the manufacturing method of the semiconductor device of embodiment. It is a schematic process sectional drawing of the manufacturing method of the semiconductor device of embodiment. It is a schematic process sectional drawing of the manufacturing method of the semiconductor device of embodiment.

Explanation of symbols

1, 100, 200 semiconductor devices
2, 101, 201 semiconductor substrate
3, 103, 203 First insulation layer
3a, 103a, 203a opening
4, 204 1st wiring layer
5, 101a, 201a through hole
6, 106, 206 Second insulation layer
7, 202 Second wiring layer
8, 107, 207 protective layer
9, 105, 205 External terminal
102 through wiring
104 wiring layer

Claims (4)

A first step of forming a first insulating layer on a first surface of a semiconductor substrate;
A second step of forming a first wiring layer on the first insulating layer;
From the second surface side opposite to the first surface of the semiconductor substrate, the first insulating layer is penetrated through the semiconductor substrate so as to expose the first insulating layer, and the first insulating layer is formed at the bottom. A third step of forming a through hole with a partially etched portion removed in the direction;
A fourth step of forming a second insulating layer covering the inner wall of the through hole and the second surface of the semiconductor substrate;
An opening is formed in the first insulating layer by removing the first insulating layer and the second insulating layer covering the first wiring layer at the bottom of the through hole to expose the first wiring layer. The fifth step,
The first insulating layer is in contact with the first wiring layer at the opening, and from the second insulating layer of the through hole to the second insulating layer on the second surface of the semiconductor substrate. A sixth step of forming a second wiring layer;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein the etched portion has a depth of less than 100% to greater than 0% of the thickness of the first insulating layer.   The method of manufacturing a semiconductor device according to claim 1, wherein the through hole and the opening have side walls configured from the same plane. A first insulating layer on a first surface of a semiconductor substrate;
A first wiring layer on the first insulating layer;
A through hole provided with a partially etched portion that penetrates the semiconductor substrate from the second surface side opposite to the first surface of the semiconductor substrate and has the first insulating layer removed in the thickness direction at the bottom. When,
A second insulating layer covering from the inner wall portion excluding the bottom of the partially etched portion of the through hole to the second surface of the semiconductor substrate;
An opening formed in the first insulating layer so that the first wiring layer in a region defined by the second insulating layer is exposed at the bottom of the through hole;
The second insulating layer is in contact with the first wiring layer at the opening of the first insulating layer and extends from the second insulating layer of the through hole to the second insulating layer of the second surface of the semiconductor substrate. And a wiring layer of
The semiconductor device, wherein the first insulating layer in contact with the opening has a smaller thickness than the first insulating layer in contact with the semiconductor substrate.

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