JP2010067901A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an IGBT diode integrated device having low on-voltage of IGBT and high reverse recovery characteristics of a diode. <P>SOLUTION: A semiconductor device 10 includes: a semiconductor substrate 12 in which a vertical IGBT 20 and a vertical diode 40 are formed. A body region 24 of the IGBT 20 is formed up to a position deeper than an anode region 42 of the diode 40. Over both an area in which the IGBT 20 is formed, and an area in which the diode 40 is formed, a crystal defect in the semiconductor substrate 12 is formed shallower than a lower limit of the body region 24 of the IGBT 20, and is distributed in higher concentration than that of the circumference in the range deeper than a lower limit of the anode region 42 of the diode 40. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a vertical IGBT and a vertical diode are formed on one semiconductor substrate.

  Patent Document 1 discloses a semiconductor device having a semiconductor substrate on which a vertical IGBT and a vertical diode are formed (hereinafter sometimes referred to as an IGBT-diode integrated device). The IGBT is used as a switching element for power control. The diode is used as a freewheeling diode that circulates a reverse current when the IGBT is off. By forming the IGBT and the diode on one semiconductor substrate, the size of the device can be reduced.

Japanese Patent Laid-Open No. 2008-4866

A technique for intentionally forming a crystal defect in a cathode region of a diode by implanting charged particles into a semiconductor substrate is known. Crystal defects function as recombination centers between holes and electrons. Therefore, if a crystal defect is formed in the cathode region, holes in the cathode region are likely to recombine with electrons in the vicinity of the crystal defect when a reverse current flows through the diode. Therefore, the reverse current can be rapidly attenuated, and the reverse recovery characteristic of the diode can be improved. As a result, loss during reverse recovery (hereinafter referred to as reverse recovery loss) can be reduced.
Here, there is a trade-off (cancellation characteristic) between the reverse recovery loss of the diode and the loss during forward conduction (hereinafter referred to as steady loss). When one of these losses is reduced, the other loss increases. That is, when the above crystal defect is formed, the reverse recovery loss is reduced, but the steady loss increases. Here, it is known that when the crystal defects are locally formed at a certain depth, the steady loss does not increase so much, while the effect of reducing the reverse recovery loss is high, and the above trade-off is improved. Furthermore, it has been found that the above trade-off relationship also changes depending on the depth at which crystal defects are locally formed. That is, when a crystal defect is locally formed at a depth near the anode region in the cathode region, recombination of electrons and holes is efficiently promoted, and the effect of reducing reverse recovery loss is enhanced. On the other hand, the steady loss hardly changes depending on the crystal defect formation position. Therefore, when a crystal defect is locally formed at a depth near the anode region in the cathode region, the trade-off relationship is improved. In other words, if a crystal defect is formed at a position far from the anode region, the effect of reducing the reverse recovery loss is diminished and the steady loss does not change, so the trade-off relationship deteriorates.

It is conceivable to apply a technique for forming crystal defects to an IGBT-diode integrated device. FIG. 5 shows an IGBT-diode integrated device in which crystal defects 140 are formed by charged particle implantation. In FIG. 5, reference numeral 110 indicates a diode, reference numeral 112 indicates an anode area, reference numeral 114 indicates a cathode area, reference numeral 120 indicates an IGBT, reference numeral 122 indicates an emitter area, and reference is made. Reference numeral 124 denotes a body region, reference numeral 126 denotes a drift region, reference numeral 128 denotes a collector region, and reference numeral 130 denotes a gate electrode. As illustrated, a crystal defect 140 is formed in the cathode region 114 of the diode 110. Thereby, the reverse recovery characteristic of the diode 110 can be improved. However, when charged particles are implanted into the entire area of the semiconductor substrate, crystal defects 140 are formed in the drift region 126 of the IGBT 120 as shown in FIG.
Here, in the IGBT as well as the diode, there is a trade-off relationship between the switching loss and the on-voltage (the on-voltage affects the steady loss) when crystal defects are formed. That is, also in the IGBT, recombination is promoted due to the formation of crystal defects, switching loss is reduced, and steady loss (ON voltage) is increased. By forming the crystal defects locally, the effect of reducing the switching loss is increased, the steady loss is not increased so much, and the trade-off relationship is improved as in the diode. However, the difference from the diode is that the depth suitable for the formation of crystal defects is the depth near the collector region in the drift region.
Therefore, the IGBT-diode integrated device shown in FIG. That is, if the crystal defect 140 is formed at a depth suitable for the diode 110 (depth near the anode region 112 in the cathode region 114), a depth inappropriate for the IGBT 120 (depth farthest from the collector region 128 in the drift region 126). 3), crystal defects 140 are formed, and the characteristics of the IGBT 120 are deteriorated. In order to avoid this, if the crystal defect 140 is formed at a depth suitable for the IGBT 120 (depth near the collector region 128 in the drift region 126), a depth that is not appropriate for the diode 110 (an anode region in the cathode region 114). A crystal defect 140 is formed at a depth far from 112, and the characteristics of the diode 110 deteriorate. As described above, since there is no appropriate crystal defect formation depth in both the diode 110 and the IGBT 120, when one characteristic is improved, the other characteristic is deteriorated.

  In order to solve this problem, it is conceivable that the crystal defect 140 is formed only in the cathode region 114 without forming the crystal defect 140 in the drift region 126. When the crystal defect 140 is to be formed in this way, it is necessary to implant charged particles into the semiconductor substrate while masking the IGBT 120 side. In order to shut out charged particles on the IGBT 120 side, a mask having a thickness of about 100 μm is required. On the other hand, the mask needs to be formed so that the end thereof coincides with the boundary between the IGBT 120 and the diode 110. For this reason, the mask needs to be formed with an accuracy of several μm level. However, a mask having a thickness of about 100 μm cannot be formed with such high precision by a normal semiconductor manufacturing technique. Therefore, the IGBT-diode integrated device cannot be manufactured with stable quality.

  As described above, the IGBT-diode integrated device has a problem that it is difficult to improve the reverse recovery characteristic of the diode without increasing the on-voltage of the IGBT.

  The present invention was created in view of the above-described circumstances, and an object of the present invention is to provide an IGBT-diode integrated device in which the on-voltage of the IGBT is low and the reverse recovery characteristic of the diode is high.

The present invention provides a semiconductor device including a semiconductor substrate on which a vertical IGBT and a vertical diode are formed. The IGBT is formed to an n-type emitter region exposed on the first surface of the semiconductor substrate, and exposed on the first surface of the semiconductor substrate, adjacent to the emitter region, and deeper than the emitter region. An n-type drift region that is adjacent to the p-type body region at a deep position with respect to the body region and is separated from the emitter region by the body region, and is exposed to the second surface of the semiconductor substrate, A p-type collector region separated from the body region by the drift region, and a gate electrode facing the body region in a range separating the emitter region and the drift region via an insulating film are provided. The diode has a p-type anode region exposed on the first surface of the semiconductor substrate and an n-type cathode region exposed on the second surface of the semiconductor substrate and adjacent to the anode region. . The body region of the IGBT is formed to a position deeper than the anode region of the diode. The crystal defects in the semiconductor substrate are shallower than the lower end of the body region of the IGBT and deeper than the lower end of the anode region of the diode over the region where the IGBT is formed and the region where the diode is formed. Distributed in high concentration.
The expressions “shallow” and “deep” mean the depth from the first surface of the semiconductor substrate. That is, “shallow” means close to the first surface, and “deep” means far from the first surface.
In this semiconductor device, the body region of the IGBT is formed to a position deeper than the anode region of the diode. The crystal defects are distributed at a high concentration in a range shallower than the lower end of the body region of the IGBT and deeper than the lower end of the anode region of the diode. That is, crystal defects are formed in a high concentration in the body region on the IGBT side, and crystal defects are formed in a high concentration in the cathode region on the diode side. On the IGBT side, crystal defects are formed in the body region, so that excessive recombination of electrons and holes does not occur in the drift region when the IGBT is turned on. When the IGBT is on, electrons pass through a channel formed in the body region, and holes pass through a body region other than the channel. Therefore, crystal defects in the body region do not promote recombination and hardly affect the characteristics of the IGBT. That is, the on-voltage of the IGBT does not increase due to crystal defects. On the diode side, since the crystal defect is formed in the cathode region, the reverse recovery characteristic of the diode is improved. Thus, according to the present invention, there is provided an IGBT-diode integrated device in which the on-voltage of the IGBT is low and the reverse recovery characteristic of the diode is high.

In the semiconductor device described above, the range of the peak half-value width of the crystal defect concentration distribution in the depth direction is preferably included in a range that is shallower than the lower end of the body region of the IGBT and deeper than the anode region of the diode.
According to such a configuration, the concentration of crystal defects existing in the IGBT drift region can be reduced to a negligible level due to variations in the distribution of crystal defects.

In addition, the present invention provides a manufacturing method capable of suitably manufacturing the semiconductor device described above.
In this manufacturing method, a semiconductor device including a semiconductor substrate on which a vertical IGBT and a vertical diode are formed is provided. The IGBT is formed to an n-type emitter region exposed on the first surface of the semiconductor substrate, and exposed on the first surface of the semiconductor substrate, adjacent to the emitter region, and deeper than the emitter region. An n-type drift region that is adjacent to the p-type body region at a deep position with respect to the body region and is separated from the emitter region by the body region, and is exposed to the second surface of the semiconductor substrate, A p-type collector region separated from the body region by the drift region, and a gate electrode facing the body region in a range separating the emitter region and the drift region via an insulating film are provided. The diode has a p-type anode region exposed on the first surface of the semiconductor substrate and an n-type cathode region exposed on the second surface of the semiconductor substrate and adjacent to the anode region. . In this manufacturing method, the body region and the anode region are formed so that the lower end of the IGBT body region is deeper than the lower end of the anode region of the diode, and charged particles are implanted into the semiconductor substrate to remove crystal defects. In forming the semiconductor substrate, the implantation energy is adjusted so that the average stop position of the charged particles is shallower than the lower end of the body region of the IGBT and deeper than the anode region of the diode, and the semiconductor substrate is inclined at an angle with respect to the semiconductor substrate. A step of implanting charged particles into the substrate.
The expressions “shallow” and “deep” mean the depth from the first surface of the semiconductor substrate. In addition, the expressions “shallow” and “deep” when implanting charged particles only indicate positions within the semiconductor substrate, and do not mean that charged particles are implanted from the first surface side. Absent. The step of implanting charged particles into the semiconductor substrate may be a step of implanting charged particles from the first surface side or a step of implanting charged particles from the second surface side.
In this manufacturing method, when charged particles are implanted at a position shallower than the lower end of the body region of the IGBT and deeper than the anode region of the diode, the charged particles are implanted at an angle inclined with respect to the semiconductor substrate. When charged particles are implanted at an angle inclined with respect to the semiconductor substrate, the variation width of the charged particle stop position in the depth direction of the semiconductor substrate can be reduced. For example, the variation width (width in the depth direction of the semiconductor substrate) of the stop position when charged particles are implanted at an angle inclined by 45 degrees with respect to the semiconductor substrate is 1 / √ of the variation width when the charged particles are implanted vertically. 2. For this reason, it is possible to suppress the formation of crystal defects in the drift region, and to form crystal defects locally at a position shallower than the lower end of the body region of the IGBT and deeper than the anode region of the diode. That is, according to this manufacturing method, an IGBT-diode integrated device with a low on-voltage of the IGBT and a high reverse recovery characteristic of the diode can be preferably manufactured.

  According to the present invention, it is possible to provide an IGBT-diode integrated device in which the on-voltage of the IGBT is low and the reverse recovery characteristic of the diode is high.

  A semiconductor device according to an embodiment and a manufacturing method thereof will be described. FIG. 1 shows a longitudinal sectional view of an IGBT-diode integrated device (hereinafter referred to as a semiconductor device 10) of this embodiment. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor substrate 12 mainly made of silicon, an insulating film formed on the surface of the semiconductor substrate 12, a metal wiring, and the like.

  An IGBT region 20 and a diode region 40 are formed in the semiconductor substrate 12.

  A plurality of trenches 30 are formed in the upper surface (first surface) 12 a of the semiconductor substrate 12 in the IGBT region 20. An insulating film 32 is formed on the wall surface of the trench 30. A gate electrode 34 is formed in the trench 30. In the region of the IGBT region 20 facing the upper surface 12a of the semiconductor substrate 12, an n-type emitter region 22 and a p-type body region 24 are selectively formed. The emitter region 22 is formed in contact with the insulating film 32. The body region 24 is formed so as to cover the emitter region 22. The body region 24 is formed in contact with the insulating film 32 below the emitter region 22. The body region 24 is formed to a position shallower than the lower end of the trench 30. A body contact region 24 a having a higher p-type impurity concentration than the other part of the body region 24 is formed in a region of the body region 24 that faces the upper surface 12 a. An n-type drift layer 26 is formed below the body region 24. The drift layer 26 is separated from the emitter region 22 by the body region 24. In a region facing the lower surface (second surface) 12b of the semiconductor substrate 12 below the drift layer 26, a p-type collector layer 28 is formed over the entire surface. The collector layer 28 is separated from the body region 24 by the drift layer 26. A number of IGBTs are formed in the IGBT region 20 by the emitter region 22, the body region 24, the drift layer 26, the collector layer 28, and the gate electrode 34. Hereinafter, the IGBT formed in the IGBT region 20 is referred to as an IGBT 20.

  A plurality of trenches 50 are formed in the upper surface 12 a of the semiconductor substrate 12 in the diode region 40. An insulating film 52 is formed on the wall surface of the trench 50. A trench electrode 54 is formed in the trench 50. A p-type anode layer 42 is formed over the entire surface of the diode region 40 facing the upper surface 12 a of the semiconductor substrate 12. The anode layer 42 is formed to a position shallower than the body region 24 of the IGBT region 20. Specifically, the body region 24 is formed to a depth of 5 μm from the upper surface 12a, and the anode layer 42 is formed to a depth of 2 μm from the upper surface 12a. Of the region facing the upper surface 12 a of the anode layer 42, an anode contact region 42 a having a higher p-type impurity concentration than the other part of the anode layer 42 is formed in a region located in the middle of the two trenches 50. An n-type cathode layer 44 is formed below the anode layer 42. A cathode contact layer 48 having an n-type impurity concentration higher than that of the other part of the cathode layer 44 is formed in a region facing the lower surface 12 b of the cathode layer 44. Hereinafter, a region having a low n-type impurity concentration in the cathode layer 44 is referred to as a cathode drift layer 46. The n-type impurity concentration in the cathode drift layer 46 is substantially equal to the n-type impurity concentration in the drift layer 26 of the IGBT region 20. A large number of diodes are formed in the diode region 40 by the anode layer 42 and the cathode layer 44. Hereinafter, the diode formed in the diode region 40 is referred to as a diode 40.

On the lower surface 12b of the semiconductor substrate 12, a lower electrode 60 is formed over the entire surface. The lower electrode 60 is in ohmic contact with the collector layer 28 and the cathode contact layer 48.
An insulating film 62 is formed on the upper surface 12 a of the semiconductor substrate 12 above the trenches 30 and 50. Each gate electrode 34 is connected to an electrode formed on the upper surface 12a of the semiconductor substrate 12 at a position not shown. Each trench electrode 54 is connected to an electrode formed on the upper surface 12a of the semiconductor substrate 12 at a position not shown. The gate electrode 34 and the trench electrode 54 are not conductive.
An upper electrode 64 is formed on the upper surface 12 a of the semiconductor substrate 12. The upper electrode 64 is formed so as to cover the insulating film 62. The upper electrode 64 is insulated from the gate electrode 34 and the trench electrode 54. The upper electrode 64 is in ohmic contact with the emitter region 22, the body contact region 24a, and the anode contact region 42a.

  Reference numeral 70 in FIG. 1 indicates a depth range between the lower end of the body region 24 and the lower end of the anode layer 42 in the semiconductor substrate 12. Hereinafter, the range 70 is referred to as a gap region 70. In this embodiment, the gap region 70 has a thickness of about 3 μm. A large number of crystal defects are formed in the gap region 70. FIG. 2 shows the concentration distribution of crystal defects in the depth direction of the semiconductor substrate 12. Note that, in the planar direction of the semiconductor substrate 12 (direction parallel to the surface of the semiconductor substrate 12), the concentration of crystal defects is substantially equal at any depth (that is, in any plane direction of the semiconductor substrate 12). Even at the position, the crystal defect concentration distribution in the depth direction is the distribution shown in FIG. The origin of the horizontal axis in FIG. 2 indicates the position of the upper surface 12 a of the semiconductor substrate 12. As shown in FIG. 2, crystal defects exist at a high concentration in the gap region 70. Further, there are slight crystal defects outside the gap region 70. Most of the crystal defects present in the gap region 70 are crystal defects intentionally formed by implanting charged particles into the semiconductor substrate 12. The crystal defects existing outside the gap region 70 are crystal defects formed unintentionally at the time of crystal growth (ingot production) or the like, or unintentionally when the charged particles are implanted into the gap region 70. This is a crystal defect formed outside of 70. A range 72 in FIG. 2 is a range having a concentration higher than the half value A2 of the peak value A1 of the crystal defect concentration (hereinafter referred to as a half width range 72). As illustrated, the full width at half maximum 72 is included in the gap region 70.

  Next, the operation of the semiconductor device 10 will be described. During the operation of the semiconductor device 10, the trench electrode 54 is maintained at a constant potential. As a result, the operation of the diode 40 is stabilized.

  Consider a case where a high potential is applied to the upper electrode 64 and a low potential is applied to the lower electrode 60. In this case, the diode 40 has a high potential on the anode side (upper electrode 64) and a low potential on the cathode side (lower electrode 60). That is, the forward voltage is applied. For this reason, the diode 40 is turned on.

  On the other hand, the IGBT 20 has a high potential on the emitter side (upper electrode 64) and a low potential on the collector side (lower electrode 60). For this reason, the IGBT 20 is not turned on.

  When the diode 40 is caused to function as a freewheeling diode, the state is switched from a state in which a forward voltage is applied to the diode 40 to a state in which a reverse voltage is applied to the diode 40. That is, the state is switched to a state in which a high potential is applied to the lower electrode 60 and a low potential is applied to the upper electrode 64. Then, the diode 40 is turned off, and a reverse current (current from the lower electrode 60 toward the upper electrode 64) flows through the diode 40. That is, electrons and holes flow through the cathode drift layer 46 in a state where the forward voltage is applied and the diode 40 is turned on. In this state, when a reverse voltage is applied to the diode 40, electrons existing in the cathode drift layer 46 are discharged to the cathode side (lower electrode 60), and holes existing in the cathode drift layer 46 are discharged to the anode side. It is discharged to (upper electrode 64). For this reason, a reverse current flows through the diode 40. The reverse current decreases as electrons and holes remaining in the cathode drift layer 46 decrease, and thereafter becomes zero. In the semiconductor device 10 of the present embodiment, a large number of crystal defects are formed in the gap region 70 of the semiconductor substrate 12 (that is, in the cathode drift layer 46). Crystal defects function as recombination centers of electrons and holes. For this reason, when a reverse voltage is applied to the diode 40, many electrons and holes disappear in the cathode drift layer 46 due to recombination. Therefore, in the diode 40, the reverse current is rapidly attenuated. That is, the power loss caused by the reverse current is very small.

  In addition, when a high potential is applied to the lower electrode 60 and a low potential is applied to the upper electrode 64, the IGBT 20 has a high potential on the collector side (lower electrode 60) and a lower potential on the emitter side (upper electrode 64). When a positive potential is applied to the gate electrode 34 in this state, the body region 24 in contact with the insulating film 32 is inverted from p-type to n-type. As a result, a channel is formed in the body region 24 in a range in contact with the insulating film 32. When the channel is formed, the potential difference between the lower electrode 60 and the upper electrode 64 (that is, the collector-emitter voltage) causes electrons to be transferred from the upper electrode 64 to the channel in the emitter region 22 and the body region 24, the drift layer. 26, and flows through the collector layer 28 to the lower electrode 60. Further, holes flow from the body contact region 24 a to the upper electrode 64 through the collector layer 28, the drift layer 26, and the body region 24 (portion other than the channel) from the lower electrode 60. That is, the IGBT 20 is turned on. As described above, a large number of crystal defects exist in the body region 24 (in the gap region 70). However, in the body region 24, since the paths through which electrons and holes flow are different, crystal defects do not function as recombination centers. Therefore, crystal defects in the body region 24 hardly affect the characteristics of the IGBT 20. The drift layer 26 has almost no crystal defects. Accordingly, recombination of electrons and holes hardly occurs in the drift layer 26. For this reason, the drift layer 26 has a large amount of electrons and holes, and the electrical resistance of the drift layer 26 is greatly reduced by the conductivity modulation phenomenon. Therefore, the on-voltage of the IGBT 20 is low. That is, high power loss does not occur in the IGBT 20.

As described above, in the semiconductor device 10 of the present embodiment, the body region 24 of the IGBT 20 is formed to a position deeper than the anode layer 42 of the diode 40. Crystal defects are distributed at a high concentration in the gap region 70 which is shallower than the lower end of the body region 24 of the IGBT 20 and deeper than the lower end of the anode layer 42 of the diode 40. That is, many crystal defects are formed in the cathode drift layer 46 of the diode 40, and almost no crystal defects are formed in the drift layer 26 of the IGBT 20. Therefore, the semiconductor device 10 has a high reverse recovery characteristic of the diode 40 and a low on-voltage of the IGBT 20. That is, the semiconductor device 10 can operate with low power loss.
In particular, in the semiconductor device 10, the gap region 70 includes a half width range 72 having a concentration higher than the half value of the peak value of the crystal defect concentration. As described above, if a crystal defect exists in the drift layer 26 of the IGBT 20, the on-voltage of the IGBT 20 increases. However, if the full width at half maximum 72 having a crystal defect concentration higher than half the peak value is present in the gap region 70, the amount of crystal defects existing outside the gap region 70 can be reduced. Therefore, the on-voltage of the IGBT 20 is reduced to an extent that is almost the same as that of an IGBT in which no crystal defects are formed.

Next, a method for manufacturing the semiconductor device 10 will be described. The semiconductor device 10 is manufactured from a semiconductor wafer having the same n-type impurity concentration as the drift layer 26 and the cathode drift layer 46. The semiconductor substrate 12 described above is obtained by dividing a semiconductor wafer, and the upper surface and the lower surface of the semiconductor wafer described below correspond to the upper surface 12a and the lower surface 12b of the semiconductor substrate 12 described above.
First, an element structure is formed on the upper surface side of a semiconductor wafer. Since the method for forming the element structure on the upper surface side is a conventionally known technique, it will be briefly described. First, the emitter region 22, the body region 24 (including the body contact region 24a), and the anode layer 42 (including the anode contact region 42a) are formed by performing impurity implantation and heat treatment on the semiconductor wafer. To do. Note that the impurity implantation step for forming the body region 24 and the impurity implantation step for forming the anode layer 42 are performed in separate steps. In the impurity implantation process for forming the body region 24, impurities are implanted deeper than the impurity implantation process for forming the anode layer 42. Thus, after the subsequent heat treatment, the body region 24 is formed to a position deeper than the anode layer 42 as shown in FIG. In this embodiment, the body region 24 is formed to a depth of 5 μm from the upper surface of the semiconductor wafer, and the anode layer 42 is formed to a depth of 2 μm from the upper surface of the semiconductor wafer. Next, trenches 30 and 50 are formed by etching. Next, the insulating films 32 and 52 are formed by thermal oxidation treatment. Next, the gate electrode 34 and the trench electrode 54 are formed by depositing polysilicon into the trenches 30 and 50. Next, an insulating film 62 is formed on the gate electrode 34 and the trench electrode 54 by CVD or the like. Next, the upper electrode 64 is formed on the semiconductor wafer by vapor deposition or the like. Further, other necessary wirings and insulating films are also formed by a conventionally known method. Thus, by forming electrodes, insulating films, wirings, and the like on the semiconductor wafer, irregularities are formed on the surface of the semiconductor wafer (surfaces of the electrodes, insulating film, wirings, and the like).

  After the element structure on the upper surface side is formed, a resist is formed on the semiconductor wafer. The resist is formed thicker than the surface irregularities described above. After the resist is formed, the resist surface is planarized by polishing or etching the resist surface.

  Next, helium ions are implanted into the semiconductor wafer from the upper surface side. FIG. 3 shows a state when helium ions are implanted into the semiconductor wafer 90. As shown in FIG. 3, an aluminum foil 94 is disposed between the helium ion irradiation device 92 and the semiconductor wafer 90. The thickness of the aluminum foil 94 is adjusted so that the average stop position of helium ions implanted into the semiconductor wafer 90 is the center of the gap region 70 (the center in the depth direction). Moreover, the arrow 96 of FIG. 3 has shown the irradiation direction (movement direction) of helium ion. As shown in the drawing, the semiconductor wafer 90 is arranged to be inclined with respect to the direction of irradiation with helium ions. In this embodiment, the semiconductor wafer 90 is arranged so that the inclination angle θ of FIG. 3 is 75.5 degrees. In this state, helium ions are irradiated from the helium ion irradiation device 92 toward the semiconductor wafer 90. Helium ions ejected from the helium ion irradiation device 92 penetrate the aluminum foil 94. When helium ions pass through the aluminum foil 94, the energy (movement speed) of the helium ions is attenuated. Helium ions penetrating the aluminum foil 94 enter the semiconductor wafer 90. Then, as it travels through the semiconductor wafer 90, it loses energy and stops. As described above, since the thickness of the aluminum foil 94 is adjusted, helium ions stop near the center of the gap region 70. The helium ions cause crystal defects when stopping in the semiconductor wafer 90. Therefore, crystal defects are formed around the center of the gap region 70.

  As described above, a resist is formed on the upper surface of the semiconductor wafer 90, and the surface of the resist is flattened. Thereby, the variation in the stop position of helium ions is reduced. That is, when the upper surface of the semiconductor wafer 90 is uneven, the unevenness of the upper surface causes variations in the position where helium ions stop. In the concave portion, helium ions are likely to stop at a deep position, and in the convex portion, helium ions are likely to stop at a shallow position. In this embodiment, since a resist is formed on the upper surface of the semiconductor wafer and the surface of the resist is flattened, variations in the stop position of helium ions due to unevenness on the upper surface of the semiconductor wafer 90 are suppressed.

  However, even if measures are taken to reduce the variation in the helium ion stop position as described above, the helium ion stop position varies. Usually, the half-value width of the variation in the stop position of helium ions (the width of the range where the distribution concentration is higher than the half value of the peak value in the distribution of the stop position of helium ions) is about 10 μm. As described above, the width of the gap region 70 is about 3 μm. For this reason, when helium ions are implanted perpendicularly to the semiconductor wafer 90, many helium ions stop outside the gap region 70. That is, many crystal defects are formed outside the gap region 70. However, in the manufacturing method of this embodiment, helium ions are implanted at an inclined angle with respect to the semiconductor wafer 90. FIG. 4 is an explanatory diagram of the stop position of helium ions. The width H1 in FIG. 4 indicates the half width (about 10 μm) of the helium ion stop position. Further, the width H2 in FIG. 4 indicates the thickness (about 3 μm) of the gap region 70. As shown in FIG. 4, in the manufacturing method of the present embodiment, helium ions are implanted into the semiconductor wafer 90 at an angle inclined by an inclination angle θ (75.5 degrees). Therefore, if the half-value width at the stop position in the driving direction 96 is H1, the half-value width H3 at the stop position in the depth direction of the semiconductor wafer 90 is cos θ times the half-value width H1. In the present embodiment, since the half width H1 is 10 μm and the inclination angle θ is 75.5 degrees, the half width H3 in the depth direction is 2.5 μm. That is, H3 <H2. For this reason, the range of the half width H3 of the stop position can be accommodated in the gap region 70. That is, as shown in FIG. 2, the crystal defects can be formed so that the full width at half maximum 72 is included in the gap region 70.

When crystal defects are formed by implanting helium ions, the resist formed on the upper surface is removed by etching or the like.
Next, an element structure is formed on the lower surface side of the semiconductor wafer. That is, the collector layer 28 and the cathode contact layer 48 are formed by performing ion implantation and heat treatment on the semiconductor wafer. This heat treatment is performed by locally heating only the lower surface of the semiconductor wafer by laser annealing or the like. Next, the lower electrode 60 is formed by vapor deposition or the like.
Next, the semiconductor wafer is diced. Thus, the semiconductor wafer is divided into a plurality of semiconductor devices 10. Thereby, the semiconductor device 10 is manufactured.

  As described above, in the manufacturing method of this embodiment, helium ions are implanted at an angle inclined with respect to the semiconductor wafer. Therefore, it is possible to suppress variations in the stop position of helium ions in the depth direction of the semiconductor wafer. That is, crystal defects can be formed only in a narrow range in the depth direction of the semiconductor wafer. Therefore, even when the width of the gap region 70 is small, crystal defects can be locally formed in the gap region 70. In order to form the gap region 70 with a large width, it is necessary to form the body region 24 to a considerably deep position. Then, since the ion implantation process for forming the body region 24 takes a long time, the manufacturing efficiency of the semiconductor device 10 is extremely reduced. If the above-described method of implanting helium ions at an inclined angle is used, it is not necessary to form the body region 24 to a very deep position, so that there is no problem in manufacturing efficiency. The semiconductor device 10 can be manufactured with high manufacturing efficiency. In this embodiment, helium ions are implanted to form crystal defects, but nitrogen ions or carbon ions may be implanted. Nitrogen ions and carbon ions have a smaller half-width at the stop position than helium ions. Therefore, crystal defects can be formed in a narrow range. Also in this case, crystal defects can be formed in a narrower range by implanting these ions into the semiconductor wafer at an inclined angle.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

1 is a cross-sectional view of a semiconductor device 10. 3 is a graph showing a crystal defect concentration distribution in the depth direction of the semiconductor device 10. The figure which shows the arrangement | positioning at the time of implanting helium ion into the semiconductor wafer 90. FIG. Explanatory drawing of the stop position of helium ion. Sectional drawing of the conventional IGBT-diode integrated apparatus which formed the crystal defect.

Explanation of symbols

10: Semiconductor device 12: Semiconductor substrate 12a: Upper surface 12b: Lower surface 20: IGBT region 22: Emitter region 24: Body region 24a: Body contact region 26: Drift layer 28: Collector layer 30: Trench 32: Insulating film 34: Gate electrode 40: diode region 42: anode layer 42a: anode contact region 44: cathode layer 46: cathode drift layer 48: cathode contact layer 50: trench 52: insulating film 54: trench electrode 60: lower electrode 62: insulating film 64: upper electrode 70: Gap region 72: Full width at half maximum

Claims (3)

A semiconductor device comprising a semiconductor substrate on which a vertical IGBT and a vertical diode are formed,
IGBT is
An n-type emitter region exposed on the first surface of the semiconductor substrate;
A p-type body region exposed on the first surface of the semiconductor substrate, adjacent to the emitter region and formed deeper than the emitter region;
An n-type drift region adjacent to the body region at a deep position and separated from the emitter region by the body region;
A p-type collector region exposed at the second surface of the semiconductor substrate and separated from the body region by a drift region;
A gate electrode facing the body region in a range separating the emitter region and the drift region through an insulating film;
Have
Diode is
A p-type anode region exposed on the first surface of the semiconductor substrate;
An n-type cathode region exposed on the second surface of the semiconductor substrate and adjacent to the anode region;
Have
The body region of the IGBT is formed to a position deeper than the anode region of the diode,
The crystal defects in the semiconductor substrate are shallower than the lower end of the body region of the IGBT and deeper than the lower end of the anode region of the diode over the region where the IGBT is formed and the region where the diode is formed. A semiconductor device characterized by being distributed at a high concentration.   2. The semiconductor according to claim 1, wherein the range of the peak half-value width of the crystal defect concentration distribution in the depth direction is included in a range shallower than the lower end of the body region of the IGBT and deeper than the anode region of the diode. apparatus. An n-type emitter region exposed on the first surface of the semiconductor substrate;
A p-type body region exposed on the first surface of the semiconductor substrate, adjacent to the emitter region and formed deeper than the emitter region;
An n-type drift region adjacent to the body region at a deep position and separated from the emitter region by the body region;
A p-type collector region exposed at the second surface of the semiconductor substrate and separated from the body region by a drift region;
A gate electrode facing the body region in a range separating the emitter region and the drift region through an insulating film;
A vertical IGBT having:
A p-type anode region exposed on the first surface of the semiconductor substrate;
An n-type cathode region exposed on the second surface of the semiconductor substrate and adjacent to the anode region;
A method for manufacturing a semiconductor device comprising a semiconductor substrate on which a vertical diode having
Forming the body region and the anode region such that the lower end of the body region of the IGBT is deeper than the lower end of the anode region of the diode;
In forming a crystal defect by implanting charged particles into a semiconductor substrate, adjusting the implantation energy so that the average stop position of the charged particles is shallower than the lower end of the body region of the IGBT and deeper than the anode region of the diode, A step of implanting charged particles into the semiconductor substrate at an angle with respect to the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising:

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