JP2010062221A - Ferroelectric gate field effect transistor, memory element using the same, and method of manufacturing the ferroelectric gate field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the degradation in ferroelectric characteristics of a ferroelectric film and electrical characteristics of a transistor in a ferroelectric gate field effect transistor of an MFS-type memory including an IFI structure in a gate structure. <P>SOLUTION: The ferroelectric gate field effect transistor includes a gate structure having an Si substrate 1, and at least an HfSiON film 2, a ferroelectric film 3, and an HfSiON film 4 laminated on the Si substrate 1 in this order. The HfSiON film 2 and the HfSiON film 4 are amorphous at baking temperature for forming the ferroelectric film 3 by heat treatment. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a ferroelectric gate field effect transistor and a memory device using the same, and more specifically, a ferroelectric gate field effect transistor of an MFS type memory including an IFI (Insulator Ferroelectric Insulator) structure in the gate structure, The present invention relates to a memory device using the same and a method of manufacturing a ferroelectric gate field effect transistor.

  Non-volatile, high-speed operation, low power consumption and the like are required as conditions necessary for a memory in an integrated circuit of a ubiquitous society.

  Ferroelectric memories are listed as promising memory candidates that satisfy these conditions, and research and development are being actively conducted.

  One of the ferroelectric memories currently in practical use is a ferroelectric capacitor type memory.

  The ferroelectric capacitor type memory has one MOS (Metal Oxide Semiconductor) transistor and a memory cell (hereinafter referred to as “1T1C type”) composed of one ferroelectric capacitor. Patent Document 1 discloses an example of such a ferroelectric capacitor type memory.

  However, in a 1T1C ferroelectric capacitor type memory, a cell is selected by a word line at the time of writing, and a voltage is applied between the bit line and the plate line to polarize the ferroelectric capacitor upward or downward.

  Further, at the time of reading, “1” and “0” are determined depending on whether or not a current due to polarization inversion flows by applying a pulse voltage. At this time, polarization is directed in the voltage direction regardless of the original state (current does not flow if the direction is the same, but if it is opposite, current is reversed and current is generated), so destructive reading is performed. For this reason, the read information is rewritten.

  In other words, the 1T1C type memory has a destructive read feature that changes the written data when reading the data, so that it is necessary to reinsert the read data after reading the data. There is a point.

  Furthermore, in the 2T2C type memory composed of two MOS transistors and two ferroelectric capacitors, it is possible to prevent information destruction during reading, but the size of the memory cell becomes very large. End up.

  Further, a ferroelectric capacitor type memory has a problem that even if it is a 1T1C type which can be used practically, the memory cell size is large and it is difficult to increase the capacity.

  As described above, in the ferroelectric capacitor type memory, it is difficult to enable non-destructive reading while reducing the size of the memory cell and increasing the capacity.

In addition, some ferroelectric capacitor type memories that have been put to practical use use PZT (PbZr _X Ti _1-X O ₃ : where 0 <X <1) as a ferroelectric material.

PZT has a problem that the relative dielectric constant (450 to 1000: ratio of the dielectric constant of the substance to the dielectric constant of vacuum) is too high. The residual polarization amount is about 25 μC / cm ² .

  Moreover, since PZT uses harmful lead (Pb), it has a problem that it has a low melting point (800 to 900 degrees Celsius) and cannot comply with environmental regulations.

In addition, PZT has a problem that when platinum, gold, or the like that can withstand high temperature treatment is used for an electrode, film fatigue is severe and remnant polarization is remarkably reduced after 10 ⁷ times or less.

  As a conventional technique for overcoming such a problem, there is a ferroelectric gate field effect transistor type memory. The ferroelectric gate field effect transistor type has a memory cell (hereinafter referred to as “1T type”) composed of one transistor having a small memory cell size. The one transistor is a transistor having a structure in which a ferroelectric (Ferroelectric) is used in an insulator portion of a MIS (Metal Insulator Semiconductor) transistor. In the MIS, M is a metal, I is an insulator, and S is a semiconductor. Further, since the polarization direction of the ferroelectric material does not change at the time of reading, theoretically non-destructive reading is possible. However, the interface leakage current of the gate insulating film portion is large, and it is difficult to put it to practical use at the present time.

  A ferroelectric gate field effect transistor type memory (hereinafter referred to as “MFS type memory”, where F is an abbreviation for “ferroelectric”) can realize a 1T type memory. It is suitable for miniaturization compared to the type memory, and further non-destructive reading is possible, so there is no need for rewriting and the time required for reading is shortened. Has been.

  The MFS type memory has a smaller memory size than a ferroelectric capacitor type memory, and can be expected to have a large capacity.

  As conditions for such a material suitable for the ferroelectric used in the MFS type memory, a low remanent polarization value, a good hysteresis rectangle (shape state), a low relative dielectric constant, a fatigue resistance and an imprint High tolerance is required.

  In addition, imprint tolerance means that after applying a pulse voltage multiple times in the same direction, even if a pulse voltage in the reverse direction is applied, the polarization may not be completely reversed once, which is called an imprint phenomenon. The resistance to this imprint phenomenon.

As materials satisfying these conditions, there are SBT (SrBi ₂ Ta ₂ O ₉ ) and BLT ((Bi, La) ₄ Ti ₃ O ₁₂ )). The above-described PZT is not preferable as a candidate for a ferroelectric material because it has a high relative dielectric constant and contains harmful Pb (lead).

  Other types of gate structures of the MFS type memory include an MFS structure, an MFIS structure, an MFMIS structure, and an MIFIS structure. Patent Document 2 discloses an example of an MFS type memory having an MFMIS structure.

In this MFMIS structure, to the partial pressure V _F of the ferroelectric film (F) sufficiently large, there is a problem that it is necessary to apply a relatively large voltage to the gate (M).

In Patent Document 2, in order to overcome such problems, the ferroelectric is constituted by a thin film of mixed crystal Sr ₂ (Ta _1-x Nb _x ) ₂ O ₇ , the dielectric constant is lowered, and the melting point is reduced. It is high.

  On the other hand, active research has been conducted to select an insulator material having a high relative dielectric constant as the material of the insulator film (I) and to reduce the film thickness.

  However, if the thickness of the insulator film (I) is made too thin, a leak current (leakage current) flows between the insulator film (I) and the gate (M), and the electrical characteristics of the transistor deteriorate. Problems arise.

  On the other hand, in recent years, research on field effect transistors using organic semiconductors as channel materials instead of group IV semiconductors and compound semiconductors has been actively conducted.

  For example, Patent Literature 3 and Non-Patent Literature 1 disclose examples of field effect transistors using organic semiconductors.

  A characteristic of a field effect transistor using an organic semiconductor is that it can be formed on a plastic film because the formation temperature of the organic semiconductor film is low.

  A field effect transistor using an organic semiconductor is expected to be a technology capable of producing a field effect transistor that is mechanical, flexible, light, excellent in impact resistance, and easy to be thinned. In addition, when a field effect transistor using an organic semiconductor is used, there is an advantage that a large-area integrated circuit can be manufactured at a low cost by using a printing process.

As described above, field effect transistors using organic semiconductors can be bent and bent even when dropped, and to realize lightweight wall-mounted TVs and computers that can be rolled up and worn like clothes. Has become a necessary technology.
JP 2007-115733 (published May 10, 2007) JP 10-326872 (released on December 8, 1998) JP 2006-13468 (released January 12, 2006) S. Steudl et al. “Influence of the dielectric roughness on the performance of pentacene transistors” Appl. Phys. Lett. 85 (2004) 4400 (issued November 8, 2004) Author Yasuo Nara, "The Forefront of Metal Gate / High Dielectric Constant Insulator Film Stack", Applied Physics, Vol.76, No.9, p.1006-1012 (2007) (issued September 10, 2007)

  As described above, the ferroelectric capacitor type memory disclosed in Patent Document 1 has a characteristic of destructive reading, and therefore, it is necessary to perform an operation of inserting the read data again after reading the data. There is. There is also a problem that the size of the memory cell is large and it is difficult to increase the capacity.

  Further, PZT as a ferroelectric material has a problem that the relative dielectric constant is too high. Further, since PZT contains Pb (lead), there is also a problem that the melting point is low.

  Further, in the MFS type memory having the MFMIS structure disclosed in Patent Document 2, since an insulator film exists in the gate in addition to the ferroelectric film, the voltage value applied to the gate is applied to the ferroelectric film. However, there is a problem that the voltage value to be applied is lowered and it is difficult to reverse the polarization of the ferroelectric film.

  Furthermore, the organic field effect transistor disclosed in Non-Patent Document 1 has a problem that the electrical characteristics of the organic field effect transistor are deteriorated when the surface of the insulator film in contact with the organic semiconductor film is rough. For example, there is a problem that current values such as drain current and carrier mobility in a transistor are lowered.

  By the way, among such MFS type memories, in the MIFIS structure, a substrate (M, gate electrode), an insulator film (I), a ferroelectric film (F), an insulator film (I), and a semiconductor film (S Are stacked in this order, and the gate structure includes the IFI structure.

  However, in this conventional MIFIS structure memory, since the insulator film crystallizes and becomes uneven when fired at a high temperature in order to form a ferroelectric film, the surface of the ferroelectric film is also uneven. Therefore, there is a problem that the electric field applied to the semiconductor film in contact with the insulator film varies.

  In addition, for example, when the semiconductor film is formed of an organic semiconductor film, the alignment characteristics of the organic semiconductor molecules are deteriorated due to the unevenness of the surface of the ferroelectric film, and the ferroelectric film and the gate electrode or the ferroelectric film are deteriorated. In addition, there is a problem that the electrical characteristics of the transistor are deteriorated such that the leak current value between the organic semiconductor films is increased and the carrier mobility such as the drain current is decreased.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a ferroelectric film field effect transistor for an MFS type memory including an IFI structure in a gate structure. It is an object of the present invention to provide a ferroelectric gate field effect transistor capable of preventing deterioration of body characteristics and electrical characteristics of the transistor, a memory device using the same, and a method of manufacturing the ferroelectric gate field effect transistor.

  In order to solve the above problems, a ferroelectric gate field effect transistor according to the present invention includes a substrate and at least a first insulator film, a ferroelectric film, and a second insulator film stacked in this order on the substrate. The first insulator film and the second insulator film are non-crystalline insulator films that are amorphous at a firing temperature for forming the ferroelectric film by heat treatment. It is characterized by being composed.

  According to another aspect of the present invention, there is provided a method for manufacturing a ferroelectric gate field effect transistor comprising: a substrate; and at least a first insulator film, a ferroelectric film, and a second insulator film on the substrate. The first insulator film and the second insulator film are amorphous at a firing temperature for forming the ferroelectric film by heat treatment. A method of manufacturing a ferroelectric gate field effect transistor comprising a conductive insulator film, the first insulator film forming step of forming the first insulator film on the substrate, and the first insulator A ferroelectric film forming step of forming the ferroelectric film on the film by heat treatment at the firing temperature; and a second insulator for forming the second insulator film on the ferroelectric film. And a film forming step.

  According to the above-described configuration and method, the ferroelectric gate field effect transistor of the present invention includes a substrate and at least a first insulator film, a ferroelectric film, and a second insulator film stacked in this order on the substrate. ing.

  Here, when the first insulator film and the second insulator film are I (Insulator) and the ferroelectric film is F (Ferroelectric), the ferroelectric gate field effect transistor has a gate structure including an IFI structure. Will be.

  Examples of such a ferroelectric gate field effect transistor having a gate structure including an IFI type structure include those having a MIFIS type and SIFIS type gate structure.

  The portion of M (metal substrate) or S (Si substrate) to be spelled first is usually used as a gate electrode, and these are collectively referred to as M. Hereinafter, the MIFIS type and SIFIS type are collectively referred to as the MIFIS type gate structure. That's it.

  The last spelled S is a semiconductor, which may be a Si semiconductor film or an organic semiconductor film described below.

  According to the ferroelectric gate field effect transistor having such a MIFIS type gate structure, one memory cell can be constituted by one transistor, so that nondestructive reading can be performed while reducing the memory size. An MFS type memory can be provided.

  In addition, since the first insulator film and the second insulator film are formed on both surfaces of the ferroelectric film, the components of the ferroelectric film are in the substrate in contact with the first insulator film, or (second insulator When another material film is formed in contact with the film, diffusion to the material film) can be prevented, so that deterioration of the ferroelectric characteristics due to diffusion of the components of the ferroelectric film is prevented. be able to.

  The ferroelectric characteristics will be described. A ferroelectric film causes a positive or negative polarization inversion when an external electric field is applied, and the polarization inversion remains even after the external electric field is removed (hereinafter referred to as “residual polarization”). ”)).

  Therefore, by including the ferroelectric film in the gate structure, a positive or negative remanent polarization can be obtained by applying an external electric field.

  For this reason, this positive or negative remanent polarization is caused in the channel region (for example, a region between the source electrode and the drain electrode when the source electrode and the drain electrode are arranged in parallel on the second insulator film). An electric field will be applied. Since the current value such as the drain current is affected by the electric field due to the residual polarization applied to the channel region, the positive or negative residual polarization can be associated with the magnitude of the current value such as the drain current.

  Therefore, for example, data can be read nondestructively by associating positive remanent polarization with “1” and negative remanent polarization with “0”.

  Further, according to the configuration and the method, the first insulator film and the second insulator film are formed of an amorphous insulator film that is amorphous at a firing temperature for forming the ferroelectric film by heat treatment. The

  According to the above configuration, the ferroelectric film can be formed without crystallizing the first insulator film and the second insulator film at the firing temperature at which the ferroelectric film is formed by heat treatment.

  As a result, the first insulator film and the second insulator film are not crystallized when baked at a high temperature, so that the surfaces thereof are kept flat, and the surface of the ferroelectric film is also kept flat. Therefore, the first insulator film, the ferroelectric film 3 and the second insulator film are laminated in this order in the IFI structure, the variation in the electric field due to the plane orientation dependence of the dielectric constant and the presence of crystal grain boundaries, It is possible to prevent the formation of a local equivalent oxide film thickness difference in the substrate in contact with the first insulator film (and the semiconductor film when the semiconductor film in contact with the second insulator film is formed).

Note that the equivalent oxide thickness (EOT) is obtained by converting the physical thickness of a high-k (high relative dielectric constant) film such as an Hf-based insulator film into an electrical film thickness equivalent to the SiO ₂ film. It is a value.

  For example, when an organic semiconductor film is employed as the semiconductor film in contact with the second insulator film, the alignment characteristics of organic semiconductor molecules of the organic semiconductor can be improved.

  For this reason, the first insulator film due to the variation in the electric field applied to the organic semiconductor film due to the deterioration of the alignment characteristics of the ferroelectric film and the deterioration of the alignment characteristics of the organic semiconductor molecules due to the deterioration of the alignment characteristics of the ferroelectric film, and It is possible to prevent deterioration of the electrical characteristics of the transistor such as an increase in leakage current between the substrates (or between the second insulator film and the organic semiconductor film) and a decrease in carrier mobility.

  As described above, in the ferroelectric gate field effect transistor of the MFS type memory including the IFI structure in the gate structure, the ferroelectric capable of preventing the deterioration of the ferroelectric characteristics of the ferroelectric film and the electrical characteristics of the transistor. A method of manufacturing a gate field effect transistor and a ferroelectric gate field effect transistor can be provided.

  In the ferroelectric gate field effect transistor of the present invention, in addition to the above configuration, the amorphous insulator film is preferably an Hf-based insulator film containing Hf, Si, O, and N.

  The Hf-based insulator film has an advantage that the melting point is higher than that of PZT containing Pb (lead).

  Further, since the Hf-based insulator film is not crystallized by a heat treatment of 700 ° C. or more (about 750 ° C.) necessary for forming the ferroelectric film, the surface does not become uneven, and the first insulator film The flatness of the surface of the ferroelectric film formed thereon is improved.

  In addition, when a semiconductor film is formed in contact with the second insulator film, variation in electric field applied to the semiconductor film can be eliminated.

  Furthermore, if the semiconductor film is an organic semiconductor film, the alignment characteristics of the organic semiconductor molecules of the organic semiconductor film can be improved. In addition, it is possible to prevent the ferroelectric film and the substrate or the organic semiconductor film from being in direct contact with each other and the constituent elements of the ferroelectric film are diffused into the substrate or the organic semiconductor film, thereby deteriorating the interface characteristics. .

  By the way, in the memory of the MIFIS structure, the ratio of the voltage value applied to the ferroelectric film to the voltage value applied to the gate is reduced with respect to the voltage value applied to the gate, similarly to the MFS type memory disclosed in Patent Document 2 described above. There is a problem that the voltage increases.

  Here, based on FIG. 6A, FIG. 6B, and FIG. 7, such a problem will be described.

  FIG. 6A illustrates an example of a MIS transistor, and FIG. 6B illustrates an example of an MFS transistor.

  As shown in FIG. 6A, the MIS transistor mainly includes a gate electrode (metal), an insulator film 8A, a source electrode 9S (source region), and a drain electrode 9D (drain region). The vicinity of the portion where the exists is a channel region. However, the portion of the organic semiconductor film 10 is not necessarily the organic semiconductor film 10 but may be a Si semiconductor film.

  On the other hand, as shown in FIG. 6B, the MFS transistor has a structure in which the insulator film 8A of the MIS transistor is replaced with a ferroelectric film 8B. Also in this case, the portion of the organic semiconductor film 10 is not necessarily the organic semiconductor film 10 but may be a Si semiconductor film.

  The gate of the MFS structure shown in FIG. 6B is a structure composed of only the gate electrode 7 and the ferroelectric film 8B, whereas the gates of the MFIS structure, the MFMIS structure and the MIFIS structure are the gate electrode (M). In addition to the ferroelectric film (F), the insulator film (I) exists.

  For this reason, the operating voltage applied to the gate electrode is different from the voltage applied to the ferroelectric film.

  More specifically, in the MFS structure, the operating voltage applied to the gate electrode is equal to the voltage value applied to the ferroelectric film, but the operating voltage is applied to the gate electrode in the MFIS structure, MFMIS structure, and MIFIS structure. In this case, a voltage is applied to the insulator film in addition to the ferroelectric film.

  For example, in the gate having the MIFIS structure described above, the first insulator film, the ferroelectric film, and the second insulator film are electrically in series.

  When such an equivalent circuit of the gate portion of the MIFIS structure is obtained, an equivalent circuit diagram shown in FIG. 7 is obtained.

The gate portion of the MIFIS structure as shown in FIG. 7, respectively, the first insulator film _{(I I)} is capacitance _{C I} of the capacitor, the ferroelectric film (F) is the capacitance _{C F} capacitor and the second insulator film It can be considered that (I _II ) corresponds to a capacitor of capacitance C _II .

When the voltage value applied to the gate (M) is V (volts), the voltage value applied to the ferroelectric film is
V _F = V / (1 + C _F / C _I + C _F / C _II ).

Therefore, in order to the partial pressure V _F of the ferroelectric film of sufficient magnitude, it can be seen that the problem it is necessary to apply a relatively large voltage to the gate can occur.

In order to solve the above problems, in the ferroelectric gate field effect transistor of the present invention, in addition to the above configuration, the Hf-based insulator film is made of Hf _α Si _β O _2α N _{4β / 3} , It is preferable that α + β = 1 and 0.7 ≦ α ≦ 0.8 and 0.2 ≦ β ≦ 0.3 are satisfied.

As a result, the relative dielectric constant of the Hf-based insulator film is about 18 to 24, which is significantly improved from the conventional about 10 to 14, and the value of the film thickness of the Hf-based insulator film in terms of the SiO ₂ equivalent film thickness is set. Since the voltage can be reduced, the ratio of the voltage value (divided voltage) applied to the ferroelectric film to the operating voltage applied to the gate can be improved. Therefore, a ferroelectric gate field effect transistor that can operate at a low voltage can be provided.

In addition to the above configuration, the ferroelectric gate field effect transistor according to the present invention satisfies 0.8 ≦ X ≦ 2.0 when the SiO ₂ equivalent film thickness of the Hf-based insulator film is X nm. Preferably it is.

Thereby, for example, when the gate electrode, the source electrode and the drain electrode are provided in the ferroelectric gate field effect transistor of the present invention, the leakage current between the gate electrode and the source electrode or between the gate electrode and the drain electrode can be reduced. Do, it is possible to set the film thickness limit of the Hf-based insulating film, the partial pressure V _F to be a sufficient size, the ferroelectric gate field effect transistor of the ferroelectric film (F) It is possible to obtain the effect of improving the retention characteristics for the recorded information.

In the ferroelectric gate field effect transistor of the present invention, in addition to the above configuration, the ferroelectric film is preferably made of SrBi ₂ Ta ₂ O ₉ (SBT).

SBT has a coercive electric field of about 40 kV / cm, which is lower than that of PZT, about 60 kV / cm, can operate at low voltage, has high fatigue resistance regardless of the electrode material, and can withstand about 10 ¹³ inversions, imprinting There is an advantage that the phenomenon is difficult to occur.

On the other hand, SBT has a problem that it is necessary to crystallize at a high temperature of 700 degrees Celsius or higher in order to obtain ferroelectric characteristics. In the ferroelectric gate field effect transistor of the present invention, this problem is solved by employing an Hf-based insulator film. The residual polarization amount of SBT is about 10 μC / cm ² and is relatively small.

  As a result, the stable ferroelectric characteristics (polarization characteristics, relative dielectric constant) of the SBT film such that the remanent polarization value is small, the hysteresis rectangle (the state of the shape) is good, the relative dielectric constant is small, and the fatigue resistance and imprint resistance are high. Therefore, it is possible to provide a ferroelectric gate field effect transistor having excellent reproducibility of recorded information.

In addition to the above configuration, the ferroelectric gate field effect transistor according to the present invention may include an organic semiconductor film on a side different from the side where the ferroelectric film is present with respect to the second insulator film. The organic semiconductor film is preferably made of a _C60 molecular film.

Accordingly, since C ₆₀ (fullerene) has good electron mobility in the n-type organic semiconductor, a ferroelectric gate field effect transistor having high electron mobility and high switching speed in the n-type organic field effect transistor is provided. be able to.

  Further, in the ferroelectric gate field effect transistor of the present invention, in addition to the above configuration, the material of the substrate is preferably Si (Silicon).

  As a result, since Si is often inexpensive and has high purity, the production cost of the ferroelectric gate field effect transistor can be reduced.

  Moreover, in the ferroelectric gate field effect transistor of the present invention, in addition to the above configuration, the firing temperature is preferably 700 ° C. or higher and 1050 ° C. or lower.

  The lower limit for crystallizing the ferroelectric film is about 700 degrees Celsius, and the upper limit for maintaining the non-crystalline property of the Hf-based insulator film is 1050 degrees Celsius.

  Thereby, the ferroelectric film can be reliably formed by heat treatment without crystallizing the first insulator film and the second insulator film.

  In the ferroelectric gate field effect transistor of the present invention, in addition to the above structure, a self-assembled monolayer is formed between the second insulator film and the organic semiconductor film. preferable.

  According to the above configuration, the self-assembled monolayer (SAM) is formed between the second insulator film and the organic semiconductor film (and the source electrode and the drain are formed on the surface of the second insulator film). In this case, when the electrode is formed on the second insulator film, between the source electrode and the drain electrode, the second insulator film is made hydrophobic to improve the alignment characteristics of the organic semiconductor molecules (with the source or drain electrode). (The adhesiveness with the second insulator film can be improved).

  In addition, since the alignment characteristics of the organic semiconductor molecules can be improved in this way, the carrier mobility in the ferroelectric gate field effect transistor of the present invention is further improved, and the ferroelectric gate field effect of the present invention is improved. The transistor can be operated at a lower voltage.

  As an example of “self-assembly”, when gold (Au) is immersed in a solution containing ethanol or water as a solvent and a self-assembled monomolecule containing S (sulfur) as a solute, a predetermined time elapses. It is known that a self-assembled monomolecular film is spontaneously formed on the surface of gold.

  The memory element of the present invention preferably uses the ferroelectric gate field effect transistor.

  As described above, in the ferroelectric gate field effect transistor of the MFS type memory including the IFI structure in the gate structure, the ferroelectric capable of preventing the deterioration of the ferroelectric characteristics of the ferroelectric film and the electrical characteristics of the transistor. A gate field effect transistor, a memory device using the same, and a method for manufacturing a ferroelectric gate field effect transistor can be provided.

  As described above, the ferroelectric gate field effect transistor of the present invention includes a substrate and a gate in which at least a first insulator film, a ferroelectric film, and a second insulator film are stacked in this order on the substrate. The first insulator film and the second insulator film are formed of an amorphous insulator film that is amorphous at a firing temperature for forming the ferroelectric film by heat treatment. It is what.

  In addition, as described above, the manufacturing method of the ferroelectric gate field effect transistor according to the present invention includes the substrate and at least the first insulator film, the ferroelectric film, and the second insulator film on the substrate in this order. The first insulator film and the second insulator film are amorphous at a firing temperature for forming the ferroelectric film by a heat treatment. A method of manufacturing a ferroelectric gate field effect transistor comprising a film, the first insulator film forming step of forming the first insulator film on the substrate, and the top of the first insulator film In addition, a ferroelectric film forming step of forming the ferroelectric film by heat treatment at the firing temperature, and a second insulator film forming step of forming the second insulator film on the ferroelectric film. A method including:

  Thereby, in the ferroelectric gate field effect transistor of the MFS type memory including the IFI structure in the gate structure, the ferroelectric that can prevent the deterioration of the ferroelectric characteristics of the ferroelectric film and the electrical characteristics of the transistor The gate field effect transistor, the memory device using the same, and the manufacturing method of the ferroelectric gate field effect transistor are provided.

  One embodiment of the present invention will be described below with reference to FIGS. 1 to 5 and FIGS.

[1. Configuration of Ferroelectric Gate Field Effect Transistor]
First, based on FIG. 1, the structure of the ferroelectric gate field effect transistor 11A which is one Embodiment of this invention is demonstrated.

  FIG. 1 is a cross-sectional view showing the element structure of a ferroelectric gate field effect transistor 11A.

As shown in FIG. 1, a ferroelectric gate field effect transistor 11A includes a Si substrate (substrate, gate electrode) 1, an HfSiON film (first insulator film, amorphous insulator film, Hf insulator film) 2. , ferroelectric film 3, HfSiON film (second insulator film, the non-crystalline insulating film, Hf-based insulating film) 4, a source electrode 5S, drain electrodes 5D and _{C 60} film _{(C 60} molecule film, an organic semiconductor Film) 6.

  The ferroelectric gate field effect transistor 11A of this embodiment has a Si substrate 1 and a gate structure in which at least an HfSiON film 2, a ferroelectric film 3, and an HfSiON film 2 are stacked in this order on the Si substrate 1. This is the configuration.

  Here, when the HfSiON film 2 and the HfSiON film 4 are I (Insulator) and the ferroelectric film 3 is F (Ferroelectric), the ferroelectric gate field effect transistor 11A has a gate structure including an IFI type structure. It will be.

  Examples of the ferroelectric gate field effect transistor having a gate structure including such an IFI type structure include those having a MIFIS type and SIFIS type gate structure (for the MIFIS type, see FIG. 10). .

  The portion of M (metal substrate) or S (Si substrate) to be spelled first is usually used as a gate electrode, and these are collectively referred to as M. Hereinafter, the MIFIS type and SIFIS type are collectively referred to as the MIFIS type gate structure. That's it.

The last spelled S is a semiconductor, which may be a Si semiconductor film or a _C60 film 6 described below.

  According to the ferroelectric gate field effect transistor 11A having such a MIFIS type gate structure, one memory cell can be constituted by one transistor, so that non-destructive reading can be performed while reducing the memory size. MFS type memory can be provided.

Further, since the HfSiON film 2 and the HfSiON film 4 are formed on both surfaces of the ferroelectric film 3, the constituent elements of the ferroelectric film 3 are in the Si substrate 1 in contact with the HfSiON film 2 or C ₆₀ in contact with the HfSiON film 4. Since diffusion to the film 6 can be prevented, deterioration of the ferroelectric characteristics due to diffusion of the constituent elements of the ferroelectric film 3 can be prevented.

  The ferroelectric characteristics will be described. The ferroelectric film 3 undergoes positive or negative polarization inversion when an external electric field is applied, and the polarization inversion remains even after the external electric field is removed (hereinafter referred to as “residual”). It has a characteristic called “polarization”.

  Therefore, by including the ferroelectric film 3 in the gate structure, a positive or negative remanent polarization can be obtained by applying an external electric field.

Therefore, so that the electric field according to the positive or negative remanent polarization (an area of the C ₆₀ film 6 located between the source electrode 5S and the drain electrode 5D) the channel region is applied. Since the current value such as the drain current IDS is influenced by the electric field due to the remanent polarization applied to the channel region, the positive or negative remanent polarization can be associated with the magnitude of the current value such as the drain current IDS.

  Therefore, for example, data can be read nondestructively by associating positive remanent polarization with “1” and negative remanent polarization with “0”.

  In the ferroelectric gate field effect transistor 11A, in particular, the HfSiON film 2 and the HfSiON film 4 are composed of an amorphous insulator film that is amorphous at the firing temperature at which the ferroelectric film 3 is formed by heat treatment. Has been.

  Thereby, the ferroelectric film 3 can be formed without crystallizing the HfSiON film 2 and the HfSiON film 4 at the firing temperature at which the ferroelectric film 3 is formed by heat treatment.

Accordingly, since the HfSiON film 2 and the HfSiON film 4 are not crystallized when fired at a high temperature, the surfaces thereof are maintained flat, and the surface of the ferroelectric film 3 is also maintained flat. The Si substrate in contact with the HfSiON film 2, the variation in electric field due to the plane orientation dependence of the dielectric constant and the presence of crystal grain boundaries in the IFI structure in which the film 2, the ferroelectric film 3, and the HfSiON film 4 are laminated in this order It is possible to prevent the formation of a local equivalent oxide thickness difference in the C ₆₀ film 6 in contact with the 1 and HfSiON films 4.

Note that the equivalent oxide thickness (EOT) is obtained by converting the physical thickness of a high-k (high relative dielectric constant) film such as an Hf-based insulator film into an electrical film thickness equivalent to the SiO ₂ film. It is a value.

For example, when the a semiconductor film in contact with HfSiON film 4 as in the present embodiment employs the organic semiconductor film, such as C ₆₀ film 6, it is possible to improve the sequence characteristics of the organic semiconductor molecules of the organic semiconductor.

For this reason, the organic semiconductor such as the C ₆₀ film 6 resulting from the surface orientation dependence of the dielectric constant and the presence of crystal grain boundaries in the IFI structure in which the HfSiON film 2, the ferroelectric film 3, and the HfSiON film 4 are laminated in this order. Between the HfSiON film 2 and the Si substrate 1 (or HfSiON) due to the deterioration of the alignment characteristics of the organic semiconductor molecules due to the variation of the electric field applied to the film and the existence of the crystal grain boundaries of the ferroelectric film 3, the HfSiON film 2 and the HfSiON film 4. It is possible to prevent deterioration of the electrical characteristics of the ferroelectric gate field effect transistor 11A such as an increase in leakage current between the film 4 and the _C60 film 6 and a decrease in carrier mobility.

  The firing temperature of the HfSiON film 2 and the HfSiON film 4 is a temperature at which the ferroelectric film 3 can be crystallized, and is 700 ° C. or more and 1050 ° C. or less.

  The lower limit for crystallizing the ferroelectric film 3 is about 700 degrees Celsius, and the upper limit for maintaining the non-crystalline properties of the HfSiON film 2 and the HfSiON film 4 is 1050 degrees Celsius.

  Thereby, the ferroelectric film 3 can be reliably formed by heat treatment without crystallizing the HfSiON film 2 and the HfSiON film 4.

  As described above, in the ferroelectric gate field effect transistor 11A of the MFS type memory including the IFI structure in the gate structure, the ferroelectric characteristics of the ferroelectric film 3 and the electrical characteristics of the ferroelectric gate field effect transistor 11A are deteriorated. The ferroelectric gate field effect transistor 11A that can be prevented can be provided.

  Next, components of the ferroelectric gate field effect transistor 11A will be described in order.

  The Si substrate 1 is used as a gate electrode, and in the present embodiment, a Si wafer is used, and the thickness is usually about 100 to 400 μm.

  The Si substrate 1 can be formed of a single crystal silicon film or a polycrystalline silicon film. In this case, the film thickness of the single crystal silicon film or the polycrystalline silicon film may be about 100 nm.

  If the Si substrate 1 is adopted as the substrate as in this embodiment, since Si is often inexpensive and has high purity, the production cost of the ferroelectric gate field effect transistor can be reduced.

  The HfSiON film (first insulator film) 2 is an Hf-based insulator film (hereinafter referred to as “HfSiON”) containing Hf, Si, O, and N. In this embodiment, the relative dielectric constant is about 23. 6 and a film thickness of 6 nm.

  The HfSiON film (second insulator film) 4 has a relative dielectric constant of about 23.6, a film thickness of 4 nm, a film surface roughness of Ra value of 0.8 nm, and Rms value of 1.0 nm.

  Here, the Ra value and the Rms value are typical parameters indicating the roughness of the film surface. The Ra value (Ra; arithmetic average roughness) is a value obtained by summing and averaging the absolute values of the unevenness from a certain average line. The Rms value (Rms; root mean square roughness) is a standard deviation value obtained by square root of the mean square of the deviation.

  The appropriate film thicknesses of the HfSiON film 2 and the HfSiON film 4 will be described later.

  The Hf-based insulator film described above has an advantage that the melting point is higher than that of PZT containing Pb (lead).

  Further, since the Hf-based insulator film is not crystallized by a heat treatment of about 700 degrees or more (about 750 degrees) necessary for forming the ferroelectric film 3, the surface does not become uneven, and the HfSiON film 2 The flatness of the surface of the ferroelectric film 3 formed thereon is improved.

  In addition, when a semiconductor film is formed in contact with the HfSiON film 4, variations in the electric field applied to the semiconductor film can be eliminated.

Furthermore, if the semiconductor film is an organic semiconductor film like the _C60 film 6 of the present embodiment, the alignment characteristics of the organic semiconductor molecules of the organic semiconductor film can be improved. Further, the ferroelectric film 3 and the organic semiconductor film such as the Si substrate 1 or the C ₆₀ film 6 are in direct contact, and the constituent elements of the ferroelectric film 3 are diffused into the substrate 1 or the C ₆₀ film 6. It is also possible to prevent the interface characteristics from deteriorating.

The material of the ferroelectric film 3 is SrBi ₂ Ta ₂ O ₉ (SBT), the relative dielectric constant is about 250, the film thickness is 300 nm, the film surface roughness is Ra value of 1.0 nm, and the R _ms value is 1.4 nm. is there.

  In addition, as a film thickness of SBT, it is about 200-400 nm normally.

SBT has a coercive electric field of about 40 kV / cm, which is lower than that of PZT, about 60 kV / cm, can operate at low voltage, has high fatigue resistance regardless of the electrode material, and can withstand about 10 ¹³ inversions, imprinting There is an advantage that the phenomenon is difficult to occur.

On the other hand, SBT has a problem that it is necessary to crystallize at a high temperature of 700 degrees Celsius or higher in order to obtain ferroelectric characteristics. In the ferroelectric gate field effect transistor of the present invention, this problem is solved by employing an Hf-based insulator film. The residual polarization amount of SBT is about 10 μC / cm ² and is relatively small.

  As a result, the stable ferroelectric characteristics (polarization characteristics, polarization characteristics, SBT film having a small remanent polarization value, a good hysteresis rectangle (state of shape), a relatively low relative dielectric constant, and high fatigue resistance and imprint resistance. Therefore, it is possible to provide the ferroelectric gate field effect transistor 11A having excellent reproducibility of recorded information.

Another example of the ferroelectric film is BLT ((Bi, La) ₄ Ti ₃ O ₁₂ )). From the BLT film, the X-ray diffraction peaks of the c-plane and (117) plane can be observed strongly. The residual polarization amount of BLT is as small as about 4 μC / cm ^{2 in} the case of the c-axis, and the coercive electric field is about 40 kV / cm. Further, BLT has a characteristic that film fatigue is reduced when 10-20% of La (lanthanum) is added to Bi (bismuth).

  In this embodiment, the material of the source electrode 5S and the drain electrode 5D is gold (Au), and the film thickness is usually about 60 to 100 nm.

Further, like the C ₆₀ film 6 of the present embodiment, the organic semiconductor film formed on the side different from the side where the HfSiON film 2 exists with respect to the ferroelectric film 3 is preferably made of C ₆₀ (fullerene). .

In the present embodiment, the C ₆₀ film (organic semiconductor film) 6 uses fullerene, and C ₆₀ is a molecule having a diameter of about 1 nm. The film thickness is usually about 100 to 300 nm.

Thus, the C ₆₀ is the electron mobility is good in the n-type organic semiconductor, a high electron mobility in n-type organic field effect transistor, that the switching speed to provide a high ferroelectric gate field effect transistor 11A it can.

[2. Manufacturing Method of Ferroelectric Gate Field Effect Transistor]
Next, a method for manufacturing the element structure of the ferroelectric gate field effect transistor 11A of this embodiment will be described with reference to FIGS.

  In addition, [2. The configuration other than that described in [Manufacturing Method of Ferroelectric Gate Field Effect Transistor] is described in [1. Configuration of Ferroelectric Gate Field Effect Transistor]. For convenience of explanation, [1. Members having the same functions as those shown in the drawing of the configuration of the ferroelectric gate field effect transistor] are given the same reference numerals, and the description thereof is omitted.

  FIG. 2 is a cross-sectional view showing the process of forming the HfSiON film 2 of the ferroelectric gate field effect transistor 11A.

  FIG. 3 is a cross-sectional view showing a process of forming the ferroelectric film 3 of the ferroelectric gate field effect transistor 11A.

  FIG. 4 is a cross-sectional view showing a process of forming the HfSiON film 4 of the ferroelectric gate field effect transistor 11A.

  FIG. 5 is a cross-sectional view showing a step of forming the source electrode 5S / drain electrode 5D of the ferroelectric gate field effect transistor 11A.

  As shown in FIG. 2, in the HfSiON film 2 formation step, first, an HfSiON film 2 as a first insulator film was formed on the Si substrate 1 to have a thickness of about 6 nm.

As a forming method, an electron beam evaporation method was used. More specifically, after soaking in SPM (sulfuric acid / sulfuric acid / hydrogen peroxide mixture; H ₂ SO ₄ : H ₂ O ₂ = 4: 1), soaking in 1% HF (hydrogen fluoride) Finally, a series of cleaning steps for cleaning with running water (ultra pure water) was repeated twice, and then performed on the Si substrate 1 by electron beam evaporation.

When forming a film by an electron beam, for example, pellets mixed at a molar ratio of 92.3: 7.7 of HfO ₂ and Si ₃ N ₄ were used. The degree of vacuum in the vapor deposition chamber during film formation was 1.5 × 10 ⁻⁹ Torr.

In the present embodiment, the degree of vacuum at the time of forming the HfSiON film 2 is 1.5 × 10 ⁻⁹ Torr, but if it is 2.0 × 10 ⁻⁹ Torr or less, the Si is uniformly covered. A film can be deposited.

  The reason why the Si substrate 1 is used is that Si is inexpensive and often has a high purity, so that the cost can be reduced in manufacturing the transistor.

The reason why the Hf-based insulator film is used as the first insulator film is that the Hf-based insulator film is not crystallized by the heat treatment at 750 degrees necessary for forming the ferroelectric film 3. If it is not crystallized, the surface will not be uneven, the flatness of the surface of the ferroelectric film 3 produced on the HfSiON film 2 will be improved, the electric field applied to the C ₆₀ film 6 will be uneven, and the HfSiON film 4 will be in contact with it. This is because the arrangement characteristics of the C ₆₀ film 6 are improved.

  Further, in the HfSiON film 2 and the HfSiON film 4, when the ferroelectric film 3 and the Si substrate 1 are in direct contact, the constituent elements of the ferroelectric film 3 diffuse into the Si substrate 1 and the interface characteristics deteriorate. It is also provided to prevent this.

The molar ratio of HfO ₂ and Si ₃ N _{4 in the} HfSiON film 2 and the HfSiON film 4 needs to be set so that it has a high relative dielectric constant and is difficult to crystallize even at high temperatures.

In the conventional example (Patent Document 1: Japanese Patent Application Laid-Open No. 2007-115733), the molar ratio between HfO ₂ and Si ₃ N ₄ is preferably in the range of 6: 4 to 8: 2.

However, in the ferroelectric gate field effect transistor 11A of the present embodiment, the ratio of HfO ₂ is increased and 92.3: 7.7 is used in order to increase the relative dielectric constant.

Thereby, the memory characteristics could be confirmed in the ferroelectric gate field effect transistor 11A. When the molar ratio is 8: 2, Hf _0.6 Si _0.4 O _1.2 N _{0.5 is obtained} , and when 92.3: 7.7, Hf _0.8 Si _0.2 O _{1 is obtained. .6} N _0.27 .

Next, in the ferroelectric film 3 forming step shown in FIG. 3, the ferroelectric film 3 made of SBT (SrBi ₂ Ta ₂ O ₉ ) is formed on the HfSiON film 2.

  More specifically, the SBT is formed by first applying an SBT precursor solution (Sr / Bi / Ta = 0.8 / 2.2 / 2) by spin coating.

  Then, it is dried at 240 ° C. and heat-treated at 750 ° C. for 1 minute in an oxygen atmosphere. After repeating the coating, drying and heat treatment steps, heat treatment was performed at 750 ° C. for 30 minutes in an oxygen atmosphere to crystallize the ferroelectric film 3.

The formed ferroelectric film 3 had a film thickness of 300 nm, and the surface roughness of the film was Ra value of 1.0 nm and _Rms value of 1.4 nm. In the heat treatment in the above process, the HfSiON film 2 is not crystallized and is amorphous.

  Here, the reason for using SBT as a material for the ferroelectric film is that it has stable ferroelectric characteristics (polarization characteristics, relative permittivity), and thus a transistor using it has excellent reproducibility of recorded information. Because.

  Further, in order to satisfy the conditions of materials suitable for the ferroelectric gate field effect transistor 11A, that is, a remanent polarization value is small, a hysteresis rectangle is good, a relative dielectric constant is small, and fatigue resistance and imprint resistance are high. But there is.

  Further, in the conventional ferroelectric gate field effect transistor, since there is a heating process after forming the ferroelectric film, lattice defects are likely to occur. However, in this embodiment, a heating process that gives lattice defects is necessary. The original characteristics of the SBT film can be used.

  Next, in the HfSiON film 4 forming step shown in FIG. 4, the HfSiON film 4 as the second insulator film is formed on the polished ferroelectric film 3 to have a thickness of about 4 nm. The forming method is an electron beam evaporation method.

  More specifically, first, a washing process in which a flowing water (ultra pure water) treatment was performed after immersion in concentrated nitric acid (67%) was repeated twice in this order.

  Thereafter, an HfSiON film 4 was formed by electron beam evaporation. The conditions for film formation were the same as those for the HfSiON film 2 except for the film thickness.

As for the roughness of the surface after the HfSiON film 4 was formed, the Ra value was 0.8 nm and the R _ms value was 1.0 nm.

The reason why the HfSiON film 4 is used as the second insulator film is that it is not crystallized by the heat treatment at 750 degrees necessary for forming the ferroelectric film 3. If crystallization, not the surface of the HfSiON film 4 is uneven, to improve the flatness of the surface of the ferroelectric film 3 formed in contact with HfSiON film 4, field variations or according to C ₆₀ film 6, This is because the sequence characteristics of the _{C 60} film 6 in contact with the HfSiON film 4 is improved.

  Here, the reason why the relative dielectric constant of the HfSiON film 2 and the HfSiON film 4 is made higher than that of the conventional example will be described.

Similar to the MFS type memory having the MFMIS structure disclosed in Patent Document 2 described above, the MIFIS structure memory is a ferroelectric film with respect to the operating voltage V (= gate voltage VG) applied to the gate electrode (Si substrate 1). 3 has a problem in that the ratio of the voltage value (divided voltage V _F ) applied to 3 is reduced and the operating voltage V is increased.

  Here, based on FIG. 6A, FIG. 6B, and FIG. 7, such a problem will be described.

  FIG. 6A illustrates an example of a MIS transistor, and FIG. 6B illustrates an example of an MFS transistor.

  As shown in FIG. 6A, the MIS transistor mainly includes a gate electrode (metal), an insulator film 8A, a source electrode 9S (source region), and a drain electrode 9D (drain region). The vicinity of the portion where the exists is a channel region. However, the portion of the organic semiconductor film 10 is not necessarily the organic semiconductor film 10 but may be a Si semiconductor film.

  On the other hand, as shown in FIG. 6B, the MFS transistor has a structure in which the insulator film 8A of the MIS transistor is replaced with a ferroelectric film 8B. Also in this case, the portion of the organic semiconductor film 10 is not necessarily the organic semiconductor film 10 but may be a Si semiconductor film.

  The gate of the MFS structure shown in FIG. 6B is a structure composed of only the gate electrode 7 and the ferroelectric film 8B, whereas the gates of the MFIS structure, the MFMIS structure and the MIFIS structure are the gate electrode (M). In addition to the ferroelectric film (F), the insulator film (I) exists.

  For this reason, the operating voltage applied to the gate electrode is different from the voltage applied to the ferroelectric film.

More specifically, in the MFS structure, the operating voltage V applied to the gate electrode is equal to the voltage value (divided voltage V _F ) applied to the ferroelectric film, but in the MFIS structure, MFMIS structure, and MIFIS structure, When a voltage is applied to the gate electrode, a voltage is applied to the insulator film in addition to the ferroelectric film.

  For example, in the gate of the MIFIS structure like the ferroelectric gate field effect transistor 11A of the present embodiment, the HfSiON film 2, the ferroelectric film 3, and the HfSiON film 4 are in an electrical series relationship.

  When such an equivalent circuit of the gate portion of the MIFIS structure is obtained, an equivalent circuit diagram shown in FIG. 7 is obtained.

As shown in FIG. 7, the gate portion of the MIFIS structure is such that the HfSiON film 2 (I _I ) has a capacitance C _I , the ferroelectric film 3 (F) has a capacitance C _F , and the HfSiON film 4 (I _II). ) it can be considered to correspond to a capacitor of capacitance C _II.

Gate: When the operating voltage applied to the (M Si substrate 1) and V (volts), the voltage value V _F applied to the ferroelectric film 3, the following equation (1).

V _F = V / (1 + C _F / C _I + C _F / C _II ) (1)
Therefore, in order to the partial pressure V _F of the ferroelectric film 3 sufficiently large it is understood that a problem that it is necessary to apply a relatively large operating voltage to the Si substrate 1 may occur.

In order to solve the above problems, in the ferroelectric gate field effect transistor 11A of the present embodiment, the HfSiON film 2 and the HfSiON film 4 (Hf-based insulator film) are Hf _α Si _β O _2α N _{4β /} consists _{of three,} preferably satisfy the alpha + beta = 1 and 0.7 ≦ α ≦ 0.8 and 0.2 ≦ β ≦ 0.3.

As a result, the relative dielectric constant of the Hf-based insulator film becomes approximately 18 to 24, which is significantly improved from the conventional approximately 10 to 14, and the value of the thickness of the Hf-based insulator film in terms of SiO ₂ can be reduced. since, with respect to the operating voltage V to be applied to the Si substrate 1, it is possible to improve the ratio of the voltage value V _F applied to the ferroelectric film 3. Therefore, the ferroelectric gate field effect transistor 11A that can operate at a low voltage can be provided.

Next, in the present embodiment, the total film thickness of the HfSiON film 2 and the HfSiON film 4 is about 10 nm, and the reason is related to the SiO ₂ equivalent film thickness.

In Non-Patent Document 2 (Applied Physics, Vol. 76, No. 9, p. 1006-1012 (2007)), the SiO ₂ equivalent film thickness of the Hf-based insulator film (high relative dielectric constant) is 0.8 nm. It is described that it is feasible.

Further, SiO ₂ film is electrons by quantum mechanical tunneling when it becomes thickness 2.0nm is transmitted through the SiO ₂ film, the dielectric constant of the HfSiON film 2 and HfSiON film 4, the SiO ₂ 3. Since it is higher than 9, it is considered that a capacitor having a SiO ₂ equivalent film thickness of 2.0 nm can be realized with a thicker film.

From the above, the SiO ₂ equivalent film thickness Xnm of the HfSiON film 2 and the HfSiON film 4 is determined as 0.8 ≦ X ≦ 2.0, and the actual film thicknesses in the HfSiON film 2 and the HfSiON film 4 used in this embodiment are as follows: It became 4.7 nm or more and 12.0 nm or less.

As described above, when the SiO ₂ equivalent film thickness of the HfSiON film 2 and the HfSiON film 4 is X nm, it is preferable that 0.8 ≦ X ≦ 2.0 is satisfied.

Accordingly, for example, the limit film thickness of the HfSiON film 2 and the HfSiON film 4 that can reduce the leakage current between the Si substrate 1 and the source electrode 5S or between the Si substrate 1 and the drain electrode 5D can be set. , the partial pressure V _F of the ferroelectric film 3 can be sufficiently large, the effect is obtained that the holding characteristics are improved with respect to the recording information of the ferroelectric gate field effect transistor 11A.

  Finally, in the step of forming the source electrode 5S and the drain electrode 5D shown in FIG.

  The source electrode 5S and the drain electrode 5D are patterned by photolithography. After the lift-off process, the substrate was immersed in 0.1% HF (hydrogen fluoride) in order to remove the resist residue, and then subjected to running water (ultra pure water) treatment.

Then, using a resistive heating method as shown in FIG. _1, and the _{C 60} film 6 made of _{C 60} was deposited a thickness of about about 200 nm. The degree of vacuum was set to 2.0 × 10 ⁻⁵ Torr in the evaporation chamber when the C ₆₀ film 6 was formed.

In this _embodiment, although the degree of vacuum during deposition of the _{C 60} film 6 and 2.0 × ¹⁰ -5 Torr, not more than 2.0 × ¹⁰ -5 Torr, sufficient electrical characteristics A measurable film can be deposited.

Here, the reason why the _C60 film 6 is used for the organic semiconductor film is a material having a high electron mobility in the n-type organic semiconductor, and therefore has a high electron mobility in the n-type organic field effect transistor, and a switching speed. This is because it is expected to become higher.

However, the degree of vacuum of 10 -4 ^Torr or more atmosphere during deposition, trap states for electrons due to the oxidation of water and C ₆₀ are generated in the C ₆₀ film 6, the electric conductivity becomes drastically poor.

Further, a HfSiON film _4, between the _{C 60} film 6, it is preferable to self-assembled monolayer is formed.

  The film thickness of the self-assembled monomolecular film is usually about 2 to 3 nm.

Thus, a self-assembled monolayer (SAM: Self-assembled-monolayer ) of between HfSiON film 4 and the _{C 60} film 6 and, HfSiON film 4, when formed between the source electrode 5S and the drain electrode 5D, HfSiON film 4 Can be made hydrophobic, the alignment characteristics of the organic semiconductor molecules of the C ₆₀ film 6 can be improved, and the adhesion between the source electrode 5S or the drain electrode 5D and the HfSiON film 4 can be improved.

  In addition, since the alignment characteristics of the organic semiconductor molecules can be improved as described above, the carrier mobility in the ferroelectric gate field effect transistor 11A can be further improved, and the operation can be performed at a lower voltage.

  As an example of “self-assembly”, when gold (Au) is immersed in a solution containing ethanol or water as a solvent and a self-assembled monomolecule containing S (sulfur) as a solute, a predetermined time elapses. It is known that a self-assembled monomolecular film is spontaneously formed on the surface of gold.

  In addition, a transparent ferroelectric can be obtained by replacing the gold electrode used for the Si substrate 1, the source electrode 5S, or the drain electrode 5D with a transparent conductive oxide film such as ITO (Indium Tin Oxide) or ZnO (zinc oxide). The body gate field effect transistor 11A can be manufactured.

  Further, by adopting an organic ferroelectric such as P (VDF-TrFE) (polyvinylidene fluoride / ethylene trifluoride copolymer) for the ferroelectric film 3, the temperature required for film formation is 150. Degree. For this reason, a PET (polyethylene terephthalate) substrate can be used, and it is also possible to fabricate a ferroelectric gate field effect transistor which is mechanically flexible and light and has excellent impact resistance.

When an n-type organic semiconductor such as the _C60 film 6 is used as the organic semiconductor film, the mobility of the transistor is increased by using a metal having a lower work function other than gold for the source or drain electrode. be able to. Examples of the metal used include copper and aluminum.

[3. Electrical Characteristics of Ferroelectric Gate Field Effect Transistor)
In addition, [3. The configurations other than those described in [Electric characteristics of ferroelectric gate field effect transistor] are described in [1. Configuration of Ferroelectric Gate Field Effect Transistor] and [2. Manufacturing method of ferroelectric gate field effect transistor]. For convenience of explanation, [1. Configuration of Ferroelectric Gate Field Effect Transistor] and [2. Members having the same functions as those shown in the drawings of [Manufacturing Method of Ferroelectric Gate Field-Effect Transistor] are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, the same description is omitted.

Next, the electrical characteristics of the ferroelectric gate field effect transistor 11A of this embodiment will be described with reference to FIG. After formation of the C ₆₀ film 6 was subjected to IDS-VG measurement of the ferroelectric gate field effect transistor 11A with a measuring terminal that is installed in the deposition chamber.

  Specifically, the source electrode 5S, the drain electrode 5D, and the gate electrode were connected to a semiconductor parameter analyzer (Agilent Technologies 4156C) using silver paste.

_Then, after the _{C 60} film 6 forming, in a vacuum (2.0 × ¹⁰ -5 Torr or less), and grounding the source electrode 5S, and the voltage applied to the drain electrode 5D is fixed to 14 V, is applied to the gate The voltage was reciprocated from 0 to 8V.

  From FIG. 9, the counterclockwise hysteresis derived from the ferroelectric memory was confirmed, and the memory characteristics were confirmed.

  As the threshold voltage, two values of 5.2V as the low threshold voltage Vth1 and 5.8V as the high threshold voltage Vth2 were obtained.

The threshold voltage is obtained from the (IDS) ^1/2 -VG characteristic.

  From the above, it became clear that the threshold voltage of a general organic field effect transistor is smaller than 10 V or more and operates at a low voltage.

[4. Memory device using ferroelectric gate field effect transistor]
Next, based on FIG. 8A and FIG. 8B, the outline of the element structure of the memory element using the ferroelectric gate field effect transistor 11A of the present embodiment and the operation principle thereof will be described.

  FIG. 8A is an equivalent circuit diagram of the memory element. As shown in the equivalent circuit diagram of FIG. 8A, the memory element includes a ferroelectric gate field effect transistor 11A, a word line 12, and a bit line 13.

  The word line 12 is connected to the gate electrode of the ferroelectric gate field effect transistor 11A (connected to the Si substrate 1 via silver paste).

  The bit line 13 is connected to the drain electrode 5D.

  A GND (Ground) line 14 is connected to the source electrode 5S.

Next, the operation of the memory element will be described. Consider now the case where the organic semiconductor film, using the n-type organic semiconductor, such as C ₆₀ film 6.

  For example, when data “1” is written, a positive voltage is applied to the word line 12, and when data “0” is written, a negative voltage is applied to the word line 12.

  When data “0” is written, the threshold voltage values of the transistors (the low threshold voltage Vth1 and the high threshold voltage Vth2 in FIG. 8B) are higher than the data “1”.

  When reading data, a constant read voltage Vr (low threshold voltage Vth1 <read current Vr <high threshold voltage Vth2) is applied to the gate electrode, that is, the word line 12, and the magnitude of the drain current IDS is read by a sense amplifier. It may be determined whether it is “0” or “1”.

  FIG. 8B is a schematic diagram showing the drain current IDS-gate voltage VG characteristics of the ferroelectric gate field effect transistor 11A when data “0” and data “1” are written in the memory element of this embodiment. is there. FIG. 8B is drawn with emphasis on hysteresis indicating the ferroelectric characteristics of the ferroelectric.

[5. Other Embodiments of Ferroelectric Gate Field Effect Transistor]
Next, a configuration of a ferroelectric gate field effect transistor 11B, which is another embodiment of the ferroelectric gate field effect transistor, and experimental data showing its characteristics will be described with reference to FIGS. 10 (a) and 10 (b). To do.

As shown in FIG. 10B, the ferroelectric gate field effect transistor 11B includes the Si substrate 1, the HfSiON film 2, the ferroelectric film 3 (SBT), the HfSiON film 4, the OTP (OTP: n-octadecyl phosphonic acid). ) Film 4a, source electrode 5S (Au), drain electrode 5D (Au), and _C60 film 6.

  The ferroelectric gate field effect transistor 11B of this embodiment shown in FIG. 10B is different from the ferroelectric gate field effect transistor 11A of FIG. 1 in that “the film surface of the ferroelectric film 3 is flattened by polishing. Only ”and“ OTP film 4a is formed ”.

  A method for producing the ferroelectric gate field effect transistor 11B is as follows.

  First, an HfSiON film 2 having a film thickness of 6 nm was deposited on the Si substrate 1 by using an electron beam evaporation method.

  Thereafter, SBT was formed with a film thickness of 400 nm by a spin coating method, and an HfSiON film 2 was further deposited thereon with a film thickness of 4 nm.

  Thereafter, Au was formed to a thickness of 80 nm by photolithography, and immersed in an OTP (OTP; n-octadecyl phosphonic acid) solution for a long time in order to improve surface characteristics.

Moreover, C _60, in order to significantly deteriorate in air, in vacuum, was deposited.

  FIG. 10A is a characteristic diagram showing the drain current IDS-gate voltage VG characteristics of the ferroelectric gate field effect transistor 11B. However, the channel width W = 30 μm and the channel length = 10 μm.

  As shown in FIG. 10A, polarization-type hysteresis was observed on the positive bias side. Further, it is considered that the current increase on the negative bias side is due to the morphology of the surface of the HfSiON film 4.

  As described above, in the ferroelectric gate field effect transistor 11A and the ferroelectric gate field effect transistor 11B of the MFS type memory including the IFI structure in the gate structure, the ferroelectric characteristics of the ferroelectric film 3 and the electrical characteristics of the transistor are improved. Ferroelectric gate field effect transistor 11A and ferroelectric gate field effect transistor 11B capable of preventing deterioration, memory element and ferroelectric gate field effect transistor 11A and ferroelectric gate field effect transistor 11B using the same The manufacturing method of can be provided.

  The ferroelectric gate field effect transistor of the present invention has a gate structure in which a substrate, a first insulator film, a ferroelectric film, and a second insulator film are sequentially stacked on the substrate. The material used for the first and second insulator films may be HfSiON.

  In the ferroelectric gate field effect transistor of the present invention, the ferroelectric film may be SBT.

Further, the ferroelectric gate field effect transistor of the present invention, the organic semiconductor film may be a C _60.

  In the ferroelectric gate field effect transistor of the present invention, the substrate may be Si.

In the ferroelectric gate field effect transistor according to the present invention, the composition ratio of HfSiON is Hf _α Si _β O _2α N _{4β / 3} , and α + β = 1 and 0.7 ≦ α ≦ 0.8 and 0 .2 ≦ β ≦ 0.3 may be satisfied.

In the ferroelectric gate field effect transistor of the present invention, the SiO ₂ equivalent film thickness Xnm of the HfSiON may be 0.8 ≦ X ≦ 2.0.

  The memory element of the present invention may use the ferroelectric gate field effect transistor.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.

  The present invention can be widely applied to the field of semiconductor memories such as RAM (random access memory) and ROM (read only memory). For example, SRAM (static RAM), DRAM (dynamic RAM), etc., IC memory such as mask ROM / EPROM / EEPROM / flash ROM, LSI (large-scale integrated circuit), VLSI (very-large-scale integrated circuit) And large-scale integrated circuits such as ULSI (ultra-large-scale integrated), and electronic devices including these IC memories and large-scale integrated circuits.

It is sectional drawing which shows the element structure of one Embodiment of the ferroelectric gate field effect transistor in this invention. It is sectional drawing which shows the 1st insulator film formation process of the said ferroelectric gate field effect transistor. It is sectional drawing which shows the ferroelectric film formation process of the said ferroelectric gate field effect transistor. It is sectional drawing which shows the 2nd insulator film formation process of the said ferroelectric gate field effect transistor. It is sectional drawing which shows the source / drain formation process of the said ferroelectric gate field effect transistor. (A) is sectional drawing which shows an example of the element structure of a bottom contact type organic field effect transistor (MFS structure), (b) is sectional drawing which shows the other example of the element structure. FIG. 3 is an equivalent circuit diagram of a MIFIS structure related to the ferroelectric gate field effect transistor. (A) is an equivalent circuit diagram of an example of a memory element using the ferroelectric gate field effect transistor, and (b) is a schematic diagram showing drain current-gate voltage characteristics for explaining a read operation of the memory element. FIG. It is an IDS-VG characteristic view regarding the ferroelectric gate field effect transistor. (A) is an IDS-VG characteristic view regarding other embodiment of the ferroelectric gate field effect transistor in this invention, (b) is sectional drawing which shows the element structure of the said other embodiment.

Explanation of symbols

1 Si substrate (substrate, gate electrode)
1M metal substrate (substrate, gate electrode)
2 HfSiON film (first insulator film, non-crystalline insulator film, Hf insulator film)
3 Ferroelectric film 4 HfSiON film (second insulator film, amorphous insulator film, Hf-based insulator film)
4a OTP film (n-octadecyl phosphonic acid film)
5S source electrode 5D drain electrode 6 C ₆₀ film (C ₆₀ molecular film, organic semiconductor film)
7 gate electrode 8A insulating film 8B ferroelectric film 9S source electrode 9D drain electrode 10 organic semiconductor film 11A, 11B ferroelectric gate field effect transistor 12 wordline 13 bit line 14 GND (ground) line _{C I,} C _II, C _F capacitance IDS drain current V operating voltage V _F voltage value or partial pressure V _{I, V II} voltage value VG the gate voltage Vr read current Vth1 low threshold voltage Vth2 high threshold voltage W a channel width L the channel length

Claims (11)

A gate structure in which a substrate and at least a first insulator film, a ferroelectric film, and a second insulator film are stacked in this order on the substrate;
The first insulator film and the second insulator film are made of an amorphous insulator film that is amorphous at a firing temperature at which the ferroelectric film is formed by heat treatment. Dielectric gate field effect transistor.   2. The ferroelectric gate field effect transistor according to claim 1, wherein the amorphous insulator film is an Hf-based insulator film containing Hf, Si, O, and N. The Hf-based insulator film is made of Hf _α Si _β O _2α N _{4β / 3} and satisfies α + β = 1, 0.7 ≦ α ≦ 0.8, and 0.2 ≦ β ≦ 0.3. 3. The ferroelectric gate field effect transistor according to claim 2, wherein 4. The ferroelectric gate field effect according to claim 2, wherein 0.8 ≦ X ≦ 2.0 is satisfied when the SiO ₂ equivalent film thickness of the Hf-based insulator film is X nm. Transistor. 5. The ferroelectric gate field effect transistor according to claim 1, wherein the ferroelectric film is made of SrBi ₂ Ta ₂ O ₉ . An organic semiconductor film is formed on a side different from the side where the ferroelectric film exists with respect to the second insulator film,
6. The ferroelectric gate field effect transistor according to claim 1, wherein the organic semiconductor film is made of a _C60 molecular film.   The ferroelectric gate field effect transistor according to any one of claims 1 to 6, wherein the material of the substrate is Si.   The ferroelectric gate field effect transistor according to any one of claims 1 to 7, wherein the firing temperature is 700 degrees Celsius or more and 1050 degrees Celsius or less.   The ferroelectric gate field effect transistor according to claim 6, wherein a self-assembled monomolecular film is formed between the second insulator film and the organic semiconductor film.   A memory element using the ferroelectric gate field effect transistor according to claim 1. The substrate has a gate structure in which at least a first insulator film, a ferroelectric film, and a second insulator film are stacked in this order on the substrate, and the first insulator film and the second insulator are provided. The body film is a method of manufacturing a ferroelectric gate field effect transistor composed of an amorphous insulator film that is amorphous at a firing temperature for forming the ferroelectric film by heat treatment,
A first insulator film forming step of forming the first insulator film on the substrate;
A ferroelectric film forming step of forming the ferroelectric film on the first insulator film by heat treatment at the firing temperature;
A method of manufacturing a ferroelectric gate field effect transistor comprising: a second insulator film forming step of forming the second insulator film on the ferroelectric film.

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