JP2010050148A - Method of measuring misalignment, and misalignment inspection mark - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a method of measuring misalignment that correctly measures the amount of misalignment of superposition between layers in a pattern of small area. <P>SOLUTION: In the method of measuring the misalignment of superposition between layers as the amount of misalignment for a semiconductor device which is fabricated by laminating a pattern of a plurality of layers, the distance between a first annular pattern formed annularly of a layer Lu on the overlying layer side and a second annular pattern formed annularly of a layer Ld on the underlying layer side so that the second annular pattern is arranged concentrically to the first annular pattern is measured, and then the amount of misalignment is calculated using the measurements. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a misalignment measuring method for measuring overlay between layers of a semiconductor device and a misalignment inspection mark.

  Conventionally, in the photolithography process and the processing process, in order to measure the amount of misalignment between the lower layer and the upper layer, the measurement of misalignment in the XY directions is performed by an optical misalignment measuring method (optical misalignment measuring device). I was doing it. In this misalignment measuring apparatus, for example, the misalignment amount of Bar in Bar Mark or Box in Box Mark is measured, and process control and misalignment amount determination are performed based on the measurement result (for example, Patent Document 1). reference).

  However, in the measurement of such misalignment amount, the measurement accuracy of the misalignment amount of the actual pattern is limited due to the miniaturization of the design rule. For this reason, a variation error occurs in the measurement of the misalignment amount, and a determination error occurs in the determination of the misalignment amount in the actual pattern, which makes it difficult to control the misalignment correction amount.

  Especially in optical misalignment measurement, the size of optical alignment measurement pattern is affected by factors other than the lithography process (underlying film thickness, optical step, shape variation, etc.), so grasp the ability of misalignment of the main body pattern. It has become very difficult to control. Furthermore, by using optical alignment measurement patterns (alignment marks), it is necessary to secure a wide area on the wafer, and the number of alignment measurement patterns is limited, making it difficult to measure and correct higher-order components. ing.

JP 2001-15419 A

  It is an object of the present invention to obtain a misalignment measuring method and misalignment inspection mark that can accurately measure an overlay misalignment amount between layers with a pattern having a small area.

  According to one aspect of the present invention, in a misalignment measuring method for measuring a misalignment amount between layers as a misalignment amount for a semiconductor device manufactured by stacking a plurality of layer patterns, the first layer And measuring the distance between the first annular pattern formed in an annular shape and the second annular pattern formed in the second layer so as to be arranged concentrically with the first annular pattern, There is provided a misalignment measuring method including a misalignment calculating step of calculating the misalignment amount using a measurement result.

  Further, according to one aspect of the present invention, in the misalignment inspection mark formed in each layer of the semiconductor device manufacturing process and used for inspecting the overlay misalignment amount between the layers, in the first layer, A first annular pattern having an annular shape is formed, and a second annular pattern having an annular shape is formed on the second layer, concentrically with the first annular pattern. A misalignment inspection mark is provided.

  According to the present invention, there is an effect that it is possible to accurately measure the amount of overlay deviation between layers with a pattern having a small area.

  Embodiments of a misalignment measuring method and misalignment inspection marks according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a misalignment measuring apparatus according to the first embodiment of the present invention. The misalignment measuring apparatus 10 is an apparatus for measuring the misalignment amount between layers using a mark for measuring overlay accuracy between layers formed on a wafer (hereinafter referred to as misalignment mark).

  The misalignment mark is, for example, a ring-shaped pattern formed for each layer, and the misalignment amount between layers is determined between the misalignment marks of the measurement target layer (the misalignment mark of the first layer and the second layer). This is measured by measuring the amount of misalignment (relative position) between the misalignment marks).

  The misalignment amount measuring apparatus 10 includes an SEM image capturing mechanism 11 and a misalignment amount calculation mechanism 12, and the misalignment amount calculation mechanism 12 includes an outline extraction unit 13, a design data input unit 14, and a misalignment amount calculation unit 15. It has.

  The SEM image capturing mechanism 11 is, for example, an SEM type measuring machine, and detects misalignment marks of each layer using an electron beam. Note that the SEM image capturing mechanism 11 may detect misalignment marks of each layer using a cross-section measuring machine (AFM, SEM, FIB) or GDS. The SEM image capturing mechanism 11 captures an SEM image of the detected misalignment mark and sends it to the contour extraction unit 13 of the misalignment amount calculating mechanism 12.

  The contour extracting unit 13 extracts a contour pattern (contour data) from the SEM image and sends it to the misalignment amount calculating unit 15. The design data input unit 14 receives semiconductor circuit pattern design data (design design data) from an external device (for example, a design data creation device), and sends it to the misalignment amount calculation unit 15.

  The misalignment amount calculation unit 15 calculates the misalignment amount between the layers based on the contour data and the design data. Specifically, the misalignment amount calculation unit 15 calculates the misalignment amount in a plurality of locations and directions using the contour data and the design data, and calculates the misalignment amount between layers using the calculation result. .

  Here, the hardware configuration of the misalignment amount calculation mechanism 12 will be described. FIG. 2 is a diagram illustrating a hardware configuration of the misalignment amount calculation mechanism. The misalignment amount calculation mechanism 12 includes a CPU (Central Processing Unit) 1, a ROM (Read Only Memory) 2, a RAM (Random Access Memory) 3, a display unit 4, and an input unit 5. In the misalignment amount calculation mechanism 12, the CPU 1, ROM 2, RAM 3, display unit 4, and input unit 5 are connected via a bus line.

  The CPU 1 calculates a misalignment amount using a misalignment amount calculation program (a misalignment amount calculation program) 7 which is a computer program. The display unit 4 is a display device such as a liquid crystal monitor, and based on instructions from the CPU 1, misalignment amounts and various information used when calculating misalignment amounts (misalignment marks, design data, contour data). Is displayed. The input unit 5 is configured to include a mouse and a keyboard, and receives instruction information (an instruction for specifying a layer from which a misalignment amount is to be calculated, parameters necessary for calculating the misalignment amount, etc.) input from the user. input. The instruction information input to the input unit 5 is sent to the CPU 1.

  The deviation amount calculation program 7 is stored in the ROM 2 and loaded into the RAM 3 via the bus line. The CPU 1 executes a deviation amount calculation program 7 loaded in the RAM 3. Specifically, in the misalignment amount calculation mechanism 12, the CPU 1 reads the misalignment amount calculation program 7 from the ROM 2 in accordance with an instruction input from the input unit 5 by the user, expands it in the program storage area in the RAM 3, and performs various processes. Execute. The CPU 1 temporarily stores various data generated in the various processes in a data storage area formed in the RAM 3.

  The deviation amount calculation program 7 executed by the misalignment amount calculation mechanism 12 of the present embodiment has a module configuration including the above-described units (the contour extraction unit 13, the design data input unit 14, and the misalignment amount calculation unit 15). The above-described units are loaded on the main storage device, and the contour extraction unit 13, the design data input unit 14, and the misalignment amount calculation unit 15 are generated on the main storage device.

  The deviation amount calculation program 7 executed by the misalignment amount calculation mechanism 12 may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Further, the deviation amount calculation program 7 executed by the misalignment amount calculation mechanism 12 of the present embodiment may be provided or distributed via a network such as the Internet. Further, the deviation amount calculation program 7 of the present embodiment may be configured to be incorporated in advance in a storage medium such as a ROM and provided to the misalignment amount calculation mechanism 12.

  Next, the position of the misalignment mark will be described. FIG. 3 is a diagram for explaining the position of the misalignment mark. FIG. 3 shows an arrangement image of misalignment marks (alignment misalignment measurement patterns) in the wafer and in the shot. The misalignment mark (misalignment inspection mark) 25 is, for example, a line and space pattern, a narrow space pattern, a hole pattern, a large defect rate pattern, a two-dimensional pattern, a solid pattern, or the like.

  A plurality of rectangular shots 22 are arranged on the wafer 21, and one to a plurality of chips are arranged in each shot 22. FIG. 3 shows a case where one chip 23 is arranged in one shot. A dicing line 24 is provided between the shots 22. The dicing line 24 is an area that becomes a cutting path when each shot 22 (chip 23) is separated from the wafer 21 after the semiconductor circuit device (integrated circuit) is formed on the wafer 21.

  In the present embodiment, the misalignment mark 25 is configured to be small, and a plurality of misalignment marks 25 are arranged at arbitrary positions on the wafer 21. For example, a plurality of misalignment marks 25 are arranged in the chip 23 (in the shot 22) and in the dicing line 24, respectively. The misalignment amount measuring apparatus 10 determines the relative positional relationship between the misalignment mark on the upper layer side and the misalignment mark on the lower layer side in a plurality of directions (all directions) between the misalignment marks 25 (at least five directions). Comparison is made and the misalignment amount is measured using the comparison result.

  In FIG. 3, the region where the misalignment mark 25 is arranged is shown in a rectangular shape, and the shape of the misalignment mark 25 in the present embodiment is, for example, an annular shape, a circular shape, a polygonal shape, or a polygonal annular shape. is there.

  Next, the amount of misalignment of the misalignment mark 25 will be described. FIG. 4 is a diagram for explaining the misalignment amount of misalignment marks. 4A is an image diagram when there is no misalignment, and FIG. 4B shows an image when misalignment occurs in each layer.

  When the semiconductor device is formed on the wafer, the patterns of the layers are sequentially stacked. At this time, the misalignment mark 25 for each layer is formed together with the pattern of each layer. The misalignment mark 25 formed in each layer has a circular shape having a different radius. Here, each misalignment mark 25 is designed so that the upper layer misalignment mark 25 has a smaller radius than the lower layer misalignment mark 25. Therefore, the radius of the misalignment mark 25 decreases as the processing process on the wafer proceeds. Further, the misalignment marks 25 for each layer formed in one region are formed so that the center positions of the misalignment marks 25 are the same.

  4A and 4B show a case where the misalignment mark 25 is formed in the order of the layer L4, the layer L3, the layer L2, and the layer L1. 4A shows the misalignment mark 25 when no misalignment occurs in the misalignment mark 25 in each of the layers L1 to L4. As shown in (a), when there is no misalignment, the misalignment marks 25 of the layers L1 to L4 are arranged concentrically, and the center of each misalignment mark 25 is the center of the misalignment mark 25 formed by the layer L4. It becomes the same position as the center C.

  FIG. 4B shows the misalignment mark 25 when misalignment occurs in the misalignment mark 25 in each of the layers L1 to L4. As shown in (b), when there is misalignment, the center position of the misalignment mark 25 in each of the layers L1 to L3 is different from the center C of the misalignment mark 25 formed in the layer L4.

  FIG. 4C shows the center position of the misalignment mark 25 in each of the layers L1 to L4 in the case of FIG. As shown in (c), the center positions c3, c2, and c1 of the misalignment marks 25 of the layers L3, L2, and L1 are center C in the layer L4 by a distance corresponding to the misalignment amount with the layer L4. It will be located at a distance away from.

  The misalignment amount measuring apparatus 10 measures misalignment amounts between all the layers L1 to L4. For example, the amount of misalignment between the layer L1, the layer L2, the layer L3, and the layer L4 is measured.

  Next, an example of the configuration of the misalignment mark 25 when the misalignment mark 25 is a polygonal ring will be described. FIG. 5 is a diagram showing an example of a configuration when the misalignment mark is a polygonal ring. FIG. 5 shows misalignment marks 25 designed for each main layer (line system, hall system).

  As shown in the figure, in the M1 (metal) layer Lm1, the GC (gate) layer Lgc, and the AA (active) layer Laa, octagonal annular patterns are used as misalignment marks 25, respectively. In the CS (hole) layer Lcs, a pattern in which a plurality of rectangular patterns are arranged in an octagonal annular region is used as the misalignment mark 25.

  When the semiconductor circuit device is formed on the wafer 21, the pattern is formed in the order of the AA layer Laa, the GC layer Lgc, the CS layer Lcs, and the M1 layer Lm1. Therefore, the misalignment mark 25 formed on the wafer 21 is also formed in the order of the AA layer Laa, the GC layer Lgc, the CS layer Lcs, and the M1 layer Lm1.

  In addition, you may arrange | position the rectangular-shaped misalignment mark 25 as needed. For example, the rectangular M1 layer Lm1 and the rectangular GC layer Lgc are arranged so that the M1 layer Lm1 and the GC layer Lgc are orthogonal to each other, and the CS layer Lcs is arranged at the center of the M1 layer Lm1 and the GC layer Lgc. You may keep it.

  Next, a method for measuring the misalignment amount will be described. Here, a case where the misalignment mark 25 formed in each layer is an annular shape will be described. First, a first measuring method of misalignment will be described. FIG. 6 is a diagram for explaining a first method of measuring the misalignment amount. In FIG. 6, the image of the misalignment mark 25 is acquired, the contour data is extracted from the acquired image of the misalignment mark 25, and the misalignment amount (residual) is measured from the positional relationship between the lower layer and the upper layer. The procedure is shown. Here, one of the layers Lu and Ld corresponds to the first layer described in the claims, and the other corresponds to the second layer described in the claims. Accordingly, one of the misalignment marks 25 of the layers Lu and Ld corresponds to the first annular pattern described in the claims, and the other corresponds to the second annular pattern described in the claims.

  The SEM image capturing mechanism 11 of the misalignment measuring apparatus 10 captures the misalignment of the misalignment mark 25 by capturing the SEM image of the layer to be measured (the upper layer Lu and the lower layer Ld). An actual pattern is acquired (s1). The SEM images of these layers Lu and Ld are sent to the contour extraction unit 13.

  The contour extraction unit 13 extracts contour data of a misalignment actual pattern from the SEM images of the layers Lu and Ld, and sends the contour data to the misalignment amount calculation unit 15. The misalignment amount calculation unit 15 measures the distance (residual) between the contour data of the layer Lu and the contour data of the layer Ld. For example, when the radius of the layer Lu is smaller than the radius of the layer Ld, the distance between the outer contour of the layer Lu and the outer contour of the inner layer Ld is the residual between the layers Lu and Ld. As measured. Specifically, the misalignment amount calculation unit 15 has a plurality of residuals between the layer Lu and the layer Ld in a plurality of directions (a direction from the layer Lu to the layer Ld or a direction from the layer Ld to the layer Lu). Measure (s2). Then, the misalignment amount calculation unit 15 calculates the misalignment amount of the overlay of the upper layer Lu with respect to the lower layer Ld based on the residuals measured in each direction. At this time, the misalignment amount calculation unit 15 calculates the misalignment amount of the low-order component and the high-order component between the layer Ld and the layer Lu.

  Next, a second measuring method of misalignment will be described. FIG. 7 is a diagram for explaining a second misalignment measuring method. FIG. 7 shows a procedure for matching the design data corresponding to the misalignment mark 25 of each layer and measuring the misalignment amount from the difference in design data between the lower layer and the upper layer.

  The SEM image capturing mechanism 11 of the misalignment measuring apparatus 10 captures the misalignment actual pattern of the misalignment mark 25 by capturing the SEM images of the upper layer Lu and the lower layer Ld that are the measurement targets. Obtain (s11). The SEM images of these layers Lu and Ld are sent to the contour extraction unit 13. The contour extraction unit 13 here sends the SEM image to the misalignment amount calculation unit 15 without extracting the contour data from the SEM image.

  The design data input unit 14 receives semiconductor circuit pattern design data (hereinafter referred to as GDS) from an external device, and sends the design data to the misalignment amount calculation unit 15. In FIG. 7, GDS is illustrated by a dotted line. The misalignment amount calculation unit 15 performs design matching between the SEM image of the misalignment actual pattern and the GDS (s12). Specifically, the GDS pattern position of the layer Lu is moved to a position corresponding to the SEM image of the layer Lu. Further, the GDS pattern position of the layer Ld is moved to a position corresponding to the SEM image of the layer Ld. In other words, the shape of the SEM image of the layer Lu is corrected with the GDS pattern shape of the layer Lu, and the shape of the SEM image of the layer Ld is corrected with the GDS pattern shape of the layer Ld. As a result, the pattern position on the GDS is moved to a position corresponding to the misalignment mark 25 on the SEM image.

  The misalignment amount calculation unit 15 measures the misalignment amount of the layer Lu with respect to the layer Ld based on the GDS of the layers Lu and Ld moved to the position corresponding to the misalignment mark 25 on the SEM image (s13). . For example, when the radius of the layer Lu is smaller than the radius of the layer Ld, the distance between the outer contour of the layer Lu and the outer contour of the inner layer Ld is the residual between the layers Lu and Ld. As measured. Here, the misalignment amount calculation unit 15 measures residuals between the layers Lu and Ld in a plurality of places and in a plurality of directions as a pattern positional relationship between the layer Lu and the layer Ld. The misalignment amount calculation unit 15 calculates the misalignment amount of the overlay of the upper layer Lu with respect to the lower layer Ld based on the residuals measured in each direction.

  Here, the case where the misalignment amount calculation unit 15 measures the residuals between the layer Lu and the layer Ld at a plurality of locations in a plurality of directions has been described. The amount of deviation of the center position may be measured. In this case, the misalignment amount calculation unit 15 calculates the aberration amount of the actual pattern (aberration amount by the exposure apparatus) based on the GDS, and calculates pattern data obtained by removing the aberration amount from the actual pattern data. Then, the misalignment amount calculation unit 15 predicts the center position of the actual pattern based on the pattern data from which the aberration amount is removed. Further, the misalignment amount calculation unit 15 uses the predicted center position of the actual pattern to perform matching between the pattern data from which the aberration amount is removed and the GDS. Specifically, the GDS center position of the layers Lu and Ld is moved to a position corresponding to the predicted center position of the actual pattern. The misalignment amount calculation unit 15 measures the misalignment amount between the layer Lu and the layer Ld on the GDS.

  Further, here, the case where the shift amount between the center positions of the layer Lu and the layer Ld is used when performing the second misalignment measuring method has been described. However, when the first misalignment measuring method is performed. Alternatively, the shift amount between the center positions of the layer Lu and the layer Ld may be used.

  In the present embodiment, the case where the design matching between the SEM image of the actual pattern of the misalignment mark 25 and the GDS has been described, but the actual pattern of the misalignment mark 25 is approximated to a predetermined shape such as an annular shape. May be.

  In this embodiment, the case where the center position of the actual pattern is predicted using the aberration amount of the actual pattern calculated from the GDS has been described. However, the center position of the actual pattern may be predicted by other methods. For example, the center position of the actual pattern may be predicted using the actual pattern data and GDS. Further, the center position of the actual pattern may be predicted by simulating the shape after development (litho shape).

  FIG. 8 is a diagram for explaining a procedure for predicting the center position of the actual pattern using the actual pattern data and GDS, and FIG. 9 is a procedure for predicting the center position of the actual pattern by simulating the litho shape. It is a figure for demonstrating.

  As shown in FIG. 8, when predicting the center position of the actual pattern using the actual pattern data and GDS, the contour extracting unit 13 extracts the contour data 72 of the actual pattern 71 (s21). Then, the misalignment amount calculation unit 15 compares the GDS 73 and the contour data 72 (s22), and calculates a residual. Then, the misalignment amount calculation unit 15 predicts the center position c5 of the actual pattern based on the residual (s23).

  As shown in FIG. 9, when the center position of the actual pattern is predicted by simulating the litho shape, the misalignment amount calculation unit 15 gives the aberration amount of the exposure apparatus to the actual pattern, and the actual pattern A litho shape (litho shape with aberration) 81 corresponding to is calculated (s31). Further, the misalignment amount calculation unit 15 calculates a litho shape (litho shape without aberration) 82 based on the GDS on which the aberration amount is not present (s32). Further, the misalignment amount calculation unit 15 compares the litho shape 81 with aberration and the litho shape 82 without aberration to predict the center position c7 of the actual pattern (s33).

  After the amount of misalignment between layers is measured by the misalignment amount measuring apparatus 10, various processes are performed using this misalignment measurement result and the dimension measurement result and shape result measured in advance. For example, DFM control, feedback to design, OPC simulation, misalignment management, dimension line width management, shape management, overlay control, dimension control, shape APC control, misalignment determination, dimension line width determination, shape determination, etc. Is done.

  When a semiconductor device such as a semiconductor device is manufactured, the misalignment amount between layers is measured by the misalignment amount measuring apparatus 10 every time processing of each layer is performed. Then, the semiconductor device is manufactured while determining whether the misalignment amount in each layer is within the normal range.

  As described above, since the residuals in various directions are measured using the annular misalignment mark 25 during the manufacturing process of the semiconductor device, the measurement error of misalignment amount can be reduced. Therefore, the misalignment amount of the actual pattern with respect to the design data can be improved between lots, between wafers, between shots, within shots, and within chips. As a result, it is possible to improve accuracy by process control (APC control), improve yield, and shorten incidental work time and measurement time.

As described above, according to the first embodiment, it is possible to accurately measure the amount of misalignment between layers using the misalignment mark 25 having a small area. Further, since the misalignment amount between layers is calculated using the actual pattern of the misalignment mark 25 and the design data of the misalignment mark 25, it is possible to accurately calculate the misalignment amount. Further, since the contour data of the actual pattern is extracted and the misalignment amount between layers is calculated using the extracted contour data, it is possible to easily calculate the misalignment amount.
(Second Embodiment)

  Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, when performing a photolithography process or a processing process, an optimum inspection condition for a defect occurring in a shot or a chip is determined.

  Conventionally, in a defect inspection performed during a photolithography process or a processing process, a determination is made as to whether a defect on a wafer can be a defect of a semiconductor device using a simulation or a defect inspection apparatus. However, in this method, the defect inspection is performed by setting a predetermined inspection condition in the defect inspection apparatus regardless of the inspection position in the shot. For this reason, a long time is required for the defect inspection time. On the other hand, when the defect inspection time is shortened, there is a problem that the inspection accuracy deteriorates.

  Therefore, in the present embodiment, defect inspection in a shot is performed by setting an inspection condition corresponding to the inspection position for each inspection position (a mesh area described later) in the shot. That is, a plurality of inspection areas are set in the shot, and efficient inspection conditions in each inspection area are determined based on the predicted inspection time for each inspection area. Further, when the defect size is known in advance, defect inspection is performed by setting a defect inspection order according to the defect size.

  FIG. 10 is a block diagram showing the configuration of the defect inspection condition setting device according to the second embodiment of the present invention. The defect inspection condition setting device 50 is a device that sets inspection conditions for defect inspection in the defect inspection device 30 that performs defect inspection of a pattern formed on a wafer. The defect inspection condition setting device 50 may set the defect inspection condition for any pattern such as a resist pattern after development, a pattern after etching, and a pattern after film formation. When the defect inspection apparatus 30 performs the defect inspection of the photomask, the defect inspection condition setting apparatus 50 may set the defect inspection condition of the photomask in the defect inspection apparatus 30.

  The defect inspection condition setting device 50 includes an instruction input unit 51, a measurement point extraction unit 52, a mesh area setting unit 53, an inspection condition setting unit 55, an output unit 56, and a control unit 59. The instruction input unit 51 uses pattern design data for performing defect inspection, inspection conditions that can be set in the defect inspection apparatus 30 (unit size of inspection area, inspection speed, etc.), inspection priority used when setting inspection conditions and inspection order. Information (hereinafter referred to as inspection priority information). Inspection priority information is information used as a judgment material when setting inspection conditions and inspection order. The number of positions (measurement points) to be measured for defect inspection, the size of defects to be inspected, and the shape of defects Such information (judgment reference value). In this embodiment, a plurality of types of inspection conditions are prepared, and inspection conditions corresponding to inspection priority information are set for each mesh area described later. Note that the inspection condition and inspection priority information may be input by the user of the defect inspection condition setting device 50 via a mouse or a keyboard, or from an external device (a storage device for inspection conditions and inspection priority information). You may enter.

  The measurement point extraction unit 52 uses the design data to extract measurement points to be inspected from within the shot or chip. In the present embodiment, a case where defect inspection is performed for each shot will be described. The mesh area setting unit 53 divides the area in the shot into a plurality of mesh areas.

  The inspection condition setting unit 55 sets, for each mesh area, inspection conditions corresponding to the mesh area from among a plurality of types of inspection conditions based on the number of measurement points in the mesh area, the size of the defect, the defect shape, and the like. The inspection condition setting unit 55 sets the defect inspection order in each mesh area based on the number of measurement points in the mesh area, the size of the defect, the defect shape, and the like. The inspection condition setting unit 55 sets the defect inspection order in each mesh so that the defect inspection is performed in the order that the possibility of being detected as a defect is high.

  The output unit 56 is connected to the defect inspection apparatus 30 and outputs the inspection conditions and defect inspection order for each mesh area set by the inspection condition setting unit 55 to the defect inspection apparatus 30. The control unit 59 controls the instruction input unit 51, the measurement point extraction unit 52, the mesh area setting unit 53, the inspection condition setting unit 55, and the output unit 56.

  Here, the hardware configuration of the defect inspection condition setting device 50 will be described. FIG. 11 is a diagram illustrating a hardware configuration of the defect inspection condition setting device. In addition, the same number is attached | subjected about the component which achieves the same function as the misalignment amount calculation mechanism 12 of 1st Embodiment shown in FIG. 2 among each component of FIG. 11, and the overlapping description is abbreviate | omitted. To do.

  Similar to the misalignment amount calculation mechanism 12, the defect inspection condition setting device 50 includes a CPU 1, a ROM 2, a RAM 3, a display unit 4, and an input unit 5. The CPU 1 calculates the misalignment amount using the inspection condition setting program 47 which is a computer program. The inspection condition setting program 47 is stored in the ROM 2 and is loaded into the RAM 3 via the bus line. The CPU 1 executes an inspection condition setting program 47 loaded in the RAM 3.

  The inspection condition setting program 47 executed by the defect inspection condition setting apparatus 50 of the present embodiment includes the above-described units (instruction input unit 51, measurement point extraction unit 52, mesh area setting unit 53, inspection condition setting unit 55, output). Unit 56 and control unit 59). Each of the above units is loaded on the main storage device, and the instruction input unit 51, measurement point extraction unit 52, mesh area setting unit 53, inspection condition setting unit 55, An output unit 56 and a control unit 59 are generated on the main storage device.

  Next, a procedure for setting defect inspection conditions will be described. FIG. 12 is a flowchart showing a defect inspection condition setting process procedure. The instruction input unit 51 of the defect inspection condition setting apparatus 50 is inputted with design data of a pattern for performing defect inspection in advance.

  The measurement point extraction unit 52 uses the design data to extract measurement points for defect inspection from within the shot (step S10). Thereafter, the inspection condition and inspection priority information that can be set in the defect inspection apparatus 30 are input to the instruction input unit 51.

  As an inspection condition, for example, an inspection condition suitable for defect inspection in a wide inspection area is an inspection area of 50 μm × 50 μm, and the inspection condition for defect inspection at an inspection speed of 60 sec is the first inspection condition. Enter as. In addition, as an inspection condition suitable for defect inspection in a narrow inspection area, an inspection area of 4.2 μm × 4.2 μm is used. The inspection condition for inspecting this inspection area at an inspection speed of 2.5 sec is the second inspection condition. Input as inspection conditions. Thereby, the inspection condition setting unit 55 registers the first inspection condition and the second inspection condition as inspection conditions that can be set in the defect inspection apparatus 30 (step S20).

  In the inspection priority information, for example, when the number of measurement points is a predetermined number (for example, 25) or more, the first inspection condition is used and the number of measurement points is less than the predetermined number (for example, 25). For example, the use of the second inspection condition is specified.

  Next, the mesh area setting unit 53 divides the shot into a plurality of areas and sets a plurality of mesh areas in the shot (step S30). FIG. 13 is a diagram for explaining the mesh area setting process. As described in the processing of step S10, after the measurement point P is extracted from the inspection area 61 in the shot (s41), the inside of the shot is subjected to mesh decomposition and the mesh area 62 is set (s42). When setting the mesh area 62, the mesh area setting unit 53 may set the mesh area 62 having a size corresponding to the inspection area size that can be set as the inspection condition in the shot. For example, the mesh area setting unit 53 sets a large mesh area 62 when a large inspection area size can be set, and sets a small mesh area when a small inspection area size can be set. 62 may be set.

  Next, the inspection condition setting unit 55 extracts the number of measurement points for each mesh area 62. At this time, when the defect size and the defect shape for each mesh area 62 have been detected, the inspection condition setting unit 55 extracts the defect size and the defect shape for each mesh area 62 (step S40).

  Then, the inspection condition setting unit 55 sets an inspection condition corresponding to the mesh area 62 among the registered inspection conditions for each mesh area 62 based on the number of measurement points, the defect size, and the defect shape for each mesh area 62. . In the present embodiment, since the first inspection condition and the second inspection condition are registered, the first inspection condition or the second inspection condition is set in each mesh area 62. For example, as the inspection priority information, when it is specified that the first inspection condition is used when the number of measurement points is 25 or more, the mesh area 62 in which 25 or more measurement points P are extracted is included. A first inspection condition is set. On the other hand, when it is specified that the second inspection condition is used when the number of measurement points is less than 25, the second inspection condition is present in the mesh area 62 from which less than 25 measurement points P are extracted. Is set.

  Note that, as the inspection priority information, inspection conditions corresponding to the defect size and the defect shape may be defined. It is stipulated that the first inspection condition is set when many defects that are likely to cause processing defects are included, and the second inspection condition is set when only a few defects that are likely to cause processing defects are included. Keep it. For example, when a predetermined number of defects of a predetermined size are included, the first inspection condition may be set to be set. Further, when a predetermined number or more of defects having a predetermined shape are included, it may be specified that the first inspection condition is set.

  Next, the inspection condition setting unit 55 sets the defect inspection order in each mesh area 62 based on the number of measurement points in each mesh area 62, the defect size, the defect shape, and the like. The inspection condition setting unit 55 sets the defect inspection order so that the defect inspection is performed in the order of the measurement points P that are highly likely to be detected as defects. For example, the inspection condition setting unit 55 may set the inspection order so that each measurement point P is defect-inspected in order of increasing defect size. Further, the inspection condition setting unit 55 may classify the defect shape at each measurement point P according to the type of shape, and set the defect inspection order in the order of defect count that is likely to be detected as a defect (step S50).

  The inspection conditions for each mesh area 62 set by the inspection condition setting unit 55 and the defect inspection order in each mesh area 62 are sent to the defect inspection apparatus 30 via the output unit 56. Thereby, the defect inspection apparatus 30 performs a defect inspection in accordance with an instruction from the defect condition setting inspection apparatus 50.

  When manufacturing a semiconductor device such as a semiconductor device, the inspection condition for each mesh area 62 and the defect inspection order in each mesh area 62 are set by the defect condition setting inspection device 50 every time processing of each layer is performed. Is done. Then, a semiconductor device is manufactured while defect inspection is performed in each layer.

  In the present embodiment, the case where the first and second inspection conditions are registered after the measurement points in the shot are extracted and before the inspection area 61 is meshed has been described. The second inspection condition may be registered before extracting the measurement points in the shot. The first and second inspection conditions may be registered after the inspection area 61 is meshed.

  As described above, according to the second embodiment, the inspection condition and the defect inspection order are set for each mesh area 62 based on the inspection priority information, the number of measurement points in the mesh area 62, and the like. It becomes possible to carry out with high accuracy in a short time.

It is a block diagram which shows the structure of the misalignment measuring apparatus which concerns on 1st Embodiment. It is a figure which shows the hardware constitutions of the misalignment amount calculation mechanism. It is a figure for demonstrating the arrangement position of a misalignment mark. It is a figure for demonstrating the amount of misalignment of the misalignment mark. It is a figure which shows an example of a structure in case a misalignment mark is a polygonal cyclic | annular form. It is a figure for demonstrating the measuring method of the 1st misalignment amount. It is a figure for demonstrating the measuring method of the 2nd misalignment amount. It is a figure for demonstrating the procedure which estimates the center position of a real pattern using real pattern data and GDS. It is a figure for demonstrating the procedure which estimates the center position of a real pattern by simulating a litho shape. It is a block diagram which shows the structure of the defect inspection condition setting apparatus which concerns on 2nd Embodiment. It is a figure which shows the hardware constitutions of a defect inspection condition setting apparatus. It is a flowchart which shows the setting process sequence of defect inspection conditions. It is a figure for demonstrating the setting process of a mesh area.

Explanation of symbols

  7 misalignment calculating program, 10 misalignment measuring device, 13 contour extracting unit, 14 design data input unit, 15 misalignment calculating unit, 25 misalignment mark, 47 inspection condition setting program, 50 defect inspection condition setting device, 52 Measurement point extraction unit, 53 mesh area setting unit, 55 inspection condition setting unit, Lu, Ld layer

Claims (5)

In a misalignment measurement method for measuring a misalignment amount of overlay between layers as a misalignment amount for a semiconductor device manufactured by laminating a pattern of a plurality of layers,
Measure the distance between the first annular pattern formed in a ring shape in the first layer and the second annular pattern formed in a ring shape in the second layer so as to be arranged concentrically with the first annular pattern. In addition, a misalignment measuring method including a misalignment calculating step of calculating the misalignment amount using the measurement result. The deviation calculating step includes:
Using the positions of the actual patterns formed as the first and second annular patterns and the design data of the first and second annular patterns, the first annular pattern and the second annular pattern The misalignment measuring method according to claim 1, wherein an misalignment amount is calculated. The deviation calculating step includes:
The contour data of the actual pattern is extracted from the actual pattern, and the misalignment amount between the first annular pattern and the second annular pattern is calculated using the extracted contour data. 3. The misalignment measuring method according to 2. The deviation calculating step includes:
The distance between the first annular pattern and the second annular pattern is measured in at least five directions from the first annular pattern toward the second annular pattern. The misalignment measuring method according to any one of the above. In the misalignment inspection mark that is formed in each layer of the semiconductor device manufacturing process and used when inspecting the amount of misalignment between the layers,
A first annular pattern having an annular shape is formed in the first layer, and a second annular pattern having an annular shape is formed on the second layer so as to be concentric with the first annular pattern. This is a misalignment inspection mark.

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