JP2010041228A - Transmitter, and communication equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transmitter and a communication system for performing stable transmission operation of signals by reducing electromagnetic wave failures without degrading a signal waveform. <P>SOLUTION: A driver circuit 230 includes a differential output circuit comprising a pair of emitter combination or source combination for outputting a digital signal. Input amplitude to a base or a gate is controlled so that ratio of currents flowing in a pair of transistors MP1 and MP2 of the differential output circuit does not exceed a fixed value smaller than 10:1. The driver circuit 230 also controls drive current of the differential output circuit by using replica circuits similar to control circuits 250 and 250A so as to stabilize the output amplitude of the differential output circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a transmission device and a communication device that realize digital data transmission in, for example, high-speed serial data communication.

  FIG. 1 is a diagram illustrating a configuration example of a general serial data communication device (see, for example, Patent Document 1).

The data communication device 1 in FIG. 1 includes a transmission device 2, a reception device 3, and a transmission line 4.
The transmission device 2 includes a transmission clock generation circuit 21, a parallel / serial conversion circuit 22, and a driver circuit 23.
The receiving device 3 includes a receiver circuit 31, a clock recovery circuit 32, and a serial / parallel conversion circuit 33.

  Usually, in the case of high-speed signal communication, a differential signal is often used as a transmission signal, and the transmission line 4 between the transmission device 2 and the reception device 3 uses a twisted pair, a coaxial line, FPC, FFC, or the like. .

In this configuration, a clock recovery circuit (CDR: Clock Data Recovery circuit) 32 that extracts a clock signal from a signal is used in the receiver 3.
This clock recovery circuit 32 generates a clock signal from the received signal.
Therefore, it is not necessary to transmit the clock signal on the transmission line 4, and the problem of the skew between the clock and the data signal in the transmission line part is solved.
In addition, since a clock signal having a steep spectral peak is not transmitted, reduction of electromagnetic interference (EMI) radiated from the transmission line can be expected.
Japanese Patent Laid-Open No. 10-145436 JP-A-9-98152

  However, in recent years, with the increase in signal transmission speed, the problem of EMI (electromagnetic interference) has also surfaced in these communication systems without a clock.

  In order to reduce this problem, it has been proposed to transmit a signal using a spread spectrum clock (see Patent Document 2).

  This Patent Document 1 discloses a technique for spreading an EMI spectrum on the frequency axis by applying a minute fluctuation to a clock frequency that is normally constant, thereby reducing the EMI spectrum peak.

  However, since this method adds fluctuation to the signal itself, there is a disadvantage that a margin for the timing of the signal becomes small and it becomes difficult to obtain a large effect as the signal speed increases.

  An object of the present invention is to provide a transmission device and a communication device capable of reducing electromagnetic interference without deteriorating a signal waveform and capable of realizing a stable signal transmission operation.

  A transmission device according to a first aspect of the present invention includes a driver circuit that sends serial data to a transmission line, and the driver circuit includes a differential output circuit of a differential pair of transistors, and the transistors of the differential pair Having at least one non-saturation type differential pair circuit that outputs a differential digital signal as a differential output signal by an on / off switching operation of the non-saturation type differential pair circuit. The amplitude of the input signal to the control terminal is controlled so as to be driven in a non-saturated manner in which a current flows through the off-side transistor during the switching operation.

  Preferably, in the non-saturated differential pair circuit, the input amplitude to the control terminal is controlled so that the ratio of the currents flowing through the paired transistors does not exceed a certain value smaller than 10: 1.

  Preferably, the drive circuit includes a first control circuit, and the differential output circuit is connected to a connection point between transistors forming the differential pair, and a current can be controlled by a current control signal. A current source; and the first control circuit includes at least one replica circuit of the differential output circuit of the non-saturated differential pair circuit, and the differential output circuit according to an output signal of the replica circuit The current control signal is supplied to the current source so as to control the drive current of the current source.

  Preferably, the replica circuit is biased to output both signals of the differential voltage signal, and the first control circuit includes an intermediate voltage and an intermediate target value of both signals of the differential voltage signal. The current control signal corresponding to the comparison result is output.

  Preferably, the driver circuit is disposed on the input side of the non-saturated differential pair circuit, has a differential output circuit of a differential pair of transistors, and a current flows through the off-side transistor during the switching operation. A saturated differential pair circuit that is not driven to be saturated, and a second control circuit that controls the saturated differential pair circuit, wherein the saturated differential pair circuit is a transistor that forms the differential pair A current source that is connected to the connection point between them and whose current can be controlled by a current control signal, and the current flows to the off-side transistor in the switching operation with respect to the non-saturated differential pair circuit. The second control circuit includes at least one replica circuit of the differential output circuit of the saturated differential pair circuit, and supplies the differential signal controlled to be desaturated. The current control signal is supplied to the current source so as to control the drive current of the current source of the differential output circuit according to the output signal of the power circuit, and the replica circuit of the first control circuit The first control circuit is biased to output both signals of the voltage signal, and the first control circuit outputs the current control signal according to the comparison result between the intermediate voltage of the two signals of the differential voltage signal and the intermediate target value. And outputs a request signal to the second control circuit in accordance with a comparison result between one signal of the differential voltage signal and the requested target value, and the second control circuit outputs a differential signal of the replica circuit. The current control signal is output in accordance with a comparison result between one signal of the voltage signal and the request signal by the first control circuit.

  Preferably, the driver circuit is disposed on the input side of the non-saturated differential pair circuit, has a differential output circuit of a differential pair of transistors, and a current flows through the off-side transistor during the switching operation. A saturated differential pair circuit that is not driven to be saturated, and a second control circuit that controls the saturated differential pair circuit, wherein the saturated differential pair circuit is a transistor that forms the differential pair A current source that is connected to the connection point between them and whose current can be controlled by a current control signal, and the current flows to the off-side transistor in the switching operation with respect to the non-saturated differential pair circuit. The second control circuit includes at least one replica circuit of the differential output circuit of the saturated differential pair circuit, and supplies the differential signal controlled to be desaturated. The current control signal is supplied to the current source so as to control the drive current of the current source of the differential output circuit according to the output signal of the power circuit, and the first control circuit A first replica circuit biased to output a signal and a second replica circuit biased to output an addition signal obtained by adding both signals of the differential voltage signal. The control circuit outputs the current control signal according to the comparison result between the output addition signal of the second replica circuit and the addition target value, and compares one signal of the first replica circuit with the requested target value In response to the result, a request signal is output to the second control circuit, and the second control circuit outputs one of the differential voltage signals of the replica circuit and the request signal from the first control circuit. And it outputs the current control signal corresponding to a result of comparison between.

  Preferably, the first non-saturation type differential pair circuit disposed on the output side of the transmission line and the first non-saturation type differential pair circuit disposed on the input side of the first non-saturation type differential pair circuit. A second non-saturated differential pair that supplies a differential signal in which the input signal amplitude is controlled to be non-saturated and the current flows through the off-side transistor during the switching operation. Saturated drive that is arranged on the input side of the circuit and the second non-saturated differential pair circuit, has a differential output circuit of a differential pair of transistors, and does not flow current to the off-side transistor during the switching operation The second non-saturated differential pair circuit is supplied with a differential signal whose input signal amplitude is controlled to be non-saturated so that current flows through the off-side transistor during the switching operation. Type differential pair circuit and the first non-saturation A first control circuit for controlling the current of the differential pair circuit, a second control circuit for controlling the current of the second unsaturated type differential pair circuit, and a current of the saturated type differential pair circuit The first and second non-saturation type differential pair circuits, and the saturation type differential pair circuit are connection points of transistors forming the differential pair. And a current source that can be controlled by a current control signal, wherein the first control circuit includes at least one replica circuit of the differential output circuit of the first non-saturated differential pair circuit. The replica circuit is biased to output both signals of the differential voltage signal, and the first control circuit compares the intermediate voltage of both signals of the differential voltage signal with an intermediate target value. Current control according to the result And outputs a request signal to the second control circuit in accordance with a comparison result between one signal of the differential voltage signal and the required target value, and the second control circuit A first replica circuit including a first replica circuit and a second replica circuit of the differential output circuit of the non-saturated differential pair circuit, wherein the first replica circuit is biased to output both signals of the differential voltage signal; The second replica circuit is biased so as to output an addition signal obtained by adding both signals of the differential voltage signal, and the second control circuit is configured to output an output addition signal of the second replica circuit and an addition target value. The current control signal according to the comparison result is output, the request signal is output to the third control circuit according to the comparison result between one signal of the first replica circuit and the required target value, and the third control circuit The control circuit of Including a replica circuit of the differential output circuit of the saturation type differential pair circuit, and according to a comparison result between one signal of the differential voltage signal of the replica circuit and the request signal by the second control circuit The current control signal is output.

  Preferably, the driver circuit is disposed on the input side of the non-saturated differential pair circuit, and is saturated and driven so that no current flows through the off-side transistor during the switching operation. In order to drive the saturation type differential pair circuit from logic to the input side of the saturation type differential pair circuit, a conversion circuit for converting into a differential pair drive signal is included, and the saturation type differential pair circuit includes: A differential digital signal that is controlled so as to be driven in a non-saturated manner in which a current flows through an off-side transistor during the switching operation is supplied to the non-saturated differential pair circuit. And an amplitude limiting circuit for limiting the amplitude of the drive signal for driving the differential pair of the saturation type differential pair circuit.

  Preferably, in order to drive the saturation type differential pair circuit from logic to the input side of the saturation type differential pair circuit, the conversion circuit converts the differential type drive signal into a differential pair drive signal. An amplitude limiting circuit for limiting an amplitude of a drive signal for driving the differential pair of the saturation type differential pair circuit;

  A communication device according to a second aspect of the present invention includes a transmission line, a transmission device, and a reception device that receives a differential digital signal transmitted from the transmission device to the transmission line. A driver circuit for sending serial data to a transmission line, the driver circuit including a differential output circuit of a differential pair of transistors, and differential digital by switching on and off of the transistors of the differential pair At least one non-saturation type differential pair circuit that outputs a signal as a differential output signal, and the non-saturation type differential pair circuit has an input signal amplitude to the control terminal of the paired transistors that is the switching It is controlled to be driven in a non-saturated manner in which a current flows through the off-side transistor during operation.

  According to the present invention, the amplitude of the input signal to the control terminal of the transistor forming the differential output circuit pair of the non-saturated differential pair circuit is driven to be desaturated so that a current flows through the off-side transistor during the switching operation. Controlled and supplied.

  According to the present invention, it is possible to reduce electromagnetic interference without deteriorating a signal waveform, and a stable signal transmission operation can be realized.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 is a diagram illustrating a basic configuration of the communication apparatus according to the embodiment of the present invention.

  The communication device 100 includes a transmission device 200, a reception device 300, and a transmission line 400.

  The transmission apparatus 200 includes a transmission clock generation circuit 210, a parallel / serial conversion circuit 220, and a driver circuit 230.

  The transmission clock generation circuit 210 receives the basic clock CLK, generates a transmission clock TCLK, and supplies it to the parallel / serial conversion circuit 220.

  The parallel / serial conversion circuit 220 converts N-bit parallel data into 1-bit serial data in synchronization with the transmission clock, and supplies the 1-bit serial data to the driver circuit 230.

The driver circuit 230 sends digital serial data, which is a differential signal from the parallel / serial conversion circuit 220, to the transmission line 400 with a low amplitude, for example, 100 mV.
The driver circuit 230 according to this embodiment includes a differential output circuit composed of an emitter coupling or a source coupling pair that outputs a digital signal.
The input amplitude to the base or gate as the control terminal is controlled so that the ratio of the currents flowing through the transistors forming the pair of the differential output circuits does not exceed a certain value smaller than 10: 1.
In other words, the input signal amplitude to the base or gate as the control terminal of the paired transistors is controlled so as to be driven in a non-saturated manner in which a current flows through the off-side transistor during the switching operation.
Further, the driver circuit 230 is configured to control the drive current of the differential output circuit using a replica circuit that is similar to the driver circuit in order to stabilize the output amplitude of the differential output circuit. ing.
The driver circuit 230 having such a configuration includes a function of reducing EMI without deteriorating a signal waveform or reducing a timing margin.
A specific configuration and function of the driver circuit 230 will be described in detail later.

  As illustrated in FIG. 2, the reception device 300 includes a receiver circuit 310, a clock recovery circuit 320, and a serial / parallel conversion circuit 330.

  The receiver circuit 310 receives the digital serial data propagated through the transmission line 400 and supplies the received serial data to the clock recovery circuit 320 and the serial / parallel conversion circuit 330.

  The clock recovery circuit 320 includes a clock recovery circuit (CDR: Clock Data Recovery circuit) that extracts a clock signal from the received serial data, and supplies the extracted recovery clock CLK to the serial / parallel conversion circuit 330.

  The serial / parallel converter circuit 330 converts the data received as serial data into N-bit parallel data in synchronization with the clock CLK recovered by the clock recovery circuit 320.

  In the case of high-speed signal communication, a differential signal is often used as a transmission signal. For the transmission line 400 between the transmission device 200 and the reception device 300, a twisted pair, a coaxial line, FPC, FFC, or the like is used.

Heretofore, the configuration and function of the communication apparatus 100 according to the present embodiment have been described.
Hereinafter, a specific configuration and function of the driver circuit 230 according to the present embodiment will be described.

  FIG. 3 is a circuit diagram showing a configuration example of the differential output circuit in the driver circuit according to the present embodiment.

  The differential output circuit 240 includes a current source I1, p-channel MOS (PMOS) transistors MP1 and MP2, and resistance elements R1 and R2.

The source of the PMOS transistor MP1 and the source of the PMOS transistor MP2 are coupled to each other, and the coupling node ND1 is connected to the current source I1.
The current source I1 is connected to the power supply potential VDD. The current source I1 is formed by a PMOS transistor, for example.
In this case, the drain of the PMOS transistor is connected to the coupling node ND1, the source is connected to the power supply potential VDD, and a current control signal ItaiSet described later is supplied to the gate as the control terminal.
The drain of the PMOS transistor MP1 is connected to one end of the resistance element R1, and an output node NDO1 of one signal Vout− of the digital differential signal is formed by the connection point.
The drain of the PMOS transistor MP2 is connected to one end of the resistance element R2, and an output node NDO2 of the other signal Vout + of the digital differential signal is formed by the connection point.
The other ends of the resistance elements R1 and R2 are connected to a reference potential, for example, a ground potential GND.
One signal Vin + of the differential voltage signal is supplied to the gate of the PMOS transistor MP1, and the other signal Vin− of the differential voltage signal is supplied to the gate of the PMOS transistor MP2.

  Although the P-type MOS transistor is used for each description, it is essentially equivalent to using an N-type MOS transistor with the power supply and GND reversed and using a bipolar transistor.

In the differential output circuit 240, the input amplitude to the gate is controlled so that the ratio of the currents flowing through the paired PMOS transistors MP1 and MP2 does not exceed a certain value smaller than 10: 1, and switching is not performed completely. It is configured as follows.
In other words, the differential output circuit 240 is configured such that the input amplitude of one of the differential voltage signals Vin + and Vin− to the gates of the PMOS transistors MP1 and MP2 is controlled and switching is not performed completely.

  Here, the reason why the input amplitude to the gate is controlled so that the ratio of the currents flowing through the PMOS transistors MP1 and MP2 forming the pair of the differential output circuit 240 does not exceed a constant value smaller than 10: 1 and the switching is not completely performed. explain.

In high-speed serial communication, a driver circuit that normally transmits digital data is required to operate at high speed.
For this reason, the driver circuit 230 employs a differential output circuit 240 composed of a source coupled or emitter coupled transistor pair as shown in FIG.

FIG. 4 is a schematic diagram illustrating an operation when the input amplitude of the differential output circuit of FIG. 3 is not limited.
FIG. 5 is a diagram for explaining the parasitic capacitance of the driver circuit.
FIG. 6 is a diagram showing an actual drive waveform pattern (eye pattern).
FIG. 7 is a diagram illustrating a power spectrum of a waveform including distortion.
FIG. 8 is a diagram illustrating an example of driver output at the time of 2.88 Gbps operation.

When the input amplitude is not limited, as shown in FIG. 4, the source-coupled PMOS transistors MP1 and MP2 are driven by the differential voltage signals Vin + and Vin−, so that the current Itail of the current source I1 becomes the current Iout1 and the current Iout1. Switch to either Iout2.
As a result, output differential voltage signals Vout + (VoutN) and Vout− (VoutP) are generated at the output nodes NDO1 and NDO2.

However, the actual driver circuit further has a parasitic capacitance CP as shown in FIG.
When high-speed switching is performed with such a driver circuit, distortion occurs in the output waveform due to the influence of the capacitance.
This is because when the transistors MP1 and MP2 are switched on / off, a charge-up current for the parasitic capacitance of the transistor on the off side flows through the transistor on the opposite side.

  In general, distortion as shown in FIG. 6 is generated in the eye pattern of the output waveform, and this distortion is caused by the non-linear behavior of the transistor, so it is difficult to completely remove it.

The distortion due to the non-linear operation of the transistor is shown in FIG. 7 on the power spectrum.
The charge-up current generated by the switching of the transistors MP1 and MP2 is generated at a cycle that is an integral multiple of the signal transmission speed.
Therefore, this distortion appears as a steep peak at a frequency that is an integral multiple of the signal transmission speed on the frequency spectrum.
Since this peak occurs in the same direction for each of the differential signals, most of the peak is a common mode component.

FIG. 8 shows the power spectrum of the common mode component included in the serial signal of 2.88 Gbps operation.
It can be seen from FIG. 8 that a steep peak exists at a frequency that is an integral multiple of the signal frequency.
Since the common mode component is much easier to radiate than the differential component, these steep common mode peaks tend to become a problem when the EMI test is performed.

  Therefore, in this embodiment, in order to prevent waveform distortion when the transistor is completely turned off, the input difference is set so that the ratio of the currents flowing through the paired transistors MP1 and MP2 does not exceed a certain value smaller than 10: 1. The input amplitude of the dynamic voltage signals Vin + and Vin− is controlled.

  FIG. 9 is a diagram showing an outline of the operation of the differential output circuit in the driver circuit according to the present embodiment.

Usually, in a driver circuit for digital communication, ON / OFF is switched by a switching operation of the transistors MP1 and MP2, and the current Itail is distributed to stabilize the output signal amplitude.
On the other hand, in the present embodiment, the transistor on the OFF side is driven to leave some current (Imargin) during the switching operation.
This makes it possible to suppress waveform distortion that occurs when the transistor is completely turned off.
Such a differential pair driving method is hereinafter referred to as “non-saturation driving (operation)”.

When this non-saturation driving method is used, the charge-up current can be reduced. Therefore, the distortion of the drive waveform can be suppressed and EMI can be reduced at the same time.
However, the output high level voltage VoutHigh and the output low level voltage VoutLow vary greatly depending on the input voltage amplitudes VinHigh and VinLow.
Furthermore, since the values of the input voltage amplitudes VinHigh and VinLow necessary for the operation vary greatly depending on the operating conditions and semiconductor process variations, a control circuit for always maintaining the above operation is required.

  FIG. 10 is a diagram illustrating an example of an overall configuration of a driver circuit that employs the non-saturation drive type differential pair circuit according to the present embodiment.

The driver circuit 230A includes a non-saturated differential pair circuit 241 as a differential output circuit and a saturated differential pair circuit 242 connected to the preceding stage of the non-saturated differential pair circuit 241.
The non-saturated differential pair circuit 241 and the saturated differential pair circuit 242 basically have the same circuit configuration as the differential output circuit of FIG.
The saturation type differential pair circuit 242 is driven by saturation so that no current flows in the off-side transistor during the switching operation.

In order to control the input amplitude for driving the non-saturated differential pair circuit 241 as the differential output circuit, the driver circuit 230A once determines the amplitude by the saturated differential pair circuit 242, and uses this output to The saturation type differential pair circuit 241 is driven.
A control circuit for controlling driving of the non-saturated differential pair circuit 241 and the saturated differential pair circuit 242 is provided.

In the present embodiment, for example, each of the driver circuits by simply using the non-saturated differential pair circuit 241 and the control circuit, or for controlling the driving of the non-saturated differential pair circuit 241 and the saturated differential pair circuit 242. Configured as a driver circuit with a control circuit.
Alternatively, in the present embodiment, as a driver circuit having a pre-saturation type differential pair circuit between the non-saturation type differential pair circuit 241 and the saturation type differential pair circuit 242 and having respective control circuits. Composed.

  FIG. 11 is a circuit diagram showing a first example of the configuration of the unsaturated differential pair circuit and its control circuit according to the present embodiment.

The control circuit 250 includes a replica circuit 251 having a configuration similar to that of the unsaturated differential pair circuit 241, comparators 252 and 253, voltage dividing resistance elements R251 and R252, and load resistances R253 and R254.
The control circuit 250 functions as a first control circuit.

The replica circuit 251 is always biased and controlled so as to output high and low, and the input / output signals are used to output the high / low output voltages Vout + and Vout− of the differential pair circuit 241. Is controlled to become the target value.
The control circuit 250 includes a control target voltage VoutHighTarget for the output voltage VoutHigh of the replica circuit 251, an intermediate output voltage (VoutLow + VoutHigh) / 2 for the High / Low output voltage, a control target voltage (VoutComTarget), and an input Low voltage VinLow voltage. Have been supplied.
The control target voltage VoutHighTarget is supplied to the inverting input (−) of the comparator 253. The high-side output voltage VoutLow of the replica circuit 251 is supplied to the non-inverting input (+) of the comparator 253.
The control target voltage VoutComTarget is supplied to the non-inverting input (+) of the comparator 252. A voltage obtained by dividing the high / low output voltages VoutHigh and VoutLow by the resistance elements R251 and R252 is supplied to the inverting input (−) of the comparator 252.

Then, a current control signal ItailSet for controlling the drive current Itail of the differential pair circuit 241 is supplied from the output of the comparator 252 to the gate of the transistor forming the current source I1 (FIG. 3) of the differential pair circuit 241.
The comparator 253 outputs a required input voltage VinHigh necessary for driving the non-saturated differential pair circuit 241.
The required input voltage VinHigh output from the comparator 253 supplies, for example, the saturated differential pair circuit 242 of the previous stage that supplies the input voltages Vin + and Vin− whose input amplitude is controlled to the non-saturated differential pair circuit 241. Supplied to the control circuit.

As described above, in the control circuit 250, the drive current Itail of the differential pair circuit is set so as to output the target output voltages VoutHigh and VoutLow, and the value of the output voltage VinHigh necessary for driving the differential output circuit is set. Output.
Since the control circuit 250 controls two values of the required input voltage VinHigh and the current control signal ItailSet, two control loops exist simultaneously. However, since the control loop of the current control signal ItaiSet is operating in the common mode and the control loop of the required input voltage VinHigh is operating in the differential mode, they are configured not to interfere with each other.
In response to the required input voltage VinHigh, a control circuit (not shown) in FIG. 11 controls the output voltage of, for example, the saturated differential pair circuit 242 in the previous stage.

  FIG. 12 is a circuit diagram showing a second example of the configuration of the unsaturated differential pair circuit and its control circuit according to the present embodiment.

The control circuit 250A of the second example includes a first replica circuit 251, a comparator 252A, 253, a second replica circuit 254, an adder 255, and a load resistor R253- having a configuration similar to that of the unsaturated differential pair circuit 241. R256.
In FIG. 12, the same components as those in FIG. 11 are denoted by the same reference numerals in order to facilitate understanding.
The control circuit 250A functions as a first or second control circuit.

As described above, the control circuit 250A has two replica circuits having a configuration similar to that of the non-saturated differential pair circuit 241.
The replica circuit 254 is biased and controlled so that all currents flow through one of the differential pairs to obtain an added output signal, and this output signal is used to control the current source I1 of the differential pair circuit 241 (FIG. 3). Determine the current Itail.
As in the case of FIG. 11, the replica circuit 251 is biased and controlled so as to always output high and low, and this input / output signal is used to control the high level of the differential pair circuit 241. Control is performed so that the / Low output voltages Vout + and Vout− become target values.

In addition to the control target voltage VoutHighTarget of the output voltage VoutHigh of the replica circuit 251 and the control target voltage VoutLowTarget of the output voltage VoutLow of the replica circuit 251, the control circuit 250A is also supplied with the input low voltage VinLow voltage.
The control circuit 250A compares the output (VoutHigh + VoutLow) of the second replica circuit 254 with the control target voltage (VoutHighTarget + VoutLowTarget) by the comparator 252A.
Then, a current control signal ItailSet for controlling the drive current Itail of the differential pair circuit 241 is supplied from the comparator 252A to the gate of the transistor forming the current source I1 (FIG. 3) of the differential pair circuit 241.
The comparator 253 outputs a required input voltage VinHigh necessary for driving the non-saturated differential pair circuit 241.

The required input voltage VinHigh output from the comparator 253 supplies, for example, the saturated differential pair circuit 242 of the previous stage that supplies the input voltages Vin + and Vin− whose input amplitude is controlled to the non-saturated differential pair circuit 241. Supplied to the control circuit.
Since the control circuit 250 controls two values of the required input voltage VinHigh and the current control signal ItailSet, two control loops exist simultaneously. However, since they are driven using different replica circuits 251 and 254, they do not interfere with each other.

  FIG. 13 is a circuit diagram showing a configuration example of a saturated differential pair circuit that drives the non-saturated differential pair circuit according to the present embodiment and a control circuit thereof.

The control circuit 260 includes a replica circuit 261 having a configuration similar to that of the saturation type differential pair circuit 242, a comparator 262, and load resistors R261 and R262.
The control circuit 260 functions as a second or third control circuit.

The replica circuit 261 is biased and controlled so as to always output high.
The control circuit 260 is supplied with the required input voltage VintHigh supplied from the control circuits 250 and 250A of the non-saturated differential pair circuit 241 as the control target voltage VinHighTarget.
The control circuit 260 compares the output VoutHigh of the replica circuit 261 with the control target voltage VinHighTarget by the comparator 262.
Then, a current control signal ItailSet for controlling the drive current Itail of the differential pair circuit 242 is supplied from the comparator 262 to the gate of the transistor forming the current source I1 (FIG. 3) of the differential pair circuit 242.
As a result, the saturated differential pair circuit 242 supplies the input voltages Vin + and Vin− with the input amplitude controlled to the non-saturated differential pair circuit 241.
The saturation type differential pair circuit 242 operates in a completely switching manner, and its amplitude is controlled by controlling the current Itail of the current source I1 by the replica circuit 261 of the control circuit 260.

  Next, corresponding to FIG. 10 described above, a configuration example of the entire driver circuit to which the circuits of FIGS. 11 to 13 are applied will be described.

  FIG. 14 is a diagram showing a configuration of a drive circuit configured by combining the circuit of FIG. 11 and the circuit of FIG.

In the drive circuit 230B, the next voltage is supplied to the first control circuit 250 in the output stage.
That is, the control circuit 250 includes a control target voltage VoutHighTarget for the output voltage VoutHigh of the replica circuit 251, an intermediate output voltage (VoutLow + VoutHigh) / 2 for the high / low output voltage, a control target voltage (VoutComTarget) for the output voltage, and an input low voltage VinLow. Voltage is being supplied.

Then, a current control signal ItailSet for controlling the drive current Itail of the differential pair circuit 241 is supplied from the output of the comparator 252 to the gate of the transistor forming the current source I1 (FIG. 3) of the differential pair circuit 241.
The comparator 253 outputs a required input voltage VinHigh necessary for driving the non-saturated differential pair circuit 241.
The required input voltage VinHigh output from the comparator 253 supplies, for example, the saturated differential pair circuit 242 of the previous stage that supplies the input voltages Vin + and Vin− whose input amplitude is controlled to the non-saturated differential pair circuit 241. This is supplied to the second control circuit 260.
The control circuit 260 compares the output VoutHigh of the replica circuit 261 with the control target voltage VinHighTarget by the comparator 262.
Then, a current control signal ItailSet for controlling the drive current Itail of the differential pair circuit 242 is supplied from the comparator 262 to the gate of the transistor forming the current source I1 (FIG. 3) of the differential pair circuit 242.
As a result, the saturated differential pair circuit 242 supplies the input voltages Vin + and Vin− with the input amplitude controlled to the non-saturated differential pair circuit 241.

  FIG. 15 is a diagram showing a configuration of a drive circuit configured by combining the circuit of FIG. 12 and the circuit of FIG.

In the drive circuit 230C, the next voltage is supplied to the first control circuit 250A in the output stage.
In addition to the control target voltage VoutHighTarget of the output voltage VoutHigh of the replica circuit 251 and the control target voltage VoutLowTarget of the output voltage VoutLow of the replica circuit 251, the control circuit 250A is also supplied with the input low voltage VinLow voltage.
Then, a current control signal ItailSet for controlling the drive current Itail of the differential pair circuit 241 is supplied from the comparator 252A to the gate of the transistor forming the current source I1 (FIG. 3) of the differential pair circuit 241.
The comparator 253 outputs a required input voltage VinHigh necessary for driving the non-saturated differential pair circuit 241.
The required input voltage VinHigh output from the comparator 253 supplies, for example, the saturated differential pair circuit 242 of the previous stage that supplies the input voltages Vin + and Vin− whose input amplitude is controlled to the non-saturated differential pair circuit 241. This is supplied to the second control circuit 260.
In the second control circuit 260, the comparator 262 compares the output VoutHigh of the replica circuit 261 with the control target voltage VinHighTarget.
Then, a current control signal ItailSet for controlling the drive current Itail of the differential pair circuit 242 is supplied from the comparator 262 to the gate of the transistor forming the current source I1 (FIG. 3) of the differential pair circuit 242.
As a result, the saturated differential pair circuit 242 supplies the input voltages Vin + and Vin− with the input amplitude controlled to the non-saturated differential pair circuit 241.

  FIG. 16 is a diagram showing a configuration of a drive circuit configured by combining the circuit of FIG. 11, the circuit of FIG. 12, and the circuit of FIG.

  In the driver circuit 230D, the circuit shown in FIG. 11 is arranged at the output stage, the circuit shown in FIG. 12 is arranged as a pre-circuit before the circuit shown in FIG. 11, and the circuit shown in FIG. 13 is arranged before the circuit shown in FIG. Yes.

  The first control circuit 250 includes a control target voltage VoutHighTarget for the output voltage VoutHigh of the replica circuit 251, an intermediate output voltage (VoutLow + VoutHigh) / 2 for the high / low output voltage, and an input low voltage. VinLow voltage is supplied.

Then, a current control signal ItailSet for controlling the drive current Itail of the differential pair circuit 241 is supplied from the output of the comparator 252 to the gate of the transistor forming the current source I1 (FIG. 3) of the differential pair circuit 241.
The comparator 253 outputs a required input voltage VinHigh necessary for driving the non-saturated differential pair circuit 241.
The required input voltage VinHigh output from the comparator 253 supplies, for example, the second non-saturated differential of the previous stage, which supplies the non-saturated differential pair circuit 241 with the input voltages Vin + and Vin− whose input amplitude is controlled. The voltage is supplied to the second control circuit 250A of the pair circuit 241A.

The control target voltage VoutHighTarget of the output voltage VoutHigh of the replica circuit 251 is supplied to the second control circuit 250A as the required input voltage VinHigh from the control circuit 250 in the output stage.
The second control circuit 250A is also supplied with the input low voltage VinLow voltage in addition to the control target voltage VoutLowTarget of the output voltage VoutLow of the replica circuit 251.
Then, a current control signal ItailSet for controlling the drive current Itail of the differential pair circuit 241 is supplied from the comparator 252A to the gate of the transistor forming the current source I1 (FIG. 3) of the differential pair circuit 241A.
The comparator 253 outputs a required input voltage VinHigh necessary for driving the second non-saturated differential pair circuit 241A.
The required input voltage VinHigh output from the comparator 253 is, for example, that of the saturated differential pair circuit 242 of the previous stage that supplies the input voltages Vin + and Vin− with controlled input amplitude to the non-saturated differential pair circuit 241A. This is supplied to the third control circuit 260.
In the third control circuit 260, the comparator 262 compares the output VoutHigh of the replica circuit 261 with the control target voltage VinHighTarget.
Then, a current control signal ItailSet for controlling the drive current Itail of the differential pair circuit 242 is supplied from the comparator 262 to the gate of the transistor forming the current source I1 (FIG. 3) of the differential pair circuit 242.
As a result, the saturated differential pair circuit 242 supplies the input voltages Vin + and Vin− with the input amplitude controlled to the non-saturated differential pair circuit 241.

  Thus, a large EMI reduction effect can be expected by combining unsaturated differential pairs in multiple stages.

  Next, consider the case where the signal input side of the driver circuit 230 is a CMOS logic circuit.

  FIG. 17 is a diagram showing an overall configuration of a driver circuit when driven by CMOS logic.

The driver circuit 230E is configured by disposing a CMOS logic differential pair conversion circuit 270 at the input stage of the driver circuit 10A of FIG.
In FIG. 17, in order to facilitate understanding, the same components as those in FIG. 10 are denoted by the same reference numerals.

  When the circuit on the signal input side of the driver circuit is a CMOS logic circuit, as shown in FIG. 17, a conversion circuit 270 from CMOS logic to a differential pair drive signal is required to drive the saturated differential pair circuit 242. It becomes.

  FIG. 18 is a diagram illustrating a typical circuit example in which a saturated differential pair is driven by a CMOS logic inverter.

In FIG. 18, the saturation type differential pair circuit 242 has the same circuit configuration as the circuit of FIG. 3, and is therefore denoted by the same reference numeral as in FIG. 3 for easy understanding.
Further, in FIG. 18, the input parts to the gates of the PMOS transistors MP1 and MP2 which are the inputs of the saturation type differential pair circuit 242 so that the CMOS logic inverters INV1 and INV2 form the CMOS inverter differential coupling part 271. Is arranged.

  However, when this circuit is used, since the differential pair of transistors is driven by a signal having the same amplitude as the power supply voltage, there is a possibility that large waveform distortion may occur due to the above-described parasitic capacitance charge-up. .

  FIG. 19 is a diagram illustrating a configuration example of a conversion circuit that drives a differential pair with CMOS logic while suppressing waveform distortion.

In this conversion circuit 270A, the drive voltage of the inverters INV4 and INV4 of the CMOS inverter unit 272 is coupled to the CMOS inverter differential coupling unit 271 by the inverters INV1 and INV2, and the signal rise and fall times are asymmetric. To alleviate.
Further, an amplitude limiting circuit 273 is used on the input side of the saturation type differential pair circuit 242 to reduce the amplitude for driving the differential pair to a constant amplitude. With these ideas, it is possible to reduce waveform disturbance in the saturation type differential pair circuit 242.

  The amplitude limiting circuit 273 of FIG. 19 includes PMOS transistors MP11 and MP12, n-channel MOS (NMOS) transistors MN11 and MN12, and resistance elements R11 to R13.

The source of the PMOS transistor MP11 and the source of the PMOS transistor MP12 are coupled to each other, and the coupling node ND1 is connected to the power supply potential VDD via the resistance element R11.
The source of the NMOS transistor NP11 and the source of the NMOS transistor NP12 are coupled to each other, and the coupling node ND12 is connected to a reference potential, for example, the ground potential GND through the resistance element R12.
The drain of the PMOS transistor MP11 and the drain of the NMOS transistor NP11 are connected, and an output node NDO11 for the differential voltage signal Vout− whose amplitude is limited by the connection point is formed.
The drain of the PMOS transistor MP12 and the drain of the NMOS transistor NP12 are connected, and an output node NDO12 of the differential voltage signal Vout + whose amplitude is limited by the connection point is formed.
A resistance element R13 is connected between the output node NDO11 and the output node NDO12.

The gate of the PMOS transistor MP11 and the gate of the NMOS transistor NP11 are connected to the output of the inverter INV4, and the gate of the PMOS transistor MP12 and the gate of the NMOS transistor NP12 are connected to the output of the inverter INV3.
Therefore, the PMOS transistor MP11 and the NMOS transistor NP11 are turned on and off in a complementary manner.
Similarly, the PMOS transistor MP12 and the NMOS transistor NP12 are turned on and off in a complementary manner.

When the output of the inverter INV3 is low and the output of the inverter INV4 is high, the PMOS transistor MP12 and the NMOS transistor NP11 are turned on. Further, the PMOS transistor MP11 and the NMOS transistor NP12 are turned off.
Therefore, in this case, the power supply potential VDD, the resistance element R11, the PMOS transistor MP12, the output nodes ND012, NDO11, the NMOS transistor NM11, the resistance element R12, and the ground potential GND line are formed.
As a result, the voltage is divided by the resistance elements R11, R12, and R13, and the differential voltage signals Vin + and Vin− whose amplitudes are limited are output from the output nodes ND012 and NDO11.

When the output of the inverter INV3 is high and the output of the inverter INV4 is low, the PMOS transistor MP12 and the NMOS transistor NP11 are turned off. Further, the PMOS transistor MP11 and the NMOS transistor NP12 are turned on.
Therefore, in this case, the power supply potential VDD, the resistance element R11, the PMOS transistor MP11, the output nodes ND011, NDO12, the NMOS transistor NM12, the resistance element R12, and the ground potential GND line are formed.
As a result, the voltage is divided by the resistance elements R11, R12, and R13, and the differential voltage signals Vin + and Vin− whose amplitudes are limited are output from the output nodes ND012 and NDO11.

  In this case, either one of the output nodes ND012 and NDO11 is switched to the power supply potential VDD side or the ground potential GND side across the resistor element R13. Therefore, the differential voltage signal Vin + whose amplitude is limited from each output node ND012 and NDO11. Vin− takes a complementary value.

  According to the circuit of FIG. 19, it is possible to reduce waveform disturbance in the saturation type differential pair circuit 242.

  FIG. 20 is a diagram illustrating another configuration example of a conversion circuit that drives a differential pair with CMOS logic while suppressing waveform distortion.

  20 is different from the conversion circuit 270A in FIG. 19 in that a feedback circuit is applied to the amplitude limiting circuit 273B.

In this amplitude limiting circuit 273B, a PMOS transistor MP13 and an NMOS transistor NP13 are arranged as current sources instead of the resistance elements R11 and R12 of the amplitude limiting circuit 273 in FIG. 19, and the resistance element R13 is divided into resistance elements R131 and R132. is there.
In order to control the gate voltage of the PMOS transistor MP13, the PMOS transistor MP14T and the resistor element R14 are connected in series between the power supply potential VDD and the ground potential GND. Then, the comparator 274 compares the target value VampTarget with the voltage at one end of the resistance element R14, and the gate voltages of the PMOS transistors MP13 and MP14 are controlled by the output.
Further, a comparator 275 is arranged to control the gate voltage of the NMOS transistor NP13.
The comparator 275 compares the voltage at the connection point of the resistance elements R131 and R132 with the target value VcomTarget, and the output controls the gate voltage of the NMOS transistor NP13.

  Thus, by using the feedback circuit for the amplitude limiting circuit 273B, the output of the amplitude limiting circuit can be kept at the minimum voltage amplitude necessary for driving the saturated differential pair circuit 242.

  Next, the operation according to the above configuration will be described.

On the transmitting device 200 side, in the parallel-serial conversion circuit, N-bit parallel data is converted into serial data in synchronization with the generated clock and supplied to the driver circuit 230.
The driver circuit 230 includes a differential output circuit 240 composed of a source coupled pair that outputs a digital signal.
The input amplitude to the gate is controlled so that the ratio of the currents flowing through the transistors MP1 and MP2 forming the pair of the differential output circuit 240 does not exceed a certain value smaller than 10: 1.
As a result, the driver circuit 230 reduces EMI without degrading the signal waveform or reducing the timing margin.
The serial data is sent to the transmission line 400 by the driver circuit 230.

The serial data transmitted through the transmission line 400 is received on the receiving device 300 side.
In the receiving device 300, serial data is received by the receiver circuit 310.
The received serial data is supplied to the clock recovery circuit 320 and the serial / parallel conversion circuit 330.
In the clock recovery circuit 320, a clock signal is extracted from the received serial data, and the extracted recovered clock CLK is supplied to the serial / parallel conversion circuit 330.
Then, the serial / parallel conversion circuit 330 converts the data received as serial data in synchronization with the clock CLK reproduced by the clock reproduction circuit 320 into N-bit parallel data.

According to the present embodiment described above, the driver circuit 230 includes a differential output circuit composed of an emitter coupling or a source coupling pair that outputs a digital signal. The input amplitude to the base or gate is controlled so that the ratio of the currents flowing through the transistors MP1 and MP2 forming a pair of the differential output circuits does not exceed a certain value smaller than 10: 1.
The driver circuit 230 is configured to control the drive current of the differential output circuit using a replica circuit similar to the control circuits 250 and 250A in order to stabilize the output amplitude of the differential output circuit. .
Therefore, according to this embodiment, EMI can be reduced without degrading the signal waveform or reducing the timing margin, and a stable signal transmission operation can be realized.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

It is a figure which shows the structural example of a general serial data communication apparatus. It is a figure which shows the basic composition of the communication apparatus which concerns on embodiment of this invention. It is a circuit diagram which shows the structural example of the differential output circuit in the driver circuit which concerns on this embodiment. It is a figure which shows the operation | movement outline diagram when the input amplitude of the differential output circuit of FIG. 3 is not restrict | limited. It is a figure for demonstrating the parasitic capacitance of a driver circuit. It is a figure which shows an actual drive waveform pattern (eye pattern). It is a figure which shows the power spectrum of the waveform containing distortion. It is a figure which shows the driver output example at the time of 2.88Gbps operation | movement. It is a figure which shows the operation | movement outline | summary of the differential output circuit in the driver circuit which concerns on this embodiment. It is a figure which shows an example of the whole structure of the driver circuit which employ | adopted the saturation drive type differential pair circuit which concerns on this embodiment. It is a circuit diagram showing an example of a configuration of a non-saturated differential pair circuit and a control circuit thereof according to the present embodiment. It is a circuit diagram which shows the 2nd example of a structure of the unsaturated type differential pair circuit which concerns on this embodiment, and its control circuit. It is a circuit diagram which shows the structural example of the saturation type differential pair circuit which drives the unsaturated type differential pair circuit which concerns on this embodiment, and its control circuit. It is a figure which shows the structure of the drive circuit comprised combining the circuit of FIG. 11 and the circuit of FIG. It is a figure which shows the structure of the drive circuit comprised combining the circuit of FIG. 12 and the circuit of FIG. It is a figure which shows the structure of the drive circuit comprised combining the circuit of FIG. 11, the circuit of FIG. 12, and the circuit of FIG. It is a figure which shows the whole structure of the driver circuit in the case of driving by CMOS logic. It is a figure which shows the typical circuit example which drives a saturation type differential pair with a CMOS logic inverter. It is a figure which shows the conversion circuit which drives a differential pair by CMOS logic, suppressing waveform distortion. It is a figure which shows the other structural example of the conversion circuit which drives a differential pair by CMOS logic, suppressing waveform distortion.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Communication apparatus, 200 ... Transmission apparatus, 210 ... Transmission clock generation circuit, 220 ... Parallel / serial conversion circuit, 230, 230A-230E ... Driver circuit, 240 ... Differential Output circuit 241, 241A ... Unsaturated differential pair circuit, 242 ... Saturated differential pair circuit, 250, 250A, 260 ... Control circuit, 300 ... Receiver, 310 ... Receiver circuit, 320... Clock recovery circuit, 330... Serial / parallel conversion circuit.

Claims (10)

It has a driver circuit that sends serial data to the transmission line,
The driver circuit
A differential output circuit of a differential pair of transistors, and at least one non-saturated differential pair circuit that outputs a differential digital signal as a differential output signal by an on / off switching operation of the transistors of the differential pair Have
The non-saturated differential pair circuit is
A transmission device in which an amplitude of an input signal to a control terminal of the paired transistors is controlled to be driven in a non-saturated manner in which a current flows through an off-side transistor during the switching operation. The non-saturated differential pair circuit is
The transmission apparatus according to claim 1, wherein an input amplitude to the control terminal is controlled so that a ratio of currents flowing through the paired transistors does not exceed a constant value smaller than 10: 1. The driver circuit
Having a first control circuit;
The differential output circuit is
A current source connected to a connection point between the transistors forming the differential pair, the current of which can be controlled by a current control signal;
The first control circuit includes:
Including at least one replica circuit of the differential output circuit of the non-saturated differential pair circuit, and controlling the driving current of a current source of the differential output circuit according to an output signal of the replica circuit; The transmission device according to claim 1, wherein a control signal is supplied to the current source. The replica circuit is
Biased to output both differential voltage signals,
The first control circuit includes:
The transmission device according to claim 3, wherein the current control signal is output in accordance with a comparison result between an intermediate voltage of both signals of the differential voltage signal and an intermediate target value. The driver circuit
Saturated differential that is arranged on the input side of the non-saturated differential pair circuit, has a differential output circuit of a differential pair of transistors, and is saturated so that no current flows through the off-side transistor during the switching operation. A counter circuit,
A second control circuit for controlling the saturated differential pair circuit,
The saturated differential pair circuit is
A current source connected to a connection point between the transistors forming the differential pair, the current of which can be controlled by a current control signal;
A differential signal that is controlled so as to be driven in a non-saturated manner in which a current flows through an off-side transistor during the switching operation is supplied to the non-saturated differential pair circuit,
The second control circuit is
The current control includes at least one replica circuit of the differential output circuit of the saturated differential pair circuit, and controls a drive current of a current source of the differential output circuit according to an output signal of the replica circuit Supply a signal to the current source,
The replica circuit of the first control circuit is:
Biased to output both differential voltage signals,
The first control circuit includes:
Output the current control signal according to the comparison result between the intermediate voltage of both signals of the differential voltage signal and the intermediate target value,
Outputting a request signal to the second control circuit in accordance with a comparison result between one signal of the differential voltage signal and the required target value;
The second control circuit is
The transmission device according to claim 3, wherein the current control signal corresponding to a comparison result between one signal of the differential voltage signal of the replica circuit and the request signal by the first control circuit is output. The driver circuit
Saturated differential that is arranged on the input side of the non-saturated differential pair circuit, has a differential output circuit of a differential pair of transistors, and is saturated so that no current flows through the off-side transistor during the switching operation. A counter circuit,
A second control circuit for controlling the saturated differential pair circuit,
The saturated differential pair circuit is
A current source connected to a connection point between the transistors forming the differential pair, the current of which can be controlled by a current control signal;
A differential signal that is controlled so as to be driven in a non-saturated manner in which a current flows through an off-side transistor during the switching operation is supplied to the non-saturated differential pair circuit,
The second control circuit is
The current control includes at least one replica circuit of the differential output circuit of the saturated differential pair circuit, and controls a drive current of a current source of the differential output circuit according to an output signal of the replica circuit Supply a signal to the current source,
The first control circuit includes:
A first replica circuit biased to output both signals of the differential voltage signal;
A second replica circuit biased to output an added signal obtained by adding both signals of the differential voltage signal,
The first control circuit includes:
Outputting the current control signal according to the comparison result between the output addition signal of the second replica circuit and the addition target value;
A request signal is output to the second control circuit according to a comparison result between one signal of the first replica circuit and the required target value,
The second control circuit is
The transmission device according to claim 3, wherein the current control signal corresponding to a comparison result between one signal of the differential voltage signal of the replica circuit and the request signal by the first control circuit is output. A first unsaturated differential pair circuit disposed on the output side of the transmission line;
The first non-saturation type differential pair circuit is arranged on the input side, and the input signal amplitude of the first non-saturation type differential pair circuit is non-flowing through the off-side transistor during the switching operation. A second non-saturated differential pair circuit for supplying a differential signal controlled to be driven in saturation;
The second non-saturation type differential pair circuit is disposed on the input side, has a differential output circuit of a transistor differential pair, and is saturation driven so that no current flows in the off-side transistor during the switching operation. A saturated differential that supplies a differential signal that is controlled so as to be driven in a non-saturated manner in which a current flows through an off-side transistor during the switching operation to the second non-saturated differential pair circuit. A counter circuit,
A first control circuit for controlling a current of the first non-saturated differential pair circuit;
A second control circuit for controlling a current of the second non-saturated differential pair circuit;
A third control circuit for controlling the current of the saturation type differential pair circuit,
The first and second non-saturated differential pair circuits, and the saturated differential pair circuit,
A current source connected to a connection point between the transistors forming the differential pair, the current of which can be controlled by a current control signal;
The first control circuit includes:
Including at least one replica circuit of the differential output circuit of the first unsaturated differential pair circuit;
The replica circuit is
Biased to output both differential voltage signals,
The first control circuit includes:
Output the current control signal according to the comparison result between the intermediate voltage of both signals of the differential voltage signal and the intermediate target value,
Outputting a request signal to the second control circuit in accordance with a comparison result between one signal of the differential voltage signal and the required target value;
The second control circuit is
Including first and second replica circuits of the differential output circuit of the second non-saturated differential pair circuit;
The first replica circuit includes:
Biased to output both differential voltage signals,
The second replica circuit includes:
Biased to output an added signal that adds both signals of the differential voltage signal,
The second control circuit is
Outputting the current control signal according to the comparison result between the output addition signal of the second replica circuit and the addition target value;
A request signal is output to the third control circuit according to a comparison result between one signal of the first replica circuit and the required target value,
The third control circuit is
Including a replica circuit of the differential output circuit of the saturated differential pair circuit;
The transmitting apparatus according to claim 3, wherein the current control signal is output in accordance with a comparison result between one signal of the differential voltage signal of the replica circuit and the request signal by the second control circuit. The driver circuit
A saturated differential pair circuit that is arranged on the input side of the non-saturated differential pair circuit and is driven to be saturated so that no current flows in the off-side transistor during the switching operation;
A conversion circuit for converting to a differential pair drive signal in order to drive the saturated differential pair circuit from logic on the input side of the saturated differential pair circuit;
The saturated differential pair circuit is
A differential signal that is controlled so as to be driven in a non-saturated manner in which a current flows through an off-side transistor during the switching operation is supplied to the non-saturated differential pair circuit,
The conversion circuit is
The transmission device according to claim 1, further comprising an amplitude limiting circuit that limits an amplitude of a drive signal that drives the differential pair of the saturation type differential pair circuit. In order to drive the saturation type differential pair circuit from logic on the input side of the saturation type differential pair circuit, a conversion circuit for converting into a differential pair drive signal is provided.
The conversion circuit is
The transmission device according to claim 5, further comprising an amplitude limiting circuit that limits an amplitude of a drive signal that drives a differential pair of the saturation type differential pair circuit. A transmission line;
A transmitting device;
A receiver for receiving a differential digital signal sent from the transmitter to the transmission line, and
The transmitter is
It has a driver circuit that sends serial data to the transmission line,
The driver circuit
A differential output circuit of a differential pair of transistors, and at least one non-saturated differential pair circuit that outputs a differential digital signal as a differential output signal by an on / off switching operation of the transistors of the differential pair Have
The non-saturated differential pair circuit is
A communication device in which an amplitude of an input signal to a control terminal of the paired transistors is controlled so as to be driven in a non-saturated manner in which a current flows through an off-side transistor during the switching operation.

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