JP2010040815A - Vertical field effect transistor, and image display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical field effect transistor in which an element area that an element occupies on a base can be made small and an off current is small, and to provide an image display apparatus using the same. <P>SOLUTION: A source electrode 3 which is a little thicker than a drain electrode 7, an insulating layer 5 which is a little thinner than the drain electrode 7, and the drain electrode 7, are stacked on an insulating substrate 1. A lower insulating layer 2 which is as thick as the drain electrode 7, a gate electrode 4 which is as thick as the source electrode 3, and an upper insulating layer 6 which is as thick as the insulating layer 5 are stacked on one side of the stack across a gap portion. At the gap portion, a semiconductor layer 8 coming into contact with the side surface of the stack and a gate insulating film 6g are disposed to form the vertical field effect transistor. As the material of the semiconductor layer 8, zinc oxide is used, which has a "c" axis aligned in a film forming direction and shows excellent mobility in the "c"-axis direction. A transistor which is transparent to visible light is formed by using the zinc oxide doped with impurities as an electrode material. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a vertical field effect transistor using zinc oxide as a semiconductor material, and an image display device using the same.

  Thin film transistors (hereinafter abbreviated as TFTs) are widely used as pixel transistors in electronic circuits, particularly active matrix circuits of image display devices.

  FIG. 11A is a cross-sectional view showing a structure of a TFT configured as a horizontal field effect transistor (hereinafter sometimes abbreviated as FET), which is shown as a conventional example in Patent Document 1 described later. is there. In the lateral FET 100, a gate electrode 102 is provided on an insulating substrate 101, a semiconductor layer 104 is provided thereon via a gate insulating film 103, and a source electrode 105 and a drain electrode 106 are further provided thereon. Yes.

  During the operation of the lateral FET 100, a channel region is formed in the semiconductor layer 104 near the gate insulating film 103 between the source electrode 105 and the drain electrode 106 by the gate voltage applied to the gate electrode 102, and flows through the channel region. The current is controlled by the gate voltage. In this case, the channel length 107 is determined by the size of the gap (gap) between the source electrode 105 and the drain electrode 106, and is almost the same as the length of the gap (gap length). The minimum value of the channel length 107 is limited by a processing technique such as photolithography for patterning the electrodes 105 and 106, and is optically limited to about several tens of nm. In a TFT formed on a large-area display screen, the practical minimum channel length 107 is about several μm in consideration of productivity.

  In TFTs currently in practical use, amorphous silicon or polycrystalline silicon is generally used as a semiconductor material constituting the semiconductor layer. Further, TFTs using a metal oxide semiconductor material or an organic semiconductor material as a semiconductor material have been studied aiming at a TFT having characteristics different from that of a silicon-based TFT.

  On the other hand, Patent Document 1 proposes a TFT configured as a vertical field effect transistor. FIG. 11B is a cross-sectional view showing an example of the structure. In the vertical FET 200, a source electrode 202, a semiconductor layer 203, and a drain electrode 204 are sequentially stacked on an insulating substrate 201. A gate insulating film 205 is provided in contact with one side surface of the stacked body in a direction perpendicular to the substrate 201, and a gate electrode 206 is provided at a position facing the stacked body with the gate insulating film 205 interposed therebetween.

  When the vertical FET 200 is operated, a channel region is formed in the semiconductor layer 203 in the vicinity of the gate insulating film 205 by the gate voltage applied to the gate electrode 206, and the current flowing through the channel region is controlled by the gate voltage. In this case, the channel length 207 is determined by the distance between the source electrode 105 and the drain electrode 106, that is, the thickness of the semiconductor layer 203, and is approximately the same as the thickness of the semiconductor layer 203. Therefore, unlike the lateral FET 100, the channel length 207 can be controlled by the film formation speed, the film formation time, or the like when forming the semiconductor layer 203 regardless of the electrode patterning step. For this reason, in the vertical FET 200, an FET having a remarkably short channel length (for example, about 0.1 μm) as compared with the lateral FET 100 can be easily manufactured with high productivity.

  Patent Document 1 exemplifies organic semiconductor materials such as pentacene and metal oxide semiconductor materials such as zinc oxide as semiconductor materials constituting the semiconductor layer. Although these semiconductor materials have a smaller mobility than silicon, it is described that the transistor performance is remarkably improved by being configured as a vertical FET 200 having a short channel length, and can be used as a practical TFT. .

  FIG. 12 is an explanatory diagram (a) illustrating a configuration of a circuit for driving an image display device by an active matrix method using a TFT as a pixel transistor, and a perspective view (b) illustrating a configuration of a pixel. (For example, see Teruhiko Yamazaki, Hideaki Kawakami, Hiroo Hori, Color TFT LCD (revised version), Kyoritsu Shuppan (2005), p. 77). In this display device, scanning lines 41 for selecting pixels in each row and data lines 42 for sending data signals to the pixels in each column are provided in a grid pattern, one at each crossing position. Pixels 300 are arranged in a matrix.

  The pixel 300 includes a display element 310, a TFT 320, and the like. In the liquid crystal display device, the display element 310 includes a common electrode, a display electrode 311 facing the common electrode, and a liquid crystal layer sandwiched between both electrodes, and forms a capacitor. In terms of circuit, the display element 310 is incorporated in the active matrix circuit as a capacitor together with the auxiliary capacitor 330. The TFT 320 is normally a TFT configured as a lateral FET illustrated in FIG. 11A (hereinafter abbreviated as a lateral TFT). The gate electrode 322 of the TFT 320 is connected to the scanning line 41, the source electrode 325 is connected to the data line 42, and the drain electrode 326 is connected to the display electrode 311 of the display element 310.

  In the liquid crystal display device configured as described above, each pixel 300 is scanned by the scanning circuit 43 and the data driver circuit 44 as follows. That is, a selection pulse is output from the scanning circuit 43 to one scanning line 41 for a certain period of one cycle. As a result, in each pixel 300 in the row corresponding to the scanning line 41, the selection pulse is applied to the gate electrode 322 of the TFT 320, and the TFT 320 is turned on. Then, during this fixed period, the luminance signal is sequentially output from the data driver circuit 44 to each data line 42, and the capacitor constituting the display element 310 of each pixel 300 is charged or discharged to the luminance signal voltage. When the scanning of all the pixels in one row is completed, a selection pulse is output to the scanning line 41 in the next row, and each pixel in a new row is sequentially scanned in the same manner as described above. By repeating the above operation, all the pixels are selected once during one cycle. The luminance signal voltage stored in the capacitor constituting the display element 310 is held until this pixel is selected in the next cycle.

JP2003-110110A (pages 3, 4, and 6-9, FIGS. 1 and 7)

  As shown in FIG. 12B, one pixel 300 is usually divided into a display area 301 occupied by the display element 310 and a control area 302 occupied by the TFT 320. Since the control region 302 is a dark portion that does not transmit light for displaying an image, if the ratio of the area of the control region 302 to the total pixel area is large, the display luminance is lowered and the contrast of the liquid crystal display device is lowered. .

  As the number of pixels per unit area increases, the pixel area decreases in inverse proportion to the number of pixels. On the other hand, since the area of the control region 302 hardly changes, the decrease in contrast due to the presence of the control region 302 is high. Finer liquid crystal display devices are remarkable (see, for example, Teruhiko Yamazaki, Hideaki Kawakami, Hiroo Hori, Color TFT liquid crystal display (revised version), Kyoritsu Shuppan (2005), p.119).

  The liquid crystal display device has been described above as an example. However, as long as the image display device is driven by the active matrix method, the situation is the same even if the image display device uses another display element other than the liquid crystal element. The image display device referred to in this specification is a device that displays data such as characters, figures, and photographs as an image by controlling the amount of emitted light or reflected light for each of a number of display elements. As another display element other than the element, an electroluminescence element, a plasma display element, an electrochemical display element, and the like can be given. In an image display device using these display elements, the circuit configuration for driving the display elements with pixel transistors varies depending on the characteristics of the display elements. However, the pixel 300 shown in FIG. The basic configuration divided into the region 302 is the same.

  Therefore, in order to realize a high-definition and high-contrast image display device, it is desirable to make the area occupied by the control region 302 as small as possible. However, as described above, as long as the lateral TFT is used as a pixel transistor, it is difficult to reduce its size to several μm or less. Thus, it is conceivable to reduce the area of the control region 302 by using a TFT configured as a vertical FET (hereinafter abbreviated as a vertical TFT) as a pixel transistor. For example, in the vertical TFT 200 proposed in Patent Document 1 shown in FIG. 11B, since the source electrode 202 and the drain electrode 204 overlap each other, the element area occupied by the element on the substrate is It is considered that it will surely become smaller than the horizontal TFT.

  However, if the vertical TFT 200 proposed in Patent Document 1 is perfect, this is not the case. For example, in the vertical TFT 200, the channel region is formed only by the application of the gate voltage in the semiconductor layer 203 in the vicinity of the gate insulating film 205, but everything between the source electrode 202 and the drain electrode 204 is formed. The semiconductor layer 203 is disposed in this region. Thus, the semiconductor layer disposed in the region that does not contribute to the formation of the channel layer is not only ineffective, but also increases the off current, that is, the current that is not controlled by the gate voltage. As a result, in the liquid crystal display device shown in FIG. 12, the luminance signal voltage stored in the display element changes during one cycle, which causes the control performance of the vertical TFT 200 with respect to the display element to deteriorate.

  The present invention has been made in view of such a situation, and an object of the present invention is to reduce the element area occupied by the element on the substrate and to reduce the off-state current, and to reduce the off-current. And providing an image display apparatus using the same.

That is, the present invention
A source electrode and a drain electrode that are stacked with an intermediate layer interposed therebetween;
An insulating layer occupying at least part of the intermediate layer;
The c-axis, which is one of the crystal axes, is composed of a zinc oxide layer oriented in the stacking direction, and is in contact with at least a part of one side surface of the stack of the source electrode, the intermediate layer, and the drain electrode. And / or a semiconductor layer disposed so as to be in contact with and connect between the source electrode and the drain electrode by occupying a part of the intermediate layer, and
A gate insulating film disposed on the side and / or side of the stacked body so as to be in contact with the side of the semiconductor layer;
The present invention relates to a vertical field effect transistor comprising a gate electrode disposed on the side of the stacked body so as to face the semiconductor layer with the gate insulating film interposed therebetween.

  An image display in which a display element and the vertical field effect transistor according to any one of claims 1 to 10 are disposed in each pixel, and the display element is driven and controlled by the vertical field effect transistor. It relates to the device.

  According to the vertical field effect transistor of the present invention, since the source electrode and the drain electrode are stacked, the element area can be reliably reduced as compared with the horizontal field effect transistor. In addition, since at least part of the intermediate layer sandwiched between the source electrode and the drain electrode is occupied by an insulating layer, unlike the vertical field effect transistor proposed in Patent Document 1, The off current does not increase unnecessarily.

  The semiconductor layer is provided so as to occupy a part of the intermediate layer even if it is provided in contact with a part of at least one side surface of the stacked body of the source electrode, the intermediate layer, and the drain electrode. In any case, the channel length of the channel region formed in the semiconductor layer is the distance between the source electrode and the drain electrode, that is, the intermediate layer. It is determined by the thickness of the intermediate layer and is approximately the same as the thickness of the intermediate layer. Therefore, the channel length can be controlled by the film formation speed and the film formation time when forming the intermediate layer, regardless of the step of patterning the electrodes. Therefore, a field effect transistor having a dramatically shorter channel length than a lateral field effect transistor can be easily manufactured with high productivity.

  Furthermore, the zinc oxide used as the semiconductor material of the semiconductor layer is a material in which the c-axis, which is one of the crystal axes, is oriented with good crystallinity in the direction of the stack when forming by vapor deposition or sputtering. In addition, it is a material that exhibits excellent mobility in the c-axis direction. As a result, the direction in which the current flows in the channel region coincides with the c-axis direction of the zinc oxide layer, and the large mobility exhibited by the zinc oxide layer in the c-axis direction can be utilized to the maximum.

  As a result, a vertical field effect transistor that can be operated at a low voltage and at a high speed as much as a silicon lateral field effect transistor even when zinc oxide having a lower mobility than silicon is used as a semiconductor material is obtained. be able to.

  In the image display device of the present invention, the vertical field effect transistor is disposed in each pixel together with the display element, and the display element is driven and controlled by the vertical field effect transistor. Since the vertical field effect transistor has a smaller element area than the horizontal field effect transistor, the display field is improved by reducing the area occupied by the vertical field effect transistor in the pixel and increasing the area occupied by the display element. Even with high definition, an image display device with high contrast can be realized.

  In the present invention, it is preferable that the insulating layer occupies all of the intermediate layer, and the semiconductor layer is disposed so as to be in contact with at least one side surface of the stacked body.

  At this time, the stacked body is composed of the source electrode, the intermediate layer, and the drain electrode having the same or substantially the same thickness, and is the same as the drain electrode with a gap portion between one side of the stacked body. A lower insulating layer having a thickness, a gate electrode having the same thickness as the source electrode, and an upper insulating layer having the same thickness as the intermediate layer are stacked, and the gate insulating film and the semiconductor layer are formed in the gap portion. It is good to be arranged.

  In such a case, when the source electrode, the intermediate layer, and the drain electrode have the same thickness, the gate electrode is provided only at a position facing the intermediate layer in the stacking direction, It is not provided at a position facing the source electrode and the drain electrode. As a result, the parasitic capacitance between the gate electrode and the source or drain electrode is minimized. The source electrode, the intermediate layer, and the drain electrode have substantially the same thickness, the source electrode is slightly thicker than the drain electrode, and the intermediate layer is slightly thinner than the drain electrode. In addition, the gate electrode is slightly provided at a position facing the source electrode and the drain electrode in addition to a position facing the intermediate layer. As a result, the gate voltage acts reliably and effectively on all the regions of the semiconductor layer that connect the source electrode and the drain electrode.

  Or it is good to arrange | position so that the said semiconductor layer may occupy a part of said intermediate | middle layer, and the said insulating layer may occupy the remainder of the said intermediate | middle layer.

  In this case, the stacked body includes the source electrode, the intermediate layer, and the drain electrode having the same or substantially the same thickness, and is in contact with one side surface of the stacked body and has a lower portion having the same thickness as the drain electrode. An insulating layer, a layer made of the gate electrode and the gate insulating film having the same thickness as the source electrode, and an upper insulating layer having the same thickness as the intermediate layer may be disposed.

  In such a case, when the source electrode, the intermediate layer, and the drain electrode have the same thickness, the gate electrode is provided only at a position facing the semiconductor layer in the stacking direction, It is not provided at a position facing the source electrode and the drain electrode. As a result, the parasitic capacitance between the gate electrode and the source or drain electrode is minimized. The source electrode, the intermediate layer, and the drain electrode have substantially the same thickness, the source electrode is slightly thicker than the drain electrode, and the intermediate layer is slightly thinner than the drain electrode. In addition, the gate electrode is slightly provided at a position facing the source electrode and the drain electrode in addition to a position facing the semiconductor layer. As a result, the gate voltage acts reliably and effectively on all the regions of the semiconductor layer.

  Further, at least one of the source electrode, the insulating layer, the drain electrode, the gate insulating film, and the gate electrode, preferably all may be made of a material that transmits visible light.

  At this time, at least one of the source electrode, the drain electrode, and the gate electrode is preferably made of zinc oxide doped with impurities. In this case, since the electrode made of doped zinc oxide and the semiconductor layer can be formed using the same film forming apparatus, productivity and film quality are improved.

  Next, a preferred embodiment of the present invention will be described specifically and in detail with reference to the drawings.

Embodiment 1
In the first embodiment, examples of vertical field effect transistors described in claims 1 to 4 and 8 to 10 will be mainly described.

  FIG. 1A is a plan view and FIG. 1B is a cross-sectional view showing the structure of a vertical field effect transistor 10 according to the first embodiment. Sectional drawing (b) is sectional drawing in the position shown by the 1B-1B line | wire in the top view (a). In the vertical FET 10, a source electrode 3 having substantially the same thickness, an insulating layer 5 serving as an intermediate layer, and a drain electrode 7 are sequentially stacked on an insulating substrate 1. However, the source electrode 3 is slightly thicker than the drain electrode 7, and the insulating layer 5 is slightly thinner than the drain electrode 7.

  The lower insulating layer 2 having the same thickness as that of the drain electrode 7, the gate electrode 4 having the same thickness as that of the source electrode 3, and the insulating layer 5, with a slight gap therebetween on one side of the laminate. The upper insulating layer 6 having a thickness is stacked. In the gap portion, the semiconductor layer 8 provided in a direction perpendicular to the substrate 1 in contact with the side surface of the stacked body and the upper insulating layer 6 are provided continuously, and between the gate electrode 4 and the semiconductor layer 8. And a gate insulating film 6g interposed therebetween.

  As shown in FIG. 1B, for example, the drain electrode 7 and the lower insulating layer 2 have a thickness of 200 to 800 nm, the source electrode 3 and the gate electrode 4 have a thickness of 210 to 840 nm, and the insulating layer 5 and the upper insulating layer. The thickness of 6 is 190 to 760 nm. The width of the semiconductor layer 8 in the gap is 0.5 to 1.0 μm, and the width of the gate insulating film 6g is 1.0 to 2.0 μm.

  In this case, in the stacking direction, the gate electrode 4 is always located at a position facing the insulating layer 5, and is disposed so as to slightly protrude above and below the position facing the drain electrode 7 and the source electrode 3. Will be. The protruding thickness is 10 to 40 nm in the above example. As a result, the gate voltage acts reliably and effectively on all regions of the semiconductor layer 8 where the source electrode 3 and the drain electrode 7 are connected. In addition, unlike the vertical FET 200 proposed in Patent Document 1, only the gate electrode 4 is provided at a position facing the source electrode 3 and the drain electrode 7. The parasitic capacitance between the electrode 3 and the drain electrode 7 becomes extremely small, and the operation stability of the vertical FET 10 is improved.

  Unlike the above, when the source electrode 3, the insulating layer 5, and the drain electrode 7 have the same thickness, the gate electrode 4 is provided only at the position where the insulating layer 5 is disposed. It is not provided at a position facing the drain electrode 7. As a result, the parasitic capacitance between the gate electrode 4 and the source electrode 3 or the drain electrode 7 is minimized. However, in order for the gate voltage to effectively act on all regions of the semiconductor layer 8 where the source electrode 3 and the drain electrode 7 are connected, the thickness is strictly controlled during film formation. It will be necessary.

  In any case, what is important is only the positional relationship between the gate electrode 4, the source electrode 3, and the drain electrode 7 in the stacking direction. Therefore, it is sufficient that the above relationship is maintained between them, and the conditions regarding the thickness of the other layers are not absolutely necessary. If the conditions are satisfied, the film forming process is simplified. In addition, since the whole is almost flat at various stages of the film forming process, there is an advantage that the film forming process becomes easy.

  In the vertical FET 10, since the source electrode 3 and the drain electrode 7 are stacked, the element area can be surely reduced as compared with the horizontal field effect transistor. In addition, since the space between the source electrode 3 and the drain electrode 7 is occupied by the insulating layer 5, unlike the vertical FET 200 proposed in Patent Document 1, the off-current does not increase unnecessarily.

  During the operation of the vertical FET 10, a channel region is formed in the semiconductor layer 8 near the gate insulating film 6g by the gate voltage applied to the gate electrode 4, and the current flowing through the channel region is controlled by the gate voltage. In this case, the channel length 9 is determined by the distance between the source electrode 3 and the drain electrode 7, that is, the thickness of the insulating layer 5, and is almost the same as the thickness of the insulating layer 5. Therefore, unlike the lateral FET, the channel length 9 can be controlled by the film forming speed and the film forming time when forming the insulating layer 5 regardless of the patterning process of the electrodes. For this reason, in the vertical FET 10, it is possible to easily and efficiently produce a FET having a short channel length (for example, about 0.1 μm) as compared with the lateral FET.

  FIG. 2 is a perspective view showing a crystal lattice of zinc oxide which is a semiconductor material of the semiconductor layer 8. Zinc oxide crystals belong to the hexagonal system, and the c-axis, which is one of the crystal axes, is a direction that is orthogonal to a regular hexagonal plane, (0002) plane, or (0001) plane. When zinc oxide is deposited on a glass substrate or the like by a vapor deposition method or a sputtering method, a structure in which the c-axis is oriented in the stacking direction, that is, in the direction perpendicular to the substrate surface, has a property that crystallinity can be obtained. Moreover, zinc oxide has anisotropy in mobility and exhibits a large mobility in the c-axis direction. As a result, in the vertical FET 10, the direction in which the current flows in the channel region coincides with the c-axis direction of the zinc oxide layer, and the zinc oxide layer uses the large mobility shown in the c-axis direction to the maximum. Can do.

  As a result, it is possible to obtain a vertical FET 10 that can be operated at a low voltage and a high speed as much as a silicon lateral field effect transistor even when zinc oxide having a lower mobility than silicon is used as a semiconductor material. it can.

  As the insulating substrate 1, a glass substrate, a quartz substrate, or the like is preferably used when light transmission is required. A plastic substrate having a relatively high heat resistance, such as a polyimide resin, a polycycloolefin resin, or a polyethersulfone resin, as long as it has heat resistance to withstand heat treatment when forming each member constituting the vertical FET 10 Can also be used. However, when used in a liquid crystal display device, it is necessary that the material has no birefringence. In addition, since the entire substrate does not need to be insulative, a metal substrate such as stainless steel having an insulating layer made of silicon nitride, silicon oxide, or the like on the surface can be used when light transmission is not necessary. . When a plastic substrate or a thin metal substrate is used, an image display device having a flexible shape can be manufactured.

  The vertical FET 10 formed on the insulating substrate 1 may be used as an individual discrete component or a monolithic structure in which a number of transistors are integrated on the same substrate as in the case of using as a pixel transistor of an image display device. It may be used as an integrated circuit.

The materials of the source electrode 3, the drain electrode 7, and the gate electrode 4 are not particularly limited, but examples thereof include aluminum Al, gold Au, silver Ag, copper Cu, nickel Ni, tungsten W, and molybdenum Mo. A metal, an alloy containing these, or a combination of these layers can be used. As the alloy, silver, palladium, copper alloy such as APC sold by Furuya Metal can be used. The materials of the lower insulating layer 2, the insulating layer 5, the upper insulating layer 6, and the gate insulating film 6g are not particularly limited. For example, silicon nitride SiN, silicon oxide SiO ₂ , aluminum oxide Al ₂ O ₃ , And spin-on glass (SOG), or a laminated film in which these are laminated in combination. SOG is a material for forming a glass layer having a thickness of about 0.1 to 1 μm by spin coating.

  Further, in order to improve the light transmittance, at least one, preferably all of the source electrode 3, the drain electrode 7, the gate electrode 4, the insulating layer 5, the lower insulating layer 2, the upper insulating layer 6, and the gate insulating film 6g are used. It is good to consist of material which permeate | transmits visible light. Since the insulating material described above is a material that transmits visible light, if the material forming the source electrode 3, the drain electrode 7, and the gate electrode 4 is a material that transmits visible light, the material is transparent to visible light. An FET can be formed. A known material such as ITO (indium tin oxide) can be used as a visible light transmissive electrode material. However, if a material whose conductivity is improved by doping impurities into zinc oxide is used, the electrode and the semiconductor layer are formed. Since it can form using the same film-forming apparatus, productivity and film quality improve, and it is preferable. As the impurity doped into zinc oxide, aluminum Al, gallium Ga, indium In, and the like are suitable as n-type impurities.

  3 to 5 are a plan view and a cross-sectional view showing a flow of a manufacturing process of the vertical FET 10. The cross-sectional view is a cross-sectional view at the same position as FIG. Hereinafter, the manufacturing process will be described with emphasis on manufacturing the visible light transmissive vertical FET 10.

Step 1: Formation of Lower Insulating Layer 2 First, as shown in FIG. 3A, after an insulating material layer is formed on an insulating substrate 1 using a known method, photolithography and reactive ion etching are performed. The lower insulating layer 2 is formed by patterning by a fine processing method such as (RIE). As the insulating substrate 1, it is preferable to use a glass substrate, a quartz substrate, or the like as a substrate that has heat resistance and transmits visible light. The lower insulating layer 2 is preferably a laminated film in which a silicon nitride SiN layer and a silicon oxide SiO ₂ layer are laminated. The thickness of the lower insulating layer 2 is slightly thinner than the thickness of the source electrode 3 and the gate electrode 4 to be formed next, for example, about 200 nm.

At this time, the silicon nitride SiN layer and the silicon oxide SiO ₂ layer are preferably formed by a plasma CVD method (chemical vapor deposition method). As an insulating material layer other than these, an aluminum oxide Al ₂ O ₃ layer may be formed by a sputtering method, or a spin-on glass (SOG) layer may be formed by a spin coating method or the like.

Step 2: Formation of Transparent Conductive Film 11 Next, as shown in FIG. 3B, a transparent conductive film 11 to be patterned later on the source electrode 3 and the gate electrode 4 is formed. As a material for the transparent conductive film 11, it is preferable to use a zinc oxide-based conductive film such as zinc oxide (AZO) doped with impurities such as Al, or a transparent conductive film typified by ITO. The thickness of the transparent conductive film 11 is slightly thicker than the thickness of the lower insulating layer 2 200 nm and is about 210 nm. A difference of 10 nm between the thickness of the transparent conductive film 11 to be the source electrode 3 and the thickness of the lower insulating layer 2 is the size of the overlap between the gate electrode 4 and the source electrode 3 in the thickness direction. At this time, the AZO film is formed by a sputtering method in which sputtering is performed simultaneously with zinc oxide and aluminum oxide as targets. The ITO film is also formed by a sputtering method.

Step 3: Formation of Source Electrode 3 and Gate Electrode 4 Next, as shown in FIG. 3C, the transparent conductive film 11 is patterned by a fine processing method such as photolithography and RIE, so that the source electrode 3 and the gate electrode are formed. 4 is formed.

Step 4: Formation of Insulating Material Layer 12 Next, as shown in FIG. 3D, an insulating material layer 12 to be patterned later into the insulating layer 5, the upper insulating layer 6, and the gate insulating film 6g is formed. The insulating material layer 12 is preferably a laminated film in which a silicon nitride SiN layer and a silicon oxide SiO ₂ layer are laminated. The thickness of the insulating material layer 12 is slightly thinner than the thickness 210 nm of the gate electrode 4, for example, about 190 nm. The thickness of the insulating material layer 12 that will later become the insulating layer 5 determines the channel length 9 of the vertical TFT 10. Further, the difference between the thickness 210 nm of the gate electrode 4 and the thickness of the insulating material layer 12, that is, 20 nm is such that the gate electrode 4 protrudes up and down to a position facing the source electrode 3 and the drain electrode 7 in the thickness direction. Become. At this time, the silicon nitride SiN layer and the silicon oxide SiO ₂ layer are preferably formed by the plasma CVD method as described above.

Step 5: Formation of insulating layer 5, upper insulating layer 6, and gate insulating film 6g Next, as shown in FIG. 3E, the insulating material layer 12 is patterned by a microfabrication method such as photolithography and RIE. Then, the insulating layer 5, the upper insulating layer 6, the gate insulating film 6g, and the trench 13 are formed.

Step 6: Formation of Transparent Conductive Film 14 Next, as shown in FIG. 3 (f), a transparent conductive film 14 to be patterned on the drain electrode 7 later is formed. The material of the transparent conductive film 14 is preferably a zinc oxide-based conductive film such as zinc oxide (AZO) doped with impurities such as Al, or a transparent conductive film typified by ITO. The thickness of the transparent conductive film 11 is about 200 nm, which is the same as the thickness of the lower insulating layer 2. A difference of 10 nm between the thickness of the transparent conductive film 14 that will later become the drain electrode 7 and the thickness of the upper insulating layer 6 is the size of the overlap between the drain electrode 7 and the gate electrode 4 in the thickness direction. At this time, the AZO film or the ITO film is formed by a sputtering method.

Step 7: Formation of Drain Electrode 7 Next, as shown in FIG. 4G, the transparent conductive film 14 is patterned by a fine processing method such as photolithography and RIE to form the drain electrode 7 and the trench 15.

Step 8: Formation of Semiconductor Material Layer 16 Next, as shown in FIG. 4H, a semiconductor material layer 16 made of zinc oxide is formed. At this time, the semiconductor material layer 16 is formed by sputtering using zinc oxide as a target. The zinc oxide deposited on the insulating substrate 1 forms a polycrystalline layer grown with the c-axis oriented in the thickness direction. The c-axis is a direction in which zinc oxide exhibits a high mobility.

Step 9: Formation of Semiconductor Layer 8 Next, as shown in FIG. 4I, the semiconductor material layer 16 is patterned by a fine processing method such as photolithography and RIE to form the semiconductor layer 8.

  The above is the manufacturing process of the vertical TFT 10.

Embodiment 2
In the second embodiment, an example of a vertical field effect transistor described in claims 5 to 7 will be mainly described.

  FIG. 6 is a plan view (a) and a cross-sectional view (b) showing the structure of the vertical field effect transistor 20 based on the second embodiment. Sectional drawing (b) is sectional drawing in the position shown by the 6B-6B line | wire in the top view (a). In the vertical FET 20, a source electrode 23 having substantially the same thickness, an insulating layer 25 and a semiconductor layer 28 constituting the intermediate layer, and a drain electrode 29 are sequentially stacked on the insulating substrate 1. However, the source electrode 23 is slightly thicker than the drain electrode 29, and the insulating layer 25 and the semiconductor layer 28 are slightly thinner than the drain electrode 29. A lower insulating layer 22 having the same thickness as the drain electrode 29, a layer made of the gate electrode 24 and the gate insulating film 26 having the same thickness as the source electrode 23, a semiconductor layer 28, An upper insulating layer 27 having the same thickness is laminated.

  The vertical FET 20 is different from the vertical FET 10 in that the semiconductor layer 28 is arranged as a part of the intermediate layer, the arrangement of the gate insulating film 26 is changed accordingly, and the surface of other members Only the arrangement in the direction has changed slightly. Therefore, it goes without saying that the same effect can be obtained in common with the vertical FET 10.

  That is, in the stacking direction, the gate electrode 24 is always located at a position facing the semiconductor layer 28, and is arranged so as to slightly protrude above and below the position facing the drain electrode 29 and the source electrode 23. As a result, the gate voltage acts reliably and effectively on all regions of the semiconductor layer 28. In addition, unlike the vertical FET 200 proposed in Patent Document 1, only the gate electrode 24 is provided at a position facing the source electrode 23 and the drain electrode 29, so the gate electrode 24 and the source The parasitic capacitance between the electrode 23 and the drain electrode 29 becomes extremely small, and the operation stability of the vertical FET 20 is improved.

  Unlike the above, when the source electrode 23, the semiconductor layer 28, and the drain electrode 29 have the same thickness, the gate electrode 24 is provided only at the position where the semiconductor layer 28 is disposed. It is not provided at a position facing the drain electrode 29. As a result, the parasitic capacitance between the gate electrode 24 and the source electrode 23 or the drain electrode 29 is minimized. However, in order for the gate voltage to effectively act on all regions of the semiconductor layer 28, it is necessary to strictly control the thickness at the time of film formation.

  In any case, what is important is only the positional relationship between the gate electrode 24, the source electrode 23, and the drain electrode 29 in the stacking direction. Therefore, it is sufficient that the above relationship is maintained between them, and the conditions regarding the thickness of the other layers are not absolutely necessary. If the conditions are satisfied, the film forming process is simplified. In addition, since the whole is almost flat at various stages of the film forming process, there is an advantage that the film forming process becomes easy.

  In the vertical FET 20, since the source electrode 23 and the drain electrode 29 are stacked, the element area can be surely reduced as compared with the horizontal field effect transistor. In addition, the intermediate layer between the source electrode 23 and the drain electrode 29 is partly occupied by the semiconductor layer 24 having a necessary and sufficient size, and the remaining part is occupied by the insulating layer 25. Unlike the proposed vertical FET 200, the off current does not increase unnecessarily.

  When the vertical FET 20 operates, a channel region is formed in the semiconductor layer 28 in the vicinity of the gate insulating film 26 by the gate voltage applied to the gate electrode 24, and the current flowing through the channel region is controlled by the gate voltage. In this case, the channel length is the same as the distance between the source electrode 23 and the drain electrode 29, that is, the thickness of the semiconductor layer 28. Therefore, unlike the lateral FET, the channel length can be controlled by the film formation speed and the film formation time when forming the semiconductor layer 28 regardless of the patterning process of the electrodes. For this reason, in the vertical FET 20, it is possible to easily and easily produce a FET having a short channel length (for example, about 0.1 μm) as compared with the lateral FET.

  As described above, the crystal of zinc oxide, which is the material of the semiconductor layer 28, has a structure in which the c-axis is oriented in the stacking direction, that is, the direction perpendicular to the substrate surface, when deposited by a vapor deposition method or a sputtering method. It has properties that can be easily obtained. Therefore, in the vertical FET 20, the direction in which the current flows in the channel region coincides with the c-axis direction of the zinc oxide layer, and the large mobility indicated by the zinc oxide layer in the c-axis direction can be utilized to the maximum. it can.

  As a result, it is possible to obtain a vertical FET 20 that can be operated at a low voltage and at a high speed as much as a silicon-based lateral field effect transistor even when zinc oxide having a lower mobility than silicon is used as a semiconductor material. it can.

  Other constituent materials are the same as those of the vertical FET 10, and therefore, overlapping is avoided and description is omitted.

  7 to 9 are cross-sectional views showing the flow of the manufacturing process of the vertical FET 20. Hereinafter, the manufacturing process will be described with emphasis on manufacturing the visible light transmissive vertical FET 20.

Step 1: Formation of Lower Insulating Layer 22 First, as shown in FIG. 7A, after an insulating material layer is formed on the insulating substrate 1 using a known method, photolithography and reactive ion etching are performed. The lower insulating layer 22 is formed by patterning by a fine processing method such as (RIE). At this time, a glass substrate or the like is used as the insulating substrate 1, and a laminated film of a silicon nitride SiN layer and a silicon oxide SiO ₂ layer is formed as the lower insulating layer 22 by a plasma CVD method, and the thickness thereof is about 200 nm, for example. To do.

Step 2: Formation of Transparent Conductive Film 51 Next, as shown in FIG. 7B, a transparent conductive film 51 to be patterned later on the source electrode 23 and the gate electrode 24 is formed. At this time, as the transparent conductive film 51, a zinc oxide-based conductive film such as AZO or a transparent conductive film typified by ITO is formed by a sputtering method. The thickness of the transparent conductive film 51 is, for example, about 210 nm.

Step 3: Formation of Source Electrode 23 and Gate Electrode 24 Next, as shown in FIG. 7C, the transparent conductive film 51 is patterned by a fine processing method such as photolithography and RIE, so that the source electrode 23 and the gate electrode are formed. 24 is formed.

Step 4: Formation of Semiconductor Layer 28 Formation of Insulating Material Layer 12 Next, as shown in FIG. 8D, after forming a semiconductor material layer made of zinc oxide by sputtering, fine processing such as photolithography and RIE is performed. The semiconductor layer 28 is formed by patterning by a method. At this time, the thickness of the semiconductor layer 28 is slightly thinner than the thickness 210 nm of the gate electrode 24, for example, about 190 nm.

Step 5: Formation of Insulating Layer 25 and Gate Insulating Film 26 Next, as shown in FIG. 8E, an insulating material layer is formed and then patterned by a microfabrication method such as photolithography and RIE to form an insulating layer. 25 and the gate insulating film 26 are formed. At this time, the insulating material layer is formed by laminating a silicon nitride SiN layer and a silicon oxide SiO ₂ layer by plasma CVD.

Step 6: Formation of Upper Insulating Layer 27 Next, as shown in FIG. 8F, after forming an insulating material layer, patterning is performed by a fine processing method such as photolithography and RIE to form the upper insulating layer 27. To do. At this time, the insulating material layer is formed by laminating a silicon nitride SiN layer and a silicon oxide SiO ₂ layer by plasma CVD.

Step 7: Formation of Drain Electrode 29 Next, as shown in FIG. 9G, after forming a transparent conductive film, the drain electrode 29 is formed by patterning by a microfabrication method such as photolithography and RIE. At this time, a zinc oxide based conductive film such as AZO or a transparent conductive film typified by ITO is formed by a sputtering method as the transparent conductive film. The thickness of the drain electrode 29 is about 200 nm, for example.

  The above is the manufacturing process of the vertical TFT 20.

Embodiment 3
In the third embodiment, an example of the image display device described in claim 11 will be described. This image display apparatus is an active matrix type in which a display element and a vertical field effect transistor 10 or 20 that is a pixel transistor are arranged in each pixel, and the display element is driven and controlled by the vertical field effect transistor 10 or 20. An image display device. Since the configuration and the driving method are as described above with reference to FIG. 12, the description thereof is omitted here.

  FIG. 10 is a plan view showing a configuration of a pixel that is a feature of the image display device of the present embodiment. As described above, in the conventional image display device, since the lateral TFT is used as the pixel transistor, it is difficult to reduce the size of the control region 302 occupied by the pixel transistor or the like. As a result, the area occupied by the display region 301 in the pixel is limited, the display luminance is lowered, and the contrast is lowered (see FIG. 10C).

  In contrast, in the present embodiment, since the vertical FET 10 or 20 having a small element area is used as the pixel transistor, the control region 32 occupied by the pixel transistor or the like is reduced in size as shown in FIG. be able to. As a result, the area occupied by the display region 31 in the pixel is increased, the display luminance is increased, and the contrast is improved. Further, in the vertical field effect transistor 10 or 20, the scanning line 41 can also serve as most of the gate electrode 4 or 24. In this way, the control area 32 can be further miniaturized and the contrast can be further improved.

  In addition, as shown in FIG. 10B, a transparent transistor using a visible light transmissive electrode material or an insulating layer material is used as the pixel transistor, and the wiring in the pixel is also formed of a visible light transmissive conductive film. The control area 34 can be made transparent. In this case, since the control area 34 can be arranged over the display area 33, the display area 33 can be expanded over the entire pixel, so that the display brightness is further increased and the contrast is improved.

  As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to these examples at all, and can be suitably changed in the range which does not deviate from the main point of invention.

  The vertical field effect transistor of the present invention is used as a pixel transistor for various electronic circuits, particularly an active matrix circuit of a display, and can contribute to an increase in contrast of an image display device.

1A and 1B are a plan view and a cross-sectional view showing a structure of a vertical FET based on Embodiment 1 of the present invention. 2 is a perspective view showing a crystal lattice of zinc oxide, which is a semiconductor material of a vertical FET. FIG. It is sectional drawing which shows the flow of the manufacturing process of vertical FET similarly. It is sectional drawing which shows the flow of the manufacturing process of vertical FET similarly. It is sectional drawing which shows the flow of the manufacturing process of vertical FET similarly. It is the top view (a) and sectional drawing (b) which show the structure of the vertical FET based on Embodiment 2 of this invention. It is sectional drawing which shows the flow of the manufacturing process of vertical FET similarly. It is sectional drawing which shows the flow of the manufacturing process of vertical FET similarly. It is sectional drawing which shows the flow of the manufacturing process of vertical FET similarly. It is a top view which shows the structure of the pixel in the image display apparatus based on Embodiment 3 of this invention. It is sectional drawing which shows the structure of the horizontal field effect transistor shown by patent document 1, and a vertical field effect transistor. FIG. 2 is an explanatory diagram (a) illustrating a configuration of a circuit that drives an image display device by an active matrix method using a TFT as a pixel transistor, and a perspective view (b) illustrating a configuration of a pixel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Lower insulating layer, 3 ... Source electrode, 4 ... Gate electrode, 5 ... Insulating layer,
6 ... Upper insulating layer, 6g ... Gate insulating film, 7 ... Drain electrode, 8 ... Semiconductor layer,
9 ... channel length, 10 ... vertical FET, 11 ... transparent conductive film, 12 ... insulating material layer,
13 ... trench, 14 ... transparent conductive film, 15 ... trench, 16 ... semiconductor material layer,
20 ... Vertical FET, 22 ... Lower insulating layer, 23 ... Source electrode, 24 ... Gate electrode,
25 ... Insulating layer, 26 ... Gate insulating film, 27 ... Upper insulating layer, 28 ... Semiconductor layer,
29 ... Drain electrode, 31 ... Display area, 32 ... Control area (miniaturization), 33 ... Display area,
34 ... Control region (transparency), 41 ... Scan line, 42 ... Data line, 43 ... Scan circuit,
44 ... Data driver circuit, 51 ... Transparent conductive film, 100 ... Horizontal FET,
DESCRIPTION OF SYMBOLS 101 ... Insulating substrate, 102 ... Gate electrode, 103 ... Gate insulating film, 104 ... Semiconductor layer,
105 ... Source electrode, 106 ... Drain electrode, 107 ... Channel length,
200 ... Vertical FET, 201 ... Insulating substrate, 202 ... Source electrode, 203 ... Semiconductor layer,
204 ... Drain electrode, 205 ... Gate insulating film, 206 ... Gate electrode,
207 ... channel length, 300 ... pixel, 301 ... display area, 302 ... control area,
310: Display element (capacitor), 311: Display electrode, 320: TFT,
322 ... Gate electrode, 323 ... Gate insulating film, 324 ... Semiconductor layer, 325 ... Source electrode, 326 ... Drain electrode

Claims (11)

A source electrode and a drain electrode that are stacked with an intermediate layer interposed therebetween;
An insulating layer occupying at least part of the intermediate layer;
The c-axis, which is one of the crystal axes, is composed of a zinc oxide layer oriented in the stacking direction, and is in contact with at least a part of one side surface of the stack of the source electrode, the intermediate layer, and the drain electrode. And / or a semiconductor layer disposed so as to be in contact with and connect between the source electrode and the drain electrode by occupying a part of the intermediate layer, and
A gate insulating film disposed on the side and / or side of the stacked body so as to be in contact with the side of the semiconductor layer;
A vertical field effect transistor comprising a gate electrode disposed on a side of the stacked body so as to face the semiconductor layer with the gate insulating film interposed therebetween.   2. The vertical field effect transistor according to claim 1, wherein all of the intermediate layer is occupied by the insulating layer, and the semiconductor layer is disposed so as to be in contact with at least one side surface of the stacked body.   The stacked body is composed of the source electrode, the intermediate layer, and the drain electrode having the same or substantially the same thickness, and has the same thickness as the drain electrode with a gap portion sandwiched between one side of the stacked body. A lower insulating layer, a gate electrode having the same thickness as the source electrode, and an upper insulating layer having the same thickness as the intermediate layer are stacked, and the gate insulating film and the semiconductor layer are disposed in the gap portion. The vertical field effect transistor according to claim 2.   4. The vertical field effect transistor according to claim 3, wherein the source electrode is slightly thicker than the drain electrode, and the intermediate layer is slightly thinner than the drain electrode.   2. The vertical field effect transistor according to claim 1, wherein a part of the intermediate layer is occupied by the semiconductor layer, and a remaining part of the intermediate layer is occupied by the insulating layer.   The stacked body includes the source electrode, the intermediate layer, and the drain electrode having the same or substantially the same thickness, and is in contact with one side surface of the stacked body, and a lower insulating layer having the same thickness as the drain electrode. The vertical field effect according to claim 5, wherein a layer made of the gate electrode and the gate insulating film having the same thickness as the source electrode, and an upper insulating layer having the same thickness as the intermediate layer are disposed. Transistor.   The vertical field effect transistor according to claim 6, wherein the source electrode is slightly thicker than the drain electrode, and the intermediate layer is slightly thinner than the drain electrode.   2. The vertical field effect transistor according to claim 1, wherein at least one of the source electrode, the insulating layer, the drain electrode, the gate insulating film, and the gate electrode is made of a material that transmits visible light.   The vertical field effect transistor according to claim 8, wherein all of the source electrode, the insulating layer, the drain electrode, the gate insulating film, and the gate electrode are made of a material that transmits visible light.   The vertical field effect transistor according to claim 8 or 9, wherein at least one of the source electrode, the drain electrode, and the gate electrode is made of zinc oxide doped with impurities.   An image display device, wherein a display element and the vertical field effect transistor according to claim 1 are arranged in each pixel, and the display element is driven and controlled by the vertical field effect transistor.

Images