JP2010040572A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus with further enhanced sensitivity. <P>SOLUTION: A CMOS image sensor (imaging apparatus) includes a PD section 11 which generates electrons, an electron multiplication section 12a for multiplying the electrons generated by the PD section 11, a first light shield section 5a formed nearby a short side 11b extending in a transfer direction (X direction) of the electrons out of an outer edge portion of the PD section 11, and a PD global reset intersection 5 provided in the PD section 11 on the opposite side from the side where the electron multiplication section 12a is disposed. Further, the light shield section 5a is formed integrally with the PD global reset interconnection 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an imaging apparatus, and more particularly, to an imaging apparatus provided with a charge increasing unit for increasing charge.

  2. Description of the Related Art Conventionally, an imaging device (CMOS image sensor) including a charge increasing unit for multiplying (increasing) electrons (charges) is known (for example, see Patent Document 1).

  The above-mentioned Patent Document 1 has a photoelectric conversion function, a photodiode section for accumulating electrons generated by photoelectric conversion, and a multiplication for applying an electric field for multiplying (increasing) electrons by impact ionization. An imaging device (CMOS image sensor) including a gate electrode is disclosed.

JP 2007-235097 A

  In the imaging device described in Patent Document 1, it is possible to increase sensitivity by multiplying electrons by impact ionization. Therefore, the imaging device is used in an environment where the amount of light is poor, such as a surveillance camera or a night vision camera. However, further improvement in sensitivity is desired.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide an imaging apparatus capable of further improving the sensitivity.

  In order to achieve the above object, an imaging device according to one aspect of the present invention includes a charge generation unit that generates a charge, a charge increase unit that increases the charge generated by the charge generation unit, and a charge generation unit. Of the outer edge portion, a first light-shielding portion formed in the vicinity of a side extending along the charge transfer direction, and a signal wiring provided on a side opposite to the side where the charge increasing portion is disposed with respect to the charge generating portion The first light shielding portion is formed integrally with the signal wiring.

  With the above configuration, the sensitivity of the imaging apparatus can be further improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view showing the overall configuration of a CMOS image sensor according to a first embodiment of the present invention. FIG. 2 is a plan view of a pixel according to the first embodiment of the present invention. 3 to 7 are diagrams for explaining a configuration of a pixel according to the first embodiment of the present invention. In the first embodiment, a case where the present invention is applied to an active CMOS image sensor which is an example of an imaging apparatus will be described.

  As shown in FIG. 1, an imaging unit 2 including a plurality of pixels 1 arranged in a matrix (matrix), a row selection register 3, and a column selection register 4 are provided.

  In the CMOS image sensor, as shown in FIG. 2, the side opposite to the side where the electron multiplying portion 12a (see FIG. 3) is formed (the arrow X1 direction side) with respect to the photodiode portion (PD portion) 11. A photodiode global reset wiring (PD global reset wiring) 5 is provided. The photodiode section (PD section) 11 is an example of the “charge generation section” in the present invention, and the electron multiplier section 12a is an example of the “charge increase section” in the present invention. The PD global reset wiring 5 is an example of the “signal wiring” in the present invention. The PD unit 11 has a function of generating electrons in accordance with the amount of incident light and storing the generated electrons. The PD global reset wiring 5 has a function of resetting electrons accumulated in the PD unit 11 of the pixel 1.

  The PD global reset wiring 5 extends in the Y direction and is disposed along the long side 11 a of the PD unit 11 in the Y direction. Here, in the first embodiment, the PD global reset wiring 5 is formed integrally with the first light shielding portion 5a having a light shielding function. The PD global reset wiring 5 is composed of a first layer wiring.

  The first light shielding portion 5 a is formed in the vicinity of the short side 11 b extending along the electron transfer direction (X direction) in the outer edge portion of the PD portion 11. The first light-shielding portion 5a protrudes and extends in a direction (arrow X2 direction side) orthogonal to the direction in which the PD global reset wiring 5 extends (Y direction) and intersects the long side 11a of the PD portion 11 in the Y direction. It arrange | positions along the short side 11b of a direction. The short side 11b in the X direction of the PD unit 11 is an example of the “side” in the present invention. A pair of the first light shielding portions 5 a is provided so as to sandwich the PD unit 11 along the pair of X-side short sides 11 b of the PD unit 11. The first light-shielding portion 5a is provided along the entire length of the short side 11b of the PD portion 11, while the tip portion of the first light-shielding portion 5a is disposed adjacent to the arrow X2 direction side of the PD portion 11, which will be described later. The signal line 23 is arranged to face the signal line 23 with a predetermined interval.

Further, as shown in FIG. 3, the pixel 1 includes a pixel separation region for separating each pixel 1 from the surface of a p-type well region 13 formed on the surface of an n-type silicon substrate (not shown). 14 is formed. On the surface of the p-type well region 13 of each pixel 1 surrounded by the pixel isolation region 14, the PD portion 11 and the n-type impurity region are spaced apart from each other by a predetermined interval so as to sandwich the buried layer 12 made of an n ⁻ -type impurity region. An FD region 15 is formed.

  The PD unit 11 is formed so as to be adjacent to the pixel isolation region 14 and adjacent to the buried layer 12. The FD region 15 has a function of holding a signal charge due to transferred electrons and converting the signal charge into a voltage. The FD region 15 is formed so as to be adjacent to the buried layer 12.

A gate insulating film 16 made of a SiO ₂ film is formed on the upper surface of the buried layer 12. On the gate insulating film 16, a transfer gate electrode 17, a multiplication gate electrode 18, a transfer gate electrode 19, a storage gate electrode 20, and a read gate electrode 21 made of a polysilicon film are on the PD portion 11 side (in the direction of arrow X 1). Side) to the FD region 15 side (arrow X2 direction side). The buried layer 12 below the multiplication gate electrode 18 is provided with an electron multiplication section 12a. In the buried layer 12 below the storage gate electrode 20, an electron storage portion 12b is provided. In addition, the FD region 15 is electrically connected to a wiring 152 formed of a first layer wiring for taking out a signal through the contact portion 151.

  As shown in FIG. 4, a signal line 23 that supplies a clock signal Φ <b> 1 for voltage control is electrically connected to the transfer gate electrode 17 via a contact portion 22. The multiplication gate electrode 18, the transfer gate electrode 19, the storage gate electrode 20 and the read gate electrode 21 are respectively provided with contact portions 24-27, wiring layers 28-31 made of the first layer wiring, and contact portions 32-35. And signal lines 44 to 47 made of third layer wiring for supplying clock signals Φ2 to Φ5 for voltage control through pad layers 36 to 39 made of second layer wiring and contact portions 40 to 43, respectively. Electrically connected. The signal lines 44 to 47 are formed for each column of the pixels 1 arranged in a matrix.

  Above the signal lines 44 to 47, a power supply wiring 48 formed of a fourth layer wiring for supplying a power supply voltage (VDD) is formed. The power supply wiring 48 is provided with an opening 48 a in a region corresponding to the PD unit 11 in plan view, and serves as a light shielding film that covers regions other than the PD unit 11, the signal line 23, and the signal line 44. It has a function. Further, as shown in FIG. 5, the power supply wiring 48 is disposed so as to cover the gap between the signal line 23 and the first light shielding portion 5 a. A microlens 49 (see FIG. 3) is provided above a region corresponding to the opening 48 a of the power supply wiring 48, and the microlens 49 has a function of collecting light incident on the pixel 1. Yes. Thereby, even when part of the light incident through the microlens 49 (obliquely incident light (arrow A shown in FIG. 6)) is incident on the PD unit 11 in the Y direction, the PD global reset wiring 5 It is possible to prevent the first light shielding portion 5a from entering the PD portion 11 of the pixel 1 adjacent in the Y direction. As shown in FIG. 3, the PD global reset wiring 5 is lower than the power supply wiring 48 (fourth layer wiring), the signal lines 44 to 47 (third layer wiring), and the pad layers 36 to 39 (second layer wiring). The first-layer wiring. Thus, the incident light is shielded by using the lower first layer wiring to shield the light using the upper layer (third wiring) wiring layer like the signal line 23a shown in FIG. Is not obstructed by the upper wiring layer, it is possible to prevent the light condensing performance of the microlens 49 provided on the pixel 1 from being lowered.

  As shown in FIG. 7, each pixel 1 is provided with a reset gate transistor Tr1, an amplification transistor Tr2, a pixel selection transistor Tr3, and a global reset transistor Tr4. A reset gate line (not shown) is connected to the gate of the reset gate transistor Tr1, and a reset signal is supplied thereto. One of the source / drain of the reset gate transistor Tr1 is connected to the power supply wiring 48 (VDD line). The other of the source / drain of the reset gate transistor Tr1 is connected to the FD region 15. The other of the source / drain of the global reset transistor Tr4 is connected to the power supply wiring 48 (VDD line). The gate of the global reset transistor Tr4 is connected to the PD global reset wiring 5. One of the source / drain of the amplification transistor Tr2 is connected to one of the source / drain (reset drain RD) of the reset gate transistor Tr1, and the other of the source / drain of the amplification transistor Tr2 is connected to the source / drain of the pixel selection transistor Tr3. Connected to one of the drains. A row selection line 61 is connected to the gate of the pixel selection transistor Tr3, and an output line 62 is connected to the other of the source / drain of the pixel selection transistor Tr3. The row selection line 61 and the output line 62 are connected to the row selection register 3 and the column selection register 4 as shown in FIG.

  8 and 9 are potential diagrams for explaining the electron transfer operation and multiplication operation of the CMOS image sensor according to the first embodiment of the present invention.

  First, when light enters the PD unit 11, electrons are generated in the PD unit 11 by photoelectric conversion. In the period A shown in FIG. 8, the electrons generated by the PD unit 11 (about 3 V) are at a higher potential (about 25 V) via the buried layer 12 (about 4 V) under the transfer gate electrode 17. The data is transferred to the buried layer 12 (electron multiplier 12a) under the multiplier gate electrode 18. Thereafter, the electrons are transferred to the buried layer 12 below the transfer gate electrode 19 in the period B, and are transferred to the buried layer 12 (electron storage unit 12b) below the storage gate electrode 20 in the period C. In the period D, the multiplied electrons described later are transferred to the FD area 15 (about 5 V).

  In the electron multiplication operation, the operation in the period A to the period C in FIG. 8 is performed, and electrons are stored in the buried layer 12 (electron storage unit 12b) under the storage gate electrode 20, as shown in FIG. In the period E, the multiplication gate electrode 18 is turned on, and in the period F, the transfer gate electrode 19 is turned on. When the storage gate electrode 20 is turned off, the electrons stored in the electron storage unit 12b are multiplied by a higher potential via the buried layer 12 (about 4 V) under the transfer gate electrode 19. While being transferred to the buried layer 12 (electron multiplier 12a) under the gate electrode 18, it is multiplied by impact ionization. In the period G, the transfer gate electrode 19 is turned off to complete the multiplication operation. Note that the operations in the above-described periods A to C and the periods E to G are performed a plurality of times. Further, after the electron multiplication operation is completed, the electrons are accumulated in the buried layer 12 (electron multiplication unit 12a) under the multiplication gate electrode 18, and the electrons are read out to the FD region 15 for each row. Has been. Thereby, it is possible to perform a global shutter that simultaneously resets the electrons accumulated in all the pixels 1 and starts the accumulation of electrons.

  In the first embodiment, as described above, the first light-shielding portion 5a causes the oblique incident light incident on the PD unit 11 to be incident on the PD unit 11 and the buried layer 12 of the adjacent pixel 1 during the electron multiplication operation. Since leakage can be suppressed, the influence of light incident on the PD portion 11 and the buried layer 12 (electrons are newly generated and become noise even if the electron multiplication operation period is extended. ) Can be suppressed. As a result, electrons accumulated in a short imaging period can be multiplied over a long time, so that the shutter speed can be increased while increasing the sensitivity of the imaging apparatus. Further, by forming the first light shielding portion 5a integrally with the PD global reset wiring 5, it is not necessary to separately provide a light shielding film dedicated to light shielding, so that the pixel structure can be simplified.

(Second Embodiment)
FIG. 10 is a plan view of a pixel according to the second embodiment of the present invention. 11 and 12 are cross-sectional views of pixels according to the second embodiment of the present invention. In the CMOS image sensor of the second embodiment, unlike the first embodiment, the light shielding portions 5a and 5b formed integrally with the PD global reset wiring 5 are arranged so as to surround the periphery of the PD portion 11. An example will be described.

  That is, in the CMOS image sensor, as shown in FIGS. 10 and 11, the PD global reset wiring 5 connects the ends of the pair of first light-shielding portions 5a on the electron multiplier 12a side (arrow X2 direction side). In addition, the PD unit 11 integrally includes a second light shielding portion 5b provided along the side 11c on the electron multiplier 12a side (arrow X2 direction side).

  As shown in FIG. 12, the transfer gate electrode 17 adjacent to the electron multiplying portion 12a side of the PD portion 11 has a signal via a contact portion 171, a pad layer 172, a contact portion 173, a pad layer 174, and a contact portion 175. A wiring 176 (third layer wiring) is connected. The signal wiring 176 is arranged at a predetermined interval in the Y direction from the second light-shielding portion 5b of the PD global reset wiring 5 when viewed in plan.

  In addition, the other structure of 2nd Embodiment is the same as that of the said 1st Embodiment.

  In the second embodiment, as described above, by arranging the second light shielding portion 5b so as to surround the periphery of the PD unit 11, oblique incident light or the like incident on the PD unit 11 during the electron multiplication operation can be obtained. Since it is possible to further suppress leakage into the periphery (the PD portion 11 of the adjacent pixel 1, the buried layer 12, and the buried layer 12 of the own pixel 1), even if the period of the electron multiplication operation is extended, the PD portion 11 and the influence of light incident on the embedded layer 12 (new generation of electrons by photoelectric conversion and noise) can be further suppressed.

  The remaining effects of the second embodiment are similar to those of the aforementioned first embodiment.

(Third embodiment)
FIG. 13 is a plan view of a pixel according to the third embodiment of the present invention. 14 and 15 are cross-sectional views of pixels according to the third embodiment of the present invention. In the CMOS image sensor of the third embodiment, the case where the light shielding film 7 (first light shielding film) is formed above the first light shielding portion 5a of the PD global reset wiring 5 in the configuration of the first embodiment will be described. .

  That is, in the CMOS image sensor, as shown in FIGS. 13 to 15, the light shielding film formed of the second layer wiring provided to overlap the first light shielding portion 5 a of the PD global reset wiring 5 and the signal line 23. 7 is arranged. This light-shielding film 7 is viewed in plan view on the electron multiplier 12a side (arrow) from the end 52b on the electron multiplier 12a side (arrow X2 direction side) of the first light-shielding part 5a of the PD global reset wiring 5. (X2 direction side) and is arranged so as to cover the gap between the first light shielding portion 5a of the PD global reset wiring 5 and the signal line 23.

  As shown in FIG. 14, the first light shielding portion 5a of the PD global reset wiring 5 and the light shielding film 7 are connected by a plurality of contact portions 71 having a light shielding function. The contact portions 71 are arranged in a straight line at equal intervals in the X direction when seen in a plan view.

  The remaining configuration of the third embodiment is similar to that of the aforementioned first embodiment.

  In the third embodiment, as described above, the light shielding film disposed above the first light shielding portion 5a and the signal line 23 so as to overlap the first light shielding portion 5a and the signal line 23 in plan view. 7, the gap between the first light-shielding part 5 a and the signal line 23 can be covered with the light-shielding film 7, so that incident light leaks from the gap between the first light-shielding part 5 a and the signal line 23. Can be suppressed.

  In the third embodiment, as described above, the first light-shielding portion 5a of the PD global reset wiring 5 and the light-shielding film 7 are connected by the plurality of contact portions 71, whereby the first global PD wiring 5 resets. Since light incident between the light shielding portion 5a and the light shielding film 7 can be shielded by the plurality of contact portions 71, it is possible to further prevent light from leaking from the pixels 1 adjacent to the Y direction side.

  The remaining effects of the third embodiment are similar to those of the aforementioned first embodiment.

(Fourth embodiment)
FIG. 16 is a plan view of a pixel according to the fourth embodiment of the present invention. 17 and 18 are cross-sectional views of pixels according to the fourth embodiment of the present invention. In the CMOS image sensor of the fourth embodiment, in the configuration of the third embodiment, the first light shielding portion 5a and the light shielding film 7a (second light shielding film) of the PD global reset wiring 5 are projected to the PD portion 11 side. The case where it forms is demonstrated.

  That is, in the CMOS image sensor, as shown in FIG. 16, the first light-shielding portion 5 a of the PD global reset wiring 5 protrudes to the PD portion 11 side (Y direction) when seen in a plan view. It is formed so as to cover a portion including the side 11b (end portion of the PD portion 11). Similarly, the light-shielding film 7a disposed above the first light-shielding part 5a also projects in the PD part 11 side (Y direction) in a plan view so as to cover the part including the short side 11b of the PD part 11. Is formed. The width of the light shielding film 7a in the Y direction is formed to be substantially the same as the width of the first light shielding portion 5a in the Y direction. Specifically, as shown in FIG. 18, the light shielding film 7 a and the first light shielding portion 5 a are formed so as to protrude from the short side 11 b of the PD portion 11 to the PD portion 11 side by a length L1. The protruding portions of the first light-shielding portion 5a and the light-shielding film 7a are arranged so as not to reach the light condensing range 491 in which light incident through the microlens 49 on the PD unit 11 is condensed. Thereby, it is possible to suppress that the condensing efficiency of PD part 11 falls.

  As shown in FIG. 17, the light shielding film 7 a is disposed so as to cover a gap formed between the signal line 23 end 52 b of the first light shielding part 5 a and the signal line 23. A plurality of contact portions 71 and 72 having a light shielding function are arranged between the first light shielding portion 5a of the PD global reset wiring 5 and the light shielding film 7a. The contact parts 71 and 72 are arranged in a straight line at equal intervals in the X direction when seen in a plan view.

  The remaining configuration of the fourth embodiment is similar to that of the aforementioned third embodiment.

  In the fourth embodiment, as described above, the first light-shielding portion 5a protrudes toward the PD portion 11 so as to cover the short side (end portion) 11b of the PD portion 11, whereby the short side of the PD portion 11 is covered. Since the portion including 11b can be shielded from light, the first light shielding portion 5a projects to the PD portion 11 side, thereby further suppressing light from leaking into the adjacent pixel 1 from the portion near the short side 11b. Can do.

  The remaining effects of the fourth embodiment are similar to those of the aforementioned third embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the above-described embodiment, an active type CMOS image sensor that amplifies the signal charge in each pixel 1 is shown as an example of the imaging device. However, the present invention is not limited to this, and the signal charge in each pixel 1 is The present invention can also be applied to a passive CMOS image sensor that does not amplify.

  Further, in the above embodiment, five electrodes of the transfer gate electrode 17, the multiplication gate electrode 18, the transfer gate electrode 19, the storage gate electrode 20 and the read gate electrode 21 are provided between the PD unit 11 and the FD region 15. Although an example is shown, the present invention is not limited to this, and the electrode between the PD unit 11 and the FD region 15 may be constituted by three electrodes or four electrodes.

  In the above embodiment, the example in which the buried layer 12, the PD portion 11, and the FD region 15 are formed on the surface of the p-type well region 13 formed on the surface of the n-type silicon substrate (not shown) is shown. The present invention is not limited to this, and the buried layer 12, the PD portion 11, and the FD region 15 may be formed on the surface of the p-type silicon substrate.

  In the above embodiment, an example is shown in which electrons are used as signal charges. However, the present invention is not limited to this, and the signal charges can be positively detected by reversing the conductivity type of the substrate impurities and the polarity of the applied voltage. A hole may be used.

  Moreover, in the said embodiment, although the example using PD global reset wiring 5 was shown as an example of the signal wiring in which the light-shielding part of this invention was integrally formed, this invention is not limited to this, The said light-shielding part is As an integrally formed signal wiring, an output wiring of an adjacent pixel may be used.

1 is a plan view showing an overall configuration of a CMOS image sensor according to a first embodiment of the present invention. 1 is a plan view of a pixel according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line 200-200 in FIG. 2. FIG. 3 is a cross-sectional view taken along line 250-250 in FIG. 2. FIG. 3 is a cross-sectional view taken along line 300-300 in FIG. 2. FIG. 3 is a cross-sectional view taken along line 350-350 in FIG. 1 is a circuit diagram showing a circuit configuration of a CMOS image sensor according to a first embodiment of the present invention. FIG. 5 is a potential diagram for explaining an electron transfer operation of the CMOS image sensor according to the first embodiment of the present invention. FIG. 6 is a potential diagram for explaining an electron multiplication operation of the CMOS image sensor according to the first embodiment of the present invention. It is a top view of the pixel by a 2nd embodiment of the present invention. It is sectional drawing along the 400-400 line of FIG. It is sectional drawing along the 450-450 line | wire of FIG. It is a top view of the pixel by a 3rd embodiment of the present invention. It is sectional drawing along the 500-500 line | wire of FIG. FIG. 15 is a cross-sectional view taken along line 550-550 in FIG. 13. It is a top view of the pixel by a 4th embodiment of the present invention. It is sectional drawing along the 600-600 line of FIG. It is sectional drawing along the 650-650 line | wire of FIG.

Explanation of symbols

5 PD global reset wiring (signal wiring)
5a 1st light shielding part 5b 2nd light shielding part 11 Photodiode part (PD part) (charge generation part)
11b Short side (side)
12a Electron multiplying part (charge increasing part)
71, 72 Contact part

Claims (3)

A charge generation unit for generating charge;
A charge increasing portion for increasing the charge generated by the charge generating portion;
A first light-shielding portion formed in the vicinity of a side extending along the charge transfer direction in the outer edge portion of the charge generation portion;
A signal wiring provided on the opposite side of the charge generation unit from the side on which the charge increase unit is disposed;
The imaging device, wherein the first light shielding portion is formed integrally with the signal wiring.   The imaging device according to claim 1, further comprising a second light-shielding portion disposed so as to surround a periphery of the charge generation unit together with the signal wiring and the first light-shielding portion.   3. The imaging device according to claim 1, wherein the first light shielding portion protrudes toward the charge generation unit so as to cover an end of the charge generation unit.

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