JP2009522706A5

JP2009522706A5 -

Info

Publication number: JP2009522706A5
Application number: JP2008548823A
Authority: JP
Filing date: 2006-12-21
Publication date: 2010-02-12
Anticipated expiration: 2026-12-21

Claims

An operation method of a memory cell array connected along a word line and a bit line,
Selecting a multi-state memory cell for sensing operation;
Discharging a sense node of the selected memory cell to ground through a bit line to which the selected memory cell is connected;
After discharging the sense node of the selected memory cell,
Applying a first voltage level to a source of the selected memory cell;
Applying a second voltage level to the word line to which the selected memory cell is connected, wherein the first and second voltage levels are independent of the data content stored in the selected cell;
Applying a corresponding voltage to the bit line to which the selected memory cell is connected after applying the first and second voltage levels;
In order to determine whether the data content of the selected memory cell corresponds to one of the first subsets of the multi-state, a voltage applied to a sense node of the selected memory cell and a first plurality of reference values Performing a first sensing operation comprising comparing, and
After the step of performing the first sensing operation, applying a third voltage level different from the second voltage level to the word line to which the selected memory cell is connected;
After applying the third voltage level, causing a corresponding voltage to be applied to the bit line to which the selected memory cell is connected;
In order to determine whether the data content of the selected memory cell corresponds to one of the second subset of the multi-states, a voltage across a sense node of the selected memory cell and a second plurality of reference values are Performing a second sensing operation comprising comparing, wherein the first and second subsets of the multi-states are different, each including a plurality of states;
Including methods.

The method of claim 1, wherein
The method wherein the first and second plurality of reference values are the same.

The method of claim 1, wherein
The method wherein the first and second subsets of the multi-state do not overlap.

The method of claim 1, wherein
The combination of the first and second subsets of the multi-state includes fewer than all of the multi-states.

The method of claim 1, wherein,
Discharging the sense node of the selected memory cell to ground through the bit line to which the selected memory cell is connected after the first sensing operation and before the second sensing operation;

The method of claim 1, wherein
A method in which the sense node corresponds to the bit line to which the selected memory cell is connected.

The method of claim 1, wherein
The method, wherein the sense node is an intermediate node of the bit line to which the selected memory cell is connected.

The method of claim 1, wherein
The method wherein the selected memory cell is one of a plurality of memory cells selected for simultaneous sensing operation.

The method of claim 8, wherein
The method wherein the plurality of memory cells selected for simultaneous sensing operation are formed along the word line.

The method of claim 1, wherein
The method wherein the array has a NAND configuration.

The method of claim 10, wherein:
The method wherein the array has a full bit line configuration.

The method of claim 1, wherein
A method in which the sensing operation is performed during a verify phase of a write operation.

The method of claim 1, wherein
The method wherein the sensing operation is performed during a read operation.

The method of claim 1, wherein
The voltage applied along the bit line in the first and second sensing operations is successively compared with at least some of the first and second reference values, respectively.

The method of claim 1, wherein
A method in which voltages applied along the bit line in the first and second sensing operations are respectively compared simultaneously with at least some of the first and second reference values.

A method of simultaneously determining, from a memory array, the states of a plurality of multi-state memory cells connected along a common word line, having a source connected to a common source line, and formed along separate bit lines. And
Discharging the memory cell to ground through the corresponding bit line;
Subsequently, applying a first voltage level to the common source line;
Subsequently, applying a second voltage level to the word line;
In response to applying the second voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of the first subset of the multi-states;
Subsequently, applying a third voltage level different from the second voltage level to the word line;
Responsive to applying the third voltage level to the word line to determine whether the data content of each of the memory cells corresponds to one of the multi-state second subset. The first and second subsets of the multi-state are different, each including a plurality of states;
Including methods.

The method of claim 16, wherein
Determining whether the data content of each of the memory cells corresponds to one of the multi-state first or second subsets;
Applying a voltage to each of the corresponding bit lines;
Comparing the voltage applied along the bit line with a plurality of reference values to determine the data content of the memory cell;
Including methods.

The method of claim 16, wherein
The method wherein the first and second subsets of the multi-state do not overlap.

The method of claim 16, wherein
The combination of the first and second subsets of the multi-state includes fewer than all of the multi-states.

The method of claim 16, wherein
The method wherein the array has a NAND configuration.

The method of claim 20, wherein
The method wherein the array has a full bit line configuration.

The method of claim 16, wherein
Determining whether each data content of said memory cell corresponds to one of a first subset and determining whether each data content of said memory cell corresponds to one of a second subset Is performed during the verify phase of the write operation.

The method of claim 16, wherein
Determining whether each data content of said memory cell corresponds to one of a first subset and determining whether each data content of said memory cell corresponds to one of a second subset Are performed during a read operation.

A method of simultaneously writing multi-state data from a memory array to a plurality of multi-state memory cells connected along a common word line and having a source connected to a common source line and formed along separate bit lines. There,
Applying a common programming pulse to the word line while controlling the amount of charge injected into each of the memory cells for each bit line based on a corresponding target state of each of the memory cells;
The next step is to execute the verify operation,
Discharging the memory cell to ground through the corresponding bit line;
Subsequently applying a first voltage level to the common source line; and
Subsequently, applying a second voltage level to the word line;
In response to applying the second voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of the first subset of the multi-states;
Subsequently, applying a third voltage level different from the second voltage level to the word line;
Responsive to applying the third voltage level to the word line to determine whether the data content of each of the memory cells corresponds to one of the multi-state second subset. The first and second subsets of the multi-state are different, each including a plurality of states;
Including methods.

25. The method of claim 24, wherein
Determining whether the data content of each of the memory cells corresponds to one of the multi-state first or second subsets;
Applying a voltage to each of the corresponding bit lines;
Comparing the voltage applied along the bit line with a plurality of reference values to determine the data content of the memory cell;
Including methods.

25. The method of claim 24, wherein
Controlling the amount of charge injected into each of the memory cells of the bit line for each bit line based on the corresponding target state of each of the memory cells may result in the corresponding target state of each of the memory cells Based on, setting a voltage level of the bit line for each bit line.

25. The method of claim 24, wherein
Controlling the amount of charge injected into each of the memory cells of the bit line for each bit line based on the corresponding target state of each of the memory cells may result in the corresponding target state of each of the memory cells And setting a current limit value of the bit line for each bit line based on the method.

Non-volatile memory,
An array of multi-state non-volatile memory cells connected along word lines and bit lines;
A row control circuit including a word line driving circuit capable of applying a plurality of word line voltage levels by being connectable to the word line to which a plurality of selected memory cells from the array are connected;
A source control circuit connectable to a common source line of the selected memory cell for applying a first voltage level greater than ground ;
A column control circuit and a data input / output circuit connectable to the bit line of the selected memory cell, including a sensing circuit connectable to a corresponding one or more sense nodes of the one or more selected memory cells;
The memory cell is discharged to ground through the corresponding bit line, and then the first voltage level is continuously applied to the common source line, and then the first voltage level is continuously applied to the common source line. while, the first word line voltage level of the word line voltage level is applied to the word line, in response to applying said first word line voltage level to the word line, each of said selected memory cell The first word line voltage level while continuing to apply the first voltage level to the common source line. response to applying a second wordline voltage level different said word line voltage level to the word line, applying a second wordline voltage level to the word line and Determining whether the data content of each of the selected memory cells corresponds to one of the second subset of the multi-states, wherein the first and second subsets of the multi-states are different, A non-volatile memory in which, in a process including a plurality of states, the memory can determine the state of the selected memory cell.

The non-volatile memory of claim 28.
Determining whether the data content of each of the selected memory cells corresponds to one of the multi-state first or second subset;
A voltage is applied to each of the corresponding bit lines;
A non-volatile memory that compares a voltage applied along the bit line with a plurality of reference values to determine the data content of the memory cell.

The non-volatile memory of claim 28.
A non-volatile memory in which the multi-state first and second subsets do not overlap.

The non-volatile memory of claim 28.
A non-volatile memory in which a combination of the first and second subsets of the multi-state includes fewer than all of the multi-states.

The non-volatile memory of claim 28.
A non-volatile memory in which the array has a NAND configuration.

The nonvolatile memory of claim 32,
A non-volatile memory in which the array has a full bit line configuration.

The non-volatile memory of claim 28.
Determining whether each data content of the selected memory cell corresponds to one of a first subset and determining whether each data content of the selected memory cell corresponds to one of a second subset The non-volatile memory being performed during the verify phase of the write operation.

The non-volatile memory of claim 28.
Determining whether each data content of the selected memory cell corresponds to one of a first subset and determining whether each data content of the selected memory cell corresponds to one of a second subset Doing a non-volatile memory that is executed during a read operation.