JP2009302151A - Production process of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a production process of a semiconductor device that controls deterioration of yield related to formation of a via hole and furthermore, improves throughput. <P>SOLUTION: A GaN layer 2 and an n-type AlGaN layer 3 are formed on an insulating substrate 1, and then, a gate electrode 4g, a source electrode 4s, and a drain electrode 4d are formed. Next, an opening 6 is so formed on the source electrode 4s, the GaN layer 2, and the n-type AlGaN layer 3 as to reach at least the front surface of the insulating substrate 1. After that, an Ni layer 8 is formed inside the opening 6. Subsequently, dry etching for treating the Ni layer 8 as an etching stopper is done at high speed, thereby forming a via hole 1s on the insulating substrate 1 that goes from its back surface side to the Ni layer 8 while depositing a compound film 19 at its sidewall by cooling and the like. Then, via wiring 16 is formed from within the via hole 1s to the back side of the insulating substrate 1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device suitable for a GaN-based (gallium nitride) high electron mobility transistor (HEMT).

  In recent years, GaN-based semiconductor devices such as GaN-based HEMTs are expected to be applied as high breakdown voltage / high-speed devices due to their physical characteristics. In order to improve the high-frequency characteristics of the GaN-based semiconductor device, a via wiring structure for reducing source inductance and radiating heat is necessary.

  Here, a conventional method for manufacturing a GaN-based HEMT will be described. 9A to 9X are cross-sectional views showing a conventional GaN-based HEMT manufacturing method in the order of steps.

  First, as shown in FIG. 9A, a GaN layer 102 and an n-type AlGaN layer 103 are formed in this order on the surface of an insulating substrate 101 made of silicon carbide (SiC). The thickness of the insulating substrate 101 is about 350 μm, and the total thickness of the GaN layer 102 and the n-type AlGaN layer 103 is about 2 μm. Next, a source electrode 104s, a gate electrode 104g, and a drain electrode 104d are selectively formed on the n-type AlGaN layer 103. Next, a SiN layer 105 is formed on the n-type AlGaN layer 103 so as to cover the source electrode 104s, the gate electrode 104g, and the drain electrode 104d.

  9B, a resist pattern 151 having an opening 151s corresponding to the source electrode 104s and an opening 151d corresponding to the drain electrode 104d is formed on the SiN layer 105. The thickness of the resist pattern 151 is about 1 μm.

  Subsequently, as shown in FIG. 9C, by patterning the SiN layer 105 using the resist pattern 151 as a mask, a contact hole 105s that matches the opening 151s is formed on the source electrode 104s, and a contact that matches the opening 151d. A hole 105d is formed on the drain electrode 104d.

  Next, the resist pattern 151 is removed, and as shown in FIG. 9D, a resist pattern 152 having an opening 152s smaller than the opening 151s and corresponding to the source electrode 104s is newly formed on the SiN layer 105 and the source electrode 104s. To form. The thickness of the resist pattern 152 is about 1 μm. The diameter of the opening 152s is about 150 μm.

  Next, as shown in FIG. 9E, the opening 106 is formed by performing ion milling of the source electrode 104s using the resist pattern 152 as a mask.

  Thereafter, the resist pattern 152 is removed, and as shown in FIG. 9F, a Ti layer and Ni layer stack or a Ti layer and Cu layer stack is formed as a seed layer 107 on the entire surface of the insulating substrate 101. Form.

  Subsequently, as shown in FIG. 9G, a resist pattern 153 having an opening 153 s corresponding to the outer edge of the source electrode 104 s is formed on the seed layer 107. The thickness of the resist pattern 153 is about 3 μm. Next, an Ni layer 108 having a thickness of about 1.2 μm is formed on the seed layer 107 in the opening 153s by electroplating.

  Next, as shown in FIG. 9H, the resist pattern 153 is removed.

  Thereafter, as shown in FIG. 9I, the seed layer 107 exposed from the Ni layer 108 is removed by performing ion milling. At this time, the Ni layer 108 is also slightly scraped, and the thickness becomes about 1 μm.

  Subsequently, as shown in FIG. 9J, a stacked body of a Ti layer, a Pt layer, and an Au layer is formed as a seed layer 109 on the entire surface on the surface side of the insulating substrate 101.

  Next, as shown in FIG. 9K, a resist pattern 154 having an opening corresponding to the outer edge of the source electrode 104s and an opening corresponding to the outer edge of the drain electrode 104d is formed on the seed layer 109. The thickness of the resist pattern 154 is about 1 μm. Next, an Au layer 110 having a thickness of about 1 μm is formed on the seed layer 109 in each opening of the resist pattern 154 by electroplating.

  Thereafter, as shown in FIG. 9L, the resist pattern 154 is removed.

  Subsequently, as shown in FIG. 9M, the seed layer 109 exposed from the Au layer 110 is removed by performing ion milling. At this time, the Au layer 110 is also slightly scraped, and the thickness becomes about 0.6 μm.

  Next, as shown in FIG. 9N, a surface protective layer 111 is formed on the entire surface of the insulating substrate 101 and the front and back of the insulating substrate 101 are reversed. Next, the back surface of the insulating substrate 101 is polished, so that the thickness of the insulating substrate 101 is about 150 μm.

  Thereafter, as shown in FIG. 9O, a Ti layer and Ni layer laminate or a Ti layer and Cu layer laminate is formed as a seed layer 112 on the back surface of the insulating substrate 101. Subsequently, a resist pattern 155 that covers a portion corresponding to the source electrode 104 s is formed on the seed layer 112. The resist pattern 155 has a thickness of about 3 μm and a diameter of about 100 μm. Next, a Ni layer 113 having a thickness of about 3.2 μm is formed on the seed layer 112 in a region excluding the resist pattern 155 by electroplating.

  Next, as shown in FIG. 9P, the resist pattern 155 is removed. Thereafter, the seed layer 112 exposed from the Ni layer 113 is removed by performing ion milling. At this time, the Ni layer 113 is also slightly shaved, and the thickness becomes about 3 μm.

Thereafter, as shown in FIG. 9Q, via holes 101s are formed by performing dry etching of the insulating substrate 101 using the Ni layer 113 as a mask. In this dry etching, a mixed gas of sulfur hexafluoride (SF ₆ ) gas and oxygen (O ₂ ) gas is used.

Subsequently, as shown in FIG. 9R, the via hole 101 s reaches the seed layer 107 by performing dry etching of the GaN layer 102 and the n-type AlGaN layer 103 using the Ni layer 113 as a mask. In this dry etching, chlorine (Cl ₂ ) gas is used. In this dry etching, the Ni layer 108 and the seed layer 107 function as an etching stopper.

  Next, as shown in FIG. 9S, a resist layer 156 is formed in the via hole 101 s and on the Ni layer 113.

  Next, as shown in FIG. 9T, the resist layer 156 is exposed and developed to leave the resist layer 156 only in the via hole 101s.

  Thereafter, as shown in FIG. 9U, the Ni layer 113 and the seed layer 112 are removed by performing ion milling or immersing in a mixed solution of sulfuric acid and hydrogen peroxide (sulfuric acid / hydrogen peroxide).

  Subsequently, as shown in FIG. 9V, the resist layer 156 is removed. Next, the seed layer 107 exposed from the via hole 101s is removed by performing ion milling. Next, a stacked body of a Ti layer, a Pt layer, and an Au layer is formed as a seed layer 114 on the entire back surface of the insulating substrate 101.

  Next, as shown in FIG. 9W, an Au layer 115 having a thickness of about 10 μm is formed on the seed layer 114 by electroplating.

  Then, as shown in FIG. 9X, the front and back of the insulating substrate 101 are reversed, and the surface protective layer 111 is removed.

  Conventionally, a GaN-based HEMT has been manufactured by such a method.

  However, in this conventional manufacturing method, it is difficult to form and stretch the via hole 101s.

  For example, the dry etching rate of the insulating substrate 101 made of SiC is easily affected by the diameter of the via hole 101s and has a large in-plane distribution. For this reason, conventionally, over-etching has been performed for the purpose of reliably reaching the via hole 101s to the GaN layer 102 and obtaining a high yield. However, under normal dry etching conditions for the insulating substrate 101, the etching selectivity between SiC and Ni is 100 or more, whereas the etching selectivity between SiC, GaN and AlGaN is as low as about 20-30. The total thickness of the GaN layer 102 and the n-type AlGaN layer 103 is as thin as about 2 μm. Therefore, as a result of over-etching, variation in the remaining ratio of the GaN layer 102 and the n-type AlGaN layer 103 is large. For example, when the variation (in-plane distribution) of the dry etching rate of the insulating substrate 101 is about ± 5%, 33% overetching (50 μm SiC etching) is performed to form the via hole 101s having a depth of 150 μm. Equivalent to the amount). Further, it is assumed that the selection ratio of SiC to GaN and AlGaN is 25. In this case, 0.4 μm of the GaN layer 102 remains in a certain portion, but there is a portion where the GaN layer 102 and the n-type AlGaN layer 103 disappear completely. If dry etching is performed on the remaining GaN layer 102 and n-type AlGaN layer 103 from this state, the seed layer 107 and the Ni layer 108 cannot function as an etching stopper in a portion where they have already completely disappeared. These are also etched. Since the Ni layer 108 has a thickness of about 1 μm, the Ni layer 108 may disappear.

  If the Ni layer 108 is formed thick, it is possible to avoid the disappearance, but in this case, another problem occurs. That is, after forming the Ni layer 108, it is necessary to form the resist pattern 154 for forming the Au layer 110 (FIG. 9K). If the thickness of the Ni layer 108 exceeds 1 μm, for example, about 3 μm. If the resist pattern 154 is not formed thick, the thickness becomes non-uniform and the pattern is likely to be distorted. That is, the pattern opening accuracy tends to be low. On the other hand, if the resist pattern 154 is formed too thick to avoid this, it becomes difficult to form the resist pattern 154 with high resolution. For this reason, in the conventional manufacturing method, the thickness of the Ni layer 108 is set to about 1 μm.

Further, in the dry etching of the insulating substrate 101 (FIG. 9Q) and the dry etching of the GaN layer 102 and the n-type AlGaN layer 103 (FIG. 9R), since the Ni layer 113 is used as a metal mask, it is performed in the same chamber. In this case, however, SF ₆ used in dry etching of the insulating substrate 101 remains, and the etching rate of the GaN layer 102 and the n-type AlGaN layer 103 becomes unstable due to this influence. FIG. 10 is a graph showing the results of an ICP dry etching experiment conducted by the inventor for confirmation. In FIG. 10, ● represents the etching rate when only Cl _{2 as an} etching gas is supplied at a flow rate of 30 sccm, ◆ represents the etching rate when N ₂ is mixed in addition to 30 sccm of Cl ₂ , Shows the etching rate when SF ₆ is mixed in addition to 30 sccm of Cl ₂ . In any measurement, the antenna power was 150 W and the bias power was 10 W. As shown in FIG. 10, when only Cl ₂ was supplied, an etching rate of 54 nm / min was obtained, and even when diluted by mixing with N ₂ , an etching rate of about 40 nm / min was obtained. On the other hand, when SF ₆ was mixed, even if the flow rate was only 1 sccm, it was remarkably reduced to 2 nm / min. Thus, if even a small amount of SF ₆ remains in the chamber, the etching rates of the GaN layer 102 and the n-type AlGaN layer 103 will be significantly reduced. Therefore, in the conventional method, before the GaN layer 102 and the n-type AlGaN layer 103 are dry-etched, the chamber is evacuated or the chamber is cleaned with chlorine plasma, which requires a long time for processing. It has become. Further, in order to shorten the processing time, a process (dry etching) that can be performed in the same chamber is performed separately in two dry etching apparatuses, or a dry etching apparatus having a multi-chamber is used. Sometimes it is divided into two chambers.

By taking these measures, it is possible to reduce the influence of SF ₆ remaining in the chamber. However, when SF ₆ adheres to the insulating substrate 101 or the like, it is difficult to eliminate the influence.

  Further, the resist layer 156 is formed so that even the Ni layer 108 and the seed layer 107 are not removed when the Ni layer 113 and the seed layer 112 used as the metal mask are removed. Is complicated. That is, it is difficult for a general spin coater or the like to drop the resist uniformly into the via hole 101s, and it becomes extremely difficult especially when the diameter is 100 μm or less. Moreover, it is difficult to leave the resist layer 156 thick only at the bottom of the via hole 101 s by resist coating techniques such as dip coating, spray coating, and dispenser. Therefore, the yield may be lowered at these points. Moreover, the apparatus which can be left thick is very expensive. For this reason, the Ni layer 113 and the seed layer 112 may be left without being removed.

  However, if the Ni layer 113 and the seed layer 112 are left, a problem occurs when the etching rate of the insulating substrate 101 is increased to improve the throughput. That is, as shown in FIG. 11, the via hole 101s becomes tapered as a result of side etching accompanying an increase in the etching rate. If the Ni layer 113 and the seed layer 112 remain at the upper end of the tapered via hole 101s, then the seed layer 114 and the Au layer 115 cannot be appropriately formed.

  Further, the side etching can be suppressed by setting the pressure in the chamber during etching to a low pressure of 1 Pa or less. In this case, however, ion collision on the side wall of the via hole 101s becomes strong, and FIG. As shown in FIG. 5, a deep notch is easily formed at the edge. When the deep notch is formed, the tip of the notch reaches the Ni layer 108 before the entire via hole 101s reaches the seed layer 107, and the Ni layer 108 is eroded or the Ni layer caused by fluorination. 108 inactivation occurs.

In addition, as with the Bosch process, there is also a technique for performing etching while depositing a fluorocarbon-based polymer on the etching sidewall while repeating etching and deposition using a deposit gas such as C ₄ F ₈ as in the Bosch process. . However, even if the etching rate of the SiC substrate is as low as 0.24 μm / min at the maximum, repeated etching and deposition will further reduce the throughput. For example, it takes 10 hours to etch on the order of 100 μm.

  Thus, with the conventional method, it is difficult to improve the throughput while the Ni layer 113 and the seed layer 112 remain.

JP 2004-363563 A JP 2004-327604 A Microelectronic Engineering 71 (2004) 329-334, Etching profile of silicon carbide in a NF3 / CH4 inductively coupled plasma, Byungwhan Kim et al. Thin Solid Films 447-448 (2004) 100-104, High rate etching of 6H-SiC in SF6-based magnetically-enhanced inductively coupled plasmas, D.W.Kim et al. Appl. Phys. Lett. 68 (1996) 3755, High etch rates of SiC in magnetron enhanced SF6 plasmas, G. F. McLane et al. Materials Science Forum Vols. 527-529 (2006), Deep Reactive Ion Etching (DRIE) of High Aspect Ratio SiC Microstructures using a Time-Multiplexed Etch-Passivate Process, Laura J. Evans et al.

  An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing a decrease in yield associated with formation of a via hole and improving throughput.

  As a result of intensive studies to solve the above-mentioned problems, the present inventor has come up with the following aspects of the invention.

  In the first method for manufacturing a semiconductor device, a compound semiconductor layer is formed on a substrate, and then an electrode is formed on the compound semiconductor layer. Next, an opening reaching at least the surface of the substrate is formed in the compound semiconductor layer. Next, a conductive layer connected to the electrode is formed in the opening. Next, by performing dry etching using the conductive layer as an etching stopper, a via hole reaching the conductive layer from the back surface side is formed in the substrate. Next, via wiring is formed from the via hole to the back surface of the substrate. Then, the dry etching is performed while forming a compound film on the sidewall of the via hole.

  In the second method for manufacturing a semiconductor device, a compound semiconductor layer is formed on a substrate, and then an electrode is formed on the compound semiconductor layer. Next, an opening reaching at least the surface of the substrate is formed in the compound semiconductor layer. Next, a conductive layer connected to the electrode is formed in the opening. Next, by performing dry etching using the conductive layer as an etching stopper, a via hole reaching the conductive layer from the back surface side is formed in the substrate. Next, via wiring is formed from the via hole to the back surface of the substrate. And the width | variety of the deepest part of the said opening part is made smaller than the width | variety in the surface of the said compound semiconductor layer of the said opening part.

  According to the manufacturing method of the semiconductor device described above, since the relationship between the via hole and the conductive layer is appropriate, a desired via hole can be easily formed. It is also possible to form an opening in the compound semiconductor layer without being affected by the gas used in forming the via hole in the insulating substrate. In addition, since a via wiring can be appropriately formed even if a metal mask is used and left while forming a via hole, it is not necessary to embed a resist or the like in the via hole. As a result, it is possible to suppress the yield reduction related to the formation of the via hole and improve the throughput.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. 1A to 1T are cross-sectional views showing a method of manufacturing a GaN-based HEMT according to the first embodiment in the order of steps.

  In the first embodiment, first, as shown in FIG. 1A, a GaN layer 2 and an n-type AlGaN layer 3 are formed in this order on the surface of an insulating substrate 1 made of silicon carbide (SiC). The insulating substrate 1 has a thickness of about 350 μm, the GaN layer 2 has a thickness of about 2 μm, and the n-type AlGaN layer 3 has a thickness of about 25 nm. Next, boron, helium, or the like is injected into the region to be the inactive region 92, thereby eliminating the two-dimensional electron gas. As a result, the inactive region 92 and the active region 91 are partitioned. Next, a source electrode 4 s, a gate electrode 4 g, and a drain electrode 4 d are selectively formed in the active region 91 on the n-type AlGaN layer 3. Thereafter, a SiN layer 5 is formed on the n-type AlGaN layer 3 to cover the source electrode 4s, the gate electrode 4g, and the drain electrode 4d. In forming the source electrode 4s, the gate electrode 4g, and the drain electrode 4d, for example, a Ti layer is formed, and then an Al layer is formed on the Ti layer.

  After the formation of the SiN layer 5, as shown in FIG. 1B, a resist pattern 51 having an opening 51s corresponding to the source electrode 4s and an opening 51d corresponding to the drain electrode 4d is formed on the SiN layer 5. The thickness of the resist pattern 51 is about 1 μm.

Next, as shown in FIG. 1C, by patterning the SiN layer 5 using the resist pattern 51 as a mask, a contact hole 5s that matches the opening 51s is formed on the source electrode 4s, and a contact hole that matches the opening 51d. 5d is formed on the drain electrode 4d. In patterning the SiN layer 5, for example, SF ₆ and CHF ₃ are supplied into the chamber at a flow rate ratio of 2:30, the antenna power is set to 500 W, and the bias power is set to 50 W to perform dry etching. In this case, the etching rate is about 0.24 μm / min.

Thereafter, the resist pattern 51 is removed, and a resist pattern 52 having an etching stopper opening 52 s located in the inactive region 92 is formed on the SiN layer 5 as shown in FIG. 1D. The thickness of the resist pattern 52 is about 10 μm. The diameter of the opening 52s is, for example, about 150 μm. Even if the thickness of the resist pattern 52 is about 10 μm, the opening 52 s having a diameter of about 150 μm can be formed with high accuracy. Subsequently, by patterning the SiN layer 5 using the resist pattern 52 as a mask, the opening 6 that matches the opening 52 s is formed in the inactive region 92. In patterning the SiN layer 5, for example, SF ₆ and CHF ₃ are supplied into the chamber at a flow rate ratio of 2:30, the antenna power is set to 500 W, and the bias power is set to 50 W to perform dry etching.

Next, as shown in FIG. 1E, the opening 6 reaches the insulating substrate 1 by performing dry etching of the n-type AlGaN layer 3 and the GaN layer 2 using the resist pattern 52 as a mask. In this dry etching, a chlorine-based gas such as Cl ₂ gas is used. Further, using an ICP dry etching apparatus, the antenna power is set to 100 W, and the bias power is set to 20 W. In this case, the etching rate of the n-type AlGaN layer 3 and the GaN layer 2 is about 0.2 μm / min.

  Note that the opening 6 may reach the inside of the insulating substrate 1.

  Next, the resist pattern 52 is removed, and as shown in FIG. 1F, a stacked body of a Ta layer and a Cu layer is formed as a seed layer 7 on the entire surface of the insulating substrate 1 by a sputtering method. The thickness of the Ta layer is about 20 nm, and the thickness of the Cu layer is about 200 nm.

  Thereafter, as shown in FIG. 1G, a resist pattern 53 having an opening 53 s exposing the entire opening 6 is formed on the seed layer 7. The opening 53s is located in the inactive region 92. Further, the thickness of the resist pattern 53 is about 3 μm.

  Subsequently, as shown in FIG. 1H, an Ni layer 8 is formed as a conductive etching stopper on the seed layer 7 in the opening 53s by electroplating. The thickness of the Ni layer 8 is about 3.2 μm. The Ni layer 8 is formed, for example, in a hot bath at 50 ° C. to 60 ° C. In this case, the plating rate is about 0.5 μm / min.

  Next, as shown in FIG. 1I, the resist pattern 53 is removed. Thereafter, the seed layer 7 exposed from the Ni layer 8 is removed by performing ion milling. At this time, the Ni layer 8 is also slightly scraped, and the thickness becomes about 3 μm. The distance between the surface of the n-type AlGaN layer 3 and the surface of the Ni layer 8 is about 1 μm.

  Subsequently, as shown in FIG. 1J, a stacked body of a Ti layer, a Pt layer, and an Au layer is formed as a seed layer 9 on the entire surface of the insulating substrate 1 by a sputtering method. The thickness of the Ti layer is about 10 nm, the thickness of the Pt layer is about 50 nm, and the thickness of the Au layer is about 200 nm.

  Next, as shown in FIG. 1K, a resist pattern 54 having an opening surrounding the entire source electrode 4s and Ni layer 8 and an opening corresponding to the outer edge of the drain electrode 4d is formed on the seed layer 9. The thickness of the resist pattern 54 is about 3 μm. Thereafter, the Au layer 10 having a thickness of about 1 μm is formed on the seed layer 9 in each opening of the resist pattern 54 by electroplating. The Au layer 10 is formed in, for example, an Au plating bath at 55 ° C. to 65 ° C. In this case, the plating rate is about 0.5 μm / min.

  Subsequently, as shown in FIG. 1L, the resist pattern 54 is removed. Subsequently, the seed layer 9 exposed from the Au layer 10 is removed by performing ion milling. At this time, the Au layer 10 is also slightly scraped, and the thickness becomes about 0.6 μm. The milling rate of the Ti layer constituting the seed layer 9 is about 15 nm / min, the milling rate of the Pt layer is about 30 nm / min, and the milling rate of the Au layer is about 50 nm / min.

  Thereafter, as shown in FIG. 1M, the surface protective layer 11 is formed on the entire surface of the insulating substrate 1 and the front and back of the insulating substrate 1 are reversed. Next, by polishing the back surface of the insulating substrate 1, the thickness of the insulating substrate 1 is set to about 150 μm.

  Subsequently, as shown in FIG. 1N, a stacked body of a Ta layer 21a and a Cu layer 21b is formed as a seed layer 21 on the back surface of the insulating substrate 1 by a sputtering method. The thickness of the Ta layer 21a is about 20 nm, and the thickness of the Cu layer 21b is about 200 nm.

  Next, as shown in FIG. 1O, a resist pattern 55 is formed on the seed layer 21 so as to cover a portion corresponding to the Ni layer 8. The resist pattern 55 has a thickness of about 3 μm and a diameter of about 100 μm. Thereafter, the Ni layer 13 having a thickness of about 3.2 μm is formed on the seed layer 21 in a region excluding the resist pattern 55 by electroplating. The Ni layer 13 is formed in a hot bath at 50 ° C. to 60 ° C., for example. In this case, the plating rate is about 0.5 μm / min.

  Subsequently, as shown in FIG. 1P, the resist pattern 55 is removed. Next, ion milling is performed to remove the seed layer 21 exposed from the Ni layer 13. At this time, the Ni layer 13 is also slightly scraped, and the thickness becomes about 3 μm.

Thereafter, as shown in FIG. 1Q, via etching 1s is formed by performing dry etching of the insulating substrate 1 using the Ni layer 13 as a mask. In this dry etching, fluoride base gas, for example, sulfur hexafluoride (SF ₆₎ gas and oxygen (O ₂₎ mixed gas of the gas. Further, using an ICP dry etching apparatus, the antenna power is 2 kW and the bias power is 200 W. Further, the pressure in the chamber is set to 5 Pa or more, for example, 10 Pa. Further, the stage on which the insulating substrate 1 is placed is cooled, and for example, the temperature of the insulating substrate 1 is suppressed to about 200 ° C. at the maximum. In cooling the stage, for example, helium gas at about 0 ° C. is passed through the stage. In this case, the etching rate of the insulating substrate 1 made of SiC is 2 μm / min or more.

When dry etching is performed under such conditions, as shown in FIG. 1Q, the compound film 19 containing Ni in the Ni layer 13, Si in the insulating substrate 1, and F in SF ₆ is formed in the via hole 1s. As it forms, it deposits on its sidewalls. The compound film 19 is hardly etched by a mixed gas of SF ₆ gas and O ₂ gas. For this reason, even if ion collision on the side wall of the via hole 1s becomes strong, side etching of the insulating substrate 1 is suppressed. Accordingly, the diameter of the via hole 1s is equal to or smaller than the diameter of the opening of the Ni layer 13.

  After the formation of the via hole 1s, as shown in FIG. 1R, a laminated body of a Ti layer, a Pt layer, and an Au layer is formed as a seed layer 14 on the entire back surface side of the insulating substrate 1 by a sputtering method. The thickness of the Ti layer is about 10 nm, the thickness of the Pt layer is about 50 nm, and the thickness of the Au layer is about 200 nm.

  Next, as shown in FIG. 1S, an Au layer 15 having a thickness of about 10 μm is formed on the seed layer 14 by electroplating. A via wiring 16 is composed of the Au layer 15 and the seed layer 14. When the Au layer 15 is formed in the via hole 1s having a diameter of about 100 μm and a depth of about 150 μm by electroplating, the Au layer 15 is formed only on the bottom and side portions of the via hole 1s, and the via hole 1s is completely formed. It is not embedded in.

  Thereafter, as shown in FIG. 1T, the front and back of the insulating substrate 1 are reversed, and the surface protective layer 11 is removed. Then, if necessary, wiring (not shown) or the like is formed to complete the GaN-based HEMT.

In such a manufacturing method, when the via hole 1s is formed, the bottoms of the seed layer 7 and the Ni layer 8 functioning as an etching stopper are in contact with the region where the via hole 1s of the insulating substrate 1 is formed. The GaN layer 2 and the n-type AlGaN layer 3 are not interposed therebetween. For this reason, even if overetching is performed, the GaN layer 2 and the n-type AlGaN layer 3 are not excessively etched. Since the Ni layer 8 is thick, the Ni layer 8 does not disappear due to overetching, and the Ni layer 8 functions reliably as an etching stopper. Further, although the Ni layer 8 is thicker than the conventional Ni layer 108, the distance between the surface of the Ni layer 8 and the surface of the n-type AlGaN layer 3 is as narrow as about 1 μm, so the thickness of the resist pattern 54 is as thin as about 1 μm. Even if it is a thing, the thickness tends to be uniform. Therefore, the pattern is hardly distorted and the pattern opening accuracy can be maintained high. Further, since the insulating substrate 1 using SF ₆ is not dry-etched before the etching of the GaN layer 2 and the n-type AlGaN layer 3, the residual SF during the dry-etching of the GaN layer 2 and the n-type AlGaN layer 3 is not performed. _No influence of ₆ .

  Therefore, according to the present embodiment, the Ni layer 8 can reliably function as an etching stopper while ensuring a high yield obtained by overetching. Therefore, it is possible to obtain a high yield while suppressing an increase in the number of processes, and the manufacturing cost is reduced.

  Further, even if the insulating substrate 1 is etched at a high speed, the shape of the via hole 1s becomes appropriate, so that an appropriate via wiring 16 can be formed while the Ni layer 13 and the seed layer 21 remain. Accordingly, since it is not necessary to form a resist film in the via hole 1s, it is possible to reduce the number of processes and the required time.

  After the surface protective layer 11 is removed, the layout viewed from the front surface side of the insulating substrate 1 is as shown in FIG. 2A, and the layout viewed from the back surface side is as shown in FIG. 2B. That is, although not shown in FIG. 1T, there is also an Au layer 10 connected to the gate electrode 4g as shown in FIG. 2A. Note that the layout shown in FIG. 2A is simple, but if a multi-finger gate structure is adopted, output can be improved. In addition, a resistor, a capacitor, and the like may be mounted to form a monolithic microwave integrated circuit (MMIC).

(Second Embodiment)
Next, a second embodiment of the present invention will be described. 3A to 3T are cross-sectional views illustrating a method of manufacturing a GaN-based HEMT according to the second embodiment of the present invention in the order of steps.

  Also in the second embodiment, first, as shown in FIG. 3A, the GaN layer 2 and the n-type AlGaN layer 3 are formed in this order on the surface of the insulating substrate 1 made of silicon carbide (SiC). Further, the SiN layer 31 is formed on the n-type AlGaN layer 3 by, for example, a plasma CVD method. Next, a Ti layer and Ni layer stack or a Ti layer and Cu layer stack is formed as a seed layer 32 on the SiN layer 31. Instead of the SiN layer 31, an SOG (spin on glass) layer or an organic polymer layer may be formed.

  After the formation of the seed layer 32, as shown in FIG. 3B, a resist pattern 61 is formed on the seed layer 32 to cover a region where an etching stopper is to be formed. The diameter of the resist pattern 61 is about 150 μm.

  Next, as shown in FIG. 3C, a Ni layer 33 is formed on the seed layer 32 in a region excluding the resist pattern 61 by electroplating.

  Thereafter, as shown in FIG. 3D, the resist pattern 61 is removed. Subsequently, the seed layer 32 exposed from the Ni layer 33 is removed by performing ion milling. At this time, the Ni layer 33 is also slightly cut.

  Subsequently, by patterning the SiN layer 31 using the Ni layer 33 as a metal mask, the opening 6 is formed in the inactive region 92 as shown in FIG. 3E.

Subsequently, by performing dry etching of the n-type AlGaN layer 3 and the GaN layer 2 using the Ni layer 33 as a metal mask, the opening 6 reaches the insulating substrate 1 as shown in FIG. 3F. In this dry etching, an ICP dry etching apparatus is used, the antenna power is 200 W, and the bias power is 50 W. Further, a chlorine-based gas, for example, Cl ₂ gas is supplied into the chamber at a flow rate of 30 sccm, and the pressure in the chamber is set to about 1 Pa. In this case, the etching rate of the n-type AlGaN layer 3 and the GaN layer 2 is about 0.29 μm / min.

  Note that the opening 6 may reach the inside of the insulating substrate 1 as in the first embodiment.

Next, by performing dry etching of the insulating substrate 1 using the Ni layer 33 as a metal mask, a tapered recess 1a having a depth of about 20 μm, for example, is formed on the surface of the insulating substrate 1 as shown in FIG. 3G. To do. In this dry etching, for example, a mixed gas of SF ₆ gas and O ₂ gas is used, the flow rate of SF ₆ gas with respect to the flow rate of O ₂ gas is set to about 2.5, and the pressure in the chamber is set to about 0.5 Pa. The antenna power is 1 kW and the bias power is 100 W. In this case, the etching rate of the insulating substrate 1 is about 0.57 μm / min.

  Thereafter, as shown in FIG. 3H, the Ni layer 33 and the seed layer 32 are removed by wet etching or the like using sulfuric acid / hydrogen peroxide.

  Subsequently, as shown in FIG. 3I, a stacked body of a Ta layer and a Cu layer is formed as a seed layer 7 on the entire surface of the insulating substrate 1 by a sputtering method.

  Next, as shown in FIG. 3J, a resist pattern 53 having an opening 53 s that exposes the entire opening 6 is formed on the seed layer 7.

  Thereafter, as shown in FIG. 3K, a Ni layer 8 is formed as a conductive etching stopper on the seed layer 7 in the opening 53s by electroplating.

  Subsequently, as shown in FIG. 3L, the resist pattern 53 is removed. Thereafter, the seed layer 7 exposed from the Ni layer 8 is removed by performing ion milling.

  Next, as shown in FIG. 3M, an opening is selectively formed in the SiN layer 31, and a source electrode 4s, a gate electrode 4g, and a drain electrode 4d are formed on the n-type AlGaN layer 3 therein. Thereafter, a SiN layer 5 is formed on the n-type AlGaN layer 3 to cover the source electrode 4s, the gate electrode 4g, and the drain electrode 4d. In forming the source electrode 4s, the gate electrode 4g, and the drain electrode 4d, for example, a Ti layer is formed, and then an Al layer is formed on the Ti layer.

  After the formation of the SiN layer 5, as shown in FIG. 3N, a resist pattern 51 having an opening 51s corresponding to the source electrode 4s, an opening 51d corresponding to the drain electrode 4d, and an opening 51v corresponding to the Ni layer 8 is formed. Is formed on the SiN layer 5. Next, by patterning the SiN layer 5 using the resist pattern 51 as a mask, a contact hole 5s that matches the opening 51s is formed on the source electrode 4s, and a contact hole 5d that matches the opening 51d is formed on the drain electrode 4d. A contact hole 5v formed and aligned with the opening 51v is formed on the Ni layer 8.

  Thereafter, the resist pattern 51 is removed, and as shown in FIG. 3O, a laminated body of a Ti layer, a Pt layer, and an Au layer is formed as a seed layer 9 on the entire surface of the insulating substrate 1 by a sputtering method.

  Subsequently, as shown in FIG. 3P, a resist pattern 54 having an opening surrounding the entire source electrode 4s and Ni layer 8 and an opening corresponding to the outer edge of the drain electrode 4d is formed on the seed layer 9. Next, an Au layer 10 having a thickness of about 1 μm is formed on the seed layer 9 in each opening of the resist pattern 54 by electroplating.

  Thereafter, as shown in FIG. 3Q, the resist pattern 54 is removed. Subsequently, the seed layer 9 exposed from the Au layer 10 is removed by performing ion milling.

  Subsequently, as shown in FIG. 3R, the surface protective layer 11 is formed on the entire surface of the insulating substrate 1 and the front and back of the insulating substrate 1 are reversed. Next, by polishing the back surface of the insulating substrate 1, the thickness of the insulating substrate 1 is set to about 150 μm. Thereafter, similarly to the first embodiment, the seed layer 21 and the Ni layer 13 are formed.

Next, dry etching of the insulating substrate 1 is performed using the Ni layer 13 as a mask, thereby forming a via hole 1s as shown in FIG. 3S. In this dry etching, fluoride base gas, for example, sulfur hexafluoride (SF ₆₎ gas and oxygen (O ₂₎ mixed gas of the gas. Further, using an ICP dry etching apparatus, the antenna power is 2 kW and the bias power is 200 W. Further, the flow rate of SF ₆ gas with respect to the flow rate of O ₂ gas is set to about 20, and the pressure in the chamber is set to a low pressure of about 0.5 Pa. Further, the stage on which the insulating substrate 1 is placed is cooled, and for example, the temperature of the insulating substrate 1 is suppressed to about 200 ° C. at the maximum. In cooling the stage, for example, helium gas at about 0 ° C. is passed through the stage. In this case, the etching rate of the insulating substrate 1 made of SiC is 1.47 μm / min or more.

  When dry etching is performed under such conditions, as shown in FIG. 3S, the pressure in the chamber is low, so that side etching does not occur and the compound film 19 is not formed, but the via hole 1s is formed at the tip thereof. It stretches while forming a notch. Further, the depth of the notch is about 12% of the etching depth. Therefore, when the depth of the via hole 1s is about 150 μm, the depth of the notch is 18 μm. The width of the notch is about 21 μm. As shown in FIG. 4, the width (b) of the bottom surface of the Ni layer 8 is preferably equal to or less than the width (d) of the portion surrounded by the notch of the via hole 1s, and the width (c) of the via hole 1s. ) Is preferably equal to or less than the width of the portion of the Ni layer 8 embedded in the GaN layer 2 (that is, the width of the opening 6) (a). Moreover, it is preferable that the depth of the recessed part 1a is more than the depth (for example, 18 micrometers) of a notch. This is to prevent the tip of the notch from reaching the Ni layer 8 before the portion surrounded by the notch of the via hole 1s.

  After the formation of the via hole 1s, as shown in FIG. 3T, the via wiring 16 is formed and the surface protective layer 11 is removed as in the first embodiment. Then, if necessary, wiring (not shown) or the like is formed to complete the GaN-based HEMT.

  Also by such a manufacturing method, the same effect as that of the first embodiment can be obtained. This is because, even if a notch is formed at the tip of the via hole 1s, a recess 1a that compensates for this is formed in the insulating substrate 1 in advance. That is, the recess 1a prevents the notch from reaching the Ni layer 8, and erosion, fluorination, and the like of the Ni layer 8 accompanying this arrival are suppressed.

(Third embodiment)
Next, a third embodiment will be described. 5A to 5E are cross-sectional views showing a method of manufacturing a GaN-based HEMT according to the third embodiment of the present invention in the order of steps.

In the third embodiment, first, as shown in FIG. 5A, processing up to the formation of the opening 6 in the SiN layer 5 is performed as in the first embodiment. Next, as shown in FIG. 5B, unlike the first embodiment, by performing isotropic etching of the n-type AlGaN layer 3 and the GaN layer 2 using the resist pattern 52 as a mask, the insulating substrate 1 is reached. The reaching tapered opening 26 is formed in the n-type AlGaN layer 3 and the GaN layer 2. In this isotropic etching, reactive ion etching (RIE) using a chlorine-based gas such as Cl ₂ gas is performed.

  Thereafter, as shown in FIG. 5C, similarly to the first embodiment, processes from the removal of the resist pattern 52 to the selective removal of the seed layer 9 are performed. Subsequently, similarly to the first embodiment, as shown in FIG. 5D, processing from the formation of the surface protective layer 11 to the formation of the via hole 1s is performed. However, the conditions for forming the via hole 1s are the same as those in the second embodiment. Therefore, as shown in FIG. 5D, the via hole 1s extends while a notch is formed at the tip thereof. In the present embodiment, since the Ni layer 8 is formed in the tapered opening 26, the arrival of the notch to the Ni layer 8 is suppressed as in the second embodiment.

  After the formation of the via hole 1s, as shown in FIG. 5E, the formation of the via wiring 16 and the removal of the surface protective layer 11 are performed as in the first embodiment. Then, if necessary, wiring (not shown) or the like is formed to complete the GaN-based HEMT.

  Also by such a manufacturing method, the same effect as the first embodiment can be obtained. This is because the Ni layer 8 is formed in the tapered opening 26 that compensates for the notch formed at the tip of the via hole 1s. That is, the opening 26 suppresses the arrival of the notch to the Ni layer 8, and erosion, fluorination, and the like of the Ni layer 8 accompanying this arrival are suppressed.

In addition, when this inventor formed the via hole 1s along 1st Embodiment and 2nd Embodiment, and image | photographed the scanning electron micrograph, the image shown in FIG. 6, FIG. 7 was obtained. In the formation of the via hole 1s according to the second embodiment, etching was performed using a mixed gas of SF ₆ gas and O ₂ gas at a pressure of 0.5 Pa. As a result, the etching rate was 1.5 μm / min, the selection ratio of the insulating substrate 1 made of SiC to the Ni layer 13 was about 50, and the depth of the notch was about 12% of the depth of the via hole 1s. .

Further, when the inventor of the present application formed a via hole 1s according to the first embodiment and investigated the composition of the compound film 19 with an energy dispersive X-ray fluorescence spectrometer (EDX), the result shown in FIG. 8 was obtained. It was. From this result, it is clear that the main component of the compound film 19 is silicon in the insulating substrate 1 made of SiC, nickel in the Ni layer 13, and fluorine in SF ₆ gas used during etching.

  As in the second embodiment, the bottom surface width (b) of the Ni layer 8 is preferably equal to or less than the width (d) of the portion surrounded by the notch of the via hole 1s. This is to prevent the tip of the notch from reaching the Ni layer 8 before the portion surrounded by the notch of the via hole 1s.

  In any of the embodiments, a sapphire substrate, a silicon substrate, a zinc oxide substrate, or the like may be used as the substrate in place of the SiC substrate. That is, the present invention is particularly useful when dry etching using a fluorine-based gas is performed when forming a via hole. However, in the first embodiment, the SiC substrate is most preferable in view of the characteristics of the compound film 19.

  In any of the embodiments, the Ni layer 13 is left, but the Ni layer 13 may be eliminated when the via hole 1s is formed by adjusting the thickness of the Ni layer 13 in advance.

It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 1st Embodiment. FIG. 1B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1A. FIG. 2B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1B. 1C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1C. 2D is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1D. 2E is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1E. 1F is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1F. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1G. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1H. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1I. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1J. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1K. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1L. FIG. 2B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1M. 1N is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1N. FIG. 10 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 10. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1P. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1Q. 1R is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1R. FIG. 2 is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1S. It is a figure which shows the layout of the surface side in 1st Embodiment. It is a figure which shows the layout of the back surface side in 1st Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 2nd Embodiment. FIG. 3B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 3A. FIG. 3B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 3B. 3C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 3C. FIG. 3D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 3D. FIG. 3E is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 3E. 3F is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 3F. FIG. 3G is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 3G. FIG. 3H is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 3H. FIG. 3D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 3I. 3J is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 3J. FIG. 3D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 3K. FIG. 3D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 3L. FIG. 3C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 3M. 3N is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 3N. FIG. 3D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 3O. FIG. 3D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 3P. 3D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 3Q. 3D is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 3R. 3D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 3S. It is a figure which shows the relationship between Ni layer 8 (etching stopper) and the via hole 1s in 2nd Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 3rd Embodiment. FIG. 5B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 5A. FIG. 5B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 5B. 5C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 5C. FIG. 5D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 5D. It is a figure which shows the SEM photograph of the via hole formed along 1st Embodiment. It is a figure which shows the SEM photograph of the via hole formed along 2nd Embodiment. It is a figure which shows the analysis result of a compound film | membrane. It is sectional drawing which shows the manufacturing method of the conventional GaN-type HEMT. It is sectional drawing which shows the manufacturing method of the conventional GaN-type HEMT following FIG. 9A. FIG. 9B is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9B. FIG. 9D is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9C. FIG. 9D is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9D. FIG. 9E is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9E. FIG. 9F is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9F. FIG. 9G is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9G. 9H is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9H. FIG. 9D is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9I. FIG. 9D is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9J. FIG. 9D is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9K. 9L is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9L. FIG. 9D is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9M. 9N is a cross-sectional view illustrating a conventional method for manufacturing a GaN-based HEMT, following FIG. 9N. FIG. 9D is a cross-sectional view showing a conventional GaN-based HEMT manufacturing method following FIG. 9O. FIG. 9D is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9P. FIG. 9D is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9Q. FIG. 9D is a cross-sectional view illustrating a conventional method for manufacturing a GaN-based HEMT, following FIG. 9R. FIG. 9D is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9S. FIG. 9D is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9T. FIG. 9D is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9U. FIG. 10 is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9V. FIG. 10 is a cross-sectional view illustrating a conventional GaN-based HEMT manufacturing method following FIG. 9W. It is a graph which shows the result of the experiment of ICP dry etching. It is a figure which shows the problem at the time of high-speed etching. It is a figure which shows the problem at the time of low-pressure etching.

Explanation of symbols

1: Insulating substrate 1a: Recess 1s: Via hole 2: GaN layer 3: n-type AlGaN layer 4d: Drain electrode 4g: Gate electrode 4s: Source electrode 6: Opening 7: Seed layer 8: Ni layer 10: Au layer 13 : Ni layer 14: Seed layer 15: Au layer 16: Via wiring 19: Compound film 21: Seed layer 26: Opening

Claims (6)

Forming a compound semiconductor layer on the substrate;
Forming an electrode on the compound semiconductor layer;
Forming an opening that reaches at least the surface of the substrate in the compound semiconductor layer;
Forming a conductive layer connected to the electrode in the opening;
Forming a via hole reaching the conductive layer from the back side of the substrate by performing dry etching using the conductive layer as an etching stopper;
Forming via wiring from the via hole to the back surface of the substrate;
Have
A method of manufacturing a semiconductor device, wherein the dry etching is performed while forming a compound film on a sidewall of the via hole. The substrate contains silicon;
The conductive layer contains nickel;
The dry etching is performed in an atmosphere containing fluorine,
2. The method of manufacturing a semiconductor device according to claim 1, wherein a film containing nickel, silicon, and fluorine is formed as the compound film. The step of forming the compound semiconductor layer includes
Forming a GaN layer on the substrate;
Forming an n-type AlGaN layer on the GaN layer;
Have
3. The method of manufacturing a semiconductor device according to claim 2, wherein the dry etching is performed using a mixed gas of sulfur hexafluoride gas and oxygen gas. Forming a compound semiconductor layer on the substrate;
Forming an electrode on the compound semiconductor layer;
Forming an opening that reaches at least the surface of the substrate in the compound semiconductor layer;
Forming a conductive layer connected to the electrode in the opening;
Forming a via hole reaching the conductive layer from the back side of the substrate by performing dry etching using the conductive layer as an etching stopper;
Forming via wiring from the via hole to the back surface of the substrate;
Have
A width of the deepest part of the opening is made smaller than a width of the opening on the surface of the compound semiconductor layer.   The method of manufacturing a semiconductor device according to claim 4, wherein the opening is formed to the inside of the substrate.   The method of manufacturing a semiconductor device according to claim 4, wherein the opening is formed up to a surface of the substrate.

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